august 2011 ? 2007 fairchild semiconductor corporation FDS86141 ? rev. c4 www.fairchildsemi.com 1 FDS86141 ? n-channel powertrench ? mosfet FDS86141 n-channel powertrench ? mosfet 100 v, 7 a, 23 m ? features ? maximum r ds(on) = 23 m ? at v gs = 10 v, i d = 7 a ? maximum r ds(on) = 36 m ? at v gs = 6 v, i d = 5.5 a ? high-performance trench technology; extremely low r ds(on) ? 100% uil tested ? rohs compliant general description this n-channel mosfet is produced using fairchild semiconductor?s advanced powertrench ? process that has been especially tailored to minimi ze the on-state resistance and maintain superior switching performance. applications ? dc-dc conversion mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 100 v v gs gate to source voltage 20 v i d drain current -continuous 7 a -pulsed 30 e as single pulse avalanche energy (note 3) 121 mj p d power dissipation t a = 25 c (note 1a) 5.0 w power dissipation t a = 25 c (note 1b) 2.5 t j , t stg operating and storage junction temperature range -55 to +150 c r ? jc thermal resistance, junction to case (note 1) 2.5 c/w r ? ja thermal resistance, junction to ambient (note 1a) 50 device marking device package reel size tape width quantity FDS86141 FDS86141 so-8 13 ?? 12 mm 2500 units so-8 d d d d s s s g pin 1 g s s s d d d d 5 6 7 8 3 2 1 4
FDS86141 ? n-channel powertrench ? mosfet www.fairchildsemi.com 2 ? 2007 fairchild semiconductor corporation FDS86141 ? rev. c4 electrical characteristics t j = 25 c unless otherwise noted. off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics symbol parameter test conditions min. typ. max. units bv dss drain-to-source breakdown voltage i d = 250 ? a, v gs = 0 v 100 v ? bv dss ???? t j breakdown voltage temperature coefficient i d = 250 ? a, referenced to 25c 67 mv/c i dss zero gate voltage drain current v ds = 80 v, v gs = 0 v 1 ? a i gss gate-to-source leakage current v gs = 20 v, v ds = 0 v 100 na v gs(th) gate-to-source threshold voltage v gs = v ds , i d = 250 ? a23.14v ?? v gs(th) ???? t j gate-to-source threshold voltage temperature coefficient i d = 250 ? a, referenced to 25c -10 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 7 a 19 23 m ? v gs = 6 v, i d = 5.5 a 27 37 v gs = 10 v, i d = 7 a, t j = 125c 33 40 g fs forward transconductance v ds = 10 v, i d = 7 a 19 s c iss input capacitance v ds = 50 v, v gs = 0 v, f = 1 mhz 703 934 pf c oss output capacitance 186 247 pf c rss reverse transfer capacitance 8.6 13 pf r g gate resistance 0.5 ? t d(on) turn-on delay time v dd = 50 v, i d = 7 a, v gs = 10 v, r gen = 6 ? 8.3 17 ns t r rise time 3.2 10 ns t d(off) turn-off delay time 14.3 26 ns t f fall time 3.2 10 ns q g(tot) total gate charge v gs = 0 v to 10 v v dd = 50 v i d = 7 a 11.8 16.5 nc total gate charge v gs = 0 v to 5 v 6.7 9.4 nc q gs total gate charge 3.4 nc q gd gate to drain ?miller? charge 3.1 nc v sd source-to-drain diode forward voltage v gs = 0 v, i s = 7 a (note 2) 0.8 1.3 v v gs = 0 v, i s = 2 a (note 2) 0.8 1.2 t rr reverse recovery time i f = 7 a, di/dt = 100 a/ ? s 43 69 ns q rr reverse recovery charge 39 62 nc notes: 1. r ? ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r ? jc is guaranteed by design while r ? ca is determined by the user's board design. 2. pulse test: pulse width < 300 ? s, duty cycle < 2.0 %. 3. starting t j = 25 o c; n-ch: l = 3 mh, i as = 9 a, v dd = 100 v, v gs = 10 v. a) 50 c/w when mounted on a 1 in 2 pad of 2 oz copper. b) 125 c/w when mounted on a minimum pad.
FDS86141 ? n-channel powertrench ? mosfet www.fairchildsemi.com 3 ? 2007 fairchild semiconductor corporation FDS86141 ? rev. c4 typical characteristics t j = 25 c unless otherwise noted. f i g u r e 1 . o n - r e g i o n c h a r a c t e r i s t i c s f i g u r e 2 . n o r m a l i z e d o n - r e s i s t a n c e vs. drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n - r e s i s t a n c e vs. junction temperature figure 4. on-resistance vs. gate-to-source voltage figure 5. transfer characteristics figure 6. source-to-drain diode forward voltage vs. source current 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 30 v gs = 7 v v gs = 5.5 v v gs = 10 v pulse duration = 80 ? s duty cycle = 0.5% max v gs = 5 v v gs = 6 v i d , drain current (a) v ds , drain to source voltage (v) 0 5 10 15 20 25 30 0 1 2 3 4 v gs = 5 v pulse duration = 80 ?? s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 6 v v gs = 7 v v gs = 5.5 v v gs = 10 v -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 i d = 7 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) 45678910 0 20 40 60 80 t j = 125 o c i d = 7 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m ? ) pulse duration = 80 ? s duty cycle = 0.5% max 2468 0 5 10 15 20 25 30 t j = 150 o c v ds = 5 v pulse duration = 80 ? s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) 0.2 0.4 0.6 0.8 1.0 1.2 0.01 0.1 1 10 30 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v)
FDS86141 ? n-channel powertrench ? mosfet www.fairchildsemi.com 4 ? 2007 fairchild semiconductor corporation FDS86141 ? rev. c4 figure 7. gate charge characteristics figur e 8. capacitance vs. drain-to-source voltage figure 9. unclamped inductive switching capabili ty figure 10. maximum continuous drain current v s . a m b i e n t t e m p e r a t u r e figure 11. forward bias safe operating area fi gure 12. single-pulse maximum powe r dissipation typical characteristics t j = 25 c unless otherwise noted. 0 3 6 9 12 15 0 2 4 6 8 10 i d = 7 a v dd = 50 v v dd = 25 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 75 v 0.1 1 10 100 5 10 100 1000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss 0.01 0.1 1 10 50 1 10 20 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) 25 50 75 100 125 150 0 2 4 6 8 v gs = 6 v r ? ja = 50 o c/w v gs = 10 v i d , drain current (a) t a , ambient temperature ( o c ) 0.01 0.1 1 10 100 600 0.01 0.1 1 10 100 10 s 100us 10 ms dc 1 s 100 ms 1 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r ? ja = 125 o c/w t a = 25 o c 10 -3 10 -2 10 -1 110 100 1000 0.5 1 10 100 500 single pulse r ? ja = 125 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec)
FDS86141 ? n-channel powertrench ? mosfet www.fairchildsemi.com 5 ? 2007 fairchild semiconductor corporation FDS86141 ? rev. c4 figure 13. junction-to-ambient transient thermal response curve typical characteristics t j = 25 c unless otherwise noted. 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.0001 0.001 0.01 0.1 1 2 single pulse r ? ja = 125 o c/w duty cycle-descending order normalized thermal impedance, z ? ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z ? ja x r ? ja + t a
FDS86141 ? n-channel powertrench ? mosfet www.fairchildsemi.com 6 ? 2007 fairchild semiconductor corporation FDS86141 ? rev. c4 physical dimensions figure 1. 8-lead, small-outline integrated circuit (soic), jedec ms -012, .150" narrow body package drawings are provided as a service to customers considering fairchil d components. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild? s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern st andard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.40 (1.04) option a - bevel edge option b - no bevel edge 0.25 cba 0.10 c
www.fairchildsemi.com FDS86141 ? n-channel powertrench ? mosfet ? 2007 fairchild semiconductor corporation FDS86141 ? rev. c4 7
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