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january 2010 doc id 13365 rev 2 1/49 49 sta333w 2-channel high-efficien cy digital audio system sound terminal? features ? wide supply-voltage range (4.5 v - 20 v) ? 2 power output configurations ? 2 channels of binary pwm (stereo mode) ? 2 channels of ternary pwm (stereo mode) ? powersso-36 with exposed pad down ? 2 channels of 24-bit ddx ? ? 100-db snr and dynamic range ? selectable 32- to 192-k hz input sample rates ? i 2 c control with selectable device address ? digital gain -80 db to +48 db in 0.5-db steps ? software volume update ? individual channel and master gain/attenuation ? individual channel and master software and hardware mute ? independent channel volume bypass ? automatic zero-detect mute ? automatic invalid input detect mute ? 2-channel i 2 s input data interface ? selectable clock input ratio ? input channel mapping ? automatic volume contro l for limiting maximum power ? 96-khz internal processing sample rate, 24-bit precision ? advanced am interference frequency switching and noise suppression modes ? thermal-overload and short-circuit protection embedded ? video application: 576 * f s input mode support applications ? lcd ? dvd ? cradle ? digital speaker ? wireless-spea ker cradle description the sta333w is an integrated circuit comprising digital audio processing, digital amplifier control and ddx ? power output stage to create a high- power, single-chip ddx ? solution for all-digital amplification with high quality and high efficiency. the sta333w power section consists of four independent half-bridges stages. these can be configured via digital control to operate in different modes. 2 channels can be provided by two full bridges, providing up to 20 w + 20 w of power. also provided in the sta333w are new advanced am radio interference reduction modes. the serial audio data input interface accepts all possible formats, including the popular i 2 s format. three channels of ddx ? processing are provided. the sta333w is part of the sound terminal? family that provides full digital audio streaming to the speaker offering cost effectiveness, low power dissipation and sound enrichment. powersso-36 package with exposed pad down (epd) table 1. device summary order code package packaging sta333w powersso-36 epd tube sta333w13tr powersso-36 epd tape and reel www.st.com
contents sta333w 2/49 doc id 13365 rev 2 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 power-on/off sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 functional pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.1 power-down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.2 reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 serial audio interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2.1 serial audio interface protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5i 2 c bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.1 data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.2 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.3 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3.2 multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
sta333w contents doc id 13365 rev 2 3/49 5.4.1 current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.2 current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.3 random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.4 random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 configuration registers (addr 0x00 to 0x05) . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.1 configuration register a (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.2 configuration register b (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1.3 configuration register c (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.4 configuration register d (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1.5 configuration register e (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1.6 configuration register f (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2 volume control registers (addr 0x06 to 0x09) . . . . . . . . . . . . . . . . . . . . . . 32 6.2.1 mute/line output configuration register (addr 0x06) . . . . . . . . . . . . . . . . 32 6.2.2 master volume register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.3 channel volume (addr 0x08, 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3 automodes? register (0x0c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4 channel configuration registers (addr 0x0e, 0x0f) . . . . . . . . . . . . . . . . . 35 6.5 variable max power correction registers (addr 0x27, 0x28) . . . . . . . . . . . 35 6.6 variable distortion compensation registers (addr 0x29, 0x2a) . . . . . . . . . 36 6.7 fault detect recovery constant registers (addr 0x2b, 0x2c) . . . . . . . . . . 36 6.8 device status register (addr 0x2d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.9 reserved registers (addr 0x2e, 0x2f, 0x30, 0x31) . . . . . . . . . . . . . . . . . 37 6.10 postscale registers (addr 0x32, 0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.11 output limit register (addr 0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.11.1 thermal and overcurrent warning output limit register . . . . . . . . . . . . . 38 7 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1 applications scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2 pll filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.3 typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 characterization data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
contents sta333w 4/49 doc id 13365 rev 2 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11 trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 47 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
sta333w list of tables doc id 13365 rev 2 5/49 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. electrical characteristics for digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. electrical specifications for power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 table 8. register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9. master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. mcs bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11. interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. ir bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 13. thermal warning recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 14. thermal warning adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 15. fault detect recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 16. serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 17. serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 18. support serial audio input formats for msb first (saifb = 0) . . . . . . . . . . . . . . . . . . . . . . . 25 table 19. supported serial audio input formats for lsb-first (saifb = 1) . . . . . . . . . . . . . . . . . . . . . 26 table 20. channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 21. ddx power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 22. ddx compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 23. overcurrent warning detect adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 24. zero detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 25. max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 26. max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 27. noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 28. am mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 29. pwm speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 30. distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 31. zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 32. zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 33. invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 34. binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 35. lrck double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 36. auto eapd on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 37. power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 38. external amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 39. master mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 40. channel mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 41. master volume offset as a function of mv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 42. channel volume as a function of cxv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 table 43. am interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 44. automodes? am switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 45. status bits description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 46. output limit values for thermal and overcurrent warnings. . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 47. powersso-36 epd dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 48. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
list of figures sta333w 6/49 doc id 13365 rev 2 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. pin connection (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. power-off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. current dead-time test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. i 2 s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. left justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 9. write-mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. read-mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. applications diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 12. pll filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 13. output configuration for stereo btl mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 14. output power vs. supply voltage (thd = 1%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 15. fft 0 dbfs (v cc = 12 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 16. fft -60 dbfs (v cc = 12 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 17. thd vs. frequency (v cc = 12 v, po = 1 w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 18. fft 0 dbfs (v cc = 18 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 19. fft -60 dbfs (v cc = 18 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 20. thd vs. frequency (v cc = 18 v, po = 1 w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 21. double-layer pcb with two copper ground areas and 16 vias . . . . . . . . . . . . . . . . . . . . . . 44 figure 22. power derating curve for pcb used as heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 23. powersso-36 epd outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
sta333w block diagram doc id 13365 rev 2 7/49 1 block diagram figure 1. block diagram protection current/thermal logic regulators bias power control ddx pll volume control channel 1a channel 1b channel 2a channel 2b i 2 s interface power digital dsp i 2 c
pin description sta333w 8/49 doc id 13365 rev 2 2 pin description 2.1 pin out figure 2. pin connection (package top view) 2.2 pin list 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 vdd_dig gnd_dig scl sda int_line reset sdi lrcki bicki xti gnd_pll filter_pll vdd_pll pwrdn gnd_dig vdd_dig n.c. n.c. gnd_sub sa test_mode vss vcc_reg out2b gnd2 vcc2 out2a out1b vcc1 gnd1 out1a gnd_reg vdd_reg config n.c. n.c. d05au1638 ep exposed pad (down) connect to ground table 2. pin description number type name description 1 pwr gnd_sub substrate ground 2i sa i 2 c select address 3 i test_mode this pin must be connected to ground 4 i/o vss internal reference at v cc - 3.3 v 5 i/o vcc_reg internal v cc reference 6 o out2b output half bridge 2b 7 pwr gnd2 power negative supply 8 pwr vcc2 power positive supply 9 o out2a output half bridge 2a
sta333w pin description doc id 13365 rev 2 9/49 10 o out1b output half bridge 1b 11 pwr vcc1 power positive supply 12 pwr gnd1 power negative supply 13 o out1a output half bridge 1a 14 pwr gnd_reg internal ground reference 15 pwr vdd_reg internal 3.3-v reference voltage 16 i config paralleled mode command 17 - n.c. no internal connection 18 - n.c. no internal connection 19 - n.c. no internal connection 20 - n.c. no internal connection 21 pwr vdd_dig positive supply digital 22 pwr gnd_dig digital ground 23 i pwrdn power down: 0: power stage is switched off then the pll is also switched off (this operation take 13 million clock cycles) 1: normal operation 24 pwr vdd_pll positive supply for pll 25 i filter_pll connection to pll filter 26 pwr gnd_pll negative supply for pll 27 i xti pll input clock, 256 * f s , or 384 * f s 28 i bicki i 2 s serial clock 29 i lrcki i 2 s left/right clock 30 i sdi i 2 s serial data channel 31 i reset reset: 0: reset state, power stage is switched off, all registers are set to default value 1: normal operation 32 o int_line fault interrupt 33 i/o sda i 2 c serial data, used as sda_out 34 i scl i 2 c serial clock 35 pwr gnd_dig digital ground 36 pwr vdd_dig digital supply --ep exposed pad for ground-plane heatsink, to be connected to gnd table 2. pin description (continued) number type name description
pin description sta333w 10/49 doc id 13365 rev 2 2.3 thermal data table 3. thermal data symbol parameter min typ max unit r th(j-case) thermal resistance junction to case (thermal pad) - 1.5 2.0 c/w t sd thermal-shutdown junction temperature 140 150 160 c t w thermal-warning temperature - 130 - c t hsd thermal-shutdown hysteresis 18 20 22 c
sta333w electrical specification doc id 13365 rev 2 11/49 3 electrical specification 3.1 absolute maximum ratings warning: stresses beyond those listed in table 4: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in table 5: recommended operating conditions are not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. in the real application, a power supply with nominal value rated within the limits of the recommended operating conditions, may experience some rising beyond the maximum operating conditions for a short time when no or very low current is being sinked (amplifier in mute state). in this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded. 3.2 recommended operating conditions table 4. absolute maximum ratings symbol parameter min typ max unit v cc analog supply voltage (pins vccx) - - 23 v v dd digital supply voltage (pins vdd_dig) - - 4.0 v i l logic input interface -0.3 - 4.0 v t op operating junction temperature 0 - 150 c t stg storage temperature -40 - 150 c table 5. recommended operating conditions symbol parameter min typ max unit v cc analog supply voltage (vccx) 4.5 - 20.0 v v dd digital supply voltage (vdd_dig) 2.7 3.3 3.6 v i l logic input interface 2.7 3.3 3.6 v t amb ambient temperature 0 - 70 c
electrical specification sta333w 12/49 doc id 13365 rev 2 3.3 electrical specificat ions - digital section 3.4 electrical specific ations - power section the specifications in ta bl e 7 below are given for the conditions v cc = 18 v, v dd = 3.3 v, f sw = 384 khz, t amb = 25 c and r l = 8 ? , unless otherwise specified. table 6. electrical characteristics for digital section symbol parameter conditions min typ max unit i il input current, no pull-up or pull-down resistor v i = 0 v - - 10 a i ih v i = v dd = 3.6 v - - 10 a v il low-level input voltage - - - 0.2 * v dd v v ih high-level input voltage - 0.8 * v dd --v v ol low-level output voltage i ol = 2 ma - - 0.4 * v dd v v oh high-level output voltage i oh = 2 ma 0.8 * v dd --v i pu pull-up current - 25 66 125 a r pu equivalent pull-up resistance --50-k ? table 7. electrical specifications for power section symbol parameter conditions min typ max unit po output power btl thd = 1% - 16 - w thd = 10% - 20 - r dson power p-channel/n-channel mosfet (total bridge) ld = 1 a - 180 250 m ? l dss power p-channel/n-channel leakage v cc = 18 v --10 a gp power p-channel r dson matching ld = 1 a 95--% gn power n-channel r dson matching ld = 1 a 95--% i ldt low-current dead time (static) resistive load, refer to figure 5 - 5 10 ns i hdt high-current dead time (dynamic) refer to figure 6 - 1020ns t r rise time resistive load, refer to figure 5 - 8 10 ns t f fall time resistive load, refer to figure 5 - 8 10 ns
sta333w electrical specification doc id 13365 rev 2 13/49 v cc supply voltage - 4.5 - 20 v i vcc supply current from v cc in power down pwrdn = 0 30 60 200 a supply current from v cc in operation pcm input signal = -60 dbfs switching frequency = 384 khz no lc filters - 3050ma i vdd_dig supply current for ddx processing (reference only) internal clock = 49.152 mhz 10 30 50 ma supply current in standby - 8 11 25 ma i lim overcurrent limit non-linear output (1) 2.23.54.3a i scp short-circuit protecti on high-impedance output (2) 2.73.85.0a v uvp undervoltage protection threshold - - 3.5 4.3 v t min output minimum pulse width no load 20 30 60 ns thd+n total harmonic distortion and noise dxx stereo mode, po = 1 w, f = 1 khz - 0.05 0.2 % dr dynamic range - - 100 - db snr signal to noise ratio in ternary mode a-weighted - 100 - db signal to noise ratio in binary mode a-weighted - 90 - psrr power supply rejection ratio dxx stereo mode, < 5 khz, v ripple = 1 v rms audio input = dither only -80-db x ta l k crosstalk dxx stereo mode, < 5 khz, one channel driven at 1 w the other channel measured -80-db peak efficiency in dxx mode po = 2 x 20 w into 8 ? -90-% 1. the i lim data is for 1 channel of btl configuration, thus, 2 * i lim drives the 2-channel btl configuration. the current limit is active when ocrb = 0 (see table 23: overcurrent warning detect adjustment bypass on page 28 . when ocrb = 1 then i sc applies. 2. the i scp current limit data is for 1 channel of btl configuration, thus, 2 * i scp drives the 2-channel btl configuration. the short-circuit curr ent is applicable when ocrb = 1 (see table 23: overcurrent warning detect adjustment bypass on page 28 . table 7. electrical specifications for power section (continued) symbol parameter conditions min typ max unit
electrical specification sta333w 14/49 doc id 13365 rev 2 3.5 power-on/off sequences the power-on/off sequences shown in figure 3 and figure 4 below ensure a pop-free turn on and turn off. figure 3. power-on sequence figure 4. power-off sequence don?t care vcc vdd_dig xti reset tr don?t care don?t care pwrdn soft eapd reg. 0x05 bit 7 = 1 tc don?t care vcc vdd_dig xti reset tr don?t care don?t care pwrdn soft eapd reg. 0x05 bit 7 = 1 tc tr = mimimum time between xti master clock stable and reset removal: 1 ms tc = minimum time between reset removal and i 2 c program sequence start: 1 ms no specific vcc and vdd_dig turn-on sequence is required clock stable means: fmax - fmin < 1 mhz vcc vdd_dig xti reset pwrdn bit eapd register 0x05 don?t care vcc vdd_dig xti don?t care soft mute reg. 0x07 data 0xfe soft eapd reg. 0x05 bit 7 = 0 don?t care fe don?t care don?t care don?t care vcc vdd_dig xti don?t care soft mute reg. 0x07 data 0xfe soft eapd reg. 0x05 bit 7 = 0 don?t care fe don?t care don?t care no specific vcc and vdd_dig turn-off sequence is required vcc vdd_dig xti mute bit eapd register 0x05 register 0x07
sta333w electrical specification doc id 13365 rev 2 15/49 3.6 testing figure 5. test circuit figure 6. current dead-time test circuit low current dead time = max(dtr,dtf) outxy vcc (3/4)vcc (1/2)vcc (1/4)vcc t dtf dtr duty cycle = 50% inxy outxy gnd +vcc m58 m57 r 8 ? + - v67 = vdc = vcc/2 d03au1458 high current dead time for bridge application = abs(dtout(a)-dtin(a))+abs(dtout(b)-dtin(b)) +v cc rload=8 ? q2 outb dtout(b) dtin(b) dtout(a) c71 470nf c70 470nf c69 470nf iout=4a iout=4a q4 q1 q3 m64 inb m63 d03au1517 m58 ina m57 dtin(a) duty cycle=a duty cycle=b duty cycle a and b: fixed to have dc output current of 4a in the direction shown in figure l68 22 l67 22 outa lout = 1.5 a lout = 1.5 a
functional description sta333w 16/49 doc id 13365 rev 2 4 functional description 4.1 functional pins 4.1.1 power-down function pin pwrdn (23) is used to power down the sta333w. pwrdn = 0 (0 v): power-down state. pwrnd = 1 (v dd ): normal operation. during the power-down sequence the output begins to mute. after the mute condition is reached the power stage is switched off and the output becomes high impedance. then the master clock to all internal hardware blocks is gated off. the pll is also switched off. the complete power-down sequen ce takes 13 million cycles. 4.1.2 reset function pin reset (31) is used to reset the sta333w. reset = 0 (0 v): reset state. reset = 1 (v dd ): normal operation. when pin reset is forced to 0 the power st age is switched off (with high-impedance output) and the master clock to all internal hardware blocks is gated off. note: reset has a higher priority than power down.
sta333w functional description doc id 13365 rev 2 17/49 4.2 serial audio interface description 4.2.1 serial audio interface protocols the sta333w serial audio input was designed to interface with standard digital audio components and to accept serial data formats. the sta333w always acts as a slave when receiving audio input from standard digital audio components. serial data for two channels is provided using 3 input pins: left/right clock lrcki (pin 29), serial clock bicki (pin 28), and serial data sdi (pin 30). the available formats are showed in ta b l e 7 and ta b l e 8 , and set through register confb on page 24 . figure 7. i 2 s figure 8. left justified 1 n n -1 2 3 bicki sdi lrclki n n -1 n n -1 3 2 1 3 2 1 1 n n -1 n n -1 2 3 sdi bicki lrclki 1 2 3
i 2 c bus specification sta333w 18/49 doc id 13365 rev 2 5 i 2 c bus specification the sta333w supports the i 2 c protocol via the input ports scl and sda. this protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. the device that controls the data transfer is known as the master and the other as the slave. the master always starts the transfer and provides the serial clock for synchronization. the sta333w is always a slave device in all of its communications. it supports up to 400 kb/s (fast-mode bit rate). 5.1 communication protocol 5.1.1 data transition or change data changes on the sda line must only occur when the scl clock is low. sda transition while the clock is high is used to identify a start or stop condition. 5.1.2 start condition start is identified by a high to low transition of the data bus sda signal while the clock signal scl is stable in the high state. a start condition must precede any command for data transfer. 5.1.3 stop condition stop is identified by low to high transition of the data bus sda signal while the clock signal scl is stable in the high state. a stop condition terminates communication between sta333w and the bus master. 5.1.4 data input during the data input the sta333w samples the sda signal on the rising edge of clock scl. for correct device operation the sda signal must be stable during the rising edge of the clock and the data can change only when the scl line is low. 5.2 device addressing to start communication between the master and the sta333w, the master must initiate a start condition. following this, the master sends onto the sda line 8 bits (msb first) corresponding to the device-select address and read or write mode. the 7 most significant bits are the device address identifiers, corresponding to the i 2 c bus definition. in the sta333w the i 2 c interface has two device addresses depending on the sa port configuration, 0x38 when sa = 0, and 0x3a when sa = 1. the 8th bit (lsb) identifies read or write operation rw, this bit is set to 1 for read mode and 0 for write mode. after a start condition the sta333w identifies the device address on the sda bus and if a match is found, acknowledges the identification during the 9th bit time. the byte following the device identification byte is the internal space address.
sta333w i 2 c bus specification doc id 13365 rev 2 19/49 5.3 write operation following the start condition the master sends a device select code with the rw bit set to 0. the sta333w acknowledges this and then waits for the byte of internal address. after receiving the internal byte address the sta333w again responds with an acknowledgement. 5.3.1 byte write in the byte write mode the master sends one data byte, this is acknowledged by the sta333w. the master then terminates the transfer by generating a stop condition. 5.3.2 multi-byte write the multi-byte write modes can start from any internal address. the master generating a stop condition terminates the transfer. figure 9. write-mode sequence 5.4 read operation 5.4.1 current address byte read following the start condition the master sends a device select code with the rw bit set to 1. the sta333w acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. 5.4.2 current address multi-byte read the multi-byte read modes can start from any internal address. sequential data bytes are read from sequential addresses within the sta333w. the master acknowledges each data byte read and then generates a stop condition terminating the transfer. 5.4.3 random ad dress byte read following the start condition the master sends a device select code with the rw bit set to 0. the sta333w acknowledges this and then the master writes the internal address byte. after receiving, the internal byte address the sta333w again responds with an acknowledgement. the master then initiates another start condition and sends the device select code with the rw bit set to 1. the sta333w acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. dev-addr ack start rw sub-addr ack data in ack stop byte write dev-addr ack start rw sub-addr ack data in ack stop multibyte write data in ack
i 2 c bus specification sta333w 20/49 doc id 13365 rev 2 5.4.4 random address multi-byte read the multi-byte read modes could start from any internal address. sequential data bytes are read from sequential addresses within the sta333w. the master acknowledges each data byte read and then generates a stop condition to terminate the transfer. figure 10. read-mode sequence dev-addr ack start rw data no ack stop current address read dev-addr ack start rw sub-addr ack dev-addr ack stop random address read data no ack start rw dev-addr ack start data ack data ack stop sequential current read data no ack dev-addr ack start rw sub-addr ack dev-addr ack sequential random read data ack start rw data ack no ack stop data rw= high
sta333w register description doc id 13365 rev 2 21/49 6 register description table 8. register summary addr name d7 d6 d5 d4 d3 d2 d1 d0 0x00 confa fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 0x01 confb c2im c1im reserved saifb sai3 sai2 sai1 sai0 0x02 confc ocrb reserved csz3 csz2 csz1 csz0 om1 om0 0x03 confd reserved zde reserved 0x04 confe sve zce dccv pwms ame nsbw mpc mpcv 0x05 conff eapd pwdn ecle ldte bcle ide reserved 0x06 mute reserved c2m c1m mmute 0x07 mvol mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 0x08 c1vol c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 0x09 c2vol c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 0x0c auto reserved amam2 amam1 amam0 amame 0x0e c1cfg reserved c1vbp reserved 0x0f c2cfg reserved c2vbp reserved 0x27 mpcc1 mpcc15 mpcc14 mpcc13 mpcc1 2 mpcc11 mpcc10 mpcc9 mpcc8 0x28 mpcc2 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 0x29 dcc1 dcc15 dcc14 dcc13 dcc12 dcc11 dcc10 dcc9 dcc8 0x2a dcc2 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 dcc0 0x2b fdrc1 fdrc15 fdrc14 fdrc13 fdrc12 fdrc11 fdrc10 fdrc9 fdrc8 0x2c fdrc2 fdrc7 fdrc6 fdrc5 fdrc4 fdrc3 fdrc2 fdrc1 fdrc0 0x2d status pllul fault uvfault reserved ocfault ocwarn tfault twarn 0x2e bist1 reserved ro1bact r5bact r4bact r3bact r2bact r1bact 0x2f bist2 reserved r01bend r5bend r4bend r3bend r2bend r1bend 0x30 bist3 reserved r5bbad r4bbad r3bbad r1bbad r1bbad 0x31 tstctl reserved 0x32 c1ps c1ps7 c1ps6 c1ps5 c1ps4 c1ps3 c1ps2 c1ps1 c1ps0 0x33 c2ps c2ps7 c2ps6 c2ps5 c2ps4 c2ps3 c2ps2 c2ps1 c2ps0 0x34 olim olim7 olim6 olim5 olim4 olim3 olim2 olim1 olim0
register description sta333w 22/49 doc id 13365 rev 2 6.1 configuration registers (addr 0x00 to 0x05) 6.1.1 configuration register a (addr 0x00) master clock select the sta333w supports sample rates of 32 kh z, 44.1 khz, 48 khz, 88.2 khz, 96 khz, 176.4 khz, and 192 khz. therefore the internal clock is: z 32.768 mhz for 32 khz z 45.1584 mhz for 44.1 khz, 88.2 khz, and 176.4 khz z 49.152 mhz for 48 khz, 96 khz, and 192 khz the external clock frequency provided to the xti pin must be a multiple of the input sample frequency (f s ). the relationship between the input clock and the input sample rate is determined by both the mcsx and the ir (input rate) register bits. the mcsx bits determine the pll factor generating the internal clock and the ir bit determines the oversampling ratio used internally. d7 d6 d5 d4 d3 d2 d1 d0 fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 01100011 table 9. master clock select bit r/w rst name description 0r/w1mcs0 master clock select: sele cts the ratio between the input i 2 s sample frequency and the input clock. 1r/w1mcs1 2r/w0mcs2 table 10. mcs bits input sample rate f s (khz) ir mcs[2:0] 101 100 011 010 001 000 32, 44.1, 48 00 576 * f s 128 * f s 256 * f s 384 * f s 512 * f s 768 * f s 88.2, 96 01 na 64 * f s 128 * f s 192 * f s 256 * f s 384 * f s 176.4, 192 1x na 32 * f s 64 * f s 96 * f s 128 * f s 192 * f s
sta333w register description doc id 13365 rev 2 23/49 interpolation ratio select the sta333w has variable interpolation (oversampling) settings such that internal processing and ddx output rates remain consis tent. the first processing block interpolates by either 2 times or 1 time (pass-through) or provides a 2-times downsample. the oversampling ratio of this interpolation is determined by the ir bits. thermal warning recovery bypass if the thermal warning adjustment is enabled (twab = 0), then the thermal warning recovery determines if the -3 db output limit is removed when thermal warning is negative. if twrb = 0 and twab = 0, then when a thermal warning disappears the -3 db output limit is removed and the gain is added back to the system. if twrb = 1 and twab = 0, then when a thermal warning disappears the -3 db output limit remains until twrb is changed to zero or the device is reset. table 11. interpolation ratio select bit r/w rst name description 4:3 r/w 00 ir [1:0] interpolation ratio select: selects internal interpolation ratio based on input i 2 s sample frequency. table 12. ir bit settings as a function of input sample rate input sample rate f s (khz) ir 1 st stage interpolation ratio 32 00 2-times oversampling 44.1 00 2-times oversampling 48 00 2-times oversampling 88.2 01 pass-through 96 01 pass-through 176.2 10 2-times downsampling 192 10 2-times downsampling table 13. thermal warning recovery bit r/w rst name description 5r/w1twrb thermal warning recovery bypass: 0: thermal warning recovery enabled 1: thermal warning recovery disabled
register description sta333w 24/49 doc id 13365 rev 2 thermal warning adjustment bypass the on-chip sta333w power output block provides feedback to the digital controller using inputs to the power control block. the twarn input is used to indicate a thermal warning condition. when twarn is asserted (set to 0) for a period of time greater than 400 ms, the power control block will force a -3db output limit (determined by twocl in coefficient ram) to the modulation limit in an attempt to eliminate the thermal warning condition. once the thermal warning output limit adju stment is applied, it remains in this state until reset, unless fdrb = 0. fault detect recovery bypass the on-chip sta333w power output block provides feedback to the digital controller using inputs to the power control block. the fault input is used to indicate a fault condition (either overcurrent or thermal). when fault is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the 3-state output (setting it to 0 which directs the power output block to begin recovery), holding it at 0 for period of time in the range of 0.1 ms to 1 second as defined by the fault detect recovery constant register (fdrc registers 0x2b, 0x2c), then toggling it back to 1. this sequence is repeated as log as the fault indication exists. this feature is enabled by default but can be bypassed by setting the fdrb control bit to 1. 6.1.2 configuration register b (addr 0x01) table 14. thermal warning adjustment bit r/w rst name description 6r/w1twab thermal warning adjustment bypass: 0: thermal warning adjustment enabled 1: thermal warning adjustment disabled table 15. fault detect recovery bit r/w rst name description 7r/w0fdrb fault detect recovery bypass: 0: fault detect recovery enabled 1: fault detect recovery disabled d7 d6 d5 d4 d3 d2 d1 d0 c2im c1im reserved saifb sai3 sai2 sai1 sai0 10000000
sta333w register description doc id 13365 rev 2 25/49 serial audio input interface format serial data interface the sta333w audio serial input interfaces with standard digital audio components and accepts a number of serial data formats. sta333w always acts a slave when receiving audio input from standard digital audio components. serial data for two channels is provided using three inputs: left/right clock lrcki, serial clock bicki, and serial data sdi. bits sai and bit saifb are used to specify the serial data format. the default serial data format is i 2 s, msb first. available formats are shown in the tables and figure that follow. serial data first bit table 16. serial audio input interface format bit r/w rst name description 0r/w0sai0 determines the interface format of the input serial digital audio interface. 1r/w0sai1 2r/w0sai2 3r/w0sai3 table 17. serial data first bit saifb format 0 msb-first 1 lsb-first table 18. support serial audio input formats for msb first (saifb = 0) bicki sai [3:0] saifb interface format 32 * f s 0000 0 i 2 s 15-bit data 0001 0 left/right justified 16-bit data 48* f s 0000 0 i 2 s 16- to 23-bit data 0001 0 left justified 16- to 24-bit data 0010 0 right justified 24-bit data 0110 0 right justified 20-bit data 1010 0 right justified 18-bit data 1110 0 right justified 16-bit data
register description sta333w 26/49 doc id 13365 rev 2 64* f s 0000 0 i 2 s 16- to 24-bit data 0001 0 left justified 16- to 24-bit data 0010 0 right justified 24-bit data 0110 0 right justified 20-bit data 1010 0 right justified 18-bit data 1110 0 right justified 16-bit data table 19. supported serial audio input forma ts for lsb-first (saifb = 1) bicki sai[3:0] saifb interface format 32* f s 1100 1 i 2 s 15-bit data 1110 1 left/right justified 16-bit data 48* f s 0100 1 i 2 s 23-bit data 0100 1 i 2 s 20-bit data 1000 1 i 2 s 18-bit data 1100 1 lsb first i 2 s 16-bit data 0001 1 left justified 24-bit data 0101 1 left justified 20-bit data 1001 1 left justified 18-bit data 1101 1 left justified 16-bit data 0010 1 right justified 24-bit data 48* f s 0110 1 right justified 20-bit data 1010 1 right justified 18-bit data 1110 1 right justified 16-bit data 64* f s 0000 1 i 2 s 24-bit data 0100 1 i 2 s 20-bit data 1000 1 i 2 s 18-bit data 1100 1 lsb first i 2 s 16-bit data 0001 1 left justified 24-bit data 0101 1 left justified 20-bit data 1001 1 left justified 18-bit data 1101 1 left justified 16-bit data 0010 1 right justified 24-bit data 0110 1 right justified 20-bit data 1010 1 right justified 18-bit data 1110 1 right justified 16-bit data table 18. support serial audio input formats for msb first (saifb = 0) (continued)
sta333w register description doc id 13365 rev 2 27/49 channel input mapping each channel received via i 2 s can be mapped to any internal processing channel via the channel input mapping regi sters. this allows for flexibility in processing. the default settings of these registers map each i 2 s input channel to its corresponding processing channel. 6.1.3 configuration register c (addr 0x02) ddx power output mode ddx compensation pulse size register table 20. channel input mapping bit r/w rst name description 6r/w0c1im 0: processing channel 1 receives left i 2 s input 1: processing channel 1 receives right i 2 s input 7r/w0c2im 0: processing channel 2 receives left i 2 s input 1: processing channel 2 receives right i 2 s input d7 d6 d5 d4 d3 d2 d1 d0 ocrb reserved csz3 csz2 csz1 csz0 om1 om0 10010111 table 21. ddx power output mode bit r/w rst name description 0 r/w 1 om0 the ddx power output mode selects the configuration of the ddx output: 00: drop compensation 01: discrete output stage: tapered compensation 10: full-power mode 11: variable drop compensation (cszx bits) 1r/w1om1 table 22. ddx compensating pulse size bit r/w rst name description 2 r/w 1 csz0 when om[1:0] = 11, this register determines the size of the ddx compensating pulse from 0 to 15 clock periods: 0000: 0 ns (0 ticks) compensating pulse size 0001: 20 ns (1 tick) clock period compensating pulse size ..... 1111: 300 ns (15 ticks) clock period compensating pulse size 3r/w0csz1 4r/w1csz2 5r/w0csz3
register description sta333w 28/49 doc id 13365 rev 2 overcurrent warning detect adjustment bypass the status bit ocwarn is used to warn of an overcurrent condition. when ocwarn is asserted (set to 0), the power control block forces an adjustment to the modulation limit (default -3db) in an attempt to eliminate the overcurrent warning condition. once the overcurrent warning volume adjustment is applied, it remains applied until the device is reset. the overcurrent limit can be changed via register olim ( output limit register (addr 0x34) on page 38 ). 6.1.4 configuration register d (addr 0x03) zero-detect mute enable setting the zde bit enables the zero-detect automatic mute. the zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. if any channel receives 2048 consecutive zero value samples (regardless of f s ) then that individual channel is muted if this function is enabled. 6.1.5 configuration r egister e (addr 0x04) max power correction variable table 23. overcurrent warning detect adjustment bypass bit r/w rst name description 7r/w1ocrb 0: overcurrent warning adjustment enabled 1: overcurrent warning adjustment disabled d7 d6 d5 d4 d3 d2 d1 d0 reserved zde reserved 01000000 table 24. zero detect mute enable bit r/w rst name description 6 r/w 1 zde 1: enable the automatic zero-detect mute d7 d6 d5 d4 d3 d2 d1 d0 sve zce dccv pwms ame nsbw mpc mpcv 11000010 table 25. max power correction variable bit r/w rst name description 0r/w0mpcv 0: use standard mpc coefficient 1: use mpcc bits for mpc coefficient
sta333w register description doc id 13365 rev 2 29/49 max power correction setting the mpc bit turns on special processing that corrects the sta333w power device at high power. this mode lowers the thd+n of a full ddx system at maximum power output and slightly below. if enabled, mpc is operational in all output modes except tapered (om[1:0] = 01) and binary. when ocfg = 00, mpc does not affect channels 3 and 4, the line-out channels. noise-shaper bandwidth selection am mode enable the sta333w features a ddx processing mode that minimizes the amount of noise generated in frequency range of am radio. this mode is intended for use when ddx is operating in a device with an am tuner active. the snr of the ddx processing is reduced to approximately 83 db in this mode, which is still greater than the snr of am radio. pwm speed mode distortion compensation variable enable table 26. max power correction bit r/w rst name description 1r/w1mpc 1: enable power bridge correction for thd reduction near maximum power output. table 27. noise-shaper bandwidth selection bit r/w rst name description 2r/w0nsbw 1: 3 rd order ns 0: 4 th order ns table 28. am mode enable bit r/w rst name description 3r/w0ame 0: normal ddx operation 1: am reduction mode ddx operation table 29. pwm speed mode bit r/w rst name description 4r/w0pwms 0: normal speed (384 khz) all channels 1: odd speed (341.3 khz) all channels table 30. distortion compensation variable enable bit r/w rst name description 5 r/w 0 dccv 0: uses preset dc coefficient. 1: uses dcc coefficient.
register description sta333w 30/49 doc id 13365 rev 2 zero-crossing volume enable the zce bit enables zero-crossing volume adjustments. when volume is adjusted on digital zero-crossings no clicks will be audible. soft volume update enable 6.1.6 configuration re gister f (addr 0x05) invalid input detect mute enable setting the ide bit enables this function, which looks at the input i 2 s data and will automatically mute if the signals are perceived as invalid. binary output mode clock loss detection detects loss of input mclk in binary mode and outputs 50% of the duty cycle. table 31. zero-crossing volume enable bit r/w rst name description 6r/w1zce 1: volume adjustments will only occur at digital zero-crossings 0: volume adjustments will occur immediately table 32. zero-crossing volume enable bit r/w rst name description 7r/w1sve 1: volume adjustments ramp according to svr settings 0: volume adjustments will occur immediately d7 d6 d5 d4 d3 d2 d1 d0 eapd pwdn ecle ldte bcle ide reserved 0101110 0 table 33. invalid input detect mute enable bit r/w rst name description 2 r/w 1 ide 1: enables the automatic invalid input detect mute table 34. binary output mode clock loss detection bit r/w rst name description 3 r/w 1 bcle binary output mode clock loss detection enable
sta333w register description doc id 13365 rev 2 31/49 lrck double trigger protection actively prevents double trigger of lrclk. auto eapd on clock loss when active will issue a power device power-do wn signal (eapd) on clock loss detection. ic power down the pwdn register is used to put the ic in a low-power state. when pwdn is 0, the output begins a soft-mute. after the mute condition is reached, eapd is asserted to power down the power stage, then the master clock to all internal hardware except the i 2 c block is gated. this puts the ic in a very low power consumption state. external amplifier power down the eapd register directly disables/enables the internal power circuitry. when eapd = 0, the internal power section is placed in a low-power state (disabled). table 35. lrck double trigger protection bit r/w rst name description 4 r/w 1 ldte lrclk double trigger protection enable table 36. auto eapd on clock loss bit r/w rst name description 5 r/w 0 ecle auto eapd on clock loss table 37. power down bit r/w rst name description 6r/w1pwdn 0: power down, low-power condition 1: normal operation table 38. external amplifier power down bit r/w rst name description 7 r/w 1 eapd 0: external power stage power down active 1: normal operation
register description sta333w 32/49 doc id 13365 rev 2 6.2 volume control regi sters (addr 0x06 to 0x09) 6.2.1 mute/line output confi guration register (addr 0x06) master mute channel mute d7 d6 d5 d4 d3 d2 d1 d0 reserved c2m c1m mmute 00000000 table 39. master mute bit r/w rst name description 0r/w0mmute 0: normal operation 1: all channels are in mute condition table 40. channel mute bit r/w rst name description 1r/w0c1m channel 1 mute: 0: not muted, it is possibl e to set the channel volume 1: hardware muted 2r/w0c2m channel 2 mute: 0: not muted, it is possibl e to set the channel volume 1: hardware muted
sta333w register description doc id 13365 rev 2 33/49 6.2.2 master volume register (addr 0x07) 6.2.3 channel volume (addr 0x08, 0x09) volume setting the volume structure of the sta333w consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. the individual channel volumes are adjustable in 0.5-db steps from +48 db to -80 db. as an example if c3v = 0x00 or +48 db and mv = 0x18 or -12 db, then the total gain for channel 3 = +36 db. the master mute when set to 1 will mute all channels at once, whereas the individual channel mutes (cxm) mute only that channel. both the master mute and the channel mutes provide a ?soft mute? with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (about 96 khz). a hard mute can be obtained by commanding a value of all 1?s (255) to any channel volume register or the master volume register. when volume offsets are provided via the master volume register any channel that whose total volume is less than -80 db is muted. all changes in volume take place at zero-crossings when zce = 1 (configuration register f) on a per channel basis as this creates the smoothest possible volume transitions. when zce = 0, volume updates will occur immediately. d7 d6 d5 d4 d3 d2 d1 d0 mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 11111111 d7 d6 d5 d4 d3 d2 d1 d0 c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 01100000 table 41. master volume offset as a function of mv mv[7:0] volume offset from channel value 00000000 (0x00) 0 db 00000001 (0x01) -0.5 db 00000010 (0x02) -1 db ?? 01001100 (0x4c) -38 db ?? 11111110 (0xfe) -127.5 db 11111111 (0xff) hard master mute
register description sta333w 34/49 doc id 13365 rev 2 6.3 automodes? register (0x0c) am interference frequency switching amam bits table 42. channel volume as a function of cxv cxv[7:0] volume 00000000 (0x00) +48 db 00000001 (0x01) +47.5 db 00000010 (0x02) +47 db ?? 01011111 (0x5f) +0.5 db 01100000 (0x60) 0 db 01100001 (0x61) -0.5 db ?? 11010111 (0xd7) -59.5 db 11011000 (0xd8) -60 db 11011001 (0xd9) -61 db 11011010 (0xda) -62 db ?? 11101100 (0xec) -80 db 11101101 (0xed) hard channel mute ?? 11111111 (0xff) hard channel mute d7 d6 d5 d4 d3 d2 d1 d0 reserved amam2 amam1 amam0 amame 00000000 table 43. am interference frequency switching bit r/w rst name description 0r/w0amame 0: switching frequency determined by pwms setting 1: switching frequency determined by amam setting table 44. automodes? am switching frequency selection amam[2:0] 48 khz / 96 khz input f s 44.1 khz / 88.2 khz input f s 000 0.535 mhz - 0.720 mhz 0.535 mhz - 0.670 mhz 001 0.721 mhz - 0.900 mhz 0.671 mhz - 0.800 mhz
sta333w register description doc id 13365 rev 2 35/49 6.4 channel configuration re gisters (addr 0x0e, 0x0f) volume bypass each channel contains an individual channel volume bypass. if a particular channel has volume bypassed via the cxvbp = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volu me setting will not affect that channel. 6.5 variable max power correction registers (addr 0x27, 0x28) mpcc bits determine the 16 msbs of the mpc compensation coefficient. this coefficient is used in place of the default coefficient when mpcv = 1. 010 0.901 mhz - 1.100 mhz 0.801 mhz - 1.000 mhz 011 1.101 mhz - 1.300 mhz 1.001 mhz - 1.180 mhz 100 1.301 mhz - 1.480 mhz 1.181 mhz - 1.340 mhz 101 1.481 mhz - 1.600 mhz 1.341 mhz - 1.500 mhz 110 1.601 mhz - 1.700 mhz 1.501 mhz - 1.700 mhz table 44. automodes? am switching frequency selection d7 d6 d5 d4 d3 d2 d1 d0 reserved c1vbp reserved 00000000 d7 d6 d5 d4 d3 d2 d1 d0 reserved c2vbp reserved 00000000 d7 d6 d5 d4 d3 d2 d1 d0 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 00011010 d7 d6 d5 d4 d3 d2 d1 d0 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 11000000
register description sta333w 36/49 doc id 13365 rev 2 6.6 variable distortion compensa tion registers (addr 0x29, 0x2a) dcc bits determine the 16 msbs of the distor tion compensation coefficient. this coefficient is used in place of the default coefficient when dccv = 1. 6.7 fault detect recovery constant registers (addr 0x2b, 0x2c) fdrc bits specify the 16-bit faul t detect recovery time delay. when status register bit fault is asserted, the tristate output is immediately asserted low and held low for the time period specified by this constant. a value of 0x0001 in this register is approximately 0.083 ms. the default value of 0x000c gives approximately 0.1 ms. note: 0x0000 is a reserved value for this register pair. this value must not be used. 6.8 device status register (addr 0x2d) this read-only register provides the fault, warning and pll status from the power control block. d7 d6 d5 d4 d3 d2 d1 d0 dcc15 dcc14 dcc13 dcc12 dcc11 dcc10 dcc9 dcc8 11110011 d7 d6 d5 d4 d3 d2 d1 d0 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 dcc0 00110011 d7 d6 d5 d4 d3 d2 d1 d0 fdrc15 fdrc14 fdrc13 fdrc12 fdrc11 fdrc10 fdrc9 fdrc8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 fdrc7 fdrc6 fdrc5 fdrc4 fdrc3 fdrc2 fdrc1 fdrc0 00001100 d7 d6 d5 d4 d3 d2 d1 d0 pllul fault uvfault reserved ocfault ocwarn tfault twarn table 45. status bits description bit r/w rst name description 0ro- twarn thermal warning: 0: junction temperature is close to the fault condition 1: normal operation 1ro- tfault thermal fault: 0: junction temperature limit detection 1: normal operation
sta333w register description doc id 13365 rev 2 37/49 6.9 reserved registers (a ddr 0x2e, 0x2f, 0x30, 0x31) these registers are not to be used. 6.10 postscale registers (addr 0x32, 0x33) postscale the sta333w provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel, which can be used to limit the maximum modulation index and therefore the peak current through the power device. the register values represent an 8-bit signed fractional number. this number is extended to a 24-bit number, by adding zeros to the right, and then directly multiplied by the data on that channel. an independent postscale is provided for each channel but all channels can use channel 1 postscale factor by setting the postscale link bit. by default, all postscale factors are set to 0x7f (pass-through). 2ro- ocwarn overcurrent warning: 0: warning 1: normal operation 3ro- ocfault overcurrent fault: 0: fault detected 1: normal operation 4--- reserved 5 ro - uvfault undervoltage warning: 0: vccx below lower voltage threshold 1: normal operation 6ro- fault power bridge fault: 0: fault detected 1: normal operation 7 ro - pllul pll lock: 0: locked 1: not locked table 45. status bits description (continued) bit r/w rst name description d7 d6 d5 d4 d3 d2 d1 d0 c1ps7 c1ps6 c1ps5 c1ps4 c1ps3 c1ps2 c1ps1 c1ps0 01111111 d7 d6 d5 d4 d3 d2 d1 d0 c2ps7 c2ps6 c2ps5 c2ps4 c2ps3 c2ps2 c2ps1 c2ps0 01111111
register description sta333w 38/49 doc id 13365 rev 2 6.11 output limit register (addr 0x34) 6.11.1 thermal and overcurrent wa rning output limit register the sta333w provides a simple mechanism for reacting to a thermal or overcurrent warning in the power device. when the twarn or ocwarn status bit is asserted, the output is limited to the olim setting. the limit can be adjusted by modifying the thermal warning/overcurrent output limit value. as for the normal postscale, the register value represents an 8-bit signed fractional number. this number is extended to a 24-bit number, by adding zeros to the right, and then directly multiplied by the data on both channels. the scaling value range is from 0x80 = -1 to 0x7f = 0.992. to avoid phase changes in the output signal only the positive range is used (0x00 to 0x7f). the default setting of 0x5a provides a -3-db limit. if the cause of the limiting is a thermal warnin g, the output limiting is removed when the thermal warning situation disappears. if the cause of the limiting is an overcurrent warning, output limiting remains in effe ct until the device is reset. d7 d6 d5 d4 d3 d2 d1 d0 olim7 olim6 olim5 olim4 olim3 olim2 olim1 olim0 01011010 table 46. output limit values for thermal and overcurrent warnings olim[7:0] attenuation (db) 0x7f 0.06 0x7e 0.13 .... .... 0x5a 3.0 .... .... 0x40 6.0 .... .... 0x28 10 .... .... 0x01 42 0x00 inf
sta333w applications information doc id 13365 rev 2 39/49 7 applications information 7.1 applications scheme for power supplies figure 11 below shows a typical applications scheme for sta333w. special care has to be taken with regard to the power supplies when laying out the pcb. in particular the 3.3- ? resistors on the digital supplies (vdd_dig) have to be placed as close as possible to the device. this prevents unwa nted oscillation on the digital parts of the device due to the inductive effects of the pcb tracks. the same rule also applies to all the decoulpling capacitors; they should be placed as close as possible to the device in order to limit the effect of spikes on the supplies. figure 11. applications diagram 7.2 pll filter it is recommended to use the circuit in figure 12 below for the pll loop filter to achieve the best performance from the device in general applications. note that the ground of this filter has to be connected to the ground of the pll without any resistive path. for the component values, it should be remembered that the greater the filter bandwidth, the shorter the lock time but the higher the pll output jitter. 9 8 100nf + 1000uf 35v 1nf scl sda reset vcc reset 100nf 3v3 1uf 35v 100nf 100nf 1uf 35v intl 100nf 100nf 3v3 3v3 3r3 3r3 lrcki pwdn 3v3 out2b xti bicki out2a gnd_sub 1 sa 2 test_mode 3 vss 4 vcc_reg 5 out2b 6 gnd2 7 vcc2 out2a out1b 10 vcc1 11 gnd1 12 out1a 13 gnd_reg 14 vdd 15 config 16 nc 17 nc 18 nc 19 nc 20 vdd_dig 21 gnd_dig 22 pwrdn 23 vdd_pll 24 filter_pll 25 pll_gnd 26 xti 27 bicki 28 lrcki 29 sdi 30 reset 31 int_line 32 sda 33 scl 34 gnd_dig 35 vdd_dig 36 out1b data pll_filt out1a 10k 100nf 1nf scl sda reset reset 100nf 100nf out2a lrcki pwdn 3v3 out2b xti bicki data pll_filt bead bead bead pll_gnd gnd_dig gnd_dig gnd_dig gnd_dig 9 8 100nf + 1000uf 35v 1nf scl sda reset vcc reset 100nf 3v3 1uf 35v 100nf 100nf 1uf 35v intl 100nf 100nf 3v3 3v3 3r3 3r3 lrcki pwdn 3v3 out2b xti bicki out2a gnd_sub 1 sa 2 test_mode 3 vss 4 vcc_reg 5 out2b 6 gnd2 7 vcc2 out2a out1b 10 vcc1 11 gnd1 12 out1a 13 gnd_reg 14 vdd 15 config 16 nc 17 nc 18 nc 19 nc 20 vdd_dig 21 gnd_dig 22 pwrdn 23 vdd_pll 24 filter_pll 25 pll_gnd 26 xti 27 bicki 28 lrcki 29 sdi 30 reset 31 int_line 32 sda 33 scl 34 gnd_dig 35 vdd_dig 36 out1b data pll_filt out1a 10k 100nf 1nf scl sda reset reset 100nf 100nf out2a lrcki pwdn 3v3 out2b xti bicki data pll_filt bead bead bead pll_gnd gnd_dig gnd_dig gnd_dig gnd_dig 9 8 100nf + 1000uf 35v 1nf scl sda reset vcc reset 100nf 3v3 1uf 35v 100nf 100nf 1uf 35v intl 100nf 100nf 3v3 3v3 3r3 3r3 lrcki pwdn 3v3 out2b xti bicki out2a gnd_sub 1 sa 2 test_mode 3 vss 4 vcc_reg 5 out2b 6 gnd2 7 vcc2 out2a out1b 10 vcc1 11 gnd1 12 out1a 13 gnd_reg 14 vdd 15 config 16 nc 17 nc 18 nc 19 nc 20 vdd_dig 21 gnd_dig 22 pwrdn 23 vdd_pll 24 filter_pll 25 pll_gnd 26 xti 27 bicki 28 lrcki 29 sdi 30 reset 31 int_line 32 sda 33 scl 34 gnd_dig 35 vdd_dig 36 out1b data pll_filt out1a 10k 100nf 1nf scl sda reset reset 100nf 100nf out2a lrcki pwdn 3v3 out2b xti bicki data pll_filt bead bead bead pll_gnd gnd_dig gnd_dig gnd_dig gnd_dig
applications information sta333w 40/49 doc id 13365 rev 2 figure 12. pll filter circuit 7.3 typical output configuration figure 13 below shows a typical output configuration used for btl stereo mode. figure 13. output configuration for stereo btl mode 100pf filter_pll 680pf 4.7nf 2k2 100pf filter_pll 680pf 4.7nf 2k2 bead pll_gnd gnd_dig 100pf filter_pll 680pf 4.7nf 2k2 100pf filter_pll 680pf 4.7nf 2k2 bead bead pll_gnd gnd_dig 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 left 100nf 6.2 out1a out1b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 right 100nf 6.2 out2a out2b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 left 100nf 6.2 out1a out1b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 left 100nf 6.2 out1a out1b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 right 100nf 6.2 out2a out2b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 right 100nf 6.2 out2a out2b 6.2
sta333w characterization data doc id 13365 rev 2 41/49 8 characterization data the following characterizations were made with r l = 8 ? and f = 1 khz unless otherwise stated. figure 14. output power vs. supply voltage (thd = 1%) figure 15. fft 0 dbfs (v cc = 12 v) 0 5 10 15 20 25 3 0 57 9 11 1 3 15 17 1 9 su pply volt a ge, v 0 5 10 15 20 25 3 0 57 9 11 1 3 15 17 1 9 o u tp u t power, w 4 ? 6 ? 8 ? 16 ? -150 +10 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz -150 +10 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz
characterization data sta333w 42/49 doc id 13365 rev 2 figure 16. fft -60 dbfs (v cc = 12 v) figure 17. thd vs. frequency (v cc = 12 v, po = 1 w) -150 +10 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz -150 +10 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz 0.01 1 0.02 0.05 0.1 0.2 0.5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz 4ohm 6ohm 8ohm 8 ? 4 ? 6 ?
sta333w characterization data doc id 13365 rev 2 43/49 figure 18. fft 0 dbfs (v cc = 18 v) figure 19. fft -60 dbfs (v cc = 18 v) figure 20. thd vs. frequency (v cc = 18 v, po = 1 w) -150 +10 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz -150 +10 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz -150 +10 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz -150 +10 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz 0.01 1 0.02 0.05 0.1 0.2 0.5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz 4ohm 6ohm 8ohm 0.01 1 0.02 0.05 0.1 0.2 0.5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz 4ohm 6ohm 8ohm 4 ? 6 ? 8 ?
package thermal characteristics sta333w 44/49 doc id 13365 rev 2 9 package thermal characteristics a thermal resistance of 25 c/w can be achieved by mounting the device on a pcb which has two copper ground areas of 3 x 3 cm and 16 vias (see figure 21 ). given that the amount of power dissipated within the device depends primarily on the supply voltage, load impedance and output modulation level the maximum estimated dissipated power for the sta333w is 3 w. with the above suggested board as heatsink, a maximum junction temperature rise, ? tj, of 75 c is possible. in consumer environm ents where 50 c is the maximum ambient temperature this provides some safety margin before the intervention of the thermal protection (t j = 150 c). figure 21. double-layer pcb with two copper ground areas and 16 vias figure 22 shows the power derating curve for the powersso-36 package on pcbs with copper areas of 2 x 2 cm 2 and 3 x 3 cm 2 . figure 22. power derating curve for pcb used as heatsink 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 pd (w) tamb ( c) copper area 2x2 cm and via holes sta333w psso36 copper area 3x3 cm and via holes 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 pd (w) tamb ( c) copper area 2x2 cm and via holes copper area 2x2 cm and via holes sta333w psso36 sta333w psso36 copper area 3x3 cm and via holes copper area 3x3 cm and via holes sta333w powersso-36
sta333w package mechanical data doc id 13365 rev 2 45/49 10 package mechanical data the sta333w comes in a 36-pin powersso package with exposed pad down (epd). figure 23 below shows the package outline and ta bl e 4 7 gives the dimensions. figure 23. powersso-36 epd outline drawing h x 45
package mechanical data sta333w 46/49 doc id 13365 rev 2 in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 47. powersso-36 epd dimensions symbol dimensions in mm dimensions in inches min typ max min typ max a 2.15 - 2.47 0.085 - 0.097 a2 2.15 - 2.40 0.085 - 0.094 a1 0.00 - 0.10 0.000 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 d 10.10 - 10.50 0.398 - 0.413 e 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - f - 2.3 - - 0.091 - g- - 0.10 - - 0.004 h 10.10 - 10.50 0.398 - 0.413 h- - 0.40 - - 0.016 k 0 - 8 degrees 0 - 8 degrees l 0.60 - 1.00 0.024 - 0.039 m - 4.30 - - 0.169 - n - - 10 degrees - - 10 degrees o - 1.20 - - 0.047 - q - 0.80 - - 0.031 - s - 2.90 - - 0.114 - t - 3.65 - - 0.144 - u - 1.00 - - 0.039 - x 4.10 - 4.70 0.161 - 0.185 y 4.90 - 7.10 0.193 - 0.280
sta333w trademarks and other acknowledgements doc id 13365 rev 2 47/49 11 trademarks and other acknowledgements ddx is a registered trademark of apogee technology inc. automodes is a trademark of apogee technology inc. ecopack is a registered trademark of stmicroelectronics. sound terminal is a trademark of stmicroelectronics.
revision history sta333w 48/49 doc id 13365 rev 2 12 revision history table 48. document revision history date revision changes 25-may-2007 1 initial release. 21-jan-2010 2 updated features for operating voltage range, digital gain increments and maximum power control on page 1 updated description on page 1 updated electrical specifications ta b l e 4 , ta b l e 3 and ta bl e 5 o n page 11 added section 3.3: electrical specifications - digital section on page 12 added chapter functional description on page 16 updated usage of pin name sda in first paragraph of chapter 5: i 2 c bus specification on page 18 added section 5.4: read operation on page 19 removed psl (register add 0x03) in table 8: register summary on page 21 updated text concerning overcurrent warning for register confc on page 27 removed bit psl in configuration register d (addr 0x03) on page 28 corrected reset value for register bit mpcv in table 25 on page 28 updated bit names and added register description table in device status register (addr 0x2d) on page 36 updated text and added olim attenuation table in output limit register (addr 0x34) on page 38 deleted mention of appsnote in section 7.3 on page 40 updated package y (min) dimension in table 47 on page 46 removed references to sta50x/51x throughout the document
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