p-channel enhancement mode power mosfet 0 8/04 /2007 rev.1.00 www.siliconstandard.com 1 SSM4409GEM product summary simple drive requirement low on-resistance fast switching characteristic rohs compliant description the advanced power mosfets from silicon standard corp. provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. the so-8 package is universally preferred for all commercial-industrial surface mount applications and suited for low voltage applications such as dc/dc converters. absolute maximum ratings pb-free; rohs-compliant symbol units v ds v v gs v i d @t a =25 a i d @t a =70 a i dm a p d @t a =25 w w/ t stg t j symbol value unit rthj-a thermal resistance junction-ambient 3a max 50 /w parameter total power dissipation 2.5 -55 to 150 operating junction temperature range -55 to 150 linear derating factor storage temperature range continuous drain current 3a -12 pulsed drain current 1 -50 0.02 parameter drain-source voltage gate-source voltage continuous drain current 3a rating -35 20 -14.5 thermal data bv dss -35v r ds(on) 7.5m i d -14.5a s s s g d d d d so-8 g d s
0 8/04 /2007 rev.1.00 www.siliconstandard.com 2 SSM4409GEM symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =-250ua -35 - - v b v dss / t j breakdown voltage temperature coefficient reference to 25 , i d =-1ma - -0.02 - v/ r ds(on) static drain-source on-resistance 2 v gs =-10v, i d =-7a - - 7.5 m v gs =-4v, i d =-7a - - 15 m v gs(th) gate threshold voltage v ds =v gs , i d =-250ua -0.8 - -2 v g fs forward transconductance v ds =-10v, i d =-7a - 13 - s i dss drain-source leakage current (t j =25 o c) v ds =-30v, v gs =0v - - -10 ua drain-source leakage current (t j =70 o c) v ds =-24v, v gs =0v - - -25 ua i gss gate-source leakage v gs =20v - - 30 ua q g total gate charge 2 i d =-14a - 55 90 nc q gs gate-source charge v ds =-30v - 10 - nc q gd gate-drain ("miller") charge v gs =-4.5v - 30 - nc t d(on) turn-on delay time 2 v ds =-15v - 18 - ns t r rise time i d =-1a - 10 - ns t d(off) turn-off delay time r g =3.3 , v gs =-10v - 160 - ns t f fall time r d =15 - 110 - ns c iss input capacitance v gs =0v - 4100 6600 pf c oss output capacitance v ds =-25v - 860 - pf c rss reverse transfer capacitance f=1.0mhz - 770 - pf source-drain diode symbol parameter test conditions min. typ. max. units v sd forward on voltage 2 i s =-14a, v gs =0v - - -1.3 v t rr reverse recovery time 2 i s =-14a, v gs =0 v , - 43 - ns q rr reverse recovery charge di/dt=100a/s - 37 - nc notes: 1.pulse width limited by max. junction temperature. 2.pulse width < 300us , duty cycle < 2%. 3.surface mounted on 1 in 2 copper pad of fr4 board a , t < 10sec (a) 1 in 2 pad of 2 oz copper (b) 125 /w when mounted on a 0.003 in 2 pad of 2 oz copper electrical characteristics @t j =25 o c (unless otherwise specified )
0 8/04 /2007 rev.1.00 www.siliconstandard.com 3 SSM4409GEM fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance v.s. gate voltage fig 4. normalized on-resistance v.s. junction temperature fi g 5. forward characteristic o f fig 6. gate threshold voltage v.s. reverse diode junction temperature 0 10 20 30 40 50 01 23 4 -v ds , drain-to-source voltage (v) -i d , dr a i n c u r r e nt (a ) t a =2 5 o c - 10v -5.0 v -4.5 v -3.0 v v g = - 2.5 v 0 10 20 30 40 50 01 23 4 -v ds , drain-to-source voltage (v) -i d , dr a i n c u r r e nt (a ) t a = 150 o c -10v - 5.0 v - 4.5 v - 3.0 v v g = - 2.5 v 6 11 16 21 26 24 68 1 0 -v gs , gate-to-source voltage (v) r ds(on\ ) (m ) i d =- 7 a t a =25 0.6 1.0 1.4 1.8 -50 0 50 100 150 t j , junction temperature ( o c) n o rmalize d r ds(on) i d =-7a v g =-10v 0.2 0.6 1.0 1.4 1.8 -50 0 50 100 150 t j , junction temperature ( o c) n o rmalize d - v gs(t h) (v ) 0 2 4 6 8 10 12 14 0 0.2 0.4 0.6 0.8 1 1.2 -v sd , source-to-drain voltage (v) -i s (a ) t j =25 o c t j =150 o c
0 8/04 /2007 rev.1.00 www.siliconstandard.com 4 SSM4409GEM fig 7. gate charge characteristics fig 8. typical capacitance characteristics fig 9. maximum safe operating area fig 10. effective transient thermal impedance fig 11. transfer characteristics fig 12. gate charge waveform q v g -4.5v q gs q gd q g charge 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 t , pulse width (s) n o rmalize d t h e rmal re spon se ( r th ja ) p dm duty factor = t/t peak t j = p dm x r thja + t a rthja=125 o c/w t t 0.02 0.01 0.05 0.1 0.2 duty factor=0.5 single pulse 0 20 40 60 012345 -v gs , gate-to-source voltage (v) -i d , dr a i n c u r r e nt (a ) t j =150 o c t j =25 o c v ds =-5v 0 4 8 12 16 0 30 60 90 120 q g , total gate charge (nc) -v gs , g a te to s o u rc e voltage ( v ) i d = - 14a v ds = - 30 v 0.01 0.1 1 10 100 0.1 1 10 100 -v ds , drain-to-source voltage (v) -i d (a ) t a =25 o c single pulse 1ms 10ms 100ms 1s dc 100 1000 10000 1 5 9 1 31 72 1 2 52 9 -v ds , drain-to-source voltage (v) c ( p f) f=1.0mhz c iss c oss c rss
SSM4409GEM 0 8/04 /2007 rev.1.00 www.siliconstandard.com 5 information furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties.
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