BLV7002 http://www.belling.com.cn - 1 - 8/18/2006 total 2 pages BLV7002 n-channel enhancement mode vertical d-mos transistor chip description n-channel enhancement mode field-effect transistor features very fast switching logic level compatible applications relay driver high speed line driver logic level translator. size structure planar type electrodes: aluminum alloy backside metal: au alloy chip size: 495 m m 490 m m chip thickness: 22020 m m. scribe street width: 50 m m pad size: 90 m m x90 m m die per wafer: 25800 absolute maximum rating symbol parame ter min. max. unit v ds drain C source voltage (dc) - 60 v v gs gate C source voltage (dc) - 20 v i d drain current (dc) - 115 ma i d m peak drain current - 0.46 a p tot total p ower d issipation - 0.2 w t stg storage temperature - 55 +150 o c t j junction tem perature - 150 o c
BLV7002 http://www.belling.com.cn - 2 - 8/18/2006 total 2 pages characteristics t j = 25 o c unless otherwise specified symbol parameter test conditions min. typ. max. unit bv dss drain - source breakdown voltage v gs =0v,i d = 250 m a 60 73 - v i dss drain - source leakage current v ds =6 0 v, v gs =0v - 1 500 n a i gss gate - source leakage current v gs = + 20 v, v ds =0v - 1 100 na v gsth gate - source threshold voltage v ds =2. 5v , i d = 250u a 1 - 2.5 v r ds on drain - source on - state resistance v gs = 10v ,i d = 100ma - 1.3 5 w c iss input capacitance - - 50 pf c os s output capacitance - - 25 pf c rss reverse transfer capacitance v ds =25v v gs =0v f =1mhz - - 5 pf t on turn-on time - - 30 ns t off turn-off time v dd =30v, i d =200ma v gs =0-10v - - 30 ns pattern drawing
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