1/4 rev. a structure silicon monolithic integrated circuit type 2ch dc/dc converter ic product series BD95830MUV features ? built in 2ch h 3 reg dc/dc converter controller ? adjustable output voltage setting (0.8v 5.5v) absolute maximum ratings (ta=25 ) parameter symbol limit unit input voltage v in 1, v in 2, v ins 15.1 *1*2 v boot voltage boot1,boot2 21.1 *1*2 v boot-sw voltage boot 1-sw1, boot2-sw2 7 *1*2 v output voltage v out 1, v out 2 7 *1*2 v output feedback voltage fb1, fb2 v reg v v reg voltage v reg 7 *1*2 v v cc voltage v cc v reg v logic input voltage en1, en2 15.1 *1*2 v power dissipation 1 pd1 0.38 *3 w power dissipation 2 pd2 0.88 *4 w power dissipation 3 pd3 3.26 *5 w power dissipation 4 pd4 4.56 *6 w operating temperature range topr -20 +100 storage temperature range tstg -55 +150 maximum junction temperature tjmax +150 *1 not to exceed pd. *2 instantaneous surge voltage, back electromotive force and voltage under less than 10% duty cycle. *3 reduced by 3.04mw/ for each increase in ta of 1 over 25 (when don t mounted on a heat radiation board ) *4 reduced by 7.04mw/ for increase in ta of 1 over 25 . (when mounted on a board 74.2mm 74.2mm 1.6mm glass-epoxy pcb(1 layer), copper foil area : 20.2mm 2 ) *5 reduced by 26.11mw/ for increase in ta of 1 over 25 . (when mounted on a board 74.2mm 74.2mm 1.6mm glass-epoxy pcb(4 layer), copper foil area: 20.2mm 2 , 2-3layer: 5505mm 2 ) *6 reduced by 36.5mw/ for increase in ta of 1 over 25 . (when mounted on a board 74.2mm 74.2mm 1.6mm glass-epoxy pcb(4 layer), copper foil area: 5505mm 2 ) operating conditions ta = 2 5 parameter symbol min. max. unit input voltage v in 1, v in 2, v ins 7.5 15 v boot voltage boot1, boot2 4.5 21 v sw voltage sw1, sw2 -0.7 15 v boot-sw voltage boot1-sw 1, boot2-sw2 4.5 5.5 v logic input voltage en1, en2 0 15 v output voltage v out 1, v out 2 0.8 5.5 v min on time tonmin - 100 ns this product is not designed to be used in a radioactive environment.
2/4 rev. a electrical characteristics (unless otherwise noted, ta=25 v cc =v reg , v in 1=v in 2=v ins =12v, v en 1=v en 2=3v, v out 1=v out 2=1.8v) parameter symbol standard value unit conditions min. typ. max. [whole device] v ins bias current i ins - 1.7 2.2 ma v ins standby current i ins_ stb - 0 10 a v en 1=v en 2=0v en low voltage1,2 v en _low 1,2 gnd - 0.3 v en high voltage1,2 v en _high 1,2 2.2 - 15 v en pull-down resistance1,2 r en1,2 28 48 68 k [5vlinear regulator] v reg standby voltage v reg _stb - - 0.1 v v en 1=v en 2=0v v reg output voltage v reg 4.8 5.0 5.2 v v ins =7.5v to 15v i reg =10ma [under voltage lock out] uvlo threshold voltage v cc_uvlo 4.0 4.3 4.6 v v cc :sweep up uvlo hysteresis voltage dv cc_uvlo 100 160 220 mv v cc :sweep down [over voltage protection] ovp threshold voltage1,2 v ovp1,2 0.86 0.96 1.06 v [h 3 reg tm control] on time1,2 ton 1,2 200 255 310 ns min off time1,2 toffmin 1,2 300 550 - ns [fet driver] high side on resistance1,2 r on_high 1,2 - 75 120 m low side on resistance 1,2 r on_low 1,2 - 50 75 m [current control] current limit 1,2 i lim 1,2 3 4 5 a [output voltage sense] fb threshold voltage1,2 v fb1,2 0.788 0.8 0.812 v fb input current1,2 i fb1,2 -1 - 1 a v out discharge current1,2 i vout1,2 5 10 - ma v out =1v, v en =0v, v cc =5v [scp] scp threshold voltage1,2 v scp1,2 0.48 0.56 0.64 v
3/4 rev. a block diagram physical dimension pin number ? pin name pin no. pin name 1,2,32 v in 1 3 v ins 4 v reg 5 v cc 6,20 gnd 7-9 v in 2 10-12 pgnd2 13-15 sw2 16 boot2 17 en2 18 v out 2 19 fb2 21 test *7 22 fb1 23 v out 1 24 en1 25 boot1 26-28 sw1 29-31 pgnd1 reverse fin *7 (unit : mm) logic input lot no. d95830 package vqfn032v5050 thermal protection r s q tsd delay h 3 reg tm controller block v reg gnd boot1 v in1 sw1 pgnd1 25 26 27 28 6, 20 reference block uvlo en2 boot2 v in2 sw2 17 16 5vreg v reg 4 3 ovp ovp driver circuit r s q h 3 reg tm controller block uvlo ocp2 scp tsd driver circuit fb1 22 en1 24 fb2 19 0.96 v fb1 ovp1 0.96 v fb2 v reg v reg v out 2 en1/uvlo v out 1 23 v out 1 v out 2 v out 1 v in v out 2 v in 18 v ins v in en1 v reg uvlo ocp1 scp tsd + - 0.56v fb2 + - 0.56v fb1 scp en2 v reg sw1 ocp1 sw2 ocp2 + - + - ovp ovp2 5 v cc v ins + pgnd2 soft start - + ref1 ss1 ref1 en1 uvlo ss1 soft start en2 uvlo ss2 en2/uvlo + - + ref2 ss2 v reg 13 14 15 10 11 12 7 8 9 1 2 32 29 30 31 ref2 uvlo bg en2 en1 21 test *7 the test pin (21pin) and the fin should be connected with the gnd.
4/4 rev. a note for use 1. absolute maximum ratings an excess in the absolute maximum ratings, such as supply voltage, temperature range of operati ng conditions, etc., can break d own the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. if any over rated values will exp ect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2. gnd pin voltage gnd, pgnd1 and pgnd2 terminal should be connected the lowest voltage, under all conditions. and al l terminals except sw should be under gnd terminal voltage under all conditions including transient situatio ns. if a terminal exists under gnd, it should be inserting a bypass route. 3. thermal design if ic is used on condition that the power loss is over the power dissipation, the reliability will become worse by heat up, suc h as reduced output current capability. also, be sure to use this ic within a power dissipation range allowing enough of margin. 4. input supply voltage input supply pattern layout shoul d be as short as possible. 5. inter-pin shorts and mounting errors note the direction and the miss-registration of ic enough when you in stall it in the set substrate. ic might destroy it as well as reversely connecting the power supply connector when installing it by mistak e. moreover, there is fear of destruction when the foreign bo dy enters between terminals, the terminal, the power supply, and grandeur and it is short-circuited. 6. actions in strong electromagnetic field use caution when using the ic in the presen ce of a strong electromagnetic field as do ing so may cause the ic to malfunction. 7. aso when using the ic, set the output transistor so that it does not exceed absolute maximum ratings or aso. 8. testing on application boards when testing the ic on an application board, connecting a capacito r to a pin with low impedance subjects the ic to stress. alwa ys discharge capacitors after each process or step. always turn the ic's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. ground the ic during assembly steps as an antistatic measure. use similar precaution when transporting or s toring the ic. 9. electrical characteristics the electrical characteri stics in the specifications may vary depending on ambient temperature, power supply voltage, circuit(s ) externally applied, and/or other conditions. it is therefore requested to care fully check them including tr ansient characteristics. 10. not of a radiation-resistant design. 11. in the event that load cont aining a large inductance component is connected to the output terminal, a nd generation of back-emf at the start-up and when output is turned off is assumed, it is requested to insert a protection diode. 12. regarding input pin of the ic this monolithic ic contains p+ isolatio n and p substrate layers between adjacent el ements in order to keep them isolated. p-n junctions are formed at the intersection of these p layers with the n layers of other elements, creating a parasitic diode or transistor. for example, the relation between each potential is as follows: when gnd > pin a and gnd > pin b, the p-n junction operates as a parasitic diode. when gnd > pin b, the p-n junction operates as a parasitic transistor. parasitic diodes can occur inevitable in t he structure of the ic. the operation of para sitic diodes can result in mutual interf erence among circuits, operational faults, or physical damage. accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the gnd (p substrate) voltage to an input pin, should not be used. 13. ground wiring pattern when using both small signal and large current gnd patterns, it is recommended to isolate the two ground patterns, placing a si ngle ground point at the ground potential of application so that the pattern wiri ng resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. be careful not to change the gnd wiring pattern of any external components, either. 14. operating ranges if it is within the operating ranges, certain circuit function s and operations are warranted in the working ambient temperature range. with respect to characteristic values , it is unable to warrant standard values of electric characteristics but there are no sudden variation s in characteristic values within these ranges. 15. thermal shutdown circuit this ic is provided with a built-in thermal shutdown (tsd) circui t, which is activated when the chip temperature reaches the th reshold value listed below. when tsd is on, the device goes to high impedance mode. no te that the tsd circuit is provided for the exclusive purpose shutting down the ic in the presence of extreme heat, and is not designed to protect the ic per se or guarantee performance when or after extreme heat conditions occur. therefore, do not operate the ic with the expectation of continued use or subsequent operation once the tsd is activated . 16.output voltage resistor setting output volage is adjusted with resistor. total 10kohm resistor is recommended so that the output voltage is not affected by the fb input current (typ. 1ua). 17. over output current protection this ic has an over current protection (4.0a[typ]), with prev ents ic from being damage by short circuit at over current. howeve r, it is recommend not to use that continuously operates the protection circuit (for instance, always the load that greatly exceeds the output current ability is connected or the output is short-circuited, etc.) in th ese protection circuits by an effective one to the destruction prevention due to brok en accident. 18. heat sink (fin) since the heat sink (fin) is connected with the sub, short it to the gnd. tsd on temperature [ ] (typ.) hysteresis temperature[ ] (typ.) 175 15 output pin resisto r transistor ( npn ) n n n pp p p substrate gnd parasitic element pin a n n p p p p substrate gnd parasitic element pin b c b e n gnd pin a parasitic element pin b other adjacent elements e b c gnd parasitic element
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