View FSA2268L10X_4816050.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

february 2012 ? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2268/2268t rev. 1.0.9 fsa2268 / fsa2268t ? low -voltage dual-spdt (0.4 ? ? ) analog switch with 16kv esd features ? 0.4 ? typical on resistance (r on ) for +3.0v supply ? 0.25 ? maximum r on flatness for +3.0v supply ? -3db bandwidth: > 50mhz ? low i cct current over an expanded control input range ? packaged in pb-free 10-lead mlp (1.4 x 1.8mm) ? power-off protection on common ports ? broad v cc operating range: 1.65 to 4.3v ? hbm jedec: jesd22-a114 - i/o to gnd: 13.5kv - power to gnd: 16.0kv ? noise immunity termination resistors in fsa2268t applications ? cell phone, pda, digital camera, and notebook ? lcd monitor, tv, and set-top box description the fsa2268 is a high-performance, dual single pole double throw (spdt) analog switch that features ultra- low r on of 0.4 ? (typical) at 3.0v v cc . the fsa2268 operates over a wide v cc range of 1.65v to 4.3v and is designed for break-before-make operation. the select input is ttl-level compatible. the fsa2268 features very low quiescent current even when the control voltage is lower than the v cc supply. this feature suits mobile handset applications by allowing direct interface with baseband processor general-pur pose i/os with minimal battery consumption. the fsa2268t includes termination resistors that improve noise immunity during overshoot excursions, off-isolation coupling, or ?pop-minimization.? important note: for additional information, please contact analogswitch@fairchildsemi.com . ordering information part number top mark package description fsa2268umx gf 10-lead, quad ultrathin molded leadless package (umlp), 1.4 x 1.8mm, 0.4mm pitch fsa2268tumx gh 10-lead, quad ultrathin molded leadless package (umlp), 1.4 x 1.8mm, 0.4mm pitch FSA2268L10X gh 10-l ead, micropak?, 1.6mm wide analog symbols 1b0 1b1 1a s1 2b0 2b1 2a s2 2b0 2b1 2a gnd s2 1b0 1b1 1a gnd s1 figure 1. fsa2268 figure 2. fsa2268t (with noise termination resistors)
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2268/2268t rev. 1.0.9 2 fsa2268 / fsa2268t ? low -voltage dual-spdt (0.4 ? v cc gnd 1 8 5 4 3 2 1b 0 1b 1 2b 0 2b 1 s1 s2 2a 1a 9 10 6 7 2 1 3 4 gnd v cc 10 2b 1 1b 1 1b 0 2b 0 2a s1 1a s2 5 9 8 7 6 figure 3. pin assignment 10-pin umlp (top-through view) figure 4. 10-lead micropak? pin descriptions pin # umlp pin # micropak? name description 1 2 1b 1 data ports 2 3 2b 0 data ports 3 4 2b 1 data ports 4 5 gnd ground 5 6 2a data ports 6 7 s2 switch select pins 7 8 s1 switch select pins 8 9 1a data ports 9 10 v cc supply voltage 10 1 1b 0 data ports truth table control input, sn function low logic level nb0 connected to na (fsa2268/22 68t); nb1 terminated to gnd (fsa2268t only) high logic level nb1 connected to na (fsa2268/22 68t); nb0 terminated to gnd (fsa2268t only)
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2268/fsa2268t rev. 1.0.9 3 fsa2268 / fsa2268t ? low -voltage dual-spdt (0.4 ? stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and st ressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. units v cc supply voltage -0.5 5.5 v v sw switch i/o voltage (1) 1b0, 1b1, 2b0, 2b1, 1a, 2a pins -0.5 v cc + 0.3 v t version nbn pin off 0 1.4 v in control input voltage (1) s1, s2 -0.5 5.5 v i ik input clamp diode current -50 ma i sw switch i/o current (continuous) 350 ma i swpeak peak switch current (pulsed at 1ms duration, <10% duty cycle) 500 ma t stg storage temperature range -65 +150 c t j maximum junction temperature +150 c t l lead temperature (soldering, 10 seconds) +260 c msl moisture sensitivity level (jedec j-std-020a) 1 level esd human body model, jedec: jesd22-a114 i/o to gnd 13.5 kv power to gnd 16.0 all other pins 9.0 charged device model, jedec: jesd22-c101 2.0 kv note: 1. input and output negative ratings ma y be exceeded if input and output di ode current ratings are observed. recommended operating conditions the recommended operating conditions table defines th e conditions for actual device operation. recommended operating conditions are specified to en sure optimal performance to the datash eet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. units v cc supply voltage 1.65 4.30 v v in control input voltage 0 v cc v v sw switch i/o voltage 0 v cc v t a operating temperature -40 +85 c
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2268/fsa2268t rev. 1.0.9 4 fsa2268 / fsa2268t ? low -voltage dual-spdt (0.4 ? all typical values are at 25o c unless otherwise specified. symbol parameter conditions v cc (v) t a =+25oc t a =-40 to +85oc unit min. typ. max. min. max. v ih input voltage high 3.6 to 4.3 1.7 v 2.7 to 3.6 1.5 2.3 to 2.7 1.4 1.65 to 1.95 0.9 v il input voltage low 3.6 to 4.3 0.7 v 2.7 to 3.6 0.5 v 2.3 to 2.7 0.4 1.65 to 1.95 0.4 i in control input leakage (s1,s2) v in =0 to v cc 1.65 to 4.30 -0.5 0.5 a i no(0ff), i nc(off) fsa2268 off leakage current of port nb0 and nb1 na=0.3v, v cc ?0.3v nb0 or nb1=v cc -0.3v, 0.3v, or floating figure 6 1.95 to 4.30 -10 10 -50 50 na i nc(off) fsa2268t off leakage current of port nb0 and nb1 (with termination resistors) na=0.3v, nb0 or nb1=0v or floating figure 6 1.95 to 4.30 -10 10 -50 50 a i a(on) on leakage current of port na na=0.3v, v cc ?0.3v nb0 or nb1=v cc -0.3v, 0.3v, or floating figure 7 1.95 to 4.30 -20 20 -100 100 na i off fsa2268 power-off leakage current (common port only 1a, 2a) common port (1a, 2a), v in =0v to 4.3v, v cc =0v nb0, nb1=floating 0v 1 a i off fsa2268t power-off leakage current (common port only 1a, 2a) common port (1a, 2a), v in =0v to 4.3v, v cc =0v nb0, nb1=0v or floating 0v 40 a r on switch on resistance (2)(5) i on =100ma, nb0 or nb1=0.7v, 3.6v figure 5 4.30 0.30 0.50 ? i on =100ma, nb0 or nb1=0.7v, 2.3v figure 5 3.00 0.40 0.55 i on =100ma, nb0 or nb1=0v, 0.7v, 1.6v, 2.3v figure 5 2.30 0.52 i on =100ma, nb0 or nb1=0v, 0.7v, 1.65v figure 5 1.65 1.00 ? r on on resistance matching between channels (3)(5) i on =100ma, nb0 or nb1=0.7v 4.30 0.04 0.13 ? 3.00 0.06 0.13 2.30 0.12 1.65 1.00 continued on following page ?
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2268/fsa2268t rev. 1.0.9 5 fsa2268 / fsa2268t ? low -voltage dual-spdt (0.4 ? dc electrical characteristics (continued) all typical values are at 25o c unless otherwise specified. symbol parameter conditions v cc (v) t a =+25oc t a =-40 to +85oc unit min. typ. max. min. max. r flat(on) on resistance flatness (4)(5) i out =100ma, nb0 or nb1=0v to v cc 4.30 0.25 ? 3.00 0.25 2.30 0.5 1.65 0.6 r term internal termination resistors (6) 200 ? i cc quiescent supply current v in =0 or v cc , i out =0 4.30 -100 100 -500 500 na i cct increase in i cc per input input at 2.6v 4.30 3 7 a input at 1.8v 7 15 notes: 2. on resistance is determined by the voltage drop betw een a and b pins at the indicat ed current through the switch. 3. ? r on =r on max ? r on min measured at identical v cc , temperature, and voltage. 4. flatness is defined as the difference between the maximum and minimum value of on resistance (r on ) over the specified range of conditions. 5. guaranteed by characterizati on, not production tested, for v cc =1.65-3.00v. 6. guaranteed by characteriza tion, not production tested.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2268/fsa2268t rev. 1.0.9 6 fsa2268 / fsa2268t ? low -voltage dual-spdt (0.4 ? ac electrical char acteristics all typical value are for v cc =3.3v at 25oc unless otherwise specified. symbol parameter conditions v cc (v) t a =+25oc t a =-40 to +85c unit figure min. typ. max. min. max. t on turn-on time nb0 or nb1=1.5v, r l =50 ? , c l =35pf 3.6 to 4.3 55 15 60 ns figure 8 figure 9 2.7 to 3.6 60 15 65 2.3 to 2.7 65 15 70 1.65 to 1.95 70 t off turn-off time nb0 or nb1=1.5v, r l =50 ? , c l =35pf 3.6 to 4.3 30 5 35 ns 2.7 to 3.6 35 5 40 2.3 to 2.7 40 5 45 1.65 to 1.95 40 t bbm break- before-make time nb0 or nb1=1.5v, r l =50 ? , c l =35pf 3.6 to 4.3 15 2 ns figure 10 2.7 to 3.6 15 2 2.3 to 2.7 15 2 1.65 to 1.95 16 2 q charge injection c l =1.0nf, v s =0v, r s =0 ? 1.65 to 4.30 25 pc figure 14 oirr off isolation f=100khz, r l =50 ? , c l =0pf 1.65 to 4.30 -70 db figure 12 xtalk crosstalk f=100khz, r l =50 ? , c l =0pf 1.65 to 4.30 -70 db figure 13 bw -3db bandwidth r l =50 ? , c l =0pf 1.65 to 4.30 >50 mhz figure 11 thd total harmonic distortion f=20hz to 20khz, r l =32 ? , v in =2v pp 1.65 to 4.30 .06 % figure 17 capacitance symbol parameter conditions v cc (v) t a =+25oc unit figure min. typ. max. c in control pin input capacitance f=1mhz 0 1.5 pf figure 15 c off b port off capacitance f=1mhz 3.3 30 pf figure 15 c on a port on capacitance f=1mhz 3.3 120 pf figure 16
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2268/fsa2268t rev. 1.0.9 7 fsa2268 / fsa2268t ? low -voltage dual-spdt (0.4 ? test diagrams select nb n na v sel = 0 or v cc i on v on r on = v on /i on gnd v in gnd v in select v sel = 0 orv cc nc a i a(off) v in gnd **each switch port is tested separately. v in figure 5. on resistance figure 6. off leakage (ports tested separately) selec t v sel = 0 o r v cc nc i a(on) v in gnd a i a(on) v in v in r l c l nb n na gnd gnd r s v sel v in gnd v out v in figure 7. on leakage figure 8. test circuit load t rise =2.5ns gnd v cc 90% 90% 10% 10% t fall =2.5ns v cc /2 v cc /2 input - v sel output - v out 90% v oh v ol t on t off 90% figure 9. turn-on / turn-off waveforms
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2268/fsa2268t rev. 1.0.9 8 fsa2268 / fsa2268t ? low -voltage dual-spdt (0.4 ? test diagrams (continued) v cc 0.9*v out v cc /2 d 0v v out input - v sel 0.9*v out t rise =2.5ns 90% 10% c l nb n r l na gnd gnd r s v sel v in gnd r l and c l are functions of the application environment (50, 75, or 100 ). c l includes test fixture and stray capacitance. v out v in gnd t - - r l and c l figure 10. break-before-make interval timing v out gnd gnd r t gnd gnd v s r s network analyzer v sel gnd r l and c l are functions of the application environment (50, 75, or 100 ). c l includes test fixture and stray capacitance. v in l figure 11. bandwidth v out gnd gnd r t gnd gnd v s r s network analyzer r t gnd r s and r t are functions of the application environment (50, 75, or 100 ). v sel gnd off-isolation = 20 log (v out /v in ) - figure 12. channel off isolation
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2268/fsa2268t rev. 1.0.9 9 fsa2268 / fsa2268t ? low -voltage dual-spdt (0.4 ? test diagrams (continued) v out gnd gnd r t gnd gnd v s r s network analyzer r t gnd r s and r t are functions of the application environment (50, 75, or 100 ). v sel gnd crosstalk = 20 log (v out /v in ) v in figure 13. adjacent channel crosstalk r s v out q = ? v out / c l ? v out v out v cc 0v input ? v sel generator gnd v s c l v sel v in b ns n gnd c l includes test fixture and stray capacitance gnd off on off ma figure 14. charge injection test v sel = 0 or v c c nb n capacitance meter ns n nb n f=1mhz v sel = 0 orv cc nb n capacitance meter ns n nb n f=1mhz figure 15. channel off capacitance figure 16. channel on capacitance v out gnd gnd r t gnd gnd v s r s audio analyzer v cntrl gnd v in r s and r t are functions of the application environment (see ac tables for specific values). v sel = 0 or v cc figure 17. total harmonic distortion
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2268/fsa2268t rev. 1.0.9 10 fsa2268 / fsa2268t ? low -voltage dual-spdt (0.4 ? physical dimensions a b c seating plane detail a pin#1 ident recommended land pattern notes: a. package does not fully conform to jedec standard. b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994. d. land pattern recommendation is based on fsc design only. e. drawing filename: mkt-umlp10arev3. top view bottom view 0.15 c 0.08 c 0.15 c 2x 2x side view 0.10 c 0.05 3 6 1 0.10 c a b 0.05 c 0.55 max. 10 1.40 1.80 0.40 0.15 0.25 (10x) 0.35 0.45 (9x) 1.70 2.10 0.40 0.663 0.563 (9x) 0.225 (10x) 1 0.152 0.10 0.10 0.55 0.45 0.10 detail a scale : 2x 1.85 1.45 0.55 0.40 0.225 (10x) 9x 0.45 pin#1 ident optional minimial toe land pattern scale : 2x lead option 1 scale : 2x lead option 2 package edge figure 18. 10-lead quad ultrathin molded leadless package (umlp) package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . for current tape and reel specifications, visi t fairchild semiconductor?s online packaging area: http://www.fairchildsemi.com/products/analog/pdf/umlp10_tnr.pdf .
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2268/fsa2268t rev. 1.0.9 11 fsa2268 / fsa2268t ? low -voltage dual-spdt (0.4 ? (continued) bottom view top view recommended land pattern side view 2x 2x notes: a. package conforms to jedec registration mo-255, variation uabd . b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994. d. presence of center pad is package supplier dependent. if present it is not intended to be soldered and has a black oxide finish. e. drawing filename: mkt-mac10arev5. 0.10 c 0.10 c 0.10 cab 0.05 c pin1 ident is 2x longer than other lines a b c 0.35 0.25 9x 9x 1 4 9 6 0.25 0.15 10 5 0.50 0.56 1.62 0.05 0.00 0.05 c 0.55 max 0.05 c 1.60 2.10 (0.35) (0.25) 0.50 10x 10x (0.11) 1.12 1.62 keepout zone, no traces or vias allowed (0.20) (0.15) 0.35 0.25 0.35 0.25 detail a detail a 2x scale 0.35 0.25 0.65 0.55 d all features (0.36) (0.29) 0.56 figure 19. 10-lead, micropak?, 1.6mm wide package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . for current tape and reel specifications, visi t fairchild semiconductor?s online packaging area: http://www.fairchildsemi.com/pr oducts/logic/pdf/micropak_tr.pdf.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fsa2268/fsa2268t rev. 1.0.9 12 fsa2268 / fsa2268t ? low -voltage dual-spdt (0.4 ?

▲Up To Search▲

Price & Availability of FSA2268L10X

	To Download FSA2268L10X Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .