mosel vitelic 1 V43648Z04VTG 3.3 volt 8m x 64 high performance 100 mhz sdram unbuffered sodimm preliminary V43648Z04VTG rev. 1.6 february 1999 features n using 8m x 8 sdrams n jedec-standard 144 pin, small-outline, dual in line memory module (sodimm) n serial presence detect with e 2 prom n nonbuffered n fully synchronous, all signals registered on positive edge of system clock n single +3.3v ( 0.3v) power supply n all device pins are lvttl compatible n 4096 refresh cycles every 64 ms n self-refresh mode n internal pipelined operation; column address can be changed every system clock n programmable burst lengths: 1, 2, 4, 8 or full page n auto precharge and piecharge all banks by a10 n data mask function by dqm n mode register set programming n programmable (cas latency: 2, 3 clocks) description the V43648Z04VTG memory module is organized 8,388,608 x 64 bits in a 144 pin sodimm. the 8m x 64 memory module uses 8 mosel-vitelic 8m x 8 sdram. the x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. part number speed grade configuration V43648Z04VTG -10 (100 mhz) 8m x 64 1 pin 2 on backside pin 144 on backside 28 29 143 8m x 8 8m x 8 8m x 8 8m x 8
2 V43648Z04VTG rev. 1.6 february 1999 mosel vitelic V43648Z04VTG pin configurations (front side/back side) note: 1. ras , cas , we cas x, cs x are active low signals. pin front pin front pin front pin back pin back pin back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vss vss dq0 dq32 dq1 dq33 dq2 dq34 dq3 dq35 vdd vdd dq4 dq36 dq5 dq37 dq6 dq38 dq7 dq39 vss vss dqmb0 dqmb4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 dqmb1 dqmb5 vdd vdd a0 a3 a1 a4 a2 a5 vss vss dq8 dq40 dq9 dq41 dq10 dq42 dq11 dq43 vdd vdd dq12 dq44 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 dq13 dq45 dq14 dq46 dq15 dq47 vss vss nc nc nc nc clk0 cke0 vdd vdd ras cas we nc cs0 nc nc nc 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 nc clk1 vss vss nc nc nc nc vdd vdd dq16 dq48 dq17 dq49 dq18 dq50 dq19 dq51 vss vss dq20 dq52 dq21 dq53 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 dq22 dq54 dq23 dq55 vdd vdd a6 a7 a8 ba0 vss vss a9 ba1 a10 a11 vdd vdd dqmb2 dqmb6 dqmb3 dqmb7 vss vss 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 dq24 dq56 dq25 dq57 dq26 dq58 dq27 dq59 vdd vdd dq28 dq60 dq29 dq61 dq30 dq62 dq31 dq63 vss vss sda scl vdd vdd pin names a0?11, ba0, ba1 address, bank select dq0?q63 data inputs/outputs ras row address strobes cas column address strobes we write enable cs 0 chip select dqmb0?qmb7 output enable cke0 clock enable clk0?lk1 clock sda serial input/output scl serial clock vdd power supply vss ground nc no connect (open)
mosel vitelic V43648Z04VTG 3 V43648Z04VTG rev. 1.6 february 1999 part number information block diagram sdram 3.3v V43648Z04VTG-02 4 mosel-vitelic manufactured v 144 pin unbuffered sodimm x8 component z refresh rate 4k 0 3 depth 8 4 banks 4 tsop width 64 lvttl v gold g t dqmb0 cas ras we cs0 v436444vog-03 u0?7 a0?11 v dd u0?7 ba0?a1 cke u0?7 u0, u4 ck0 v ss u1, u5 10 scl sda 10 u2, u6 ck1 u3, u7 10 10 spd a0 a1 a2 dqm u0 dq0-7 dqm u4 dqmb4 dq32-39 dqmb1 dqm u1 dq8-15 dqm u5 dqmb5 dq40-47 dqmb2 dqm u2 dq16-23 dqm u6 dqmb6 dq48-55 dqmb3 dqm u3 dq24-31 dqm u7 dqmb7 dq56-63
4 V43648Z04VTG rev. 1.6 february 1999 mosel vitelic V43648Z04VTG serial presence detect information a serial presence detect storage device e 2 prom ?is assembled onto the module. informa- tion about the module configuration, speed, etc. is written into the e 2 prom device during module pro- duction using a serial presence detect protocol (i 2 c synchronous 2-wire bus) spd-table for -10 pc modules: byte number function described sdp entry value hex value 100 mhz -10pc 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses (without bs bits) 12 0c 4 number of column addresses (for x8 sdram) 9 09 5 number of dimm banks 1 01 6 module data width 64 40 7 module data width (continued) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl=3 10.0 ns a0 10 sdram access time from clock at cl=3 6.0 ns 60 11 dimm config (error det/corr.) none 00 12 refresh rate/type self-refresh, 15.6 m s80 13 sdram width, primary x8 08 14 error checking sdram data width n/a / x8 00 15 minimum clock delay from back to back random column address t ccd = 1 clk 01 16 burst length supported 1, 2, 4, 8 & full page 8f 17 number of sdram banks 4 04 18 supported cas latencies cl = 2 & 3 06 19 cs latencies cs latency = 0 01 20 we latencies wl = 0 01 21 sdram dimm module attributes non buffered/non reg. 00 22 sdram device attributes: general vcc tol 10% 06 23 minimum clock cycle time at cas latency = 2 10.0 ns a0 24 maximum data access time from clock for cl = 2 6.0 ns 60 25 minimum clock cycle time at cl = 1 not supported 00 26 maximum data access time from clock at cl = 1 not supported 00 27 minimum row precharge time t rp 20 ns 14 28 minimum row active to row active delay t rrd 16 ns 10 29 minimum ras to cas delay t rcd 20 ns 14
mosel vitelic V43648Z04VTG 5 V43648Z04VTG rev. 1.6 february 1999 absolute maximum ratings dc characteristics t a = 0 c to 70 c; v ss = 0 v; v dd , v ddq = 3.3v 0.3v 30 minimum ras pulse width t ras 45 ns 2d 31 module bank density (per bank) 64 mbyte 10 32 sdram input setup time 2.0 ns 20 33 sdram input hold time 1 ns 10 34 sdram data input setup time 2.0 ns 20 35 sdram data input hold time 1 ns 10 36-61 superset information (may be used in future) 00 62 spd revision revision 1 12 63 checksum for bytes 0 - 62 f4 64-125 manufacturers? information (optional) (ffh if not used) xx 126 max. frequency specification 100 mhz 64 127 100 mhz support details af 128+ unused storage location 00 parameter max. units voltage on vdd supply relative to v ss -1 to 4.6 v voltage on input relative to v ss -1 to 4.6 v operating temperature 0 to +70 c storage temperature -55 to 125 c power dissipation 8w symbol parameter limit values unit min. max. v ih input high voltage 2.0 v cc +0.3 v v il input low voltage ?.5 0.8 v v oh output high voltage (i out = ?.0 ma) 2.4 v v ol output low voltage (i out = 2.0 ma) 0.4 v i i(l) input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0v) ?0 40 m a i o(l) output leakage current (dq is disabled, 0v < v out < v cc ) ?0 40 m a spd-table for -10 pc modules: (continued) byte number function described sdp entry value hex value 100 mhz -10pc
6 V43648Z04VTG rev. 1.6 february 1999 mosel vitelic V43648Z04VTG capacitance t a = 0 c to 70 c; v dd = 3.3v 0.3v, f = 1 mhz standby and refresh currents 1 t a = 0 c to 70 c, v cc = 3.3v 0.3v symbol parameter limit values unit c i1 input capacitance (a0 to a11, ras , cas , we )20pf c i2 input capacitance (cs0 )25pf c icl input capacitance (clk0-clk1) 28 pf c i3 input capacitance (cke0) 20 pf c i4 input capacitance (dqmb0-dqmb7) 10 pf c i0 input/output capacitance (dq0-dq63) 10 pf c sc input capacitance (scl, sa0-2) 8 pf symbol parameter test conditions 8m x 64 unit note i cc 1 operating current burst length = 4, cl = 3 t rc > = t rc (min), t ck > = t ck (min), io = 0 ma 2 bank interleave operation 700 ma 1,2 i cc 2p precharged standby current in power down mode cke< = v il (max), t ck > = t ck (min) 24 ma i cc 2n precharged standby current in non-power down mode cke> = v ih (min), t ck > = t ck (min), input changed once in 3 cycles 160 ma cs = high i cc 3p active standby current in power down mode cke< = v il (max), t ck > = t ck (min) 24 ma i cc 3n active standby current in non-power down mode cke> = v ih (min), t ck > = t ck (min), input changed one time 230 ma cs = high i cc 4 burst operating current burst length = full page, t rc = infinite, cl = 3, t ck > = t ck (min), io = 0 ma 2 banks activated 700 ma 1, 2 i cc 5 auto refresh current t rc >= t rc (min) 735 ma 1,2 i cc 6 self refresh current cke = <0,2 v 8 ma 1,2 l-version 3.2 ma
mosel vitelic V43648Z04VTG 7 V43648Z04VTG rev. 1.6 february 1999 ac characteristics 3,4 t a = 0 to 70 c; v ss = 0v; v cc = 3.3v 0.3v, t t = 1 ns # symbol parameter limit values unit note -10 min. max. clock and clock enable 1t ck clock cycle time cas latency = 3 cas latency = 2 10 12 ns ns 2f ck system frequency cas latency = 3 cas latency = 2 100 100 mhz mhz 3t ac clock access time cas latency = 3 cas latency = 2 7 7 ns ns 4,5 4t ch clock high pulse width 3 ns 6 5t cl clock low pulse width 3 ns 6 6t cs input setup time 2.5 ns 7 7t ch input hold time 1 ns 7 8t cksp cke setup time (power down mode) 2.5 ns 8 9t cksr cke setup time (self refresh exit) 8 ns 9 10 t t transition time (rise and fall) 1 ns common parameters 11 t rcd ras to cas delay 24 ns 12 t rc cycle time 73 120k ns 13 t ras active command period 48 ns 14 t rp precharge time 24 ns 15 t rrd bank to bank delay time 20 ns 16 t ccd cas to cas delay time (same bank) 1 clk refresh cycle 17 t srex self refresh exit time 10 ?s9 18 t ref refresh period (4096 cycles) 64 ms 8 read cycle 19 t oh data out hold time 3 ns 4 20 t lz data out to low impedance time 0 ns 21 t hz data out to high impedance time 3 9 ns 10 22 t dqz dqm data out disable latency 2 clk write cycle 23 t dpl data input to precharge (write recovery) 2 clk 24 t dal data in to active/refresh 5 clk 11 25 t dqw dqm write mask latency 0 clk
8 V43648Z04VTG rev. 1.6 february 1999 mosel vitelic V43648Z04VTG notes: 1. the specified values are valid when addresses are changed no more than once during t ck (min.) and when no operation commands are registered on every rising clock edge during t rc (min). values are shown per module bank. 2. the specified values are valid when data inputs (dq?) are stable during t rc (min.). 3. all ac characteristics are shown for device level. an initial pause of 100 m s is required after power-up, then a precharge all banks command must be given followed by 8 auto refresh (cbr) cycles before the mode register set operation can begin. 4. ac timing tests have v il = 0.4v and v ih = 2.4v with the timing referenced to the 1.4v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown. specific tac and toh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1v / ns edge rate between 0.8v and 2.0v. 5. if clock rising time is longer than 1 ns, a time (t t /2 -0.5) ns has to be added to this parameter. 6. rated at 1.5v 7. if t t is longer than 1 ns, a time (t t -1) ns has to be added to this parameter. 8. any time that the refresh period has been exceeded, a minimum of two auto (cbr) refresh commands must be given to ?ake-up?the device. 9. self refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to t rc is satisfied once the self refresh exit command is registered. 10. referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. t dal is equivalent to t dpl + t rp . 1.4v 1.4v tsetup thold tac tac tlz toh thz clock input output 50 pf i/o z=50 ohm + 1.4 v 50 ohm 2.4v 0.4v t t tcl tch i/o measurement conditions for tac and toh 50 pf
mosel vitelic V43648Z04VTG 9 V43648Z04VTG rev. 1.6 february 1999 package diagram 144 pin sodimm 2.661 0.039 1.25 0.150 max. .787 typ. .157 1 pin 2 on backside pin 144 on backside 28 29 143 note: 1. all dimensions in inches.
mosel vitelic worldwide offices V43648Z04VTG mosel vitelic 3910 n. first street, san jose, ca 95134-1501 ph: (408) 433-6000 fax: (408) 433-0952 tlx: 371-9461 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. ?copyright 1999, mosel vitelic inc. 2/99 printed in u.s.a. u.s. sales offices u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 852-2665-4883 fax: 852-2664-7535 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 1 creation road i science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-578-3344 fax: 886-3-579-2838 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-3231801 fax: 65-3237013 japan wbg marine west 25f 6, nakase 2-chome mihama-ku, chiba-shi chiba 261-71 phone: 81-43-299-6000 fax: 81-43-299-6555 ireland & uk block a unit 2 broomfield business park malahide co. dublin, ireland phone: +353 1 8038020 fax: +353 1 8038049 germany (continental europe & israel ) 71083 herrenberg benzstr. 32 germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 southwestern suite 200 5150 e. pacific coast hwy. long beach, ca 90804 phone: 562-498-3314 fax: 562-597-2174 central & southeastern 604 fieldwood circle richardson, tx 75081 phone: 972-690-1402 fax: 972-690-0341
|
