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[ak4753] ms1311-e-00 2011/07 - 1 - general description the ak4753 is a two input, four out put audio codec with integrated digital signal processing. the outputs can be configured either as si ngle-ended or differential. an internal pll allows the chip to run in master clock free mode. the digital signal proce ssing block includes an alc/limiter, 5 configurable biquads for eq, volume control, and 4 th -order filters for each output channel to enable a variety of configurations. wide dynamic range is achieved with 96db s/n for the adc, and 103db s/n for the dac?s. a two-input 8-bit sar adc is integrated for processing of external potentiometers, supporting volume and bass control functions. a small external eep-rom is used to store the coefficient values for the dsp blocks. the ak4753 is controlled by an i 2 c control interface. features ? digital audio input interface ? data format: msb-first, two?s complement ? 16, 20, or 24-bits, i2s, msb justified, lsb justified, or dsp mode ? audio sampling rates: 8khz to 48khz ? analog audio input ? single-ended input stereo 24-bit audio adc ? s/n: 96db s/(n+d): 85db ? digital high-pass filter for dc-offset correction ? analog audio output ? four-channel 24-bit audio dac ? single-ended or differential output ? s/n: 103db s/(n+d): 88db ? 8-bit sar adc with two input selector ? digital mixer for balancing inputs ? digital signal processing block: dsp1, dsp2 independently ? configurable alc / limiter function ? volume control: 0db to -127db, 0.5db steps, mute ? pre-gain setting: 0db, +6db, +12db, +18db ? post-gain setting: 0db, +3.5db, +6db, +8db ? five programmable biquads for eq ? 4 th -order high-pass filter or low-pass filter ? integrated pll for master clock-free operation ? pll ? input frequency: 24.576mhz, 24m hz, 22.5792mhz, 12.288mhz, 12mhz, and 11.2896mhz (xti/mcki pin) 1fs (lrck pin), 32fs or 64fs (bick pin) ? input level: cmos or ac-coupled (xti/mcki pin) ? master clock input: 256fs, 512fs, 1024fs ? p i/f: i 2 c bus-slave (400khz fast-mode) ? eep-rom control i/f: i 2 c bus-master (400khz fast-mode) ? ta = -30 ~ +85c ? power supply: analog (avdd): 3.0 ~ 3.6v (typ 3.3v) digital (dvdd: 3.0 ~ 3.6v (typ 3.3v) ? package: 32 pin qfn (4 x 4 mm, 0.4mm pitch) 2-in, 4-out codec with dsp functions ak4753
[ak4753] ms1311-e-00 2011/07 - 2 - block diagram lrck bick sdti ainl ainr serial audio interface stereo adc dsp1 serial interface scl sda pdn test bypass dvdd vss2 avdd vss1 vcom datt dsp2 control eep control eescl eesda extee a/d sain1 sain2 lout1/lout+ dac1 rout1/lout- lout2/rout+/mout+ rout2/rout-/mout- dac2 flt x?tal oscillator xti/mcki xto pll reg reg t1 t2 t1 t2 muten sto hpf/lpf 4th order pre gain +18db limiter five biquads post gain +8db dsp block figure 1. block diagram
[ak4753] ms1311-e-00 2011/07 - 3 - ordering guide AK4753EN ? 30 +85 c 32 pin qfn (4 x 4 mm, 0.4mm pitch) akd4753 evaluation board for ak4753 pin layout nc xt o xti/mcki dvdd vss2 reg bypass nc bi ck lrck sdti s t o muten scl sda eescl vcom lout2/rout+/mout+ rout2/rout-/mout- rout1/lout- lout1/lout+ avdd vss1 ai nl eesd a e x tee pdn flt test sain1 sain2 a inr AK4753EN top view 25 2 6 27 28 29 30 31 32 24 23 22 1 16 1 5 14 13 12 11 10 9 21 20 19 2 3 4 5 6 7 8 18 17
[ak4753] ms1311-e-00 2011/07 - 4 - pin/function no. pin name i/o function 1 vcom o common voltage output pin this pin must be connected to vss1 with the capacitors of 2.2 f capacitor in series. lout2 o lch line-amp output 2 pin single-ended mode (spc1-0 bits = ?11?) rout+ o rch line-amp positive output pin differential mode (spc1- 0 bits = ?00?, ?01?) 2 mout+ o mono line-amp positive output pin differential mode ( spc1-0 bits = ?10?) rout2 o rch line-amp output 2 pin single-ended mode (spc1-0 bits = ?11?) rout ? o rch line-amp negative output pin differential mode (spc1- 0 bits = ?00?, ?01?) 3 mout ? o mono line-amp negative output pin differential mode ( spc1-0 bits = ?10?) rout1 o rch line-amp output 1 pin single-ended mode (spc1-0 bits = ?10?, ?11?) 4 lout ? o lch line-amp negative output pin differential mode (spc1- 0 bits = ?00?, ?01?) lout1 o lch line-amp output 1 pin single-ended mode (spc1-0 bits = ?10?, ?11?) 5 lout+ o lch line-amp positive output pin differential mode (spc1- 0 bits = ?00?, ?01?) 6 avdd - analog power supply pin, 3.0v ~ 3.6v 7 vss1 - ground 1 pin 8 ainl i l channel analog input pin 9 ainr i r channel analog input pin 10 sain2 i 8-bit sar adc analog input 2 pin 11 sain1 i 8-bit sar adc analog input 1 pin 12 test i test input pin this pin must be connected to vss2. 13 flt o pll loop filter pin this pin must be connected to vss1 with one resistor and one capacitor in series. 14 pdn i power down pin when ?l?, the ak4753 is in power-down mode and is held in reset. the ak4753 must be always reset upon power-up. 15 extee i eep-rom enable pin ?h?: eep-rom download mode ?l?: serial control mode 16 eesda i/o eep-rom control data input/output pin 17 eescl o eep-rom control data clock output pin 18 sda i/o control data input/output pin 19 scl i control data clock input pin 20 muten o mute control output pin. ?h?: normal operation ?l?: mute 21 sto o eep-rom status output pin ?h?: read error ?l?: no error 22 sdti i audio serial data input pin 23 lrck i/o input/output channel clock pin 24 bick i/o audio serial data clock pin 25 nc - no connect pin no internal bonding. this pin must be connected to vss2.
[ak4753] ms1311-e-00 2011/07 - 5 - no. pin name i/o function 26 xto o x?tal clock output pin xti i x?tal / external clock input pin 27 mcki i external master clock input pin 28 dvdd - digital power supply pin, 3.0v ~ 3.6v 29 vss2 - ground 2 pin 30 reg o regulator ripple filter pin this pin must be connected to vss2 with 2.2 f capacitor in series. 31 bypass i bypass control input pin ?h?: dsp bypass mode ?l?: normal operation 32 nc - no connect pin no internal bonding. this pin must be connected to vss2. note 1. all input pins except analog input pins (ainl, ainr, sain1, sain2) must not be left floating. handling of unused pin the unused i/o pins must be processed appropriately as below. classification pin name setting analog ainl, ainr, sain1, sain2, flt, lout1/lout+, rout1/lout-, lout2/rout+/mout+, rout2/rout-/mout- open xto, sda, eesda, eescl, muten, sto open digital lrck, bick, sdti, xti/mcki, extee, test, scl t hese pins must be connected to vss2.
[ak4753] ms1311-e-00 2011/07 - 6 - absolute maximum ratings (all vss pins =0v; note 2 ) parameter symbol min max units power supplies: analog digital avdd dvdd -0.3 -0.3 4.2 4.2 v v analog input voltage ( note 3 ) vina1 -0.3 avdd+0.3 v digital input voltage ( note 4 ) vind -0.3 dvdd+0.3 v input current, any pin except supplies iin -10 +10 ma ambient operating temperature ta -30 85 c storage temperature tstg -65 150 c note 2. all voltage with respect to ground. all vss pins must be connected to the common analog ground. note 3. ainl pin, ainr pin, sain1 pin, sain2 pin. note 4. bypass, pdn, eesda, xti/mcki, bick, lrck, sdti, scl, sda, test pins warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (all vss pins =0v; note 2 ) parameter symbol min typ max units power supplies ( note 5 ) analog digital difference avdd dvdd |dvdd-avdd| 3.0 3.0 - 3.3 3.3 0 3.6 3.6 0.3 v v v note 5. the power up sequence between avdd and dvdd is not critical. each power supplies should be powered up during the pdn pin = ?l?. avdd and dvdd must be the same voltage at the pdn pin = ?h?. the pdn pin should be ?h? after all power supplies are powered up. all power supplies should be powered on, only a part of these power supplies cannot be powered off. (power off means power supplies equal to ground or power supplies are floating.) do not turn off only the ak4753 under the condition that a surrounding device is powered on and the i2c bus is in use. warning: akm assumes no responsibility for the usage beyond the conditions in this datasheet.
confidential [ak4753] ms1311-e-00 2011/07 - 7 - analog characteristics (codec) (ta=25 c; avdd=dvdd=3.3v; vss1=vss2=0v; fs=44.1khz; bick=64fs; signal frequency=1khz; 24-bit data; measurement band width =20hz 20khz; unless otherwise specified) parameter min typ max units dac analog output characteristics: dac lout1/rout1, lout2/rout2 pins, single-ended mode (spc1-0 bits = ?11?), hpf=lpf=eq(5-biquads)=li miter=off, datt= 0db, r l =5k ? resolution - - 24 bits s/(n+d) (0dbfs) 75 85 - db dr (-60dbfs with a-weighted) 87 97 - db s/n (a-weighted) 87 97 - db interchannel isolation 80 95 - db interchannel gain mismatch - 0 0.5 db output voltage aout=0.68 x avdd 1.98 2.24 2.51 vpp load resistance (ac load) 5 - - k load capacitance - - 150 pf power supply rejection ratio ( note 6 ) - 50 - db dac analog output characteristics: dac lout+/-, rout+/- pins, differential mode (spc 1-0 bits = ?00?), hpf=lpf=eq(5-biquads)=li miter=off, datt= 0db, r l =5k ? s/(n+d) (0dbfs) 78 88 - db dr (-60dbfs with a-weighted) 93 103 - db s/n (a-weighted) 93 103 - db interchannel isolation 95 110 - db interchannel gain mismatch - 0 0.5 db output voltage aout=0.70 x avdd 2.08 2.31 2.54 vpp load resistance (ac load) 5 - - k load capacitance - - 150 pf power supply rejection ( note 6 ) - 50 - db adc to dac characteristics: ainl/ainr pins dac lout1/rout1, lout2/rout2 pins, single-ended mode (spc1-0 bits = ?11?), hpf=lpf=eq(5-biquads)=li miter=off, datt= 0db, r l =5k ? input voltage ain=0.8xavdd 2.38 2.64 2.90 vpp input resistance 24 35 - k s/(n+d) (-1dbfs) 73 84 - db dr (-60dbfs with a-weighted) 83 94 - db s/n (a-weighted) 83 94 - db adc to dac characteristics: ainl/ainr pins dac lout+/-, rout+/- pins, differential mode (spc1- 0 bits = ?00?, ?01?), hpf=lpf=eq(5-biquads)=li miter=off, datt= 0db, r l =5k ? input voltage ain=0.8xavdd 2.38 2.64 2.90 vpp input resistance 24 35 - k s/(n+d) (-1dbfs) 74 85 - db dr (-60dbfs with a-weighted) 85 96 - db s/n (a-weighted) 85 96 - db note 6. psrr is applied to avdd and dvdd with 1khz, 50mvpp.
confidential [ak4753] ms1311-e-00 2011/07 - 8 - parameter min typ max units power supplies all circuit power-up (pdn pin = ?h?) ( note 7 ) differential mode (spc1- 0 bits = ?00?) avdd - 5.8 8.7 ma dvdd - 4.2 6.3 ma single-ended mode (spc1-0 bits = ?11?) avdd - 9.0 13.5 ma dvdd - 4.6 6.9 ma power-down (pdn pin = ?l?) ( note 7 ) avdd + dvdd - 1 10 a note 7. pll master mode (mcki=12mhz), pmad =pmdig=pmlo1=pmlo2=pms ar=pmpll bits = ?1?. note 8. all digital input pins are fixed to dvdd or vss2. analog characteristics (8-bit sar adc) (ta=25 c; avdd=dvdd =3.3v; vss1=vss2=0v; unless otherwise specified) parameter min typ max units 8-bit sar adc characteristics resolution - 8 - bits no missing codes 7 8 - bits integral nonlinearity error - - 1 lsb differential nonlinearity error - - 1 lsb analog input voltage range 0 - avdd v offset error - - 1 lsb gain error - - 1 lsb accuracy ( note 9 ) - - 1.2 % potentiometer resistance ( figure 2 ) vr - - 100 k ? note 9. accuracy is the difference between the output code when 1.1v is input to sain1 or sain2 pin and the ?ideal? code at 1.1v. sain1/2 pin potentiometer vr sar adc avdd figure 2. potentiometer resistance
confidential [ak4753] ms1311-e-00 2011/07 - 9 - filter characteristics (ta =-30 ~ 85 c; avdd=dvdd=3.0v ~ 3.6v; fs=44.1khz; hpf=lpf=eq(5-biquads)=limiter=off) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 10 ) 0.16db pb 0 - 17.3 khz ? 0.66db - 19.4 - khz ? 1.1db - 19.9 - khz ? 6.9db - 22.1 - khz stopband sb 26.1 - - khz passband ripple pr - - 0.16 db stopband attenuation sa 73 - - db group delay ( note 11 ) gd - 15 - 1/fs group delay distortion gd - 0 - s adc digital filter (hpf): frequency response ? 3.0db fr - 0.9 - hz ? 0.1db - 6.0 - hz dac digital filter: passband ( note 12 ) 0.05db pb 0 - 20.0 khz ? 6.0db - 22.05 - khz stopband sb 24.1 - - khz passband ripple pr - - 0.05 db stopband attenuation sa 53 - - db group delay ( note 13 ) gd - 25 - 1/fs dac digital filter (lpf) + scf: frequency response: 0 20.0khz fr - 0.4 - db note 10. the passband and stopband frequencies scale with fs (system sampling rate). each response refers to that of 1khz. note 11. a calculating delay time which induced by digital filtering. this time is from the input of an analog signal to the setting of 24-bit data of both channels to the adc output register. note 12. the passband and stopband frequencies scale with fs (system sampling rate). each response refers to that of 1khz. note 13. a calculating delay time which induced by digital filtering. this time is from setting the 24-bit data of both channels to input register to the output of analog signal. dc characteristics (ta=-30 ~ 85 c; avdd=dvdd= 3.0v ~ 3.6v) parameter symbol min typ max units high-level input voltage vih 70 % dvdd - - v low-level input voltage vil - - 30 % dvdd v input voltage at ac c oupling (xti/mcki pin) ( note 14 ) vac 40%dvdd - - vpp high-level output voltage ( note 15 ) (iout = ? 100 a) voh dvdd ? 0.4 - - v low-level output voltage ( note 15 ) (except sda, eesda, eescl pins: iout = 100 a) vol - - 0.4 v (sda, eesda, eescl pins: iout = 3ma) vol - - 0.4 v input leakage current iin - - 10 a note 14. it is a case when ac coupling capa citor is connected to the xti/mcki pin. note 15. except xto pin.
confidential [ak4753] ms1311-e-00 2011/07 - 10 - switching characteristics (ta=-30 ~ 85 c, avdd= dvdd= 3.0v ~ 3.6v, c l =20pf; unless otherwise specified) parameter symbol min typ max units crystal resonator frequency fxtal 11.2896 - 12.288 mhz pll master mode (pll reference clock = xti/mcki pin) mcki input timing frequency fclk 11.2896 - 24.576 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns ac pulse width tacw 18.5 - - ns lrck output timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh - tbck - ns except dsp mode: duty cycle duty - 50 - % bick output timing period bcko bit = ?0? tbck - 1/(32fs) - ns bcko bit = ?1? tbck - 1/(64fs) - ns duty cycle dbck - 50 - % pll slave mode (pll reference clock = lrck pin) lrck input timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % bick input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns pll slave mode (pll reference clock = bick pin) lrck input timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % bick input timing period pll3-0 bits = ?0010? tbck - 1/(32fs) - ns pll3-0 bits = ?0011? tbck - 1/(64fs) - ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns
confidential [ak4753] ms1311-e-00 2011/07 - 11 - parameter symbol min typ max units external slave mode mcki input timing frequency 256fs fclk 1.8816 - 12.288 mhz 512fs fclk 3.7632 - 13.312 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck input timing frequency 256fs fs 7.35 - 48 khz 512fs fs 7.35 - 26 khz 1024fs fs 7.35 - 13 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % bick input timing period tbck 312.5 - - ns pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns external master mode mcki input timing frequency 256fs fclk 1.8816 - 12.288 mhz 512fs fclk 3.7632 - 13.312 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck output timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh - tbck - ns except dsp mode: duty cycle duty - 50 - % bick output timing period bcko bit = ?0? tbck - 1/(32fs) - ns bcko bit = ?1? tbck - 1/(64fs) - ns duty cycle dbck - 50 - %
confidential [ak4753] ms1311-e-00 2011/07 - 12 - parameter symbol min typ max units audio interface timing (dsp mode) master mode lrck ? ? to bick ? ? ( note 16 ) tdbf 0.5 x tbck ? 40 0.5 x tbck 0.5 x tbck +40 ns lrck ? ? to bick ? ? ( note 17 ) tdbf 0.5 x tbck ? 40 0.5 x tbck 0.5 x tbck +40 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns slave mode lrck ? ? to bick ? ? ( note 16 ) tlrb 0.4 x tbck - - ns lrck ? ? to bick ? ? ( note 17 ) tlrb 0.4 x tbck - - ns bick ? ? to lrck ? ? ( note 16 ) tblr 0.4 x tbck - - ns bick ? ? to lrck ? ? ( note 17 ) tblr 0.4 x tbck - - ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns audio interface timing (r ight/left justified & i 2 s) master mode bick ? ? to lrck edge ( note 18 ) tmblr ? 40 - 40 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns slave mode lrck edge to bick ? ? ( note 18 ) tlrb 50 - - ns bick ? ? to lrck edge ( note 18 ) tblr 50 - - ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns note 16. msbs, bckp bits = ?00? or ?11?. note 17. msbs, bckp bits = ?01? or ?10?. note 18. bick rising edge must not occur at the same time as lrck edge.
confidential [ak4753] ms1311-e-00 2011/07 - 13 - parameter symbol min typ max units control interface timing (i 2 c bus-slave): scl, sda pins ( note 19 ) scl clock frequency fscl1 - - 400 khz bus free time between transmissions tbuf1 1.3 - - s start condition hold time (prior to first clock pulse) thd1:sta 0.6 - - s clock low time tlow1 1.3 - - s clock high time thigh1 0.6 - - s setup time for repeated start condition tsu1:sta 0.6 - - s sda hold time from scl falling ( note 20 ) thd1:dat 0 - - s sda setup time from scl rising tsu1:dat 0.1 - - s rise time of both sda and scl lines tr1 - - 0.3 s fall time of both sda and scl lines tf1 - - 0.3 s capacitive load on bus cb1 - - 400 pf setup time for stop condition tsu1:sto 0.6 - - s pulse width of spike noise suppressed by input filter tsp1 0 - 50 ns eep-rom control interface timing (i 2 c bus-master): eescl, eesda pins ( note 19 ) eescl clock frequency fscl2 200 280 400 khz bus free time between transmissions tbuf2 1.3 - - s start condition hold time (prior to first clock pulse) thd:sta2 0.6 - - s clock low time tlow2 1.3 - - s clock high time thigh2 0.6 - - s setup time for repeated start condition tsu2:sta 0.6 - - s eesda hold time from eescl falling ( note 20 ) thd2:dat 0 - 0.9 s eesda setup time from eescl rising tsu2:dat 0.1 - - s rise time of both eesda and eescl lines tr2 - - 0.3 s fall time of both eesda and eescl lines tf2 - - 0.3 s capacitive load on bus cb2 - - 400 pf setup time for stop condition tsu2:sto 0.6 - - s pulse width of spike noise suppressed by input filter tsp2 0 - 50 ns power-down & reset timing pdn pulse width ( note 21 ) tpd 10 - - ms note 19. i 2 c-bus is a trademark of nxp b.v. note 20. data must be held long enough to bridge the 300ns-transition time of scl and eescl. note 21. the ak4753 can be reset by the pdn pin = ?l?.
confidential [ak4753] ms1311-e-00 2011/07 - 14 - timing diagram mcki input measurement point vss2 tacw t acw vss2 1/fclk 1000pf 100k vac figure 3. mcki ac coupling timing lrck 1/fclk mcki tclkh tclkl vih vil 1/fs tlrckh tlrckl 50%dvdd duty = tlrckh x fs x 100 tlrckl x fs x 100 bick tbck tbckh tbckl 50%dvdd dbck = tbckh / tbck x 100 tbckl / tbck x 100 figure 4. clock timing (pll/ext master mode) lrck bick 50%dvdd tdbf 50%dvdd tlrckh bick 50%dvdd (bckp = "0") (bckp = "1") tsds sdti vil tsdh vih figure 5. audio interface timing (pll/ext master mode, dsp mode, msbs = ?0?)
confidential [ak4753] ms1311-e-00 2011/07 - 15 - lrck bick 50%dvdd tdbf 50%dvdd tlrckh bick 50%dvdd (bckp = "1") (bckp = "0") tsds sdti vil tsdh vih figure 6. audio interface timing (pll/ext master mode, dsp mode, msbs = ?1?) lrck 50%dvdd bick 50%dvdd tsds sdti vil tsdh vih tmblr figure 7. audio interface timing (pll/ ext master mode, except dsp mode) 1/fs lrck vih tlrckh vil tbck bick tbckh tbckl vih vil tblr bick vih vil (bckp = "0") (bckp = "1") figure 8. clock timing (pll slave mode; pll reference clock = lrck or bick pin, dsp mode, msbs = ?0?)
confidential [ak4753] ms1311-e-00 2011/07 - 16 - 1/fs lrck vih tlrckh vil tbck bick tbckh tbckl vih vil tblr bick vih vil (bckp = "1") (bckp = "0") figure 9. clock timing (pll slave mode; pll reference clock = lrck or bick pin, dsp mode, msbs = ?1?) lrck bick tsds sdti vil tsdh vih tlrb tlrckh msb vil vih vil vih bick vil vih (bckp = "0") (bckp = "1") figure 10. audio interface timing (pll slave mode, dsp mode; msbs = ?0?) lrck bick tsds sdti vil tsdh vih tlrb tlrckh msb vil vih vil vih bick vil vih (bckp = "1") (bckp = "0") figure 11. audio interface timing (pll slave mode, dsp mode, msbs = ?1?)
confidential [ak4753] ms1311-e-00 2011/07 - 17 - 1/fclk mcki tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil tlrckh tlrckl duty = tlrckh x fs x 100 tlrckl x fs x 100 figure 12. clock timing (ext slave mode) lrck vih vil tblr bick vih vil tlrb tsds sdti vil tsdh vih figure 13. audio interface timing (pll/ ext slave mode, except dsp mode) stop start start stop thigh thd:dat sda scl tbuf tlow tr tf tsu:dat vih vil thd:sta tsu:sta vih vil tsu:sto tsp figure 14. i 2 c bus mode timing tpd pdn vil figure 15. power down & reset timing
[ak4753] ms1311-e-00 2011/07 - 18 - operation overview overview of ak4753 the ak4753 is an audio codec with integrated digital signal processors. it is easy to use since the two inputs 8-bit sar adc and eep-rom i/f are integrated. the sar adc has 2-channel input selector and the ad conversion is executed sequentially. the sain1 value is used to control the internal datt. the sain2 value is used to control the gain of the eq. when the analog input of the sain1/2 changes, the register value of the datt/eq is changed automatically. this external eep-rom is used to store the coefficient values for the dsp blocks, and the setting data. when the ak4753 is powered up, it reads the data in eep-rom at firs t, and maps these values into the internal registers. the following contents are stored in eep-rom. a. fundamental function -output configuration setting (stereo m ode, 2.1-channel mode or 4-channel mode) -pll mode setting: master or slave, pll reference clock, sampling frequency -audio interface format -datt -post-gain and pre-gain setting for dsp1/2 -limiter setting for dsp1/2 b. coefficient data for dsp1/2 -coefficient data of lpf/hpf -coefficient data of five biquads
[ak4753] ms1311-e-00 2011/07 - 19 - system clock there are the following four methods to interface with external devices. ( table 1 , table 2 ) mode pmpll bit m/s bit pll3-0 bits figure pll master mode 1 1 table 4 figure 20 figure 21 pll slave mode (pll reference clock: lrck or bick pin) 1 0 table 4 figure 22 figure 23 ext slave mode 0 0 x figure 24 ext master mode 0 1 x figure 25 figure 26 table 1. clock mode setting (x: don?t care) mode xti/mcki pin bick pin lrck pin pll master mode selected by pll3-0 bits output (selected by bcko bit) output (1fs) pll slave mode (pll reference clock: lrck or bick pin) gnd input (selected by pll3-0 bits) input (1fs) ext slave mode selected by fs1-0 bits input ( 32fs) input (1fs) ext master mode selected by fs1-0 bits output (selected by bcko bit) output (1fs) table 2. clock pins state in clock mode master mode/slave mode the m/s bit selects either master or sl ave mode. m/s bit = ?1? selects master mode and ?0? selects slave mode. when the ak4753 is in power-down mode (pdn pin = ?l?) and when exits reset state, the ak4753 is in slave mode. after exiting reset state, the ak4753 goes to master mode by changing m/s bit = ?1?. when the ak4753 is in master mode, the lrck and bick pins are a floating state until m/s bit becomes ?1?. the lrck and bick pins of the ak4753 must be pulled-down or pulled-up by the resistor (about 100k ) externally to avoid the floating state. m/s bit mode 0 slave mode (default) 1 master mode table 3. select master/slave mode
[ak4753] ms1311-e-00 2011/07 - 20 - crystal oscillator circuit a clock for the xti/mcki pin can be generated by the following three methods. 1. x?tal mode (pwxtal bit= ?1?) xti xto ak4683 160k c c (typ) figure 16. x?tal mode note: the value of the capacitor de pends on a crystal (typ.10-40pf). 2. external clock mode (pwxtal bit= ?1?) note: do not input a clock beyond the voltage of dvdd. xti/mcki xto ak4683 external clock 160k (typ) xti/mcki xto ak4683 external clock c 160k (typ) figure 17. direct connection figure 18. ac coupling connection (input: cmos level) (input: 40%dvdd, c=1000pf) 3. off mode of xti/mcki, xto pins (pwxtal bit= ?0?) xti/mcki xto ak4683 160k (typ) figure 19. off mode ak4753 ak4753 ak4753 ak4753
[ak4753] ms1311-e-00 2011/07 - 21 - pll mode (pmpll bit = ?1?) when pmpll bit = ?1?, the bu ilt-in high precision pll work s according to the clock which is set by fs3-0 bits and pll3-0 bits. the pll lock time is shown in table 4 , whenever the ak4753 is supplied to a stable clock after pll is powered-up (pmpll bit = ?0? ?1?) or sampling fre quency changes. 1. pll mode setting flt pin rp, cp mode pll3 bit pll2 bit pll1 bit pll0 bit pll reference clock input pin input frequency rp[ ] cp[f] pll lock time (max) 0 0 0 0 0 lrck pin 1fs 10k 100n 40 ms (default) 1 0 0 1 0 bick pin 32fs 10k 4.7n 4 ms 2 0 0 1 1 bick pin 64fs 10k 4.7n 4 ms 3 0 1 0 0 xti/mcki pin 11.2896mhz 10k 4.7n 4 ms 4 0 1 0 1 xti/mcki pin 12.288mhz 10k 4.7n 4 ms 5 0 1 1 0 xti/mcki pin 12mhz 10k 4.7n 4 ms 6 0 1 1 1 xti/mcki pin 24mhz 10k 4.7n 4 ms 7 1 1 0 0 xti/mcki pin 22.5792mhz 10k 4.7n 4 ms 8 1 1 0 1 xti/mcki pin 24.576mhz 10k 4.7n 4 ms others others n/a (*fs: sampling frequency, n/a: not available) table 4. pll mode setting 2. sampling frequency setting in pll mode in the case of pll2 bit = ?1?, and the reference clock is in put to the xti/mcki pin or the crystal oscillator circuit is used, the sampling frequency can be set according to table 5 . mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency 0 0 0 0 0 8khz (default) 1 0 0 0 1 12khz 2 0 0 1 0 16khz 3 0 0 1 1 24khz 4 0 1 0 0 7.35khz 5 0 1 0 1 11.025khz 6 0 1 1 0 14.7khz 7 0 1 1 1 22.05khz 10 1 0 1 0 32khz 11 1 0 1 1 48khz 14 1 1 1 0 29.4khz 15 1 1 1 1 44.1khz others others n/a (reference clock = xti/mcki pin) (n/a: not available) table 5. sampling frequency setting (pmpll bit = ?1?) in the case of pll2 bit = ?0? and the reference clock is input to the lrck or bick pins, the sampling frequency is set by fs3 and fs2 bits according to table 6. mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency range 0 0 0 x x 7.35khz fs 12khz (default) 1 0 1 x x 12khz < fs 24khz 2 1 0 x x 24khz < fs 48khz others others n/a (pll reference: clock: lrck or bick pin) (x: don?t care, n/a: not available) table 6. sampling frequency setting (pll2 bit = ?0? and pmpll bit = ?1?)
[ak4753] ms1311-e-00 2011/07 - 22 - pll un-lock 1. pll master mode (pmpll bit = ?1?, m/s bit = ?1?) in this mode, the bick and lrck pins go to ?l? befo re the pll goes to lock state after pmpll bit = ?0? ?1? ( table 7 ). after the pll is locked, a first period of lrck and bick may be invalid clock, but these clocks return to normal state after a period of 1/fs. when sampling frequency is changed, the bick and lrck pins do not output irregular frequency clocks but go to ?l? by setting pmpll bit to ?0?. pll state bick pin lrck pin pmpll bit ?0? ? ?1? ?l? output ?l? output pll unlock (except for the above) not fixed not fixed pll lock table 8 1fs output table 7. clock operation at pll master mode (pmpll bit = ?1?, m/s bit = ?1?) pll master mode (pmpll bit = ?1?, m/s bit = ?1?) when an external clock (11.2896mhz, 12mhz, 12.288mhz, 22.5792mhz, 24mhz or 24.576mhz) is input to the xti/mcki pin or the crystal oscillator circuit is used, the bick and lrck clocks are generated by an internal pll circuit. the bick output frequency is sel ected between 32fs or 64fs, by bcko bit ( table 8 ). ak4753 dsp bick lrck sdti bclk lrck sdto mcki 1fs 32fs, 64fs 11.2896mhz, 12mhz, 12.288mhz 22.5792mhz, 24mhz, 24.576mhz figure 20. pll master mode (external clock mode) ak4753 dsp bick lrck sdti bclk lrck sdto xti 1fs 32fs, 64fs x?tal 11.2896mhz, 12mhz, 12.288mhz 22.5792mhz, 24mhz, 24.576mhz xto figure 21. pll master mode (x?tal mode) bcko bit bick output frequency 0 32fs 1 64fs (default) table 8. bick output frequency at master mode
[ak4753] ms1311-e-00 2011/07 - 23 - pll slave mode (pmpll bit = ?1?, m/s bit = ?0?) a reference clock of pll is selected among the input clocks to the bick or lrck pin. required clock for the ak4753 is generated by an internal pll circuit. in put frequency is selected by pll3-0 bits ( table 4 ). sampling frequency corresponds to a range from 7.35khz to 48khz by changing fs3-0 bits ( table 6 ). ak4753 dsp mcki bick lrck sdti bclk lrck sdto 1fs 32fs or 64fs figure 22. pll slave mode (pll reference clock: bick pin) ak4753 dsp mcki bick lrck sdti bclk lrck sdto 1fs 32fs figure 23. pll slave mode (pll reference clock: lrck pin) ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) when pmpll bit is ?0?, the ak4753 changes to ext mode. master clock is input from the xti/mcki pin, the internal pll circuit is not operated. this mode is compatible with i/f of a normal audio codec. the clocks required to operate the ak4753 are mcki (256fs, 512fs or 1024fs), lrck (fs) and bick ( 32fs). the master clock (mcki) should be synchronized with lrck. the phase between these clocks is not important. the input frequency of mcki is selected by fs1-0 bits ( table 9 ). mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 x 0 0 256fs 7.35khz 48khz (default) 1 x 0 1 1024fs 7.35khz 13khz 2 x 1 0 512fs 7.35khz 26khz 3 x 1 1 512fs 7.35khz 26khz table 9. mcki frequency at ext slave mode (p mpll bit = ?0?, m/s bit = ?0?) (x: don?t care)
[ak4753] ms1311-e-00 2011/07 - 24 - the s/n of the dac at low sampling frequencies is worse th an at high sampling frequencies due to out-of-band noise. the out-of-band noise can be improved by using higher frequency of the master clock. the s/n of the dac output through lout1/rout1 and lout2/rout2 pins is shown in table 10 . mcki s/n (fs=8khz, 20khzlpf + a-weighted) 256fs 87 db 512fs 96 db 1024fs 97 db table 10. relationship between mcki and s/n of lout1/rout1 and lout2/rout2 pins (spc1-0 bits = ?00?) ak4753 dsp mcki bick lrck sdti bclk lrck sdto 1fs 32fs mclk 256fs, 512fs or 1024fs figure 24. ext slave mode ext master mode (pmpll bit = ?0?, m/s bit = ?1?) the ak4753 becomes ext master mode by setting pmpll bit = ?0? or the m/s bit = ?1?. master clock is input from the xti/mcki pin or the crystal oscillator circuit is used, the internal pll circuit is not operated. the clock required to operate the ak4753 is xti/mcki (256fs, 512fs or 1024fs). the input frequency of xti/mcki is selected by fs1-0 bits ( table 11 ). mode fs3-2 bits fs1 bit fs0 bit xti/mcki input frequency sampling frequency range 0 x 0 0 256fs 7.35khz 48khz (default) 1 x 0 1 1024fs 7.35khz 13khz 2 x 1 0 512fs 7.35khz 26khz 3 x 1 1 512fs 7.35khz 26khz table 11. xti/mcki frequency at ext master mode (pmpll bit = ?0?, m/s bit = ?1?) (x: don?t care) the s/n of the dac at low sampling frequencies is worse th an at high sampling frequencies due to out-of-band noise. the out-of-band noise can be improved by using higher frequency of the master clock. the s/n of the dac output through lout1/rout1 and lout2/rout2 pins is shown in table 12 . xti/mcki s/n (fs=8khz, 20khzlpf + a-weighted) 256fs 87 db 512fs 96 db 1024fs 97 db table 12. relationship between xti/mcki and s/n of lout1/rout1 and lout2/rout2 pins (spc1-0 bits = ?00?)
[ak4753] ms1311-e-00 2011/07 - 25 - ak4753 dsp mcki bick lrck sdti bclk lrck sdto 1fs 32fs or 64fs mclk 256fs, 512fs or 1024fs figure 25. ext master mode (external clock mode) ak4753 dsp bick lrck sdti bclk lrck sdto xti 1fs 32fs, 64fs x?tal 256fs, 512fs or 1024fs xto figure 26. ext master mode (x?tal mode) bcko bit bick output frequency 0 32fs 1 64fs (default) table 13. bick output frequency at master mode
[ak4753] ms1311-e-00 2011/07 - 26 - system reset upon power-up, the ak4753 must be reset by bringing the pdn pin = ?l?. this ensures that all internal registers reset to their initial values. the pdn pin must be set to ?l? at power-up. when pmadc bit is changed from ?0? to ?1?, the initialization cycle of adc starts. the adc outputs settle to data correspondent to the input signals after the end of initialization. the time from the input of analog signals to the output of analog signals including the initialization cycle of adc is 1098 /fs=25ms@fs= 44.1khz. audio interface format eight types of the data formats are available and are selected by setting the dif2-0 bits ( table 14 ). in all modes, the serial data is msb first, 2?s compleme nt format. audio interface formats can be used in both master mode and slave mode. lrck and bick are output from the ak4753 in master mode, but must be input to the ak4753 in slave mode. mode dif2 bit dif1 bit dif0 bit sdti lrck bick figure 0 0 0 0 16-bit dsp mode h/l 32fs table 15 1 0 0 1 16-bit lsb justified h/l 32fs figure 31 2 0 1 0 16/20/24-bit msb justified h/l 32fs or 48fs figure 33 3 0 1 1 16/20/24-bit i 2 s compatible l/h 32fs or 48fs figure 34 (default) 4 1 0 0 20-bit lsb justified h/l 40fs figure 32 5 1 0 1 24-bit lsb justified h/l 48fs figure 32 6 1 1 0 20-bit dsp mode h/l 48fs table 16 7 1 1 1 24-bit dsp mode h/l 48fs table 17 table 14. audio interface format in mode 1/2/3/4/5, the sdti is latched on the rising edge (? ?) of bick. in modes 0/6/7 (dsp mode), the audio i/f timing is changed by bckp and msbs bits. when bckp bit = ?0?, the sdti is latched on the falling edge (? ?) of bick. when bckp bit = ?1?, the sdti is latched on the rising edge (? ?) of bick. msbs bit can shift the position of the msb data of sd ti to the position of the half cycle of the bick.
[ak4753] ms1311-e-00 2011/07 - 27 - dif2 dif1 dif0 msbs bckp audio interface format figure 0 0 msb data of sdti is latched on the falling edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 27 (default) 0 1 msb data of sdti is latched on the rising edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 28 1 0 msb data of sdti is latched on the falling edge (? ?) of the first bick after the falling edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 29 0 0 0 1 1 msb data of sdti is latched on the rising edge (? ?) of the first bick after the rising edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 30 table 15. audio interf ace format in mode 0 dif2 dif1 dif0 msbs bckp audio interface format figure 0 0 msb data of sdti is latched on the falling edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 35 (default) 0 1 msb data of sdti is latched on the rising edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 36 1 0 msb data of sdti is latched on the falling edge (? ?) of the first bick after the falling edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 37 1 1 0 1 1 msb data of sdti is latched on the rising edge (? ?) of the first bick after the rising edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 38 table 16. audio interf ace format in mode 6 dif2 dif1 dif0 msbs bckp audio interface format figure 0 0 msb data of sdti is latched on the falling edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 39 (default) 0 1 msb data of sdti is latched on the rising edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 40 1 0 msb data of sdti is latched on the falling edge (? ?) of the first bick after the falling edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 41 1 1 1 1 1 msb data of sdti is latched on the rising edge (? ?) of the first bick after the rising edge (? ?) of the first bick after the rising edge (? ?) of lrck. figure 42 table 17. audio interf ace format in mode 7
[ak4753] ms1311-e-00 2011/07 - 28 - lrck (master) lrck (slave) 1/fs 15:msb, 0:lsb 63 0 1 2 14 15 16 17 22 23 24 25 26 30 31 32 33 34 35 36 37 bick(64fs) sdti(i) lch rch 59 60 61 62 63 15 14 13 1 0 15 9 8 7 6 1 0 0 figure 27. mode 0 timing (bckp bit= ?0?, msbs bit= ?0?) lrck (master) lrck (slave) 1/fs 15:msb, 0:lsb 63 0 1 2 14 15 16 17 22 23 24 25 26 30 31 32 33 34 35 36 37 bick(64fs) sdti(i) lch rch 59 60 61 62 63 15 14 13 1 0 15 9 8 7 6 1 0 0 figure 28. mode 0 timing (bckp bit= ?1?, msbs bit= ?0?) 1/fs 15:msb, 0:lsb 63 0 1 2 14 15 16 17 22 23 24 25 26 30 31 32 33 34 35 36 37 bick(64fs) sdti(i) lch rch 59 60 61 62 63 15 14 13 1 0 15 9 8 7 6 1 0 0 lrck (master) lrck (slave) figure 29. mode 0 timing (bckp bit= ?0?, msbs bit= ?1?) 1/fs 15:msb, 0:lsb 63 0 1 2 14 15 16 17 22 23 24 25 26 30 31 32 33 34 35 36 37 bick(64fs) sdti(i) lch rch 59 60 61 62 63 15 14 13 1 0 15 9 8 7 6 1 0 0 lrck (master) lrck (slave) figure 30. mode 0 timing (bckp bit= ?1?, msbs bit= ?1?)
[ak4753] ms1311-e-00 2011/07 - 29 - lrck 31 0 1 15 16 23 24 31 0 1 15 16 23 24 31 bick(64fs) sdti(i) mode1 0 1 2 3 4 15 14 8 7 13 0 15 8 7 0 don?t care don?t care don?t care lch data rch data 15:msb, 0:lsb figure 31. mode 1 timing lrck 31 0 1 8 12 23 31 0 1 8 12 23 31 bick(64fs) sdti(i) mode4 19:msb, 0:lsb 0 1 2 3 4 19 8 0 19 8 1 0 19 5 23:msb, 0:lsb don?t care don?t care don?t care lch data rch data sdti(i) mode5 23 19 20 8 0 23 19 8 1 0 22 21 20 19 don?t care don?t care don?t care figure 32. mode 4/5 timing lrck bick sdti(i) 16bit 14 0 don?t 14 13 12 11 15 15 lch data rch data sdti(i) 20bit 18 4 20 0 don?t 18 17 16 15 19 19 sdti(i) 24bit 22 8 4 20 0 don?t 22 21 20 19 23 23 14 0 don?t 15 18 4 20 0 don?t 19 22 8 4 20 0 don?t 23 figure 33. mode 2 timing lrck bick sdti(i) 16bit 14 0 don?t 14 13 12 11 15 15 lch data rch data sdti(i) 20bit 18 4 20 0 don?t 18 17 16 15 19 19 sdti(i) 24bit 22 8 4 20 0 don?t 22 21 20 19 23 23 14 0 don?t 15 18 4 20 0 don?t 19 22 8 4 20 0 don?t 23 figure 34. mode 3 timing
[ak4753] ms1311-e-00 2011/07 - 30 - lrck (master) lrck (slave) 1/fs 19:msb, 0:lsb 63 0 1 2 14 20 21 23 24 25 26 27 37 38 39 40 41 42 43 44 45 bick(64fs) sdti(i) lch 46 61 62 63 19 18 17 0 19 16 15 14 13 9 2 1 0 0 rch figure 35. mode 6 timing (bckp bit= ?0?, msbs bit= ?0?) lrck (master ) lrck (slave) 1/fs 19:msb, 0:lsb 63 0 1 2 14 20 21 23 24 25 26 27 37 38 39 40 41 42 43 44 45 bick(64fs) sdti(i) lch 46 61 62 63 19 18 17 0 19 16 15 14 13 9 2 1 0 rch 0 figure 36. mode 6 timing (bckp bit= ?1?, msbs bit= ?0?) lrck (master) lrck (slave) 1/fs 19:msb, 0:lsb 63 0 1 2 14 20 21 23 24 25 26 27 37 38 39 40 41 42 43 44 45 bick(64fs) sdti(i) lch 46 61 62 63 19 18 17 0 19 16 15 14 13 9 2 1 0 rch 0 figure 37. mode 6 timing (bckp bit= ?0?, msbs bit= ?1?) lrck (master) lrck (slave) 1/fs 19:msb, 0:lsb 63 0 1 2 14 20 21 23 24 25 26 27 37 38 39 40 41 42 43 44 45 bick(64fs) sdti(i) lch 46 61 62 63 19 18 17 20 19 16 15 14 13 9 2 1 0 rch 0 figure 38. mode 6 timing (bckp bit= ?1?, msbs bit= ?1?)
[ak4753] ms1311-e-00 2011/07 - 31 - lrck (master) lrck (slave) 1/fs 23:msb, 0:lsb 63 0 1 2 14 20 21 23 24 25 26 27 37 38 39 40 41 46 47 48 49 bick(64fs) sdti(i) 50 61 62 63 0 23 22 21 4 3 0 23 22 21 1 10 9 8 7 2 1 lch rch 0 figure 39. mode 7 timing (bckp bit= ?0?, msbs bit= ?0?) lrck (master) lrck (slave) 1/fs 23:msb, 0:lsb 63 0 1 2 14 20 21 23 24 25 26 27 37 38 39 40 41 46 47 48 49 bick(64fs) sdti(i) 50 61 62 63 0 23 22 21 4 3 0 23 22 21 1 10 9 8 7 2 1 lch rch 0 figure 40. mode 7 timing (bckp bit= ?1?, msbs bit= ?0?) lrck (master) lrck (slave) 1/fs 23:msb, 0:lsb 63 0 1 2 14 20 21 23 24 25 26 27 37 38 39 40 41 46 47 48 49 bick(64fs) sdti(i) 50 61 62 63 0 23 22 21 4 3 0 23 22 21 1 10 9 8 7 2 1 lch rch 0 figure 41. mode 7 timing (bckp bit= ?0?, msbs bit= ?1?) lrck (master) lrck (slave) 1/fs 23:msb, 0:lsb 63 0 1 2 14 20 21 23 24 25 26 27 37 38 39 40 41 46 47 48 49 bick(64fs) sdti(i) 50 61 62 63 0 23 22 21 4 3 0 23 22 21 1 10 9 8 7 2 1 lch rch 0 figure 42. mode 7 timing (bckp bit= ?1?, msbs bit= ?1?)
[ak4753] ms1311-e-00 2011/07 - 32 - dsp input signals setting the ak4753 has three input sources for dsp. the inputs of digital, analog and mix signals can be changed by sel1-0 bits. in the initialization, the setting is sel1-0 bits = ?00? (analog input). digital-in adc dsp block sw1 sel1-0 bits mix figure 43. dsp input source sel1 bit sel0 bit dsp input source note 0 0 analog default 0 1 digital 1 0 mix (analog source)/2 + digital source/2 1 1 n/a table 18. dsp input setting (n/a: not available) bypass mode the ak4753 has a bypass pin for the dsp bypass mode. when the bypass pin is ?l?, the dsp blocks are enabled. when the bypass pin is ?h?, the dsp blocks are disabled and the datt outputs are skipped over the dsp blocks to the dac. bypass pin mode h dsp bypass mode l normal operation table 19. bypass mode datt dsp1 dac1 dsp2 dac2 bypass pin ?h? ?l? ?h? ?l? ?l? ?h? ?l? ?h? mix l+r 2 figure 44. bypass mode
[ak4753] ms1311-e-00 2011/07 - 33 - the ak4753 has a mute control output pin (muten pin) for external speaker amplifier. in order to prevent a pop noise through the ak4753, the mtuen pin is connected to a mute pin or a standby pin of the external speaker amplifier. bypass pin muten pin dsp status on off h l h l lout/rout pins (1) (2) (3) (4) (2) (5) 2ms (typ) 2ms (typ) 2ms (typ) 2ms (typ) figure 45. bypass mode control sequence (1) when the bypass pin turns ?h?, the muten pin is set ?l?. (2) pop noise occuers after 2ms(@fs=48khz), when the dsp bypass mode is changed. (3) dsp bypass mode is chaneged, then the mu ten pin is set ?h? af ter 2ms(@fs=48khz). (4) when the bypass pin turns ?l?, the muten pin is set ?l?. (5) dsp bypass mode is chaneged, then the mu ten pin is set ?h? af ter 2ms(@fs=48khz).
[ak4753] ms1311-e-00 2011/07 - 34 - audio dac outputs configurations the ak4753 has three modes as audio dac configurations; stereo mode, 2.1-channels mode and 4-channels mode. each mode is selected by spc1-0 bits. in the initializati on, the setting of the spc1-0 bits is ?00? (stereo mode). digital-in adc datt dsp1 for l1, r1 hpf, lpf eq, limiter dac1 dig dsp2 for l2, r2 hpf, lpf eq, limiter dac2 dig l1, r1 sw1 sw2 1 0 sel1-0 bits spc1-0 bits sw3 dac1l ana dac2l ana dac1r ana dac2r ana sw4 0: r1 or r1+r2 ? dac2l or 2r2 or m 0: l1, r1 1: l1+l2, r1+r2 l1+m, r1+m l1+l2, r1+r2 0: l, r 1: m, m 0 1 0 1 sw2, 3, 4, 5, 6 1: l2 or m l2, r2 or m, m or l, r l1 or l1+l2 ? dac1l or r1 sw5 0 1 sw6 0 ? 1 or r1+r2 or r1+m + + l+r 2 pmdig pmlo2 pmlo1 mix ? m = figure 46. block diagram of signal path
[ak4753] ms1311-e-00 2011/07 - 35 - 1. stereo mode (spc1-0 bits = ?00?: sw2 = ?0?, sw3= ?0?, sw4= ?0?, sw5= ?0?, sw6= ?0?) table 20 shows the signal status and output condition when spc1-0 bits= ?00?. this output configuration is suitable for a traditional stereo speaker system. refer to the figure 55 for functions and signal paths of the dsp block. digital-in adc datt dsp1 for l1, r1 hpf, lpf eq, limiter dac1 dig dsp2 for l2, r2 hpf, lpf eq, limiter dac2 dig l1, r1 sw1 sw2 1 0 sel1-0 bit spc1-0 bit sw3 dac1l ana dac2l ana dac1r ana dac2r ana sw4 0: l1, r1 0 1 0 1 sw2, 3, 4, 5, 6 l, r l1+ sw5 0 ? 1 sw6 0 ? 1 + + l1 ? r1+ r1 ? mix figure 47. block diagram for signal path (spc1-0 bits =?00?) output setting signal and output block spc1 bit spc0 bit audio signal polarity dac pin output + dac1l lout+ l1+ l1 ? dac1r lout ? l1 ? + dac2l rout+ r1+ 0 (default) 0 (default) r1 ? dac2r rout ? r1 ? table 20. stereo mode setting and output signal details block2 block1 ak4753 lout+ l ch r ch lout ? rout+ rout ? analog source l ch r ch a nalog-in digital source digital-in l1 r1 2-channel (full-differential) figure 48. 2-channels (stereo) mode
[ak4753] ms1311-e-00 2011/07 - 36 - 2. stereo mode (hpf, lpf individual mode) (spc1-0 bits = ?01?: sw2 = ?0?, sw3= ?1?, sw4= ?0?, sw5= ?0?, sw6= ?0?) table 21 shows the signal status and output condition when spc1- 0 bits = ?01?. this output configuration is suitable for a stereo speaker system which needs i ndividual effects of dsp. l1(hi), l2(lo), r1 (hi) and r2 (lo) is an example of the dsp setting. l1(hi), r1(hi) are signals which were after hpf in dsp1. and l2(lo), r2(lo) are signals which were applied lpf in dsp2. refer to the figure 55 for functions and signal paths of the dsp block. digital-in adc datt dsp1 for l1, r1 hpf, lpf eq, limiter dac1 dig dsp2 for l2, r2 hpf, lpf eq, limiter dac2 dig l1, r1 sw1 sw2 1 0 sel1-0 bit spc1-0 bit sw3 dac1l ana dac2l ana dac1r ana dac2r ana sw4 1: l1+l2, r1+r2 l1+l2, r1+r2 0: l, r 0 1 0 1 sw2, 3, 4, 5, 6 l2, r2 l, r +( l1+l2 ) sw5 0 ? 1 sw6 0 ? 1 + + ? ( l1+l2 ) +( r1+r2 ) ? ( r1+r2 ) mix figure 49. block diagram for signal path (spc1-0 bits = ?01?) output setting signal and output block spc1 bit spc0 bit audio signal polarity dac pin output + dac1l lout+ l+ l1(hi)+l2(lo) ? dac1r lout ? l ? + dac2l rout+ r+ 0 1 r1(hi)+r2(lo) ? dac2r rout ? r ? table 21. stereo mode setting and output signal status details block2 block1 ak4753 lout+ l ch r ch lout ? rout+ rout ? analog source l ch r ch a nalog-in digital source digital-in l1+l2 r1+r2 2-channel (full-differential) figure 50. 2-channels (stereo) mode
[ak4753] ms1311-e-00 2011/07 - 37 - 3. 2.1-channels mode (spc1-0 bits = ?10?: sw2 = ?1?, sw3= ?0?, sw4= ?1?, sw5= ?1?, sw6= ?0?) table 22 shows the signal status and output condition when spc1- 0 bits = ?10?. this output configuration is suitable for a 2.1 channel application with a subwoofer. sw output is an example of the dsp setting. l1(hi), r1(hi) are signals which were after hpf in dsp1. m(lo) is signal whic h was after lpf in dsp2. refer to the figure 55 for functions and signal paths of the dsp block. digital-in adc datt dsp1 for l1, r1 hpf, lpf eq, limiter dac1 dig dsp2 for l2, r2 hpf, lpf eq, limiter dac2 dig l1, r1 sw1 sw2 1 sel1-0 bit spc1-0 bit sw3 dac1l ana dac2l ana dac1r ana dac2r ana sw4 0: l1, r1, 1: m, m 0 1 sw2, 3, 4, 5, 6 m, m l, r l1 sw5 ? 1 sw6 0 ? + + r1 + m ? m l+r 2 mix m = figure 51. block diagram for signal path (spc1-0 bits = ?10?) output setting signal and output block spc1 bit spc0 bit audio signal polarity dac pin output non dac1l lout1 l l1(hi)+r1(hi) non dac1r rout1 r + dac2l lout2 sw+ 1 0 m(lo) ? dac2r rout2 sw ? table 22. 2.1-channels mode setting and output signal status details (sw: subwoofer, m: mono mix) block2 block1 ak4753 lout1 l ch sw ch rout1 mout+ mout ? analog source l ch r ch a nalog-in digital source digital-in l1,r1 m r ch 1-channel (full-differential) 2-channel (single-ended) figure 52. 2.1-channels mode (sw: subwoofer, m: mono mix)
[ak4753] ms1311-e-00 2011/07 - 38 - 4. 4-channels mode (spc1-0 bits = ?11?: sw2 = ?0?, sw3= ?0?, sw4= ?1?, sw5= ?1?, sw6= ?1?) table 23 shows the signal status and output condition when spc1-0 bits = ?11?. this output configuration is suitable for a two-way speaker system. l1(hi), l2(lo), r1 (hi) and r2 (lo) is an example of th e dsp setting. l1(hi), r1(hi) are signals which were after hpf in dsp1. l2(lo) and r2(lo) are signals which were after lpf in dsp2. refer to the figure 55 for functions and signal paths of the dsp block. digital-in adc datt dsp1 for l1, r1 hpf, lpf eq, limiter dac1 dig dsp2 for l2, r2 hpf, lpf eq, limiter dac2 dig l1, r1 sw1 sw2 0 sel1-0 bit spc1-0 bit sw3 dac1l ana dac2l ana dac1r ana dac2r ana sw4 0: l1, r1, 0: l, r 0 1 sw2, 3, 4, 5, 6 l2, r2 l, r l1 sw5 ? 1 sw6 ? 1 + + r1 l2 r2 mix figure 53. block diagram for signal path (spc1-0 bits = ?11?) output setting signal and output block spc1 bit spc0 bit audio signal polarity dac pin singnal non dac1l lout1 l(hi) l1(hi)+r1(hi) non dac1r rout1 r(hi) non dac2l lout2 l(lo) 1 1 l2(lo)+r2(lo) non dac2r rout2 r(lo) table 23. 4-channels mode setting and output signal status details (hi: high frequency signal, lo: low frequency signal) block2 block1 ak4753 lout1 l(hi) ch rout1 lout2 rout2 analog source l ch r ch a nalog-in digital source digital-in l1,r1 r(hi) ch l2,r2 l(lo) ch r(lo) ch 4-channel (single-ended) figure 54. 4-channels mode and output bridge configuration (example: hi= high frequency signal, lo= low frequency signal are for two-way speaker system.)
[ak4753] ms1311-e-00 2011/07 - 39 - dsp functions and signal path the ak4753 has two dsp circuit blocks and one digital volume circuit (datt). each dsp block can be set individually for hpf/lpf, five biquads eq, pre-gain, limiter, and post-gain. hpf/ lpf pre gain any coefficient hpf/lpf: 1fa 19-0 1fb 19-0 1fc 19-0 any coefficient eq1-5: 1e_1-5a 19-0 1e_1-5b 19-0 1e_1-5c19-0 limiter five biquads datt any coefficient datt: l/r7-0 ats1-0 any coefficient pre-gain: 1preg 1-0 any coefficient hpf/ lpf pre gain any coefficient hpf/lpf: 2fa 19-0 2fb 19-0 2fc 19-0 any coefficient eq1-5: 2e_1-5a 19-0 2e_1-5b 19-0 2e_1-5c 19-0 limiter five biquads any coefficient pre-gain: 2preg 1-0 any coefficient dsp1 for l1, r1 dsp2 for l2, r2 post gain any coefficient post-gain: 1pstg 1-0 post gain any coefficient post-gain: 2pstg 1-0 figure 55. dsp functions and signal path refer to the each description of the function for deta il settings. available effects of the dsp are shown in table 28 . those effects in each function block of the dsp1 and dsp2 are set together, ?l1 and r1? or ?l2 and r2?.
[ak4753] ms1311-e-00 2011/07 - 40 - digital volume and gain control the ak4753 has three volume controls as gain setting of the amplifier outputs. digital volume control is the general volume to adjust the output signal level in normal operation. pre-gain and post-gain are for gain setting of the signal level in the signal path. 1. digital volume (datt) the ak4753 has a built-in channel independent digital volume (datt) with 256 levels in 0.5db steps including mute. the transition time between the set levels by l7-0 b its (r7-0 bits) can be set by dvtm bit. when dvtm bit = ?0? ( table 25 ), the transition time from 0db(00h ) to mute(ffh) is 1 024/fs (21.3ms@fs=48khz). when the pdn pin is set to ?l?, the volume level is initialized to mute(ffh). the transition between the set levels is soft transition. therefore a switching noise does not occu r within the transition. when the pmsar bit = ?1?, the volume and gain follows the sar value and the register setting of datt (l/r7-0 bits) is invalid. l/r7-0 bits attenuation level 00h 0db 01h ? 0.5db 02h ? 1.0db 03h ? 1.5db : : fdh ? 126.5db feh ? 127.0db ffh mute ( ? ) (default) table 24. digital volume att value att speed dvtm bit 0db to mute 1 step 0 1024/fs 4/fs (default) 1 256/fs 1/fs table 25. transition time among att7-0 setting values of the digital volume 2. pre-gain the ak4753 has the four steps volume before a limiter ci rcuit. the volume levels of l channel and r channel are in common in one dsp block, but levels between two dsp blocks are independent. volume levels are set by 1preg1-0 and 2preg1-0 bits ( table 26 ). when the set level is changed, a switching noise occurs because the volume level is re-written by the register directory. 1preg1-0 bits 2preg1-0 bits gain(db) step 00 0.0 (default) 01 +6.0 10 +12.0 11 +18.1 6.0db table 26. pre-gain setting 3. post-gain the ak4753 has the four steps volume after the limiter ci rcuit. the volume levels of l channel and r channel are in common in one dsp block, but those levels between two dsp blocks are independent. volume levels are set by 1pstg1-0 and 2pstg1-0 bits ( table 27 ). when the set level is changed, a switching noise occurs because the volume level is re-written by the register directory. 1pstg1-0 bits 2pstg1-0 bits gain(db) 00 0.0 (default) 01 +3.5 10 +6.0 11 +8.0 table 27. post-gain setting
[ak4753] ms1311-e-00 2011/07 - 41 - dsp block available setting of hpf, lpf and 5-progr ammable biquads in stereo mode, 2.1 channel mode and 4-channel mode are shown in table 28 . hpf, lpf and 5eq in table 28 should be set carefully according to the frequency response of the speaker which is actually used. the parameter of eac h setting can be set freely for application requests. output available setting channel mode channel pin signal dsp setting channel hpf lpf 5 eq pre-gain limiter post-gain out1 l+ l ch out2 l ? dsp1 l1 l1 l1 l1 l1 l1 out3 r+ stereo r ch out4 r ? dsp1 r1 r1 r1 r1 r1 r1 l(hi)+ dsp1 l1 (l1) l1 l1 l1 l1 out1 l(lo)+ dsp2 (l2) l2 l2 l2 l2 l2 l(hi) ? dsp1 l1 (l1) l1 l1 l1 l1 l ch out2 l(lo) ? dsp2 (l2) l2 l2 l2 l2 l2 r(hi)+ dsp1 r1 (r1) r1 r1 r1 r1 out3 r(lo)+ dsp2 (r2) r2 r2 r2 r2 r2 r(hi) ? dsp1 r1 (r1) r1 r1 r1 r1 stereo (hpf, lpf) r ch out4 r(lo) ? dsp2 (r2) r2 r2 r2 r2 r2 l ch out1 l(hi) dsp1 l1 (l1) l1 l1 l1 l1 r ch out2 r(hi) dsp1 r1 (r1) r1 r1 r1 r1 out3 m(lo)+ 2.1-channels sw ch out4 m(lo) ? dsp2 (m) m m m m m l (hi) ch out1 l1(hi) ds p1 l1 (l1) l1 l1 l1 l1 r (hi) ch out2 r1(hi) dsp1 r1 (r1) r1 r1 r1 r1 l (lo) ch out3 l2(lo) dsp2 (l2) l2 l2 l2 l2 l2 4-channels r (lo) ch out4 r2(lo) dsp2 (r2) r2 r2 r2 r2 r2 table 28. available settings for dsp and signal path of each speaker configuration (sw: subwoofer, m: mono mix) hpf / lpf any coefficient hpf/lpf: 1fa 19-0, 2fa 19-0 1fb 19-0, 2fb 19-0 1fc 19-0, 2fc 19-0 figure 56. digital hpf/lpf
[ak4753] ms1311-e-00 2011/07 - 42 - hpf and lpf coefficients hpf and lpf are controlled by 1filsel and 2filsel bits. when 1filsel and 2filsel bits= ?1?, this block works as a hpf. when 1filsel and 2filsel bits= ?0?, this block works as a lpf. on/off switching of this block can be controlled by 1filen and 2filen bits. when the block of hpf/lpf becomes off mode by 1filen and 2filen bits= ?0?, the audio data passes this block by 0db gain. the setting of the coefficients should be made when the ak4753 is in the state that 1filen bit =2filen bit= ?0?. fs: sampling frequency fc: cutoff frequency (-6db point) register setting ( note 22 ) 1fa19-0, 2fa19-0 bits = a 1fb19-0, 2fb19-0 bits = b 1fc19-0, 2fc19-0 bits = c 1filsel bit 2filsel bit ?0? (lpf) ?1? (hpf) a ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? + fs fc fs fc 2 tan 1 tan 4 1 cos 2 1 1 ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? fs fc fs fc fs fc 2 2 tan 1 tan 4 1 cos 2 1 tan 1 b ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? fs fc fs fc fs fc 2 2 tan 1 tan 4 1 cos 2 1 tan 1 1 2 c ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? fs fc fs fc fs fc fs fc 2 2 tan 1 tan 4 1 cos 2 1 tan 1 tan 4 1 cos 2 1 transfer function 2 2 1 2 1 1 2 1 ) ( ? ? ? ? ? ? ? ? + + + + = ? ? ? ? cz bz z z a z h 2 2 1 2 1 1 2 1 ) ( ? ? ? ? ? ? ? ? + + + ? = ? ? ? ? cz bz z z a z h the cutoff frequency should be set within the range as follows. hpf: 1.042x10 -3 fc/fs 0.24 fc_min = 50hz fc_max = 11.5khz @ fs=48khz lpf: 5.208x10 -3 fc/fs 0.24 fc_min = 250hz fc_max = 11.5khz @ fs=48khz other fs settings lower than above for lpf are shown in table 29 . fc/fs fc(@fs=48khz) a(dec) b(dec) c(dec) 1.921x10 -3 94.8hz 5 -259845 128793 2.137x10 -3 103.9hz 6 -259624 128576 2.333x10 -3 112.0hz 7 -259426 128382 : : : : : : : : : : 5.208x10 -3 250hz 34 -256079 125144 table 29. low frequency band setting of lpf
[ak4753] ms1311-e-00 2011/07 - 43 - five programmable biquads this block can be used as an equalizer or notch filter. 5-band equalizer (eq1, eq2, eq3, eq4 and eq5) is on/off independently by eq1, eq2, eq3, eq4 and eq5 bits. when the equalizer is off, the audio data passes this block by 0db gain. e1a19-0, e1b19-0 and e1c19-0 bits set the coefficient of eq1. e2a19-0, e2b19-0 and e2c19-0 bits set the coefficient of eq2. e3a19-0, e3b19-0 and e3c19-0 bits set the coefficient of eq3. e4a19-0, e4b19-0 and e4c19-0 bits set the coefficient of eq4. e5 a19-0, e5b19-0 and e5c19-0 bits set the coefficient of eq5. eqx (x=1~5) coefficient should be set when eqx bit = ?0? or pmdac bit = ?0 ?. when the sa2 bit = ?1?, k 1 gain must be set to ?1? for the dsp channel selected by the sa2sel bit. fs: sampling frequency fo 1 ~ fo 5 : center frequency fb 1 ~ fb 5 : band width where the gain is 3db different from center frequency k 1 ~ k 5 : gain ( -1 k n < 3 ) register setting ( note 22 ) eq1: e1a19-0 bits =a 1 , e1b19-0 bits =b 1 , e1c19-0 bits =c 1 eq2: e2a19-0 bits =a 2 , e2b19-0 bits =b 2 , e2c19-0 bits =c 2 eq3: e3a19-0 bits =a 3 , e3b19-0 bits =b 3 , e3c19-0 bits =c 3 eq4: e4a19-0 bits =a 4 , e4b19-0 bits =b 4 , e4c19-0 bits =c 4 eq5: e5a19-0 bits =a 5 , e5b19-0 bits =b 5 , e5c19-0 bits =c 5 (msb=e1a19, e1b19, e1c19, e2a19, e2b19, e2c19, e3a19, e3b19, e3c19, e4a19, e4b19, e4c19, e5a19, e5b19, e5c19; lsb= e1a0, e1b0, e1c0, e2a0, e2b0 , e2c0, e3a0, e3b0, e3c0, e4a0, e4b0, e4c0, e5a0, e5b0, e5c0) a n = k n x tan ( fb n /fs) 1 + tan ( fb n /fs) b n = cos(2 fo n /fs) x 2 1 + tan ( fb n /fs) , c n = 1 ? tan ( fb n /fs) 1 + tan ( fb n /fs) , (n = 1, 2, 3, 4, 5) transfer function h n (z) = a n 1 ? z ? 2 1 ? b n z ? 1 ? c n z ? 2 h(z) = 1 + h 1 (z) + h 2 (z) + h 3 (z) + h 4 (z) + h 5 (z) (n = 1, 2, 3, 4, 5) the fbn should be set within the range as follows. fbn/fs 0.25 the f0n (center frequency) should be set within the range as follows. 3.125x10 -3 f0n/fs < 0.4969 when the f0n/fs is less than 3.125x10 -3 , the step width of the f0n which can be set up becomes the biggest in the case of fbn/fs=0.25. ( table 30 ) f0n/fs f0n(@fs=48khz) an (dec) (kn=-1) bn (dec) cn (dec) 8.542x10 -4 41hz -65536 131070 0 1.083x10 -3 52hz -65536 131069 0 1.229x10 -3 59hz -65536 131068 0 : : : : : 3.125x10 -3 150hz -65536 131047 0 table 30. the center frequency in the low frequency band (when the coefficients of an, bn and cn is fbn/fs=0.25) note 22. translation the filter coefficient calculated by th e equations above from real number to binary code (2?s complement) x = (real number of filter coefficient calculated by the equations above) x 2 17 x should be rounded to integer, and then should be translated to binary code (2?s complement). msb of each filter coefficient se tting register is sign bit.
[ak4753] ms1311-e-00 2011/07 - 44 - limiter operation almt1 bit controls on/off of the limiter operation of the dsp1 block. almt2 bit controls on/off of the limiter operation of the dsp2 block. dsp1 block and dsp2 block are controlled completely independent by limiter mode control, timer select and reference level control bits. 1. limiter movement during a limiter operation, when either lch or rch exceeds the limiter detection level ( table 31 ), the vol values (same value for lch and rch) are attenuated automatically by the amount defined by the limiter att step set by lmat1-0 bits ( table 32 ). when zelmn bit = ?0? (zero cro ss detection is enabled), lfstn bit = ?0? (fast limiter is enabled) and the output level is less than full-scale, the vol values (lch and rch) are changed by a limiter operation at the individual zero crossing points of lch and rch or at the zero crossing timeout. ztm1-0 bits set the zero crossing timeout period of both limiter and recovery operation ( table 33 ). when the output level exceeds full-scale, vol values are immediately (period: 1/fs) changed. when lfstn bit= ?1? (fast limiter is disabled), vol values are changed at the i ndividual zero crossing point of each channels or at the zero crossing timeout regardless of the output level. when zelmn bit = ?1? (zero cross detection is disabled), vol values are immediately (p eriod: 1/fs) changed by a limiter operation. attenuation step is fixed to 1 step regardless of the lmat1-0 bits setting. after completing the attenuate operatio n, unless almt1 bit or almt2 bit is changed to ?0?, the operation repeats when the input signal level exceeds limiter detection level. lmth1 bit lmth0 bit limier detection level recovery waiting counter reset level 0 0 limiter output ? 2.5dbfs ? 2.5dbfs > limiter output ? 4.1dbfs (default) 0 1 limiter output ? 4.1dbfs ? 4.1dbfs > limiter output ? 6.0dbfs 1 0 limiter output ? 6.0dbfs ? 6.0dbfs > limier output ? 8.5dbfs 1 1 limiter output ? 8.5dbfs ? 8.5dbfs > limier output ? 12dbfs table 31. limiter detection level / recovery counter reset level limiter att step (0.375db/step) lmat1 bit lmat0 bit limiter output lmth limiter output fs limiter output fs + 6db limiter output fs + 12db 0 0 1 1 1 1 (default) 0 1 2 2 2 2 1 0 2 4 4 8 1 1 1 2 4 8 table 32. limiter att step zero crossing timeout period ztm1 bit ztm0 bit 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms (default) 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 33. zero crossing timeout period
[ak4753] ms1311-e-00 2011/07 - 45 - 2. limiter recovery operation a limiter recovery operation waits for the wtm2-0 bits ( table 34 ) to be set after completing a limiter operation. if the input signal does not exceed ?recove ry waiting counter reset level? ( table 31 ) during the wait time, the limiter recovery operation is completed. the vol values (lch and rch) are automatically increm ented by rgain1-0 bits ( table 35 ) up to the set reference level ( table 36 ) with zero crossing detection which timeout period is set by ztm1-0 bits ( table 33 ). then the vol?s are set to the same value for both channels . this limiter recovery operation is executed at a period set by wtm2-0 bits. when zero cross is detected at both channels during the wait period set by wtm2-0 bits, a limiter recovery operation waits until wtm2-0 period and the next recovery operation is completed. if ztm1-0 is longer than wtm2-0 and no zero crossing occurs, a limiter recovery operation is made at a period set by ztm1-0 bits. for example, when the current vol value is 30h and rgain1-0 bits are set to ?01? (2 steps), vol is changed to 32h by the limiter operation and then the input signal level is gained by 0.75db (=0.375db x 2). when the vol value exceeds the reference level (ref7-0 bits ), the vol values are not increased. when ?limiter recovery waiting counter reset level (lmth1-0) output signal < limiter detection level (lmth1-0)? during a limiter recovery operation, the waiting timer of limiter recovery operation is reset. when ?limiter recovery waiting counter reset level (lmth1-0) > output signal?, the waiting timer of limiter recovery operation starts. the limiter operation corresponds to the impulse noise. when the impulse noise is input, limiter recovery operation is faster than a normal recovery opera tion (fast recovery operation). when large noise is input to microphone instantaneously, quality of small signal level in the large noise can be improved by this fast recovery operation. the speed of fast recovery operation is set by rfst1-0 bits ( table 37 ). recovery operation waiting period wtm2 bit wtm1 bit wtm0 bit 8khz 16khz 44.1khz 0 0 0 128/fs 16ms 8ms 2.9ms (default) 0 0 1 256/fs 32ms 16ms 5.8ms 0 1 0 512/fs 64ms 32ms 11.6ms 0 1 1 1024/fs 128ms 64ms 23.2ms 1 0 0 2048/fs 256ms 128ms 46.4ms 1 0 1 4096/fs 512ms 256ms 92.9ms 1 1 0 8192/fs 1024ms 512ms 185.8ms 1 1 1 16384/fs 2048ms 1024ms 371.5ms table 34. recovery operation waiting period rgain1 bit rgain0 bit gain step 0 0 1 step 0.375db (default) 0 1 2 step 0.750db 1 0 3 step 1.125db 1 1 4 step 1.500db table 35. recovery gain step
[ak4753] ms1311-e-00 2011/07 - 46 - ref7-0 bits gain(db) step (db) f1h 0 (default) f0h -0.375 efh -0.75 : : a0h -30.375 9fh -30.75 9eh -31.125 : : 0.375 50h -60.375 4fh -60.75 4eh -61.125 : : 02h -89.625 01h -90.0 00h mute table 36. reference level at recovery operation rfst1 bit rfst0 bit recovery speed 0 0 4 times (default) 0 1 8 times 1 0 16times 1 1 n/a table 37. fast recovery speed setting (n/a: not available) 3. example of the li miter operation setup an example of the limiter setting is shown in table 38 . fs=8khz fs=44.1khz register name comment data operation data operation lmth1-0 limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs zelmn limiter zero crossing detection 0 enable 0 enable ztm1-0 zero crossing timeout period 01 32ms 11 23.2ms wtm2-0 recovery waiting period *wtm2-0 bits should be the same or longer data as ztm1-0 bits. 001 32ms 011 23.2ms ref7-0 reference level at recovery operation f1h 0db f1h 0db lmat1-0 limiter att step 00 1 step 00 1 step rgain1-0 recovery gain step 00 1 step 00 1 step rfst1-0 fast recovery speed 00 4 times 00 4 times table 38. example of the limiter operation setting
[ak4753] ms1311-e-00 2011/07 - 47 - line outputs line outputs of the ak4753 have internal resisters in series. the resister value is 200 ? (typ). by just connecting small capacitors between vss1 and each the lout1/2 or rout1/2 pi n, high frequency noise will be significantly reduced. lout1/2 rout1/2 c 150pf (max) 200 (t yp) 1 f ak4753 figure 57. external circuit for stereo line outputs (in case of using high frequency noise reduction circuit.) the ak4753 has a mute control output pin (muten pin) for external speaker amplifier. in order to prevent a pop noise through the ak4753, the mtuen pin is connected to a mute pin or a standby pin of the external speaker amplifier. in the pll mode, when the pll is unlocked or the line outputs are disabled, the muten outputs ?l?. when the pll is locked and the line outputs are enabled, the muten outputs ?h?. pmlo1/2 bit muten pin lout1/2, rout1/2 pins normal output 4ms (typ) mute off mute on mute on figure 58. line outputs control sequence
[ak4753] ms1311-e-00 2011/07 - 48 - sar 8-bit adc the ak4753 incorporat es a 8-bit successive approximation resist or a/d converter for dc measurement. by connecting potentiometers, the gain of datt can be controlled by sain1and the gain of eq1 can be controlled by sain2. the a/d converter output for the sain1 pin is a straight binary format as shown in table 39 . input voltage output code attenuation level (avdd ? 1.0lsb) ~ avdd 00h 0db (avdd ? 2.0lsb) ~ (avdd ? 1.0lsb) 01h -0.5db : : : 1.0lsb ~ 2.0lsb feh -127db 0 ~ 1.0lsb ffh mute ( ? ) table 39. output code for the sain1 pin the a/d converter output for the sain2 pin is a straight binary format as shown in table 40 . input voltage output code (avdd ? 1.0lsb) ~ avdd 00h (avdd-2.0lsb) ~ (avdd ? 1.0lsb) 01h : : 1.0lsb ~ 2.0lsb feh 0 ~ 1.0lsb ffh table 40. output code for the sain2 pin output code gain@eq1 k 1 @eq1 00h ~ 04h 05h ~ 09h +12.0db 2.981 0ah ~ 0eh +11.5db 2.758 0fh ~ 13h +11.0db 2.548 14h ~ 18h +10.5db 2.350 : : : 7dh ~ 81h 0db 0 : : : e6h ~ eah -10.5db -0.701 ebh ~ efh -11.0db -0.718 f0h ~ f4h -11.5db -0.734 f5h ~ f9h fah ~ ffh -12.0db -0.749 table 41. gain setting of eq1 sa2sel bit k 1 0 dsp1 (default) 1 dsp2 table 42. source for the sain2 pin sa2 bit sain2 pin 0 disable (default) 1 enable table 43. configuration for the sain2 pin
[ak4753] ms1311-e-00 2011/07 - 49 - cycle time ctm1 bit ctm0 bit fs=8khz fs=44.1khz 0 0 4/fs 0.5ms 0.09ms (default) 0 1 8/fs 1.0ms 0.18ms 1 0 16/fs 2.0ms 0.36ms 1 1 32/fs 4.0ms 0.73ms table 44. cycle time setting lrck pin 1/ 8fs conv (sain1) sampling (sain1) idol cycle time (c tm1-0 bits) cycle time internal sequence 7/8fs 1/8fs conv (sain2) sampling (sain2) 7/8fs sampling (sain1) 7/8fs conv (sain1) 1/8fs figure 59. sar control se quence (sa2 bit = ?1?)
[ak4753] ms1311-e-00 2011/07 - 50 - eep-rom interface (extee pin = ?h?) the ak4753 has eep-rom i/f to read out the coefficient values for the dsp blocks and the setting data from an external eep-rom to the internal register. dsp function is easily realized in the system using eep-rom without extra microprocessor. the external eep-rom must be connected to the eescl and eesda pin of the ak4753. the ak4753 can operate as a master device on the i 2 c bus network. a connection example is shown in figure 60 . 1. eep-rom data read operation before start downloading, data must be written to the eep-rom. the ak4753 should be powered up when the pdn pin = ?l ?. after all power supplies are on and the extee pin= ?h?, the ak4753 starts down loading the data from the eep-rom when the pdn pin ( figure 61 ) is set to ?h?. the internal osc of the ak4753 is powered-up by this start se tting, and the register data are readout from the eep-rom. the ak4753 i 2 c master device assumes that there is not another i 2 c master device on the same bus during downloading data. therefore, the i 2 c i/f of the microprocessor should be set to hi-z sate or powered-down. this data download from eep-rom takes 6ms (max). in the eep-rom data read operation, error detection results of an eep-rom data read can be monitored on the sto pin. the sto pin outputs ?l? when no errors are found. when a read error is detected, the internal l ogic circuit repeats data read from eepro m for nine times (max). if errors are detected for nine times, the read operation is stopped and the sto pin outputs ?h?. eeprom scl sda eeprom interface eesda eescl extee = ?h? a k4753 2.2k dvdd pdn 2.2k start at ?h? sto figure 60. connection example of the ak4753 and eep-rom (i 2 c) pdn pin(i) dvdd, avdd coefficient value for dsp, setting data eep-rom i/f internal osc eeprom ak4753 figure 61. eep-rom download sequence
[ak4753] ms1311-e-00 2011/07 - 51 - eesda slave address s s t a r t r/w="0" a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address (00h) s slave address r/w="1" s t a r t data(n+1) a c k n a c k m a s t e r m a s t e r m a s t e r m a s t e r "1010000" "1010000" a c k e e p e e p e e p figure 62. eep-rom sequential read sequence 1 0 1 0 0 0 0 r/w figure 63. slave address byte for eep-rom read operation 0 0 0 0 0 0 0 0 figure 64. sub address byte for eep-rom read operation d7 d6 d5 d4 d3 d2 d1 d0 figure 65. data byte for eep-rom read operation 2. eep-rom memory map the ak4753 only supports 1k bytes or larger i 2 c type eep-rom. the eep-rom is used for storing the control registers. the contents of eep-rom memory map are same as the register map. (1) fundamental function block addr contents 00h signal path 01h sar control 02h mode setting 1 03h mode setting 2 04h power management 05h lch datt 06h rch datt 07h gain setting 08h dsp1 limiter mode control 09h dsp1 timer select 0ah dsp1 reference level 0bh dsp2 limiter mode control 0ch dsp2 timer select 0dh dsp2 reference level
[ak4753] ms1311-e-00 2011/07 - 52 - (2) dsp1 function block addr contents 0eh dsp1 hpf/lpf setting 0fh~17h dsp1 filter coefficient 18h dsp1 eq select 19h~21h dsp1 eq1 coefficient 22h~2ah dsp1 eq2 coefficient 2bh~33h dsp1 eq3 coefficient 34h~3ch dsp1 eq4 coefficient 3dh~45h dsp1 eq5 coefficient (3) dsp2 function block addr contents 46h dsp2 hpf/lpf setting 47h~4fh dsp2 filter coefficient 50h dsp2 eq select 51h~59h dsp2 eq1 coefficient 5ah~62h dsp2 eq2 coefficient 63h~6bh dsp2 eq3 coefficient 6ch~74h dsp2 eq4 coefficient 75h~7dh dsp2 eq5 coefficient 7fh reserved
[ak4753] ms1311-e-00 2011/07 - 53 - serial control interface (i2c-bus control: extee pin = ?l?) the ak4753 supports the fast-mode i 2 c-bus (max: 400khz). pull-up resistors at the sda and scl pins must be connected to (dvdd+0.3)v or less voltage. 1. write operations figure 66 shows the data transfer sequence for the i 2 c-bus mode. all commands are pr eceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition ( figure 72 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant seven bits of the slave address are fixed as ?0010010? ( figure 67 ). if the slave address matches that of the ak4753, the ak4753 generates an ac knowledge and the operation is executed. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 73 ). a r/w bit value of ?1? indicates that the read operation is to be executed, and ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the ak4753. the format is msb first, and those most significant 1bit is fixed to zero ( figure 68 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 69 ). the ak4753 generates an acknowledge after each byte is received. data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition ( figure 72 ). the ak4753 can perform more than one by te write operation per sequence. after receipt of the thir d byte the ak4753 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after receiving each data packet the internal address counter is incremented by one, and the next data is automatically taken in to the next address. if the address exceeds 7dh prior to generating a stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. high or low state of the data line can only be changed when the clock signal on the scl line is low ( figure 74 ) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 66. data transfer sequence at i 2 c bus mode 0 0 1 0 0 1 0 r/w figure 67. the first byte 0 a6 a5 a4 a3 a2 a1 a0 figure 68. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 69. the third byte
[ak4753] ms1311-e-00 2011/07 - 54 - 2. read operations set the r/w bit = ?1? for the read opera tion of the ak4753. after transmission of data, the master can read the next address?s data by generating an acknowle dge instead of terminating the write cycl e after the receipt of the first data word. after receiving each data packet the internal addres s counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds 7dh prior to generating stop condition, the address counter will ?roll over? to 00h and th e data of 00h will be read out. the ak4753 supports two basic read operations: current address read and random address read. 2-1. current address read the ak4753 has an internal ad dress counter that maintains the address of the last accesse d word incremented by one. therefore, if the last access (either a read or write) were to address ?n?, the next current read operation would access data from the address ?n+1?. afte r receipt of the slave address with r/w bit ?1?, the ak4753 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the ak4753 ceases the transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) n a c k p s t o p data(n) m a s t e r m a s t e r m a s t e r m a s t e r m a s t e r figure 70. current address read 2-2. random address read the random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit ?1?, the master must first perform a ?dummy? write operation. the master issues a start request, a slave address (r/w bit = ?0?) and then the re gister address to read. after the register address is acknowledged, the master immediately reissues the start request and th e slave address with the r/w bit ?1?. the ak4753 then generates an acknowledge, 1 byte of data and in crements the internal address counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the ak4753 ceases the transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k n a c k m a s t e r m a s t e r m a s t e r m a s t e r figure 71. random address read
[ak4753] ms1311-e-00 2011/07 - 55 - scl sda stop condition start condition s p figure 72. start condition and stop condition scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 73. acknowledge (i 2 c bus) scl sda data line stable; data valid change of data allowed figure 74. bit transfer (i 2 c bus)
[ak4753] ms1311-e-00 2011/07 - 56 - register map in this section, the fundamental functions (address: 00h to 0dh), the dsp1 functions (address: 0eh to 45h), and the dsp2 functions (address: 46h to 7dh) are shown in three subsections. note 23. pdn pin = ?l? resets the registers to their default values. note 24. the bits defined as 0 must contain a ?0? value. 1. register map of fundamental function addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h sar control ctm1 ctm0 sa2sel sa2 pmsar 0 0 0 01h signal path almt1 almt2 spc1 spc0 0 sel1 0 sel0 02h mode setting 1 fs3 fs2 fs1 fs0 pll3 pll2 pll1 pll0 03h mode setting 2 bcko m/s bckp msbs 0 dif2 dif1 dif0 04h power management pmpll 0 pmlo2 pmlo1 pmdig pwxtl 0 pmadc 05h lch datt l7 l6 l5 l4 l3 l2 l1 l0 06h rch datt r7 r6 r5 r4 r3 r2 r1 r0 07h gain setting 1pstg1 1pstg0 1preg1 1preg0 2pstg1 2pstg0 2preg1 2preg0 08h dsp1 limiter mode control 1lfstn 1zelmn 1rgain1 1rgain0 1l mat1 1lmat0 1lmth1 1lmth0 09h dsp1 timer select 1rfst1 1rfst0 1wtm2 1wtm1 1wtm0 1ztm1 1ztm0 dvtm 0ah dsp1 reference level 1ref7 1ref6 1ref5 1ref4 1ref3 1ref2 1ref1 1ref0 0bh dsp2 limiter mode control 2lfstn 2zelmn 2rgain1 2rgain0 2l mat1 2lmat0 2lmth1 2lmth0 0ch dsp2 timer select 2rfst1 2rfst0 2wtm2 2wtm1 2wtm0 2ztm1 2ztm0 0 0dh dsp2 reference level 2ref7 2ref6 2ref5 2ref4 2ref3 2ref2 2ref1 2ref0 2. register map of dsp1 function addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh hpf/lpf setting 0 0 0 0 0 0 1filsel 1filen 0fh dsp1 filter a coefficient 1 1fa7 1fa6 1fa5 1fa4 1fa3 1fa2 1fa1 1fa0 10h dsp1 filter a coefficient 2 1fa15 1fa14 1fa13 1fa12 1fa11 1fa10 1fa9 1fa8 11h dsp1 filter a coefficient 3 0 0 0 0 1fa19 1fa18 1fa17 1fa16 12h dsp1 filter b coefficient 1 1fb7 1fb6 1fb5 1fb4 1fb3 1fb2 1fb1 1fb0 13h dsp1 filter b coefficient 2 1fb15 1fb14 1fb13 1fb12 1fb11 1fb10 1fb9 1fb8 14h dsp1 filter b coefficient 3 0 0 0 0 1fb19 1fb18 1fb17 1fb16 15h dsp1 filter c coefficient 1 1fc7 1fc6 1fc5 1fc4 1fc3 1fc2 1fc1 1fc0 16h dsp1 filter c coefficient 2 1fc15 1fc14 1fc13 1fc12 1fc11 1fc10 1fc9 1fc8 17h dsp1 filter c coefficient 3 0 0 0 0 1fc19 1fc18 1fc17 1fc16
[ak4753] ms1311-e-00 2011/07 - 57 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 18h dsp1 eq select 0 0 0 1eq5 1eq4 1eq3 1eq2 1eq1 19h dsp1 eq1 a coefficient 1 1e1a7 1e1a6 1e1a5 1e1a4 1e1a3 1e1a2 1e1a1 1e1a0 1ah dsp1 eq1 a coefficient 2 1e1a15 1e1a14 1e1a13 1e1a12 1e1a11 1e1a10 1e1a9 1e1a8 1bh dsp1 eq1 a coefficient 3 0 0 0 0 1e1a19 1e1a18 1e1a17 1e1a16 1ch dsp1 eq1 b coefficient 1 1e1b7 1e1b6 1e1b5 1e1b4 1e1b3 1e1b2 1e1b1 1e1b0 1dh dsp1 eq1 b coefficient 2 1e1b15 1e1b14 1e1b13 1e1b12 1e1b11 1e1b10 1e1b9 1e1b8 1eh dsp1 eq1 b coefficient 3 0 0 0 0 1e1b19 1e1b18 1e1b17 1e1b16 1fh dsp1 eq1 c coefficient 1 1e1c7 1e1c6 1e1c5 1e1c4 1e1c3 1e1c2 1e1c1 1e1c0 20h dsp1 eq1 c coefficient 2 1e1c15 1e1c14 1e1c13 1e1c12 1e1c11 1e1c10 1e1c9 1e1c8 21h dsp1 eq1 c coefficient 3 0 0 0 0 1e1c19 1e1c18 1e1c17 1e1c16 22h dsp1 eq2 a coefficient 1 1e2a7 1e2a6 1e2a5 1e2a4 1e2a3 1e2a2 1e2a1 1e2a0 23h dsp1 eq2 a coefficient 2 1e2a15 1e2a14 1e2a13 1e2a12 1e2a11 1e2a10 1e2a9 1e2a8 24h dsp1 eq2 a coefficient 3 0 0 0 0 1e2a19 1e2a18 1e2a17 1e2a16 25h dsp1 eq2 b coefficient 1 1e2b7 1e2b6 1e2b5 1e2b4 1e2b3 1e2b2 1e2b1 1e2b0 26h dsp1 eq2 b coefficient 2 1e2b15 1e2b14 1e2b13 1e2b12 1e2b11 1e2b10 1e2b9 1e2b8 27h dsp1 eq2 b coefficient 3 0 0 0 0 1e2b19 1e2b18 1e2b17 1e2b16 28h dsp1 eq2 c coefficient 1 1e2c7 1e2c6 1e2c5 1e2c4 1e2c3 1e2c2 1e2c1 1e2c0 29h dsp1 eq2 c coefficient 2 1e2c15 1e2c14 1e2c13 1e2c12 1e2c11 1e2c10 1e2c9 1e2c8 2ah dsp1 eq2 c coefficient 3 0 0 0 0 1e2c19 1e2c18 1e2c17 1e2c16 2bh dsp1 eq3 a coefficient 1 1e3a7 1e3a6 1e3a5 1e3a4 1e3a3 1e3a2 1e3a1 1e3a0 2ch dsp1 eq3 a coefficient 2 1e3a15 1e3a14 1e3a13 1e3a12 1e3a11 1e3a10 1e3a9 1e3a8 2dh dsp1 eq3 a coefficient 3 0 0 0 0 1e3a19 1e3a18 1e3a17 1e3a16 2eh dsp1 eq3 b coefficient 1 1e3b7 1e3b6 1e3b5 1e3b4 1e3b3 1e3b2 1e3b1 1e3b0 2fh dsp1 eq3 b coefficient 2 1e3b15 1e3b14 1e3b13 1e3b12 1e3b11 1e3b10 1e3b9 1e3b8 30h dsp1 eq3 b coefficient 3 0 0 0 0 1e3b19 1e3b18 1e3b17 1e3b16 31h dsp1 eq3 c coefficient 1 1e3c7 1e3c6 1e3c5 1e3c4 1e3c3 1e3c2 1e3c1 1e3c0 32h dsp1 eq3 c coefficient 2 1e3c15 1e3c14 1e3c13 1e3c12 1e3c11 1e3c10 1e3c9 1e3c8 33h dsp1 eq3 c coefficient 3 0 0 0 0 1e3c19 1e3c18 1e3c17 1e3c16
[ak4753] ms1311-e-00 2011/07 - 58 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 34h dsp1 eq4 a coefficient 1 1e4a7 1e4a6 1e4a5 1e4a4 1e4a3 1e4a2 1e4a1 1e4a0 35h dsp1 eq4 a coefficient 2 1e4a15 1e4a14 1e4a13 1e4a12 1e4a11 1e4a10 1e4a9 1e4a8 36h dsp1 eq4 a coefficient 3 0 0 0 0 1e4a19 1e4a18 1e4a17 1e4a16 37h dsp1 eq4 b coefficient 1 1e4b7 1e4b6 1e4b5 1e4b4 1e4b3 1e4b2 1e4b1 1e4b0 38h dsp1 eq4 b coefficient 2 1e4b15 1e4b14 1e4b13 1e4b12 1e4b11 1e4b10 1e4b9 1e4b8 39h dsp1 eq4 b coefficient 3 0 0 0 0 1e4b19 1e4b18 1e4b17 1e4b16 3ah dsp1 eq4 c coefficient 1 1e4c7 1e4c6 1e4c5 1e4c4 1e4c3 1e4c2 1e4c1 1e4c0 3bh dsp1 eq4 c coefficient 2 1e4c15 1e4c14 1e4c13 1e4c12 1e4c11 1e4c10 1e4c9 1e4c8 3ch dsp1 eq4 c coefficient 3 0 0 0 0 1e4c19 1e4c18 1e4c17 1e4c16 3dh dsp1 eq5 a coefficient 1 1e5a7 1e5a6 1e5a5 1e5a4 1e5a3 1e5a2 1e5a1 1e5a0 3eh dsp1 eq5 a coefficient 2 1e5a15 1e5a14 1e5a13 1e5a12 1e5a11 1e5a10 1e5a9 1e5a8 3fh dsp1 eq5 a coefficient 3 0 0 0 0 1e5a19 1e5a18 1e5a17 1e5a16 40h dsp1 eq5 b coefficient 1 1e5b7 1e5b6 1e5b5 1e5b4 1e5b3 1e5b2 1e5b1 1e5b0 41h dsp1 eq5 b coefficient 2 1e5b15 1e5b14 1e5b13 1e5b12 1e5b11 1e5b10 1e5b9 1e5b8 42h dsp1 eq5 b coefficient 3 0 0 0 0 1e5b19 1e5b18 1e5b17 1e5b16 43h dsp1 eq5 c coefficient 1 1e5c7 1e5c6 1e5c5 1e5c4 1e5c3 1e5c2 1e5c1 1e5c0 44h dsp1 eq5 c coefficient 2 1e5c15 1e5c14 1e5c13 1e5c12 1e5c11 1e5c10 1e5c9 1e5c8 45h dsp1 eq5 c coefficient 3 0 0 0 0 1e5c19 1e5c18 1e5c17 1e5c16 3. register map of dsp2 function addr register name d7 d6 d5 d4 d3 d2 d1 d0 46h hpf/lpf setting 0 0 0 0 0 0 2filsel 2filen 47h dsp2 filter a coefficient 1 2fa7 2fa6 2fa5 2fa4 2fa3 2fa2 2fa1 2fa0 48h dsp2 filter a coefficient 2 2fa15 2fa14 2fa13 2fa12 2fa11 2fa10 2fa9 2fa8 49h dsp2 filter a coefficient 3 0 0 0 0 2fa19 2fa18 2fa17 2fa16 4ah dsp2 filter b coefficient 1 2fb7 2fb6 2fb5 2fb4 2fb3 2fb2 2fb1 2fb0 4bh dsp2 filter b coefficient 2 2fb15 2fb14 2fb13 2fb12 2fb11 2fb10 2fb9 2fb8 4ch dsp2 filter b coefficient 3 0 0 0 0 2fb19 2fb18 2fb17 2fb16 4dh dsp2 filter c coefficient 1 2fc7 2fc6 2fc5 2fc4 2fc3 2fc2 2fc1 2fc0
[ak4753] ms1311-e-00 2011/07 - 59 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 4eh dsp2 filter c coefficient 2 2fc15 2fc14 2fc13 2fc12 2fc11 2fc10 2fc9 2fc8 4fh dsp2 filter c coefficient 3 0 0 0 0 2fc19 2fc18 2fc17 2fc16 50h dsp2 eq select 0 0 0 2eq5 2eq4 2eq3 2eq2 2eq1 51h dsp2 eq1 a coefficient 1 2e1a7 2e1a6 2e1a5 2e1a4 2e1a3 2e1a2 2e1a1 2e1a0 52h dsp2 eq1 a coefficient 2 2e1a15 2e1a14 2e1a13 2e1a12 2e1a11 2e1a10 2e1a9 2e1a8 53h dsp2 eq1 a coefficient 3 0 0 0 0 2e1a19 2e1a18 2e1a17 2e1a16 54h dsp2 eq1 b coefficient 1 2e1b7 2e1b6 2e1b5 2e1b4 2e1b3 2e1b2 2e1b1 2e1b0 55h dsp2 eq1 b coefficient 2 2e1b15 2e1b14 2e1b13 2e1b12 2e1b11 2e1b10 2e1b9 2e1b8 56h dsp2 eq1 b coefficient 3 0 0 0 0 2e1b19 2e1b18 2e1b17 2e1b16 57h dsp2 eq1 c coefficient 1 2e1c7 2e1c6 2e1c5 2e1c4 2e1c3 2e1c2 2e1c1 2e1c0 58h dsp2 eq1 c coefficient 2 2e1c15 2e1c14 2e1c13 2e1c12 2e1c11 2e1c10 2e1c9 2e1c8 59h dsp2 eq1 c coefficient 3 0 0 0 0 2e1c19 2e1c18 2e1c17 2e1c16 5ah dsp2 eq2 a coefficient 1 2e2a7 2e2a6 2e2a5 2e2a4 2e2a3 2e2a2 2e2a1 2e2a0 5bh dsp2 eq2 a coefficient 2 2e2a15 2e2a14 2e2a13 2e2a12 2e2a11 2e2a10 2e2a9 2e2a8 5ch dsp2 eq2 a coefficient 3 0 0 0 0 2e2a19 2e2a18 2e2a17 2e2a16 5dh dsp2 eq2 b coefficient 1 2e2b7 2e2b6 2e2b5 2e2b4 2e2b3 2e2b2 2e2b1 2e2b0 5eh dsp2 eq2 b coefficient 2 2e2b15 2e2b14 2e2b13 2e2b12 2e2b11 2e2b10 2e2b9 2e2b8 5fh dsp2 eq2 b coefficient 3 0 0 0 0 2e2b19 2e2b18 2e2b17 2e2b16 60h dsp2 eq2 c coefficient 1 2e2c7 2e2c6 2e2c5 2e2c4 2e2c3 2e2c2 2e2c1 2e2c0 61h dsp2 eq2 c coefficient 2 2e2c15 2e2c14 2e2c13 2e2c12 2e2c11 2e2c10 2e2c9 2e2c8 62h dsp2 eq2 c coefficient 3 0 0 0 0 2e2c19 2e2c18 2e2c17 2e2c16
[ak4753] ms1311-e-00 2011/07 - 60 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 63h dsp2 eq3 a coefficient 1 2e3a7 2e3a6 2e3a5 2e3a4 2e3a3 2e3a2 2e3a1 2e3a0 64h dsp2 eq3 a coefficient 2 2e3a15 2e3a14 2e3a13 2e3a12 2e3a11 2e3a10 2e3a9 2e3a8 65h dsp2 eq3 a coefficient 3 0 0 0 0 2e3a19 2e3a18 2e3a17 2e3a16 66h dsp2 eq3 b coefficient 1 2e3b7 2e3b6 2e3b5 2e3b4 2e3b3 2e3b2 2e3b1 2e3b0 67h dsp2 eq3 b coefficient 2 2e3b15 2e3b14 2e3b13 2e3b12 2e3b11 2e3b10 2e3b9 2e3b8 68h dsp2 eq3 b coefficient 3 0 0 0 0 2e3b19 2e3b18 2e3b17 2e3b16 69h dsp2 eq3 c coefficient 1 2e3c7 2e3c6 2e3c5 2e3c4 2e3c3 2e3c2 2e3c1 2e3c0 6ah dsp2 eq3 c coefficient 2 2e3c15 2e3c14 2e3c13 2e3c12 2e3c11 2e3c10 2e3c9 2e3c8 6bh dsp2 eq3 c coefficient 3 0 0 0 0 2e3c19 2e3c18 2e3c17 2e3c16 6ch dsp2 eq4 a coefficient 1 2e4a7 2e4a6 2e4a5 2e4a4 2e4a3 2e4a2 2e4a1 2e4a0 6dh dsp2 eq4 a coefficient 2 2e4a15 2e4a14 2e4a13 2e4a12 2e4a11 2e4a10 2e4a9 2e4a8 6eh dsp2 eq4 a coefficient 3 0 0 0 0 2e4a19 2e4a18 2e4a17 2e4a16 6fh dsp2 eq4 b coefficient 1 2e4b7 2e4b6 2e4b5 2e4b4 2e4b3 2e4b2 2e4b1 2e4b0 70h dsp2 eq4 b coefficient 2 2e4b15 2e4b14 2e4b13 2e4b12 2e4b11 2e4b10 2e4b9 2e4b8 71h dsp2 eq4 b coefficient 3 0 0 0 0 2e4b19 2e4b18 2e4b17 2e4b16 72h dsp2 eq4 c coefficient 1 2e4c7 2e4c6 2e4c5 2e4c4 2e4c3 2e4c2 2e4c1 2e4c0 73h dsp2 eq4 c coefficient 2 2e4c15 2e4c14 2e4c13 2e4c12 2e4c11 2e4c10 2e4c9 2e4c8 74h dsp2 eq4 c coefficient 3 0 0 0 0 2e4c19 2e4c18 2e4c17 2e4c16 75h dsp2 eq5 a coefficient 1 2e5a7 2e5a6 2e5a5 2e5a4 2e5a3 2e5a2 2e5a1 2e5a0 76h dsp2 eq5 a coefficient 2 2e5a15 2e5a14 2e5a13 2e5a12 2e5a11 2e5a10 2e5a9 2e5a8 77h dsp2 eq5 a coefficient 3 0 0 0 0 2e5a19 2e5a18 2e5a17 2e5a16 78h dsp2 eq5 b coefficient 1 2e5b7 2e5b6 2e5b5 2e5b4 2e5b3 2e5b2 2e5b1 2e5b0 79h dsp2 eq5 b coefficient 2 2e5b15 2e5b14 2e5b13 2e5b12 2e5b11 2e5b10 2e5b9 2e5b8 7ah dsp2 eq5 b coefficient 3 0 0 0 0 2e5b19 2e5b18 2e5b17 2e5b16 7bh dsp2 eq5 c coefficient 1 2e5c7 2e5c6 2e5c5 2e5c4 2e5c3 2e5c2 2e5c1 2e5c0 7ch dsp2 eq5 c coefficient 2 2e5c15 2e5c14 2e5c13 2e5c12 2e5c11 2e5c10 2e5c9 2e5c8 7dh dsp2 eq5 c coefficient 3 0 0 0 0 2e5c19 2e5c18 2e5c17 2e5c16
[ak4753] ms1311-e-00 2011/07 - 61 - register definitions of fundamental function addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h sar control ctm1 ctm0 sa2sel sa2 pmsar 0 0 0 r/w r/w r/w r/w r/w r/w rd rd rd default 0 0 0 0 0 0 0 0 pmsar: sar adc power management 0: power-down (default) 1: power-up sa2: sain2 enable 0: sain2 disable (default) 1: sain2 enable sa2sel: sain2 output configuration setting ( table 42 ) 0: setting for dsp1 (default) 1: setting for dsp2 ctm1-0: cycle time setting ( table 44 ) default: ?00? addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h signal path almt1 almt2 spc1 spc0 0 sel1 0 sel0 r/w r/w r/w r/w r/w rd r/w rd r/w default 0 0 0 0 0 0 0 0 sel1-0: dsp input setting ( table 18 ) 00: analog-in (default) 01: digital-in 10: mix spc1-0: line output configuration setting ( table 20 , table 21 , table 22 , table 23 ) those bits select the output mode to 2-channels mode, 2.1-channels mode, and 4-channels mode. default: ?00? almt2: dsp2 limiter enable 0: limiter disable (default) 1: limiter enable almt1: dsp1 limiter enable 0: limiter disable (default) 1: limiter enable addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h mode setting 1 fs3 fs2 fs1 fs0 pll3 pll2 pll1 pll0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pll3-0: pll reference clock select ( table 4 ) default: ?0000? (lrck pin) fs3-0: sampling frequency select ( table 5 , table 6 ) and mcki frequency select ( table 9 , table 11 ) fs3-0 bits select sampling frequency at pll mode and mcki frequency at ext mode.
[ak4753] ms1311-e-00 2011/07 - 62 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h mode setting 2 bcko m/s bckp msbs 0 dif2 dif1 dif0 r/w r/w r/w r/w r/w rd r/w r/w r/w default 1 0 0 0 0 0 1 1 dif2-0: audio interface format ( table 14 ) default: ?011? (i 2 s) msbs: lrck polarity at dsp mode ( table 15 , table 16 , table 17 ) 0: the rising edge (? ?) of lrck is half clock of bick before the channel change. (default) 1: the rising edge (? ?) of lrck is one clock of bick before the channel change. bckp: bick polarity at dsp mode ( table 15 , table 16 , table 17 ) 0: sdti is latched by the falling edge (? ?) of bick. (default) 1: sdti is latched by the rising edge (? ?) of bick. m/s: master / slave mode setting 0: slave mode (default) 1: master mode bcko: bick output frequency select at master mode ( table 8 ) addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h power management pmpll 0 pmlo2 pmlo1 pmdig pwxtl 0 pmadc r/w r/w rd r/w r/w r/w r/w rd r/w default 0 0 0 0 0 0 0 0 pmadc: adc power management 0: power-down (default) 1: power-up pwxtl: the power management of the crystal oscillation circuit 0: power off (default) 1: power on pmdig: dsp & dac digital power management 0: power-down (default) 1: power-up pmlo1: line out1 power management and external mute control 0: power-down (default) 1: power-up pmlo2: line out2 power management and external mute control 0: power-down (default) 1: power-up pmpll: pll power management 0: ext mode and power-down (default) 1: pll mode and power-up
[ak4753] ms1311-e-00 2011/07 - 63 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h lch datt l7 l6 l5 l4 l3 l2 l1 l0 06h rch datt r7 r6 r5 r4 r3 r2 r1 r0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 l7-0, r7-0: digital attenuation control ( table 24 ) default: ?ffh? (mute) addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h gain setting 1pstg1 1pstg0 1preg1 1preg0 2pstg1 2pstg0 2preg1 2preg0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 2preg1-0: dsp2 pre-gain setting ( table 26 ) default: ?00? 2pstg1-0: dsp2 post-gain setting ( table 27 ) default: ?00? 1preg1-0: dsp1 pre-gain setting ( table 26 ) default: ?00? 1pstg1-0: dsp1 post-gain setting ( table 27 ) default: ?00? addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h dsp1 limiter mode control 1lfstn 1zelmn 1rgain1 1rgain0 1l mat1 1lmat0 1lmth1 1lmth0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 1lmth1-0: dsp1 limiter detection level / recovery counter reset level ( table 31 ) default: ?00? 1lmat1-0: dsp1 limiter att step ( table 32 ) default: ?00? 1rgain1-0: dsp1 recovery gain step ( table 35 ) default: ?00? 1zelmn: dsp1 zero crossing detec tion enable at limiter operation 0: enable (default) 1: disable 1lfstn: dsp1 limiter functions when the output was bigger than full scale 0: when output is bigger than full scale, vol value is changed instantly. (default) 1: the output is changed by the limiter operation at the ze ro crossing point or at th e zero crossing timeout.
[ak4753] ms1311-e-00 2011/07 - 64 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h dsp1 timer select 1rfst1 1rfst0 1wtm2 1wtm1 1wtm0 1ztm1 1ztm0 dvtm r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 1rfst1-0: dsp1 firs t recovery speed ( table 37 ) default: ?00? (4times) 1wtm2-0: dsp1 recovery waiting period ( table 34 ) default: ?000? (128/fs) 1ztm1-0: dsp1 limiter/recovery operation zero crossing timeout period ( table 33 ) default: ?00? (128/fs) dvtm: digital volume transition time setting 0: 1061/fs (default) 1: 256/fs this is the transition time between l/r7-0 bits = 00h and ffh. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah dsp1 reference level 1ref7 1ref6 1ref5 1ref4 1ref3 1ref2 1ref1 1ref0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 0 0 0 1 1ref7-0: dsp1 reference level at recovery operation ( table 36 ) default: ?f1h? (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh dsp2 limiter mode control 2lfstn 2zelmn 2rgain1 2rgain0 2l mat1 2lmat0 2lmth1 2lmth0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 2lmth1-0: dsp2 limiter detection level / recovery counter reset level ( table 31 ) default: ?00? 2lmat1-0: dsp2 limiter att step ( table 32 ) default: ?00? 2rgain1-0: dsp2 recovery gain step ( table 35 ) default: ?00? 2zelmn: dsp2 zero crossing detec tion enable at limiter operation 0: enable (default) 1: disable 2lfstn: dsp2 limiter functions when the output was bigger than full scale 0: when output is bigger than full scale, vol value is changed instantly. (default) 1: the output is changed by the limiter operation at the ze ro crossing point or at th e zero crossing timeout.
[ak4753] ms1311-e-00 2011/07 - 65 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch dsp2 timer select 2rfst1 2rfst0 2wtm2 2wtm1 2wtm0 2ztm1 2ztm0 0 r/w r/w r/w r/w r/w r/w r/w r/w rd default 0 0 0 0 0 0 0 0 2rfst1-0: dsp2 firs t recovery speed ( table 37 ) default: ?00? (4times) 2wtm2-0: dsp2 recovery waiting period ( table 34 ) default: ?000? (128/fs) 2ztm1-0: dsp2 limiter/recovery operation zero crossing timeout period ( table 33 ) default: ?00? (128/fs) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh dsp2 reference level 2ref7 2ref6 2ref5 2ref4 2ref3 2ref2 2ref1 2ref0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 0 0 0 1 2ref7-0: dsp2 reference level at recovery operation ( table 36 ) default: ?f1h? (0db)
[ak4753] ms1311-e-00 2011/07 - 66 - register definitions of dsp1 function each setting of the function is shown below. to distinguish dsp1 and dsp2, ?1? is added to the head of each bit name for dsp1, and ?2? is added for dsp2. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh hpf/lpf setting 0 0 0 0 0 0 1filsel 1filen r/w rd rd rd rd rd rd r/w r/w default 0 0 0 0 0 0 0 0 1filen: high pass and low pass filter enable bit 0: hpf and lpf disable (default) 1: hpf and lpf enable 1filsel: hpf or lpf select bit 0: lpf becomes ef fective (default) 1: hpf becomes effective addr register name d7 d6 d5 d4 d3 d2 d1 d0 0fh dsp1 filter a coefficient 1 1fa7 1fa6 1fa5 1fa4 1fa3 1fa2 1fa1 1fa0 10h dsp1 filter a coefficient 2 1fa15 1fa14 1fa13 1fa12 1fa11 1fa10 1fa9 1fa8 11h dsp1 filter a coefficient 3 0 0 0 0 1fa19 1fa18 1fa17 1fa16 12h dsp1 filter b coefficient 1 1fb7 1fb6 1fb5 1fb4 1fb3 1fb2 1fb1 1fb0 13h dsp1 filter b coefficient 2 1fb15 1fb14 1fb13 1fb12 1fb11 1fb10 1fb9 1fb8 14h dsp1 filter b coefficient 3 0 0 0 0 1fb19 1fb18 1fb17 1fb16 15h dsp1 filter c coefficient 1 1fc7 1fc6 1fc5 1fc4 1fc3 1fc2 1fc1 1fc0 16h dsp1 filter c coefficient 2 1fc15 1fc14 1fc13 1fc12 1fc11 1fc10 1fc9 1fc8 17h dsp1 filter c coefficient 3 0 0 0 0 1fc19 1fc18 1fc17 1fc16 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 1fa19-0, 1fb19-0, 1fc19-0: hpf and lpf coefficient setting bit default: ?00000h?
[ak4753] ms1311-e-00 2011/07 - 67 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 18h dsp1 eq select 0 0 0 1eq5 1eq4 1eq3 1eq2 1eq1 r/w rd rd rd r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 1eq1: equalizer 1 coefficient setting enable 0: disable (default) 1: enable when 1eq1 bit is ?1?, settings of 1e1a19-0, 1e1b19-0 and 1e1c19-0 bits are enabled. when 1eq1 bit is ?0?, the audio data passes this block by 0db gain. 1eq2: equalizer 2 coefficient setting enable 0: disable (default) 1: enable when 1eq2 bit is ?1?, settings of 1e2a19-0, 1e2b19-0 and 1e2c19-0 bits are enabled. when 1eq2 bit is ?0?, the audio data passes this block by 0db gain. 1eq3: equalizer 3 coefficient setting enable 0: disable (default) 1: enable when 1eq3 bit is ?1?, settings of 1e3a19-0, 1e3b19-0 and 1e3c19-0 bits are enabled. when 1eq3 bit is ?0?, the audio data passes this block by 0db gain. 1eq4: equalizer 4 coefficient setting enable 0: disable (default) 1: enable when 1eq4 bit is ?1?, settings of 1e4a19-0, 1e4b19-0 and 1e4c19-0 bits are enabled. when 1eq4 bit is ?0?, the audio data passes this block by 0db gain. 1eq5: equalizer 5 coefficient setting enable 0: disable (default) 1: enable when 1eq5 bit is ?1?, settings of 1e5a19-0, 1e5b19-0 and 1e5c19-0 bits are enabled. when 1eq5 bit is ?0?, the audio data passes this block by 0db gain. addr register name d7 d6 d5 d4 d3 d2 d1 d0 19h dsp1 eq1 a coefficient 1 1e1a7 1e1a6 1e1a5 1e1a4 1e1a3 1e1a2 1e1a1 1e1a0 1ah dsp1 eq1 a coefficient 2 1e1a15 1e1a14 1e1a13 1e1a12 1e1a11 1e1a10 1e1a9 1e1a8 1bh dsp1 eq1 a coefficient 3 0 0 0 0 1e1a19 1e1a18 1e1a17 1e1a16 1ch dsp1 eq1 b coefficient 1 1e1b7 1e1b6 1e1b5 1e1b4 1e1b3 1e1b2 1e1b1 1e1b0 1dh dsp1 eq1 b coefficient 2 1e1b15 1e1b14 1e1b13 1e1b12 1e1b11 1e1b10 1e1b9 1e1b8 1eh dsp1 eq1 b coefficient 3 0 0 0 0 1e1b19 1e1b18 1e1b17 1e1b16 1fh dsp1 eq1 c coefficient 1 1e1c7 1e1c6 1e1c5 1e1c4 1e1c3 1e1c2 1e1c1 1e1c0 20h dsp1 eq1 c coefficient 2 1e1c15 1e1c14 1e1c13 1e1c12 1e1c11 1e1c10 1e1c9 1e1c8 21h dsp1 eq1 c coefficient 3 0 0 0 0 1e1c19 1e1c18 1e1c17 1e1c16
[ak4753] ms1311-e-00 2011/07 - 68 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 22h dsp1 eq2 a coefficient 1 1e2a7 1e2a6 1e2a5 1e2a4 1e2a3 1e2a2 1e2a1 1e2a0 23h dsp1 eq2 a coefficient 2 1e2a15 1e2a14 1e2a13 1e2a12 1e2a11 1e2a10 1e2a9 1e2a8 24h dsp1 eq2 a coefficient 3 0 0 0 0 1e2a19 1e2a18 1e2a17 1e2a16 25h dsp1 eq2 b coefficient 1 1e2b7 1e2b6 1e2b5 1e2b4 1e2b3 1e2b2 1e2b1 1e2b0 26h dsp1 eq2 b coefficient 2 1e2b15 1e2b14 1e2b13 1e2b12 1e2b11 1e2b10 1e2b9 1e2b8 27h dsp1 eq2 b coefficient 3 0 0 0 0 1e2b19 1e2b18 1e2b17 1e2b16 28h dsp1 eq2 c coefficient 1 1e2c7 1e2c6 1e2c5 1e2c4 1e2c3 1e2c2 1e2c1 1e2c0 29h dsp1 eq2 c coefficient 2 1e2c15 1e2c14 1e2c13 1e2c12 1e2c11 1e2c10 1e2c9 1e2c8 2ah dsp1 eq2 c coefficient 3 0 0 0 0 1e2c19 1e2c18 1e2c17 1e2c16 2bh dsp1 eq3 a coefficient 1 1e3a7 1e3a6 1e3a5 1e3a4 1e3a3 1e3a2 1e3a1 1e3a0 2ch dsp1 eq3 a coefficient 2 1e3a15 1e3a14 1e3a13 1e3a12 1e3a11 1e3a10 1e3a9 1e3a8 2dh dsp1 eq3 a coefficient 3 0 0 0 0 1e3a19 1e3a18 1e3a17 1e3a16 2eh dsp1 eq3 b coefficient 1 1e3b7 1e3b6 1e3b5 1e3b4 1e3b3 1e3b2 1e3b1 1e3b0 2fh dsp1 eq3 b coefficient 2 1e3b15 1e3b14 1e3b13 1e3b12 1e3b11 1e3b10 1e3b9 1e3b8 30h dsp1 eq3 b coefficient 3 0 0 0 0 1e3b19 1e3b18 1e3b17 1e3b16 31h dsp1 eq3 c coefficient 1 1e3c7 1e3c6 1e3c5 1e3c4 1e3c3 1e3c2 1e3c1 1e3c0 32h dsp1 eq3 c coefficient 2 1e3c15 1e3c14 1e3c13 1e3c12 1e3c11 1e3c10 1e3c9 1e3c8 33h dsp1 eq3 c coefficient 3 0 0 0 0 1e3c19 1e3c18 1e3c17 1e3c16 34h dsp1 eq4 a coefficient 1 1e4a7 1e4a6 1e4a5 1e4a4 1e4a3 1e4a2 1e4a1 1e4a0 35h dsp1 eq4 a coefficient 2 1e4a15 1e4a14 1e4a13 1e4a12 1e4a11 1e4a10 1e4a9 1e4a8 36h dsp1 eq4 a coefficient 3 0 0 0 0 1e4a19 1e4a18 1e4a17 1e4a16 37h dsp1 eq4 b coefficient 1 1e4b7 1e4b6 1e4b5 1e4b4 1e4b3 1e4b2 1e4b1 1e4b0 38h dsp1 eq4 b coefficient 2 1e4b15 1e4b14 1e4b13 1e4b12 1e4b11 1e4b10 1e4b9 1e4b8 39h dsp1 eq4 b coefficient 3 0 0 0 0 1e4b19 1e4b18 1e4b17 1e4b16 3ah dsp1 eq4 c coefficient 1 1e4c7 1e4c6 1e4c5 1e4c4 1e4c3 1e4c2 1e4c1 1e4c0 3bh dsp1 eq4 c coefficient 2 1e4c15 1e4c14 1e4c13 1e4c12 1e4c11 1e4c10 1e4c9 1e4c8 3ch dsp1 eq4 c coefficient 3 0 0 0 0 1e4c19 1e4c18 1e4c17 1e4c16
[ak4753] ms1311-e-00 2011/07 - 69 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 3dh dsp1 eq5 a coefficient 1 1e5a7 1e5a6 1e5a5 1e5a4 1e5a3 1e5a2 1e5a1 1e5a0 3eh dsp1 eq5 a coefficient 2 1e5a15 1e5a14 1e5a13 1e5a12 1e5a11 1e5a10 1e5a9 1e5a8 3fh dsp1 eq5 a coefficient 3 0 0 0 0 1e5a19 1e5a18 1e5a17 1e5a16 40h dsp1 eq5 b coefficient 1 1e5b7 1e5b6 1e5b5 1e5b4 1e5b3 1e5b2 1e5b1 1e5b0 41h dsp1 eq5 b coefficient 2 1e5b15 1e5b14 1e5b13 1e5b12 1e5b11 1e5b10 1e5b9 1e5b8 42h dsp1 eq5 b coefficient 3 0 0 0 0 1e5b19 1e5b18 1e5b17 1e5b16 43h dsp1 eq5 c coefficient 1 1e5c7 1e5c6 1e5c5 1e5c4 1e5c3 1e5c2 1e5c1 1e5c0 44h dsp1 eq5 c coefficient 2 1e5c15 1e5c14 1e5c13 1e5c12 1e5c11 1e5c10 1e5c9 1e5c8 45h dsp1 eq5 c coefficient 3 0 0 0 0 1e5c19 1e5c18 1e5c17 1e5c16 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 1e1a19-0, 1e1b19-0, 1e1c19-0: equalizer 1 coefficient (20-bit x3) default: ?00000h? 1e2a19-0, 1e2b19-0, 1e2c19-0: equalizer 2 coefficient (20-bit x3) default: ?00000h? 1e3a19-0, 1e3b19-0, 1e3c19-0: equalizer 3 coefficient (20-bit x3) default: ?00000h? 1e4a19-0, 1e4b19-0, 1e4c19-0: equalizer 4 coefficient (20-bit x3) default: ?00000h? 1e5a19-0, 1e5b19-0, 1e5c19-0: equalizer 5 coefficient (20-bit x3) default: ?00000h?
[ak4753] ms1311-e-00 2011/07 - 70 - register definitions of dsp2 function each setting of the function is shown below. to distinguish dsp1 and dsp2, ?1? is added to the head of each bit name for dsp1, and ?2? is added for dsp2. addr register name d7 d6 d5 d4 d3 d2 d1 d0 46h hpf/lpf setting 0 0 0 0 0 0 2filsel 2filen r/w rd rd rd rd rd rd r/w r/w default 0 0 0 0 0 0 0 0 2filen: high pass and low pass filter enable bit 0: hpf and lpf disable (default) 1: hpf and lpf enable 2filsel: hpf or lpf select bit 0: lpf becomes ef fective (default) 1: hpf becomes effective addr register name d7 d6 d5 d4 d3 d2 d1 d0 47h dsp2 filter a coefficient 1 2fa7 2fa6 2fa5 2fa4 2fa3 2fa2 2fa1 2fa0 48h dsp2 filter a coefficient 2 2fa15 2fa14 2fa13 2fa12 2fa11 2fa10 2fa9 2fa8 49h dsp2 filter a coefficient 3 0 0 0 0 2fa19 2fa18 2fa17 2fa16 4ah dsp2 filter b coefficient 1 2fb7 2fb6 2fb5 2fb4 2fb3 2fb2 2fb1 2fb0 4bh dsp2 filter b coefficient 2 2fb15 2fb14 2fb13 2fb12 2fb11 2fb10 2fb9 2fb8 4ch dsp2 filter b coefficient 3 0 0 0 0 2fb19 2fb18 2fb17 2fb16 4dh dsp2 filter c coefficient 1 2fc7 2fc6 2fc5 2fc4 2fc3 2fc2 2fc1 2fc0 4eh dsp2 filter c coefficient 2 2fc15 2fc14 2fc13 2fc12 2fc11 2fc10 2fc9 2fc8 4fh dsp2 filter c coefficient 3 0 0 0 0 2fc19 2fc18 2fc17 2fc16 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 2fa19-0, 2fb19-0, 2fc19-0: hpf and lpf coefficient setting bit default: ?00000h?
[ak4753] ms1311-e-00 2011/07 - 71 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 50h dsp2 eq select 0 0 0 2eq5 2eq4 2eq3 2eq2 2eq1 r/w rd rd rd r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 2eq1: equalizer 1 coefficient setting enable 0: disable (default) 1: enable when 2eq1 bit is ?1?, settings of 2e1a19-0, 2e1b19-0 and 2e1c19-0 bits are enabled. when 2eq1 bit is ?0?, the audio data passes this block by 0db gain. 2eq2: equalizer 2 coefficient setting enable 0: disable (default) 1: enable when 2eq2 bit is ?1?, settings of 2e2a19-0, 2e2b19-0 and 2e2c19-0 bits are enabled. when 2eq2 bit is ?0?, the audio data passes this block by 0db gain. 2eq3: equalizer 3 coefficient setting enable 0: disable (default) 1: enable when 2eq3 bit is ?1?, settings of 2e3a19-0, 2e3b19-0 and 2e3c19-0 bits are enabled. when 2eq3 bit is ?0?, the audio data passes this block by 0db gain. 2eq4: equalizer 4 coefficient setting enable 0: disable (default) 1: enable when 2eq4 bit is ?1?, settings of 2e4a19-0, 2e4b19-0 and 2e4c19-0 bits are enabled. when 2eq4 bit is ?0?, the audio data passes this block by 0db gain. 2eq5: equalizer 5 coefficient setting enable 0: disable (default) 1: enable when 2eq5 bit is ?1?, settings of 2e5a19-0, 2e5b19-0 and 2e5c19-0 bits are enabled. when 2eq5 bit is ?0?, the audio data passes this block by 0db gain. addr register name d7 d6 d5 d4 d3 d2 d1 d0 51h dsp2 eq1 a coefficient 1 2e1a7 2e1a6 2e1a5 2e1a4 2e1a3 2e1a2 2e1a1 2e1a0 52h dsp2 eq1 a coefficient 2 2e1a15 2e1a14 2e1a13 2e1a12 2e1a11 2e1a10 2e1a9 2e1a8 53h dsp2 eq1 a coefficient 3 0 0 0 0 2e1a19 2e1a18 2e1a17 2e1a16 54h dsp2 eq1 b coefficient 1 2e1b7 2e1b6 2e1b5 2e1b4 2e1b3 2e1b2 2e1b1 2e1b0 55h dsp2 eq1 b coefficient 2 2e1b15 2e1b14 2e1b13 2e1b12 2e1b11 2e1b10 2e1b9 2e1b8 56h dsp2 eq1 b coefficient 3 0 0 0 0 2e1b19 2e1b18 2e1b17 2e1b16 57h dsp2 eq1 c coefficient 1 2e1c7 2e1c6 2e1c5 2e1c4 2e1c3 2e1c2 2e1c1 2e1c0 58h dsp2 eq1 c coefficient 2 2e1c15 2e1c14 2e1c13 2e1c12 2e1c11 2e1c10 2e1c9 2e1c8 59h dsp2 eq1 c coefficient 3 0 0 0 0 2e1c19 2e1c18 2e1c17 2e1c16
[ak4753] ms1311-e-00 2011/07 - 72 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 5ah dsp2 eq2 a coefficient 1 2e2a7 2e2a6 2e2a5 2e2a4 2e2a3 2e2a2 2e2a1 2e2a0 5bh dsp2 eq2 a coefficient 2 2e2a15 2e2a14 2e2a13 2e2a12 2e2a11 2e2a10 2e2a9 2e2a8 5ch dsp2 eq2 a coefficient 3 0 0 0 0 2e2a19 2e2a18 2e2a17 2e2a16 5dh dsp2 eq2 b coefficient 1 2e2b7 2e2b6 2e2b5 2e2b4 2e2b3 2e2b2 2e2b1 2e2b0 5eh dsp2 eq2 b coefficient 2 2e2b15 2e2b14 2e2b13 2e2b12 2e2b11 2e2b10 2e2b9 2e2b8 5fh dsp2 eq2 b coefficient 3 0 0 0 0 2e2b19 2e2b18 2e2b17 2e2b16 60h dsp2 eq2 c coefficient 1 2e2c7 2e2c6 2e2c5 2e2c4 2e2c3 2e2c2 2e2c1 2e2c0 61h dsp2 eq2 c coefficient 2 2e2c15 2e2c14 2e2c13 2e2c12 2e2c11 2e2c10 2e2c9 2e2c8 62h dsp2 eq2 c coefficient 3 0 0 0 0 2e2c19 2e2c18 2e2c17 2e2c16 63h dsp2 eq3 a coefficient 1 2e3a7 2e3a6 2e3a5 2e3a4 2e3a3 2e3a2 2e3a1 2e3a0 64h dsp2 eq3 a coefficient 2 2e3a15 2e3a14 2e3a13 2e3a12 2e3a11 2e3a10 2e3a9 2e3a8 65h dsp2 eq3 a coefficient 3 0 0 0 0 2e3a19 2e3a18 2e3a17 2e3a16 66h dsp2 eq3 b coefficient 1 2e3b7 2e3b6 2e3b5 2e3b4 2e3b3 2e3b2 2e3b1 2e3b0 67h dsp2 eq3 b coefficient 2 2e3b15 2e3b14 2e3b13 2e3b12 2e3b11 2e3b10 2e3b9 2e3b8 68h dsp2 eq3 b coefficient 3 0 0 0 0 2e3b19 2e3b18 2e3b17 2e3b16 69h dsp2 eq3 c coefficient 1 2e3c7 2e3c6 2e3c5 2e3c4 2e3c3 2e3c2 2e3c1 2e3c0 6ah dsp2 eq3 c coefficient 2 2e3c15 2e3c14 2e3c13 2e3c12 2e3c11 2e3c10 2e3c9 2e3c8 6bh dsp2 eq3 c coefficient 3 0 0 0 0 2e3c19 2e3c18 2e3c17 2e3c16 6ch dsp2 eq4 a coefficient 1 2e4a7 2e4a6 2e4a5 2e4a4 2e4a3 2e4a2 2e4a1 2e4a0 6dh dsp2 eq4 a coefficient 2 2e4a15 2e4a14 2e4a13 2e4a12 2e4a11 2e4a10 2e4a9 2e4a8 6eh dsp2 eq4 a coefficient 3 0 0 0 0 2e4a19 2e4a18 2e4a17 2e4a16 6fh dsp2 eq4 b coefficient 1 2e4b7 2e4b6 2e4b5 2e4b4 2e4b3 2e4b2 2e4b1 2e4b0 70h dsp2 eq4 b coefficient 2 2e4b15 2e4b14 2e4b13 2e4b12 2e4b11 2e4b10 2e4b9 2e4b8 71h dsp2 eq4 b coefficient 3 0 0 0 0 2e4b19 2e4b18 2e4b17 2e4b16 72h dsp2 eq4 c coefficient 1 2e4c7 2e4c6 2e4c5 2e4c4 2e4c3 2e4c2 2e4c1 2e4c0 73h dsp2 eq4 c coefficient 2 2e4c15 2e4c14 2e4c13 2e4c12 2e4c11 2e4c10 2e4c9 2e4c8 74h dsp2 eq4 c coefficient 3 0 0 0 0 2e4c19 2e4c18 2e4c17 2e4c16
[ak4753] ms1311-e-00 2011/07 - 73 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 75h dsp2 eq5 a coefficient 1 2e5a7 2e5a6 2e5a5 2e5a4 2e5a3 2e5a2 2e5a1 2e5a0 76h dsp2 eq5 a coefficient 2 2e5a15 2e5a14 2e5a13 2e5a12 2e5a11 2e5a10 2e5a9 2e5a8 77h dsp2 eq5 a coefficient 3 0 0 0 0 2e5a19 2e5a18 2e5a17 2e5a16 78h dsp2 eq5 b coefficient 1 2e5b7 2e5b6 2e5b5 2e5b4 2e5b3 2e5b2 2e5b1 2e5b0 79h dsp2 eq5 b coefficient 2 2e5b15 2e5b14 2e5b13 2e5b12 2e5b11 2e5b10 2e5b9 2e5b8 7ah dsp2 eq5 b coefficient 3 0 0 0 0 2e5b19 2e5b18 2e5b17 2e5b16 7bh dsp2 eq5 c coefficient 1 2e5c7 2e5c6 2e5c5 2e5c4 2e5c3 2e5c2 2e5c1 2e5c0 7ch dsp2 eq5 c coefficient 2 2e5c15 2e5c14 2e5c13 2e5c12 2e5c11 2e5c10 2e5c9 2e5c8 7dh dsp2 eq5 c coefficient 3 0 0 0 0 2e5c19 2e5c18 2e5c17 2e5c16 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 2e1a19-0, 2e1b19-0, 2e1c19-0: equalizer 1 coefficient (20-bit x3) default: ?00000h? 2e2a19-0, 2e2b19-0, 2e2c19-0: equalizer 2 coefficient (20-bit x3) default: ?00000h? 2e3a19-0, 2e3b19-0, 2e3c19-0: equalizer 3 coefficient (20-bit x3) default: ?00000h? 2e4a19-0, 2e4b19-0, 2e4c19-0: equalizer 4 coefficient (20-bit x3) default: ?00000h? 2e5a19-0, 2e5b19-0, 2e5c19-0: equalizer 5 coefficient (20-bit x3) default: ?00000h?
[ak4753] ms1311-e-00 2011/07 - 74 - system design figure 75 and figure 76 shows the system connection diagram. an evaluation board (akd4753) is available for fast evaluation as well as suggestions for peripheral circuitry. p power supply 3.0 3.6v 10u potentiometer (vol control) nc xto xti dvdd vss2 reg bypass nc bic k lrc k sdt i sto muten eescl lout2 rout2 rout1 lout1 a vdd vss1 ainl eesda extee pdn flt test sain1 sain2 ain r a k4753 top view 25 26 27 28 29 30 31 32 24 23 16 15 14 13 12 11 10 9 22 21 20 19 18 1 2 3 4 5 6 7 8 sc l sd a speaker external speaker-amp a nalog ground digital ground c p 10 r p vcom x?tal c c potentiometer (bass gain control) 17 avdd 2.2u 0.1u avdd analo g in 0.1u 2.2u 10u ?l?: mute ?h?: normal operation digital in ?l?: normal operation ?h?: dsp bypass mode notes: - vss1 and vss2 of the ak4753 must be distributed separately from the ground of external controllers. - all digital input pins must not be left floating. - when the ext mode is used (pmpll bit = ?0?), flt pin can be open. - when the pll mode is used (pmpll bit = ?1?), ?cp? and ?rp? must be set according to table 5 . - ?c? value is dependent on the crystal. - when the ak4753 is used in master mode, lrck and bick pins are floating before m/s bit is changed to ?1?. therefore, around 100k pull-up/down resistor must be connected to lrck and bick pins of the ak4753. - 0.1 f capacitors at power supply pins should be cera mic capacitors. other capacitors do not have specific types. figure 75. system connection diagram (serial control mode: extee pin = ?l?)
[ak4753] ms1311-e-00 2011/07 - 75 - eep-rom power supply 3.0 3.6v 10u potentiometer (vol control) nc xto xti dvdd vss2 reg bypass nc bic k lrc k sdt i sto muten eescl lout2 rout2 rout1 lout1 a vdd vss1 ainl eesda extee pdn flt test sain1 sain2 ain r a k4753 top view 25 26 27 28 29 30 31 32 24 23 16 15 14 13 12 11 10 9 22 21 20 19 18 1 2 3 4 5 6 7 8 sc l sd a speaker external speaker-amp a nalog ground digital ground c p 10 r p vcom x?tal c c potentiometer (bass gain control) 17 avdd 2.2u 0.1u avdd analo g in 0.1u 2.2u 10u ?l?: mute ?h?: normal operation digital in dvdd reset ic ?l?: normal operation ?h?: dsp bypass mode notes: - vss1 and vss2 of the ak4753 must be distributed separately from the ground of external controllers. - all digital input pins must not be left floating. - when the ext mode is used (pmpll bit = ?0?), flt pin can be open. - when the pll mode is used (pmpll bit = ?1?), ?cp? and ?rp? must be set according to table 5 . - ?c? value is dependent on the crystal. - when the ak4753 is used in master mode, lrck and bick pins are floating before m/s bit is changed to ?1?. therefore, around 100k pull-up/down resistor must be connected to lrck and bick pins of the ak4753. - 0.1 f capacitors at power supply pins should be cera mic capacitors. other capacitors do not have specific types. figure 76. system connection diagram (eep-rom download mode: extee pin = ?h?)
[ak4753] ms1311-e-00 2011/07 - 76 - 1. grounding and power supply decoupling the ak4753 requires careful attention to power supply and grounding arrangements. if avdd and dvdd are supplied separately, the power-up sequence is no t critical. vss1 and vss2 of the ak475 3 must be connected to the analog ground plane. system analog ground and digital ground must be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors mu st be as near to the ak4753 as possible, with the small value ceramic capacitor being the nearest. 2. internal regulated voltage power supply the input voltage to the reg pin is used as power supply (typ. 1.8v) for the internal digital circuit. a 2.2 f50% ceramic capacitor connected between the reg and vss2 pins eliminates the effects of high frequency noise. this capacitor in particular should be connected as close as possible to the pin. no load current may be drawn from the reg pin. all digital signals, especially clocks, should be kept away from the reg pin in order to avoid unwanted coupling into the ak4753. 3. voltage reference vcom is a signal ground of this chip. a 2.2 f50% ceramic capacitor connected be tween this pin and the vss1 pin eliminates the effects of high frequency noise. this capacitor in particular should be connected as close as possible to the pin. no load current may be drawn from the vcom pin. all digital signals, especially clocks, must be kept away from the vcom pin in order to avoid unwanted coupling into the ak4753. 4. analog inputs the line inputs are single-ended. the input signal range scales with nominally at typ. 2.64vpp (0.8 x avdd), centered around the internal signal ground (avdd/2). usually the input signal is ac coupled usin g a capacitor. the cut-off frequency is fc = 1/ (2 rc). the ak4753 can accept input voltages from vss1 to avdd. 5. analog outputs the input data format for the dac is 2?s complement. the output voltage is a positive full scale for 7fffffh (@24-bit) and a negative full scale for 800000h (@24-bit). the ideal output is vcom voltage for 000000h (@24-bit). the line outputs are single -ended or differential a nd centered at avdd/2.
[ak4753] ms1311-e-00 2011/07 - 77 - control sequence clock setup when any circuits of the ak4753 are powered-up, the clocks must be supplied. 1. pll master mode bick pin lrck pin pw xtl bit pmpll bit (addr:04h, d2,d7) 4ms (max) output (1) (5) power supply pdn pin regulator vcom (2) xti/mcki pin (4) (3) input m/s bit (addr:01h, d3) 1ms(max) example: audio i/f format: msb justified bick frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ? h? (3) addr:02h, data:f4h addr:03h, data:c2h re g ulator, vcom powe r -up ( 4 ) addr:04h, data:84h bick and lrck outpu t figure 77. clock set up sequence (1) (1) after power up, pdn pin ?l? ? ?h? ?l? time of 10ms or more is needed to reset the ak4753. (2) power up vcom and regulator power up time is 1ms (max). to write register is forbidden during this period. (3) fs3-0, pll3-0, bcko, bckp, msbs and dif2-0 bits must be set during this period. (4) pwxtl and pmpll bits change from ?0? to ?1?. then pll starts after the crystal oscillator becomes stable or xti/mcki pin is supplied from an exte rnal source. pll lock time is 4ms (max). (5) the ak4753 starts to output the lrck and bick clocks after the pll became stable. then normal operation starts.
[ak4753] ms1311-e-00 2011/07 - 78 - 2. pll slave mode (lrck or bick pin) internal clock pmpll bit (addr:04h, d7) 40ms (max) output (1) (5) power supply pdn pin regulator vcom (2) lrck pin bick pin (4) (3) input 1ms(max) 4fs of example: audio i/f format : msb justified pll reference clock: bick bick frequency: 64fs sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? ( 4 ) addr:04h, data:80h (3) addr:02h, data:83h addr:03h, data:02h regulator, vcom power-up figure 78. clock set up sequence (2) (1) after power up: pdn pin ?l? ? ?h? ?l? time of 10ms or more is needed to reset the ak4753. (2) power up vcom and regulator power up time is 1ms (max). to write register is forbidden during this period. (3) fs3-2, pll3-0, bckp, msbs and dif2-0 b its must be set during this period. (4) pwxtl and pmpll bits change from ?0? to ?1?. th en pll starts after pll reference clock (lrck or bick pin) is supplied from an external source. pll lock time is 40ms (max) when lrck is a pll reference clock. pll lock time is 4ms (max) when bick is a pll reference clock. (5) normal operation stats after that the pll is locked.
[ak4753] ms1311-e-00 2011/07 - 79 - 3. ext slave mode (1) power supply pdn pin regulator vcom (2) mcki pin bick pin lrck pin (4) (3) input 1ms(max) example: (1) power supply & pdn pin = ? l? ? ?h? mcki, bick and lrck input (3) addr:02h, data:00h addr:03h, data:02h regulator, vcom power-up audio i/f format: msb justified input mcki frequency: 256fs sampling frequency: 44.1khz figure 79. clock set up sequence (3) (1) after power up: pdn pin ?l? ? ?h? ?l? time of 10ms or more is needed to reset the ak4753. (2) power up vcom and regulator power up time is 1ms (max). to write register is forbidden during this period. (3) fs1-0, bckp, msbs and dif2-0 bits must be set during this period. (4) normal operation starts after the mcki, lrck and bick are supplied. 4. ext master mode bick pin lrck pin pw xtl bit (addr:04h, d2) output (1) power supply pdn pin regulator vcom (2) xti/mcki pin (3) input m/s bit (addr:03h, d6) 1ms(max) (4) example: audio i/f format: msb justified input mcki frequency: 256fs bick frequency: 64fs sampling frequency: 44.1khz ( 1 ) power suppl y & pdn pin = ?l? ? ? h? (3) addr:02h, data:00h addr:03h, data:82h re g ulator, vcom powe r -up (4) addr:03h, data:c2h bick and lrck outpu t figure 80. clock set up sequence (4) (1) after power up: pdn pin ?l? ? ?h? ?l? time of 10ms or more is needed to reset the ak4753. (2) power up vcom and regulator power up time is 1ms (max). to write register is forbidden during this period. (3) fs1-0, bcko, bckp, msbs an d dif2-0 bits must be set during this period. (4) m/s bit should be set to ?1? after the crystal oscillator becomes stable or mcki is supplied from an external source. then lrck and bick are output.
[ak4753] ms1311-e-00 2011/07 - 80 - dac outputs fs3-0 bits (addr:02h, d7-4) 0000 normal output (1) (9) (7) (11) (12) siglnal path (addr:01h) 00h ffh (3) (8) (2) (6) dsp1 limiter control (addr:08-0ah) xx....x (4) dsp2 limiter control (addr:0b-0dh) (5) dsp1 eq coef (addr:18-45h) 00h e0h l/r7-0 bits (addr:05h&06h, d7-0) dsp1 filter coef (addr:0e-17h) dsp2 eq coef (addr:50-7dh) dsp2 filter coef (addr:46-4fh) pmlo1/2 bits pmdig bit pmadc bit (addr:04h, d5-4,d3,d0) (10) gain setting (addr:07h) limiter state limiter disable limiter enable limiter disable lout1/2 pins mout+/- pins muten pin mute off mute on 4ms (typ) 1111 xx....x xx....x xx....x xx....x xx....x xx....x xx....x xx....x xx....x xx....x xx....x xx....x xx....x mute on example: pll maste r mode audio i/f format: msb justified input mcki frequ ency:11. 2896mhz sampling frequency: 44.1khz input signal setting: analog d ac output configuratio n: 2.1ch mode digital volume: ? 30db l imiter and eq: enable ( 2 ) addr:01h, data:e0h ( 1 ) addr:02h, data:f4h ( 9 ) addr:46h, data:01h ( 10 ) addr:50h, data:1fh ( 11 ) addr:04h, data:bdh ( 12 ) addr:04h, data:84h pla y back ( 3 ) addr:05h &06h, data:00h (7) addr:0eh, data:03h (5) addr:08h, data:01h addr:09h, data:1eh a ddr:0 a h, data:30h (6) addr:0bh, data:01h addr:0ch, data:1eh addr:0dh, data:30h ( 4 ) addr:07h, data:55h (8) addr:18h, data:1fh figure 81. dac output sequence at first, clocks must be supplied acc ording to ?clock set up? sequence. (1) set up a sampling frequency (fs3-0 bits). when the ak4753 is pll mode, dac of (11) must be powered-up in consideration of pll lock time after a sampling frequency is changed. (2) set up the path of analog input ? dac ? 2.1ch output and the almt1/2 bits: sel1-0 bits = ?00? ? ?00?, spc1-0 bits = ?00? ? ?10?, almt1/2 bits = ?0? ?1? (3) set up the output digital volume (addr = 05h, 06h) after dac is powered-up, the digital volume changes fro m default value (mute) to the register setting value by the soft transition. (4) set up the pre-gain and post-gain: 1pre g1-0 bits = 2preg1-0 bits = ?00? ?01?, 1pstg1-0 bits = 2pstg1-0 bits = ?00? ?01? (5) set up 1lmth1-0, 1lmat1-0, 1rga in1-0, 1zelmn, 1lfstn, 1ztm1-0, 1wtm2-0 and 1rfsn1-0 bits (addr = 08h, 09h) and the ref value (addr: 0ah) for limiter of dsp1 set up 2lmth1-0, 2lmat1-0, 2rgain1-0, 2zelmn, 2lfstn, 2ztm1-0, 2wtm2- 0 and 2rfsn1-0 bits (addr = 0bh, 0ch) and the ref value (addr: 0dh) for limiter of dsp2 (6) set up coefficient of lpf/hpf for dsp1 (addr: 0eh ~ 17h) (7) set up coefficient of eq for dsp1 (addr: 18h ~ 45h) (8) set up coefficient of lpf/hpf for dsp2 (addr: 46h ~ 4fh) (9) set up coefficient of eq for dsp2 (addr: 50h ~ 7dh) (10) power up the adc, dsp, dac and line-amp: pmadc = pmdig = pmlo1 = pmlo2 bits = ?0? ?1? when almt1 bit or almt2 bit = ?1?, limiter operation starts from the gain set by l/r7-0 bits after the initialization cycle of adc (1 059/fs = 24ms @fs=44.1khz). (11) power down the adc, dsp, dac and line-amp: pmadc = pmdig = pmlo1 = pmlo2 bits = ?1? ?0?
[ak4753] ms1311-e-00 2011/07 - 81 - stop of clock when the ak4753 is not used, the master clock can be stopped. 1. pll master mode external mcki pwxtl bit pmpll bit (addr:04h, d2,d7) input (2) (1) example: audio i/f format: msb justified bick frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz ( 2 ) sto p an external mcki ( 1 ) addr:04h, data:00h figure 82. clock stopping sequence (1) (1) power down cristal oscillator and pll: pwxtl, pmpll bits = ?1? ?0? (2) stop an external master clock. 2. pll slave mode (lrck or bick pin) external bick pmpll bit (addr:04h, d7) input (1) (2) external lrck input (2) example audio i/f format : msb justified pll reference clock: bick bick frequency: 64fs (1) addr:04h, data:00h ( 2 ) stop the external clocks figure 83. clock stopping sequence (2) (1) power down pll: pmpll bit = ?1? ?0? (2) stop the external bick and lrck clocks. 3. ext slave mode external lrck input (1) external bick input (1) external mcki input (1) example audio i/f format :msb justified input mcki frequency:256fs ( 1 ) sto p the external clocks figure 84. clock stopping sequence (3) (1) stop the external mcki, bick and lrck clocks.
[ak4753] ms1311-e-00 2011/07 - 82 - 4. ext master mode lrck output bick output external mcki input (1) "h" or "l" "h" or "l" pwxtl bit (addr:04h, d2) example audio i/f format :msb justified input mcki frequency:256fs (1) addr:04h, data:00h or stop the external mcki figure 85. clock stopping sequence (4) (1) power down cristal oscillator (pwxtl bit = ?1? ?0?) or stop mcki clock. bick and lrck are fixed to ?h? or ?l?. power down power supply current can also be shut down (typ. 1 a) by stopping clocks and setting pdn pin = ?l?. when the pdn pin = ?l?, the registers are initialized.
[ak4753] ms1311-e-00 2011/07 - 83 - package 32pin qfn (unit: mm) 2.8 0.1 0.4 bsc 0.20 0.05 2.8 0.1 1 9 16 25 4.0 0.1 4.0 0.1 0.35 0.10 b a 8 32 17 24 exposed pad c0.35 0.05max 0.75 0.05 0.10 m c a b 0.08 c c * note: the exposed pad on the underside must be open or connected to the ground. package & lead frame material package molding compound: epoxy resin, halogen (bromine and chlorine) free lead frame material: cu alloy lead frame surface treatment: solder (pb free) plate
[ak4753] ms1311-e-00 2011/07 - 84 - marking 4753 xxxx 1 xxxx: date code identifier (4 digits)
[ak4753] ms1311-e-00 2011/07 - 85 - revision history date (yy/mm/dd) revision reason page/line contents 11/07/15 00 first edition important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the incorporatio n of these external circuits, application circuits, software and other related information in the design of your equipments. akm as sumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor auth orized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medi cine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who di stributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all resp onsibility and liability for and hold akm harmless from any and all claims arising from th e use of said product in the absence of such notification.

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