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1/12 april 2004 STD45NF75 n-channel 75v - 0.018 ? -40a dpak stripfet? ii power mosfet typical r ds (on) = 0.018 ? 100% avalanche tested gate charge minimized surface-mounting dpak (to-252) power package in tape & reel (suffix ?t4") description this power mosfet is the latest development of stmicroelectronis unique "single feature size?" strip-based process. the resulting transistor shows extremely high packing density for low on- resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. applications high current, switching applications type v dss r ds(on) i d STD45NF75 75 v <0.024 ? 40 a (**) 1 3 dpak to-252 (suffix ?t4?) internal schematic diagram ordering information absolute maximum ratings ( ?) pulse width limited by safe operating area. (**) current limited by package (1) i sd 40a, di/dt 800a/s, v dd v (br)dss , t j t jmax (2) starting t j = 25 o c, i d = 20 a, v dd = 40v sales type marking package packaging STD45NF75t4 d45nf75 dpak tape & reel symbol parameter value unit v ds drain-source voltage (v gs = 0) 75 v v dgr drain-gate voltage (r gs = 20 k ? ) 75 v v gs gate- source voltage 20 v i d (**) drain current (continuous) at t c = 25c 40 a i d drain current (continuous) at t c = 100c 30 a i dm ( ?) drain current (pulsed) 160 a p tot total dissipation at t c = 25c 100 w derating factor 0.67 w/c dv/dt (1) peak diode recovery voltage slope 20 v/ns e as (2) single pulse avalanche energy 500 mj t stg storage temperature -55 to 175 c t j operating junction temperature
STD45NF75 2/12 thermal data electrical characteristics (t case = 25 c unless otherwise specified) off on (* ) dynamic rthj-case thermal resistance junction-case max 1.5 c/w rthj-pcb thermal resistance junction-pcb max see curve on page 6 c/w t l maximum lead temperature for soldering purpose (for 10 sec. 1.6 mm from case) 275 c symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a v gs = 0 75 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating v ds = max rating t c = 125c 1 10 a a i gss gate-body leakage current (v ds = 0) v gs = 20 v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs i d = 250 a 24v r ds(on) static drain-source on resistance v gs = 10 v i d = 20 a 0.018 0.024 ? symbol parameter test conditions min. typ. max. unit g fs (*) forward transconductance v ds = 25 v i d =20 a 50 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 25v, f = 1 mhz, v gs = 0 1760 360 140 pf pf pf
3/12 STD45NF75 switching on switching off source drain diode (*) pulsed: pulse duration = 300 s, duty cycle 1.5 %. ( ?) pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time v dd = 37 v i d = 20 a r g =4.7 ? v gs = 10 v (resistive load, figure 3) 15 40 ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd =60 v i d =40a v gs = 10v (see test circuit, figure 4) 60 13 23 80 nc nc nc symbol parameter test conditions min. typ. max. unit t d(off) t f turn-off delay time fall time v dd = 37 v i d = 20 a r g =4.7 ?, v gs = 10 v (resistive load, figure 3) 55 12 ns ns symbol parameter test conditions min. typ. max. unit i sd i sdm ( ? ) source-drain current source-drain current (pulsed) 40 160 a a v sd (*) forward on voltage i sd = 40 a v gs = 0 1.5 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 40 a di/dt = 100a/s v dd = 30 v t j = 150c (see test circuit, figure 5) 120 410 7.5 ns nc a electrical characteristics (continued) thermal impedance safe operating area
STD45NF75 4/12 output characteristics transfer characteristics transconductance static drain-source on resistance gate charge vs gate-source voltage capacitance variations
5/12 STD45NF75 . . normalized gate threshold voltage vs temperature normalized on resistance vs temperature source-drain diode forward characteristics normalized breakdown voltage vs temperature. power derating vs tc max id current vs tc .
STD45NF75 6/12 thermal resistance rthj-a vs pcb copper area allowable iav vs. time in avalanche max power dissipation vs pcb copper area the previous curve gives the safe operating area for unclamped inductive loads, single pulse or repetitive, under the following conditions: p d(ave) = 0.5 * (1.3 * bv dss * i av ) e as(ar) = p d(ave) * t av where: i av is the allowable current in avalanche p d(ave) is the average power dissipation in avalanche (single pulse) t av is the time in avalanche to derate above 25 o c, at fixed i av , the following equation must be applied: i av = 2 * (t jmax - t case )/ (1.3 * bv dss * z th ) where: z th = k * r th is the value coming from normalized thermal response at fixed pulse width equal to t av .
7/12 STD45NF75 parameter node value ctherm1 7 - 6 6 * 10 -4 ctherm2 6 - 5 8 * 10 -3 ctherm3 5 - 4 2 * 10 -2 ctherm4 4 - 3 6 * 10 -2 ctherm5 3 - 2 9.65 * 10 -2 ctherm6 2 - 1 6 * 10 -1 rtherm1 7 - 6 0.045 rtherm2 6 - 5 0.105 rtherm3 5 - 4 0.150 rtherm4 4 - 3 0.225 rtherm5 3 - 2 0.375 rtherm6 2 - 1 0.600 spice thermal model
STD45NF75 8/12 fig. 4.1: gate charge test waveform fig. 1: unclamped inductive load test circuit fig. 1: unclamped inductive load test circuit fig. 2: unclamped inductive waveform fig. 3: switching times test circuits for resistive load fig. 3.1: switching time waveform fig. 4: gate charge test circuit
9/12 STD45NF75 fig. 5: diode switching test circuit fig. 5.1: diode recovery times waveform
STD45NF75 10/12 dim. mm inch min. typ. max. min. typ. max. a 2.2 2.4 0.086 0.094 a1 0.9 1.1 0.035 0.043 a2 0.03 0.23 0.001 0.009 b 0.64 0.9 0.025 0.035 b2 5.2 5.4 0.204 0.212 c 0.45 0.6 0.017 0.023 c2 0.48 0.6 0.019 0.023 d 6 6.2 0.236 0.244 e 6.4 6.6 0.252 0.260 g 4.4 4.6 0.173 0.181 h 9.35 10.1 0.368 0.397 l2 0.8 0.031 l4 0.6 1 0.023 0.039 == d l2 l4 1 3 == b e == b2 g 2 a c2 c h a1 detail "a" a2 detail "a" to-252 (dpak) mechanical data 0068772-b
11/12 STD45NF75
STD45NF75 12/12 i nformation furnished is believed to be accurate and reliable. ho wever, stmicroelectronics assumes no responsibility for the con sequence s o f use of such information nor for any infringement of patents or other rights of third parties which may result from its use. n o license is grante d b y implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicatio n are subje ct t o change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics produ cts are n ot a uthorized for use as critical components in life support devices or systems without express written approval of stmicroelectron ics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco -singapore - spain - sweden - switzerland - united kingdom - united states. www.st.com

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