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hym5v 72a80 4 a f -series unb uffered 8 mx 72 bit cmos dram module based on 8 mx 8 dram, edo, ecc, 3.3v, 4k /8k -refresh this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev.0 5 / july .9 8 ? 199 8 hyundai semiconductor description the hym5v 72a804a f -series is a 8 mx 72 -bit edo mode cmos dram module consisting of nine 8mx8 tsop and one 2048-bit eeprom on a 168 pin glass-epoxy printed circuit board. 0.1 m f and 0.01 m f decoupling capacitors are mounted for each dram. the hym5v 72a804af g-series is gold plated socket type dual in-line memory module suitable for easy interchange and addition of 64 m byte memory. features max. active power dissipation speed 8k 4k 50 3.56w 4.54w 60 2.92w 3.89w fast access time and cycle time speed trac tcac thpc 5 0 5 0ns 13 ns 25ns 6 0 6 0ns 15 ns 30ns 168-pin unb uffered dimm serial presence detect with eeprom extended data out operation single power supply of 3.3v 10% read-modify-write capability lvttl compatible inputs and outputs /cas-before-/ras, /ras-only, hidden and self refresh capability refresh cycles part no. ref. hym5v72a804a f-series 4k hym5v72a834a f-series 8k a a /cas-before-/ras refresh, hidden refresh mode : 4k cycles / 64ms pin discription /ras0 , / ras 2 row address strobe /cas0 - cas 7 , column address strobe /we0, /we2 write enable /oe0, /oe2 output enable a0 -a12 address input (8k product) a0 -a11 address input (4k product) dq0 - dq 63 data input / output cb0-cb7 check bit scl serial pd clock input sda serial pd data input/output sa0-sa2 serial pd address input vcc power (+3.3v) vss ground
hym5v72a804a f-series 2 pin name # name # name # name # name 1 vss 43 vss 85 vss 127 vss 2 dq0 44 /oe2 86 dq32 128 nc 3 dq1 45 /ras2 87 dq33 129 nc 4 dq2 46 /cas2 88 dq34 130 /cas6 5 dq3 47 /cas3 89 dq35 131 /cas7 6 vcc 48 /we2 90 vcc 132 nc 7 dq4 49 vcc 91 dq36 133 vcc 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10 dq7 52 cb2 94 dq39 136 cb6 11 dq8 53 cb3 95 dq40 137 cb7 12 vss 54 vss 96 vss 138 vss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 vcc 101 dq45 143 vcc 18 vcc 60 dq20 102 vcc 144 dq52 19 dq14 61 nc 103 dq46 145 nc 20 dq15 62 nc 104 dq47 146 nc 21 cb0 63 nc 105 cb4 147 nc 22 cb1 64 vss 106 cb5 148 vss 23 vss 65 dq21 107 vss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55 26 vcc 68 vss 110 vcc 152 vss 27 /we0 69 dq24 111 nc 153 dq56 28 /cas0 70 dq25 112 /cas4 154 dq57 29 /cas1 71 dq26 113 /cas5 155 dq58 30 /ras0 72 dq27 114 nc 156 dq59 31 /oe0 73 vcc 115 nc 157 vcc 32 vss 74 dq28 116 vss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 vss 120 a7 162 vss 37 a8 79 nc 121 a9 163 nc 38 a10 80 nc 122 a11 164 nc 39 *a12 81 nc 123 nc 165 sa0 40 vcc 82 sda 124 vcc 166 sa1 41 vcc 83 scl 125 nc 167 sa2 42 nc 84 vcc 126 nc 168 vcc note : 1.a12 is used for 8k-refresh product (hym5v72a834 a f-series)
hym5v72a804 a f-series 3 serial presence detect byte number function described function value byte0 # of byte written into serial memory at module manufacturer 128 bytes 80h byte1 total # of bytes of spd memory device 256 bytes 08h byte2 fundamental memory type edo 02h byte3 # of row addresses on this assembly 12(4k ref) 13(8k ref) 0ch 0dh byte4 # of column addresses on this assembly 11(4k ref) 10(8k ref) 0bh 0ah byte5 # of module banks on this assembly 1 bank 01h byte6 data width of this assembly 72 bits 48h byte7 data width of this assembly(continued) - 00h byte8 voltage interface standard of this assembly lvttl 01h byte9 trac 50ns 32h 60ns 3ch byte10 tcac 13ns 15ns 0dh 0fh byte11 dimm configuration type ecc 02h byte12 refresh rate/type 4k/8k ref, normal(15.6 m s) 00h byte13 primary dram width x8 08h byte14 error checking dram width x8 08h byte15-61 undefined undefined ffh byte62 spd data revision code initial 00h byte63 checksum for byte 0-62 4k/8k ref. 50ns 0dh normal(15.6 m s) 60ns 19h byte64-125 manufacturer data field hyundai mfd - byte126-127 reserved - ffh byte128-255 undefined undefinded ffh note : 1.serial pd interface is standard iic architecture. 2.pull-up resistors(4.7k typical value) are required on all open collector bus devices(scl and sda). 3.current sink capability on scl and sda (iol max) must be at least 3ma to maintain a valid low level. 4.checksum can be obtained by adding the binary values in byte 0-62, and eliminate all but low order byte. the low order byte would be the `checksum`. 5.refer to hyundai manufacturer data spec for byte 64-125.
hym5v72a804a f-series 4 block diagram note : 1.a12 is used for 8k-refresh product (hym5v72a834 a f-series)
hym5v72a804a f-series 5 absolute maximum ratings symbol parameter rating unit t a ambient temperature 0 to 70 c t stg storage temperature -55 to 150 c v in , v out voltage on any pin relative to v ss -0.5 to 4.6 v v cc voltage on v cc relative to v ss -0.5 to 4.6 v i os short circuit output current 50 ma p d power dissipation 9 w t solder soldering temperature time 260 10 c sec note: operation at or above absolute maximum ratings can adversely affect device reliability. recommended dc operating conditions (t a =0 c to 70 c ) symbol parameter min. typ. max. unit v cc power supply voltage 3.0 3.3 3.6 v v ih input high voltage 2.0 - v cc +0.3 v v il input low voltage -0.3 - 0.8 v note: all voltages are referenced to v ss .
hym5v72a804 a f-series 6 dc characteristics (t a =0 c to 70 c , v cc =3.3v 10%, v ss =0v, unless otherwise noted.) symbol parameter test conditions speed max. current unit 8k product 4k product i cc1 operating current /ras, /cas cycling trc=trc (min.) 50 60 99 0 8 10 126 0 108 0 ma i cc2 lvttl standby current /ras = /cas 3 v ih other inputs 3 v ss 9 9 ma i cc3 /ras-only refresh current /ras cycling /cas = v ih trc = trc (min.) 50 60 99 0 81 0 12 60 10 80 ma i cc4 edo mode current /cas cycling /ras = v il thpc = thpc (min.) 50 60 10 80 9 0 0 117 0 99 0 ma i cc5 cmos standby current /ras = /cas 3 v cc - 0.2v sl-part 4.5 2.7 4.5 2.7 ma i cc6 /cas-before-/ras refresh current trc=trc (min.) 50 60 99 0 81 0 1 26 0 1 08 0 ma i cc7 battery back-up current (sl-part) v ih = v cc - 0.2v, v il = 0.2v /cas = cbr cycling or 0.2v /oe & /we = v ih = v cc - 0.2v address = don`t care, dqs & cbs = open, trc=31.25 m s 4.95 4.95 ma i cc8 self refresh current (sl-part) /ras & /cas = 0.2v other pins are same as i cc 7 4. 05 4.05 ma symbol parameter test condition min. max unit i li input leakage current(any input) v ss v in v cc + 0.3, all other pins not under test=v ss - 45 45 m a i lo output leakage current(any input) v ss v out v cc /ras & /cas at v ih - 5 5 m a v ol output low voltage i ol = 2.0ma - 0.4 v v oh output high voltage i oh = -2.0ma 2.4 - v note 1. i cc1 , i cc3 , i cc4 and i cc6 dependent on output loading and cycle rates(trc and thpc). 2. specified values are obtained with outputs unloaded. 3. i cc is specified as an average current. in i cc 1, i cc 3, i cc 6, address can be changed only once while /ras=vil. in i cc 4, address can be changed maximum once while /cas=v ih within one edo mode cycle time thpc. 4. only /ras(max.) = 1 m s is applied to refresh of battery backup but tras(max.) = 10 m s is applied to normal functional operation. 5. i cc 5(max.) = 2.7ma, i cc 7 and i cc 8 are applied to sl-part only. 6. v oh = 2.0v, v ol = 0.8v at ac functional test.
hym5v 72 a 8 04 a f -series 7 ac characteristics (t a =0 c to 70 c , vcc=3.3v 10%, vss=0v, unless otherwise noted.) h ym 5 v72 a80 4a / hym5v72a834aa # symbol parameter -50 -60 -70 unit note min . max . min . max . min . max. 1 trc random read or write cycle time 90 - 110 - ns 2 trwc read-modify-write cycle time 12 8 - 1 53 - ns 3 thpc edo mode cycle time 2 5 - 30 - ns 4 thprw c edo mode read-modify-write cycle time 67 - 73 - ns 5 trac access time from /ras - 50 - 60 ns 4,5,10,11 6 tcac access time from /cas - 13 - 15 ns 4,5,10 7 taa access time from column address - 25 - 30 ns 4,5,11 8 tcpa access time from /cas precharge - 28 - 35 ns 4 9 tclz /cas to output low impedance 3 - 3 - ns 3 1 0 tcez output buffer turn-off delay from /cas 3 1 3 3 1 3 ns 1 1 tt transition time (rise and fall) 2 50 2 50 ns 4 1 2 trp /ras precharge time 30 - 40 - ns 1 3 tras /ras pulse width 50 10k 60 10k ns 1 4 trasp /ras pulse width (edo mode) 50 100k 60 100k ns 1 5 trsh /ras hold time 1 3 - 15 - ns 1 6 tcsh /cas hold time 4 0 - 4 5 - ns 1 7 tcas /cas pulse width 8 10k 10 10k ns 1 8 trcd /ras to /cas delay 1 7 37 20 45 ns 10 1 9 trad /ras to column address delay time 1 3 25 15 30 ns 11 2 0 tcrp /cas to /ras precharge time 5 - 5 - ns 2 1 tcp /cas precharge time 8 - 10 - ns 2 2 tasr row address set-up time 0 - 0 - ns 2 3 trah row address hold time 8 - 10 - ns 2 4 tasc column address set-up time 0 - 0 - ns 2 5 tcah column address hold time 8 - 10 - ns 2 6 tar column address hold time from /ras 45 - 50 - ns 2 7 tral column address to /ras lead time 25 - 30 - ns 2 8 trcs read command set-up time 0 - 0 - ns 2 9 trch read command hold time referenced to /cas 0 - 0 - ns 7 3 0 trrh read command hold time referenced to /ras 0 - 0 - ns 7 3 1 twch write command hold time 10 - 10 - ns 3 2 twcr write command hold time from /ras 40 - 45 - ns 3 3 twp write command pulse width 8 - 10 - ns 3 4 trwl write command to /ras lead time 15 - 15 - ns 3 5 tcwl write command to /cas lead time 8 - 10 - ns
hym5v 72 a 8 04 a f -series 8 a c characteristics (continued) hym5v72a804a/hym5v72a834a # symbol parameter -50 -60 -70 unit note min . max . min . max . min . max. 3 6 tds data-in set-up time 0 - 0 - ns 8 3 7 tdh data-in hold time 10 - 10 - ns 8 3 8 tdhr data-in hold time referenced to /ras 40 - 45 - ns 3 9 tref refresh period (8192 cycles) - 64 - 64 ms 12,13 refresh period (4096 cycles) - 64 - 64 ms 12 refresh period (sl-part) - 128 - 128 ms 12,13 4 0 twcs write command set-up time 0 - 0 - ns 9 4 1 tcwd /cas to /we delay time 34 - 36 - ns 9 4 2 trwd /ras to /we delay time 70 - 80 - ns 9 4 3 tawd column address to /we delay time 45 - 50 - ns 9 4 4 tcsr /cas set-up time (cbr cycle) 5 - 5 - ns 4 5 tchr /cas hold time (cbr cycle) 10 - 10 - ns 4 6 trpc /ras to /cas precharge time 5 - 5 - ns 4 7 tcpt /cas precharge time (cbr counter test) 25 - 30 - ns 4 8 troh /ras hold time referenced to /oe 0 - 0 - ns 4 9 toea /oe access time - 13 - 15 ns 5 0 toed /oe to data delay 13 - 15 - ns 5 1 toez output buffer turn off delay time from /oe 0 10 0 15 ns 6 5 2 toeh /oe command hold time 13 - 15 - ns 5 3 tcpwd /we delay time from /cas precharge 45 - 54 - ns 9 5 4 trhcp /ras hold time from /cas precharge 30 - 35 - ns 5 5 twrp /we to /ras precharge time(cbr cycle) 10 - 10 - ns 5 6 twrh /we to /ras hold time (cbr cycle) 10 - 10 - ns 5 7 twts write command set-up time (test mode in) 10 - 10 - ns 5 8 twth write command hold time (test mode in) 10 - 10 - ns 5 9 trass /ras pulse width (self refresh) 100k - 100k - us 6 0 trps /ras precharge time (self refresh) 100 - 100 - ns 6 1 tchs /cas hold time (self refresh) -50 - -50 - ns 6 2 tdoh output data hold time 5 - 5 - ns 6 3 trez output buffer turn-off delay from /ras 0 10 0 15 ns 6 6 4 twez output buffer turn-off delay from /we 0 10 0 15 ns 6 6 5 twed /we to data delay time 15 - 15 - ns 6 6 toep /oe precharge time 5 - 5 - ns 6 7 twpe /we pulse width (edo cycle) 5 - 5 - ns 6 8 toch /oe to /cas hold time 5 - 5 - ns 6 9 tcho /cas hold time to /oe 5 - 5 - ns
hym5v72a804a f-series 9 note 1. an initial pause of 200 m s is required after power-up followed by 8 /ras cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 /cas-before-/ras initialization cycles instead of 8 /ras-only refresh cycles are required. the device should be carefully initialized to be prevented from being entered into multi bit test mode during initialization. 2. if /ras=vss during power-up, the hym5v72a804 a / hym5v72a834 a could begin an active cycle. this condition results in higher current than necessary current which is demanded from the power supply during power-up. 3. it is recommended that /ras and /cas track with vcc during power-up or be held at a valid v ih in order to minimize the power-up current. 4. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. transition times are measured between v ih (min.) and v il (max.), and are assumed to be 5ns for all inputs. 5. measured at v oh =2.0v and v ol =0.8v with a load equivalent to 1 ttl loads and 100pf. 6. twez, trez, tcez and toez define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. either trch or trrh must be satisfied for a read cycle. 8. these parameters are referenced to /cas leading edge in early write cycles and to /we leading edge in read-modify-write cycles and late write cycle. 9. twcs, trwd, tcwd, tawd and tcpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if twcs 3 twcs(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. if trwd 3 trwd(min.), tcwd 3 tcwd(min.), tawd 3 tawd(min.), and tcpwd 3 tcpwd(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 10. operation within the trcd(max.) limit ensures that trac(max.) can be met. trcd(max.) is specified as a reference point only. if trcd is greater than the specified trcd(max.) limit, then access time is controlled by tcac. 11. operation within the trad(max.) limit ensures that trac(max.) can be met. trad(max.) is specified as a reference point only. if trad is greater than the specified trad(max.) limit, then access time is controlled by taa. 12. tref(max.)=128ms is applied to sl-parts. 13. a burst of 8192 /ras-only refresh cycles must be executed within 64ms (128ms for sl-parts) after exiting self refresh. (cbr refresh & hidden refresh : 4k cycle/64ms) capacitance (t a =0 c to 70 c , vcc=3.3v 10%, vss=0v, f = 1mhz, unless otherwise noted.) symbol parameter typ. max. unit c in1 input capacitance (a0 - a12) - 55 pf c in2 input capacitance (/we0, /we2, /oe0, /oe2) - 45 pf c in3 input capacitance (/ras0, /ras2) - 45 pf c in4 input capacitance (/cas0 - /cas7) - 22 pf c dq data input /output capacitance (dqs, cbs) - 14 pf
hym5v72a804a f-series 10 package information
hym5v72a804 a f-series 11 ordering information part number ref. power package hym5v72a804 a t fg 4k normal t so p hym5v72a8 3 4 a tfg 8 k normal tsop

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