rev. 0.1 11/05 copyright ? 2005 by silicon laboratories AN239 AN239 e xpanding adc1 d ynamic r ange for the si8250 1. introduction the si8250 data sheet specifies a common mode input range of 0.6 to 1.2 v for adc1. th is range effectively limits the dynamic voltage output range in voltage-controlled conv erters. for example, the output range for a 3.3 v power supply designed to generate a 1.00 v sense would have an absolute maximum dynamic range of 1.98 to 3.96 v. in reality, the active regulation point would need to be some thing greater than 1.98 v and less than 3.96 v since these are on the very fringes of the common mode specification. if a design requires wider dynamic output voltage range (e.g., 2.00?5.70 v) then a simple resistor divider will not work. this application note discusses a simple and inexpensive solution to expand the dynamic range for applications such as power factor correction and wide variable output power supplies. 2. adc1 common mode limits the specified common mode range for adc1 (figure 1) is from 0.6 v to the voltage reference which is typically 1.2 v. this simply means that the in put voltages to a dc1 from both v sense and the refdac should stay within the range of 0.6 to 1.2 v referenced to the common gr ound to achieve good linear response. for input voltages much lower than the common mode specification, adc1 exhibits non-linear characteristics. figure 2 shows an example of the adc1 dc response when the inputs are sign ificantly out of specificatio n. for input voltages above the common mode range the input is effectively ?cut off? yielding no change in the adc output. figure 1. adc1 block diagram figure 2. adc1 results below th e common mode specification v sense refdac 10 mhz 6-bit adc + - to pid filter pid input mux adc1dat 3 2 1 0 read/write sfr bus refdac0h refdac0l 200 khz 12-bit adc + refdac0h refdac0l + - bits [11:6] bits [8:3] -1 6 6 6 9 adc1 output 6 mv step, v sense = 301 mv, v ref = 1.226 v -32 -22 -12 -2 8 18 28 0 50 100 150 200 refdac adc1data actual data ideal data
AN239 2 rev. 0.1 3. dynamic range limit the simplest and most economical feedback approach is to di vide the output voltage with a simple resistor divider as shown in figure 3. figure 3. resistor divider thus, the output voltage is proportional to the inverted re sistor divider ratio, equation 2, times the sense voltage as shown in equation 1. for simplicity, the in verted resistor divider ratio from th is point forward will be referred to as the ratio. equation 1. output voltag e/sense voltage relation equation 2. inverted resistor divider ratio similarly, it is easily shown that the range of the output voltage is proportional by the ratio to the range of the sense voltage, and this is where fundamental limits can be seen. the range of the sense voltage is bounded by the common mode input specification, ? vs = 1.2?0.6 v = 0.6 v. equation 3. output / sense dynamic range relation for example, the operating range for a particular design is 2.2 to 5.5 v with 200 mv of operating margin on either side. thus, the absolute range of the supply is defined to be 2.0 to 5.7 v. however, starting with the minimum sense voltage at the minimum output voltage, th e maximum achievable outp ut voltage is 2.0 v + ? vs = 4.0 v. at an output of 4.0 v, the sense voltage is at its maximum limit of 1.2 v. this graphica l relationship is shown in figure 4. thus the desired 5.7 v maximum range is not achievable with the feedback circuit shown in figure 3. figure 4. output voltage limit v in v sense the power stage and filter si8250 r s r x v s v out v o v s = r s r x + r x ------------------- - = v oh v ol ? v sh v sl ? = v ? o v ? s = 2.0 v 4.0 v 5.7 v within the common mode range 0.6 v 1.2 v v out v s 0 v 0 v out of range
AN239 rev. 0.1 3 4. expanding the dynamic range to dynamic range may be expanded by allowing the ratio in equation 1 and equation 3 to be variable. this is accomplished by changing the value of r x in figure 3. one solution is to connect parallel resistors to port pins on the si8250 as shown in figure 5. to change the ratio, drive one of the connect ed port pins low to engage a parallel resistance or allow the pin to float (high impedance) to disengage a parallel resistance. figure 5. feedback with common mode compensation 4.1. adding margin to the common mode limits it is important to add margin to the co mmon mode limits to ensure that adc1 is not converting at the boundary of the common mode range. operating at the boundary ultima tely affects the transient response performance. for example, if the reference dac shown in figure 1 is set to deliver a 1.17 v signal to adc1, this would leave 30 mv operating margin for adc1 vs (min). in a situation where adc1 is set to deliver a 6 mv resolution, 30 mv is only 5 lsb. thus, if a positive going transient were to occur, the maximum possible error from adc1 would be 5 lsbs. thus, the loop response is asymmetrical in this example. the bandwidth is severely limited for positive transients (up to 5 lsb), while the bandwidth for negative going tr ansients would be limited only by the maximum dynamic range of adc1 (up to 32 lsb). therefore, it is necessary to calculate the operating limits set by deciding the maximum allowed transient m (lsb) . the ratios and resistor values are determined based on these operating limits. equa tion 4 defines the minimum sense voltage vs (min) and equation 5 defines the maximum sense voltage vs (max). in these equations v step is the resolution of adc1 (mv), and v com is the common mode voltage. equation 4. minimum sense voltage equation 5. maximum sense voltage r s r 1 r 2 r 3 v sense p0.0 v out p0.1 from filter p0.n r n r x r 1 r 2 r 3 r n || || || = v smin () v com min () mv step () + = v smin () 0.6v m v step () + = v smax () v com max () mv step () ? = v smax () 1.2v m v step () ? =
AN239 4 rev. 0.1 4.2. determining the ratios as shown earlier in equation 2, the ratio is defined by the resistor divi der. as shown in figure 5, there will be some number of resistors that will be used to adjust the ratio. the ratios must be determined to find the number of resistors and their values for the circuit shown in figure 5. equation 6 and equation 7 are used to determine the ratios and peak voltages for these ratios. equation 6 is a recursive function that relates the prev ious maximum output voltage v(n?1) to the next maximum output voltage v(n) for a given ratio. each voltage step represents the maximum output voltage that can be achieved for a particular ratio. it is derived by relating the maximum output voltage for one ratio to the minimum output of the next ratio. equation 7 is essentially the sa me as equation 2 written in another form. it provides the ratio for the calculated maximum voltage provided by equation 6. each successive maximum voltage is calculated with equa tion 6. start from the minimum voltage of the desired range, and iterate equation 6 until the voltage exceed s the desired maximum output voltage. the number of iterations determine the number of resistors needed to achieve the desired voltage range. for each iteration of equation 6 an ratio can be calculated with equation 7. the ratio will be used in the next section to determine the resistor values. equation 6. max output steps equation 7. the alpha ratio for a given peak output for example, as used previously, the desi red operating range is from 2.0 to 5.7 v. equation 6 is iterated three times yielding a maximum voltage of 8.4 v, which exceeds the 5.7 v requirement. then the three ratios are calculated. the ratios for this example are presented graphically in fi gure 6. therefore, the circuit in figure 5 only requires three resistors to achieve the desired 2. 0 to 5.7 v operating range. the exact re sistor values are calculated in ?4.3. determining the parallel resistors?. v n v n1 ? v smax () v smin () ------------------- - = where v 0 v out min () = n v n v smin () ------------------ =
AN239 rev. 0.1 5 figure 6. graphical determination of the ratios 4.3. determining th e parallel resistors once the ratios are determined, they must be decomposed to individual resistor values. the equivalent resistance, r xn , is calculated from the associated ratio. equation 8 gives these re sistances for each successive r xn . note that r xn represents the equivalent resistance, wh ich is a composition of parallel resistors. equation 8. the equivalent resistance equation 9 defines r xn as a cascade of parallel resistors where n represents the sequence of parallel resistors. for example, r x2 is the equivalent resistance of r 1 in parallel with r 2 . equation 9. parallel resistance the individual resistor values are extracted from equation 10. equation 10. the resistor in terms of the previous and current parallel resistance dynamic range for vsense 0 1 2 3 4 5 6 7 8 9 13579 voltage out v 1 v 2 v 3 v o u t ( m a x ) v o u t ( m i n ) 2.00v to 8.42v ratio r xn r s n 1 ? --------------- = r xn r 1 r 2 || r 3 r n || || || = r n r xn 1 ? r xn r xn 1 ? r xn ? -------------------------------- =
AN239 6 rev. 0.1 4.4. design example an output range from 2.0 to 5.7 v is desired for a part icular power supply (this example is used quite often throughout this application note). the high-side margin is specified to be 32 lsb, and the low-side margin is specified to be 16 lsb. the adc resolution is set at 4 mv. these settings yield a sens e voltage range of 0.664 to 1.072 v. the high-side resistor, r s , is specified to be 7500 ? . the results are easily calculated with a spreadsheet and are shown in figure 7. the resulting circuit is shown in figure 8. figure 7. example spreadsheet calculations for a wide dynamic output figure 8. the example voltage sense circuit v alue unit 2.00 v 0.60 v 1.20 v 16 lsb 32 lsb 0.004 v 7500 ohms 0.664 v 1.072 v vs(min) vs(max) vout(min) vcom(min) vcom(max) step size parameter low offset high offset rs n n vn rxn rn 1 3.01 3.23 3727.54 3727.54 2 4.86 5.21 1941.58 4052.35 3 7.85 8.42 1094.76 2510.04 4 12.67 13.59 642.41 1554.73 5 20.46 21.94 385.35 963.00 6 33.04 35.42 234.11 596.49 7 53.34 57.18 143.30 369.47 v in r s r 1 v sense p0.0 v out p0.1 2.51k 4.05k r 3 r 2 3.73k 7.5k the power stage and filter si8250
AN239 rev. 0.1 7 5. code overview code must also be developed to manipulate the po rt pins and accommodate the wider operating range. in essence, the desired output is checked against the thre shold range, and the corresponding port pins are driven accordingly. each pin can be driven low to engage the resistor, thus raising the peak output voltage. or each pin can be allowed to float, thus lowering the peak output voltage. for each range, the refdac output also must be changed to correspond to the appropriate output voltage r ange. this operation is best described in a program flow example. figure 9 shows the program flow that could be used to change the output voltage for the example described in ?4.4. design example?. figure 9. program flow example change output is < 3.23v? is < 5.21v? yes inhibit integration write new refdac value drive p0.0 low drive p0.1 low drive p0.0 low float p0.1 float p0.0 float p0.1 write new refdac value write new refdac value done yes no no enable integration
AN239 8 rev. 0.1 5.1. a code example coding the flowchart shown in figure 9 can be accomp lished in many forms, the code discussed here and presented below is just one example. a parameter representing the desired output voltage is passe d in. the range of the parameter is specified from 0 to 10 v, which includes the desired range of 2.0 to 5.7 v wit h more than sufficient resolution. next, the desired range is decoded from the request. (i.e., in the example, ?4.4. design example? , is the output within the 2.00?3.23 v, 3.23?5.21 v, or 5.21?8.42 v range?) once the range is decoded the scaled refdac value is calculated and stored in a temporary location. also the resistor settings are stored in a temporary location. the loop is briefly opened while the settings are written (refdac and resistors); then the loop is closed again. // this function sets the output voltage. the 16-bit parameter 'vout' // represents a voltage between 0v and 10v. the output ranges are as // follows: // voltage range scale factor res2 res3 // 2.00v - 3.23v 46 1 1 // 3.23v - 5.21v 75 1 0 // 5.21v - 8.42v 121 0 0 // // the scale factor is calculated from the following equation: // scale factor = vn * vref * 65535 / 10 / vs(max) / 511 void setvout(unsigned int vout) { unsigned int _temp; bit _tempr2; bit _tempr3 // if the desired output is less than 3.23v if (vout < 0x522d) { // float both resistors _tempr2 = 1; _tempr3 = 1; // scale the internal voltage to the real voltage _temp = vout / 46; } else // if the desired output is less than 5.21v if (vout < 0x8560) { // tie res2 to ground and float res3 _tempr2 = 0; _tempr3 = 1; // scale the internal voltage to the real voltage _temp = vout / 75; } else // otherwise the output is less that 8.42v { // tie both resistors to ground _tempr2 = 0; _tempr3 = 0; // scale the internal voltage to the real voltage _temp = vout / 121; } // set the resistors res2 = _tempr2; res3 = _tempr3; // write to the refdac refdac0h = _temp >> 8; refdac0l = _temp; // clear the integrator pidkicn |= 0x80; pidkicn &= ~0x80; }
AN239 rev. 0.1 9 6. summary although adc1 on the si8250 does have a specified commo n mode range; this does not necessarily limit the dynamic range of the output of a volt age controlled power supply. as describ ed in this application note, it is relatively easy and inexpensive to add dynamic range pr ogramming with just a few extra resistors and some code.
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