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ultralow noise vgas with preamplifier and programmable r in ad8331/ad8332/ad8334 rev. g information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2003C2010 analog devices, inc. all rights reserved. features ultralow noise preamplifier (preamp) voltage noise = 0.74 nv/hz current noise = 2.5 pa/hz 3 db bandwidth ad8331 : 120 mhz ad8332 , ad8334 : 100 mhz low power ad8331 : 125 mw/channel ad8332 , ad8334 : 145 mw/channel wide gain range with programmable postamp ?4.5 db to +43.5 db in lo gain mode 7.5 db to 55.5 db in hi gain mode low output-referred noise: 48 nv/hz typical active input impedance matching optimized for 10-bit/12-bit adcs selectable output clamping level single 5 v supply operation ad8332 and ad8334 available in lead frame chip scale package applications ultrasound and sonar time-gain controls high performance automatic gain control (agc) systems i/q signal processing high speed, dual adc drivers general description the ad8331 / ad8332/ ad8334 are single-, dual-, and quad- channel, ultralow noise linear-in-db, variable gain amplifiers (vgas). optimized for ultrasound systems, they are usable as a low noise variable gain element at frequencies up to 120 mhz. included in each channel are an ultralow noise preamp (lna), an x-amp? vga with 48 db of gain range, and a selectable gain postamp with adjustable output limiting. the lna gain is 19 db with a single-ended input and differential outputs. using a single resistor, the lna input impedance can be adjusted to match a signal source without compromising noise performance. the 48 db gain range of the vga makes these devices suitable for a variety of applications. excellent bandwidth uniformity is maintained across the entire range. the gain control interface provides precise linear-in-db scaling of 50 db/v for control voltages between 40 mv and 1 v. factory trim ensures excellent part-to-part and channel-to-channel gain matching. functional block diagram 03199-001 vol voh v mid lna 48db attenuator enb inh lmd v in v ip loplon gain ad8331/ad8332/ad8334 + ? clamp rclmp hil o v cm 3.5db or 15.5db 19db pa vcm bias vga bias and interpolator gain control interface 21db figure 1. signal path block diagram 60 50 40 30 20 10 0 ?10 100k 1m 10m 100m 1g gain (db) frequency (hz) 03199-002 v gain = 1v v gain = 0.8v v gain = 0.6v v gain = 0.4v v gain = 0.2v v gain = 0v hi gain mode figure 2. frequency response vs. gain differential signal paths result in superb second- and third- order distortion performance and low crosstalk. the low output-referred noise of the vga is advantageous in driving high speed differential adcs. the gain of the postamp can be pin selected to 3.5 db or 15.5 db to optimize gain range and output noise for 12-bit or 10-bit converter applications. the output can be limited to a user-selected clamping level, preventing input overload to a subsequent adc. an external resistor adjusts the clamping level. the operating temperature range is ?40c to +85c. the ad8331 is available in a 20-lead qsop package, the ad8332 is available in 28-lead tssop and 32-lead lfcsp packages, and the ad8334 is available in a 64-lead lfcsp package.
ad8331/ad8332/ad8334 rev. g | page 2 of 56 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 4 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 typical performance characteristics ........................................... 12 test circuits ..................................................................................... 20 measurement considerations ................................................... 20 theory of operation ...................................................................... 24 overview ...................................................................................... 24 low noise amplifier (lna) ..................................................... 25 variable gain amplifier ............................................................ 27 postamplifier ............................................................................... 28 applications information .............................................................. 30 lnaexternal components .................................................... 30 driving adcs ............................................................................. 32 overload ...................................................................................... 32 optional input overload protection ....................................... 32 layout, grounding, and bypassing .......................................... 33 multiple input matching ........................................................... 33 disabling the lna ...................................................................... 33 ultrasound tgc application ................................................... 34 high density quad layout ....................................................... 34 ad8331 evaluation board ............................................................ 39 general description ................................................................... 39 user-supplied optional components ..................................... 39 measurement setup.................................................................... 39 board layout ............................................................................... 39 ad8331 evaluation board schematics .................................... 40 ad8331 evaluation board pcb layers ................................... 42 ad8332 evaluation board ............................................................ 43 general description ................................................................... 43 user-supplied optional components ..................................... 43 measurement setup.................................................................... 43 board layout ............................................................................... 43 evaluation board schematics ................................................... 44 ad8332 evaluation board pcb layers ................................... 46 ad8334 evaluation board ............................................................ 47 general description ................................................................... 47 configuring the input impedance ........................................... 48 measurement setup.................................................................... 48 board layout ............................................................................... 48 evaluation board schematics ................................................... 49 ad8334 evaluation board pcb layers ................................... 51 outline dimensions ....................................................................... 53 ordering guide .......................................................................... 55 revision history 10/10rev. f to rev. g changes to quiescent current per channel parameter, table 1 ................................................................................................ 6 changes to pin 1, table 3 ................................................................. 8 changes to pin 1 and pin 28, table 4 and pin 4 and pin 5, table 5 ................................................................................................ 9 changes to figure 6 and table 6 ................................................... 10 changes to figure 33 ...................................................................... 16 changes to figure 64 ...................................................................... 22 changes to figure 70 ...................................................................... 24 changes to low noise amplifier (lna) section and figure 74 .......................................................................................... 25 changes to figure 94 ...................................................................... 38 changes to general descriptions section, figure 95 caption, table 10, and board layout section ............................................. 39 changes to figure 96 ...................................................................... 40 changes to figure 97 ...................................................................... 41 changes to figure 98 and figure 103 ........................................... 42 deleted ad8331 bill of materials section and table 11; renumbered sequentially ............................................................. 43 changes to figure 104 ................................................................... 43 changes to figure 106 ................................................................... 45 changes to figure 107 ................................................................... 46 changes to figure 113 ................................................................... 47 changes to figure 114 and board layout section ..................... 48 deleted ad8332 bill of materials section and table 13; renumbered sequentially ............................................................. 48 changes to figure 115 ................................................................... 49 changes to figure 116 ................................................................... 50 changes to figure 117 to figure 120 ........................................... 51 changes to figure 121 ................................................................... 52 deleted ad8334 bill of materials section and table 15; renumbered sequentially ............................................................. 54
ad8331/ad8332/ad8334 rev. g | page 3 of 56 4/08rev. e to rev. f changed r fb to r iz throughout ..................................................... 4 changes to figure 1 ........................................................................... 1 changes to table 1, lna and vga characteristics, output offset voltage, conditions ............................................................... 4 changes to quiescent current per channel and power down current parameters ........................................................................... 6 changes to table 2 ............................................................................ 7 changes to table 3, pin 1 description ........................................... 8 changes to table 4, pin 1 and pin 28 descriptions ...................... 9 changes to table 5, pin 4 and pin 5 descriptions ........................ 9 changes to table 6, pin 2, pin 15, and pin 20 descriptions ...... 10 changes to table 6, pin 61 description ....................................... 11 changes to typical performance characteristics section, default conditions .......................................................................... 12 changes to figure 25 ...................................................................... 15 changes to figure 39 ...................................................................... 17 changes to figure 55 through figure 68 ................................... 20 changes to theory of operation, overview section ................. 24 changes to low noise amplifier section and figure 74 ........... 25 changes to active impedance matching section, figure 75, and figure 77 ................................................................................... 26 changes to figure 78 ...................................................................... 27 changes to equation 6, table 7, figure 81, and figure 82 ......... 30 changes to figure 83 ...................................................................... 31 changes to figure 88 ...................................................................... 32 switched figure 89 and figure 90 ................................................. 33 changes to figure 89 ...................................................................... 33 changes to ultrasound tgc application section...................... 34 incorporated ad8331-eval data sheet, rev. a ....................... 39 changes to user-supplied optional components section and measurement setup section ................................................... 39 changes to figure 95 ...................................................................... 39 changes to figure 97 ...................................................................... 41 added figure 98 .............................................................................. 42 incorporated ad8332-evalz data sheet, rev. d ..................... 44 incorporated ad8334-eval data sheet, rev. 0 ........................ 49 updated outline dimensions ........................................................ 55 changes to ordering guide ........................................................... 57 4/06rev. d to rev. e added ad8334 ................................................................... universal changes to figure 1 and figure 2 .................................................... 1 changes to table 1 ............................................................................ 4 changes to table 2 ............................................................................ 7 changes to figure 7 through figure 9 and figure 12 ................. 12 changes to figure 13, figure 14, figure 16, and figure 18 ....... 13 changes to figure 23 and figure 24 ............................................. 14 changes to figure 25 through figure 27 ...................................... 15 changes to figure 31 and figure 33 through figure 36 ............ 16 changes to figure 37 through figure 42 ...................................... 17 changes to figure 43, figure 44, and figure 48 .......................... 18 changes to figure 49, figure 50, and figure 54 .......................... 19 inserted figure 56 and figure 57 .................................................. 20 inserted figure 58, figure 59, and figure 61 ............................... 21 changes to figure 60 ...................................................................... 21 inserted figure 63 and figure 65 .................................................. 22 changes to figure 64 ...................................................................... 22 moved measurement considerations section ............................ 23 inserted figure 67 and figure 68 .................................................. 23 inserted figure 70 and figure 71 .................................................. 24 change to figure 72 ........................................................................ 24 changes to figure 73 and low noise amplifier section ........... 25 changes to postamplifier section ................................................. 28 changes to figure 80 ...................................................................... 29 changes to lnaexternal components section ...................... 30 changes to logic inputsenb, mode, and hilo section ... 31 changes to output decoupling and overload sections ............ 32 changes to layout, grounding, and bypassing section ............ 33 changes to ultrasound tgc application section ..................... 34 added high density quad layout section ................................. 34 inserted figure 94 ........................................................................... 38 updated outline dimensions ........................................................ 39 changes to ordering guide ........................................................... 40 3/06rev. c to rev. d updated format ................................................................. universal changes to features and general description .............................. 1 changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 6 changes to ordering guide ........................................................... 34 11/03rev. b to rev. c addition of new part ......................................................... universal changes to figures ............................................................. universal updated outline dimensions ........................................................ 32 5/03rev. a to rev. b edits to ordering guide ................................................................. 32 edits to ultrasound tgc application section ........................... 25 added figure 71, figure 72, and figure 73.................................. 26 updated outline dimensions ........................................................ 31 2/03rev. 0 to rev. a edits to ordering guide ................................................................. 32
ad8331/ad8332/ad8334 rev. g | page 4 of 56 specifications t a = 25c, v s = 5 v, r l = 500 , r s = r in = 50 , r iz = 280 , c sh = 22 pf, f = 10 mhz, r clmp = , c l = 1 pf, vcm pin floating, ?4.5 db to +43.5 db gain (hilo = lo), and differential output voltage, unless otherwise specified. table 1. parameter test conditions/comments min typ max unit 1 lna characteristics gain single-ended input to differential output 19 db input to output (single-ended) 13 db input voltage range ac-coupled 275 mv input resistance r iz = 280 50 r iz = 412 75 r iz = 562 100 r iz = 1.13 k 200 r iz = 6 k input capacitance 13 pf output impedance single-ended, either output 5 ?3 db small signal bandwidth v out = 0.2 v p-p 130 mhz slew rate 650 v/s input voltage noise r s = 0 , hi or lo gain, r iz = , f = 5 mhz 0.74 nv/hz input current noise r iz = , hi or lo gain, f = 5 mhz 2.5 pa/hz noise figure f = 10 mhz, lop output active termination match r s = r in = 50 3.7 db unterminated r s = 50 , r iz = 2.5 db harmonic distortion at lop1 or lop2 v out = 0.5 v p-p, single-ended, f = 10 mhz hd2 ?56 dbc hd3 ?70 dbc output short-circuit current pin lon, pin lop 165 ma lna and vga characteristics ?3 db small signal bandwidth v out = 0.2 v p-p ad8331 120 mhz ad8332, ad8334 100 mhz ?3 db large signal bandwidth v out = 2 v p-p ad8331 110 mhz ad8332, ad8334 90 mhz slew rate ad8331 lo gain 300 v/s hi gain 1200 v/s ad8332, ad8334 lo gain 275 v/s hi gain 1100 v/s input voltage noise r s = 0 , hi or lo gain, r iz = , f = 5 mhz 0.82 nv/hz noise figure v gain = 1.0 v active termination match r s = r in = 50 , f = 10 mhz, measured 4.15 db r s = r in = 200 , f = 5 mhz, simulated 2.0 db unterminated r s = 50 , r iz = , f = 10 mhz, measured 2.5 db r s = 200 , r iz = , f = 5 mhz, simulated 1.0 db output-referred noise ad8331 v gain = 0.5 v, lo gain 48 nv/hz v gain = 0.5 v, hi gain 178 nv/hz ad8332, ad8334 v gain = 0.5 v, lo gain 40 nv/hz v gain = 0.5 v, hi gain 150 nv/hz output impedance, postamplifier dc to 1 mhz 1
ad8331/ad8332/ad8334 rev. g | page 5 of 56 parameter test conditions/comments min typ max unit 1 output signal range, postamplifier r l 500 , unclamped, either pin v cm 1.125 v differential 4.5 v p-p output offset voltage ad8331 differential, v gain = 0.5 v ?50 5 +50 mv common mode ?125 ?25 +100 mv ad8332, ad8334 differential, 0.05 v v gain 1.0 v ?20 5 +20 mv common mode ?125 C25 +100 mv output short-circuit current 45 ma harmonic distortion v gain = 0.5 v, v out = 1 v p-p, hi gain ad8331 hd2 f = 1 mhz ?88 dbc hd3 ?85 dbc hd2 f = 10 mhz ?68 dbc hd3 ?65 dbc ad8332, ad8334 hd2 f = 1 mhz ?82 dbc hd3 ?85 dbc hd2 f = 10 mhz ?62 dbc hd3 ?66 dbc input 1 db compression point v gain = 0.25 v, v out = 1 v p-p, f = 1 mhz to 10 mhz 1 dbm two-tone intermodulation distortion (imd3) ad8331 v gain = 0.72 v, v out = 1 v p-p, f = 1 mhz ?80 dbc v gain = 0.5 v, v out = 1 v p-p, f = 10 mhz ?72 dbc ad8332, ad8334 v gain = 0.72 v, v out = 1 v p-p, f = 1 mhz ?78 dbc v gain = 0.5 v, v out = 1 v p-p, f = 10 mhz ?74 dbc output third-order intercept ad8331 v gain = 0.5 v, v out = 1 v p-p, f = 1 mhz 38 dbm v gain = 0.5 v, v out = 1 v p-p, f = 10 mhz 33 dbm ad8332, ad8334 v gain = 0.5 v, v out = 1 v p-p, f = 1 mhz 35 dbm v gain = 0.5 v, v out = 1 v p-p, f = 10 mhz 32 dbm channel-to-channel crosstalk (ad8332, ad8334) v gain = 0.5 v, v out = 1 v p-p, f = 1 mhz ?98 db overload recovery v gain = 1.0 v, v in = 50 mv p-p/1 v p-p, f = 10 mhz 5 ns group delay variation 5 mhz < f < 50 mhz, full gain range 2 ns accuracy absolute gain error 2 0.05 v < v gain < 0.10 v ?1 +0.5 +2 db 0.10 v < v gain < 0.95 v ?1 0.3 +1 db 0.95 v < v gain < 1.0 v ?2 ?1 +1 db gain law conformance 3 0.1 v < v gain < 0.95 v 0.2 db channel-to-channel gain matching 0.1 v < v gain < 0.95 v 0.1 db gain control interface (pin gain) gain scaling factor 0.10 v < v gain < 0.95 v 48.5 50 51.5 db/v gain range lo gain ?4.5 to +43.5 db hi gain 7.5 to 55.5 db input voltage (v gain ) range 0 to 1.0 v input impedance 10 m response time 48 db gain change to 90% full scale 500 ns common-mode interface (pin vcmx) input resistance 4 current limited to 1 ma 30 output cm offset voltage v cm = 2.5 v ?125 ?25 +100 mv voltage range v out = 2.0 v p-p 1.5 to 3.5 v
ad8331/ad8332/ad8334 rev. g | page 6 of 56 parameter test conditions/comments min typ max unit 1 enable interface (pin enb, pin enbl, pin enbv) logic level to enable power 2.25 5 v logic level to disable power 0 1.0 v input resistance pin enb 25 k pin enbl 40 k pin enbv 70 k power-up response time v inh = 30 mv p-p 300 s v inh = 150 mv p-p 4 ms hilo gain range interface (pin hilo) logic level to select hi gain range 2.25 5 v logic level to select lo gain range 0 1.0 v input resistance 50 k output clamp interface (pin rclmp; hi or lo gain) accuracy hilo = lo r clmp = 2.74 k, v out = 1 v p-p (clamped) 50 mv hilo = hi r clmp = 2.21 k, v out = 1 v p-p (clamped) 75 mv mode interface (pin mode) logic level for positive gain slope 0 1.0 v logic level for negative gain slope 2.25 5 v input resistance 200 k power supply (pin vps1, pin vps2, pin vpsv, pin vpsl, pin vpos) supply voltage 4.5 5.0 5.5 v quiescent current per channel ad8331 20 25 ma ad8332 22 27.5 32 ma ad8334 24 29.5 34 power dissipation per channel no signal ad8331 125 mw ad8332, ad8334 138 mw power-down current vga and lna disabled ad8331 50 240 400 a ad8332 50 300 600 a ad8334 50 600 1200 a lna current ad8331 (enbl) each channel 7.5 11 15 ma ad8332, ad8334 (enbl) each channel 7.5 12 15 ma vga current ad8331 (enbv) 7.5 14 20 ma ad8332, ad8334 (enbv) 7.5 17 20 ma psrr v gain = 0 v, f = 100 khz ?68 db 1 all dbm values are referred to 50 . 2 the absolute gain refers to the theoretical gain expression in equation 1. 3 best-fit to linear-in-db curve. 4 the current is limited to 1 ma typical.
ad8331/ad8332/ad8334 rev. g | page 7 of 56 absolute maximum ratings table 2. parameter rating voltage supply voltage (vpsn, vpsv, vpsl, vpos) 5.5 v input voltage (inhx) v s + 200 mv enb, enbl, enbv, hilo voltage v s + 200 mv gain voltage 2.5 v power dissipation ru package 1 (ad8332) 0.96 w cp-32 package (ad8332) 1.97 w rq package 1 (ad8331) 0.78 w cp-64 package (ad8334) 0.91 w temperature operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering 60 sec) 300c ja ru package 1 (ad8332) 68c/w cp-32 package2 2 (ad8332) 33c/w rq package 1 (ad8331) 83c/w cp-64 package 3 (ad8334) 24.2c/w 1 4-layer jedec board (2s2p). 2 exposed pad soldered to board, nine thermal vias in padjedec, 4-layer board j-std-51-9. 3 exposed pad soldered to board, 25 thermal vias in padjedec, 4-layer board j-std-51-9. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad8331/ad8332/ad8334 rev. g | page 8 of 56 pin configurations and function descriptions 03199-003 mode vip gain vin lop coml lmd lon vpsl inh 1 2 3 4 5 6 7 8 9 10 rclmp comm voh enbv vcm vpos vol hilo enbl comm 20 19 18 17 16 15 14 13 12 11 ad8331 top view (not to scale) pin 1 indicator figure 3. 20-lead qsop pin configuration (ad8331) table 3. 20-lead qsop pin fu nction description (ad8331) pin no. nemonic description 1 lmd lna midsupply bypass pin; connect a capacitor for midsupply hf bypass 2 inh lna input 3 vpsl lna 5 v supply 4 lon lna inverting output 5 lop lna noninverting output 6 coml lna ground 7 vip vga noninverting input 8 vin vga inverting input 9 mode gain slope logic input 10 gain gain control voltage 11 vcm common-mode voltage 12 rclmp output clamping level 13 hilo gain range select (hi or lo) 14 vpos vga 5 v supply 15 voh noninverting vga output 16 vol inverting vga output 17 comm vga ground 18 enbv vga enable 19 enbl lna enable 20 comm vga ground
ad8331/ad8332/ad8334 rev. g | page 9 of 56 03199-004 vcm2 rclmp comm vol2 voh2 vip2 gain vin2 lop2 com2 lmd2 lon2 vps2 inh2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 com1 lop1 lmd1 lon1 vps1 inh1 voh1 enb vip1 vcm1 vin1 vpsv vol1 hilo 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ad8332 top view (not to scale) pin 1 indicator figure 4. 28-lead tssop pin configuration (ad8332) 03199-005 lop2 com2 vip2 vin2 vcm2 mode gain rclmp lop1 com1 vip1 vin1 vcm1 hilo enbl enbv lmd2 lon2 nc = no connect vps2 inh2 8 7 6 5 1 4 3 2 29303132 28 252627 lmd1 lon1 vps1 inh1 1413 91 2 1110 comm vol2 voh2 15 16 20 17 18 19 voh1 vol1 21 22 23 24 nc vpsv comm ad8332 top view (not to scale) pin 1 indicator figure 5. 32-lead lfcsp pin configuration (ad8332) table 4. 28-lead tssop pin function description (ad8332) pin no. mnemonic description 1 lmd2 ch 2 lna midsupply pin; connect a capacitor for midsupply hf bypass 2 inh2 ch2 lna input 3 vps2 ch2 supply lna 5 v 4 lon2 ch2 lna inverting output 5 lop2 ch2 lna noninverting output 6 com2 ch2 lna ground 7 vip2 ch2 vga noninverting input 8 vin2 ch2 vga inverting input 9 vcm2 ch2 common-mode voltage 10 gain gain control voltage 11 rclmp output clamping resistor 12 voh2 ch2 noninverting vga output 13 vol2 ch2 inverting vga output 14 comm vga ground (both channels) 15 vpsv vga supply 5 v (both channels) 16 vol1 ch1 inverting vga output 17 voh1 ch1 noninverting vga output 18 enb enablevga/lna 19 hilo vga gain range select (hi or lo) 20 vcm1 ch1 common-mode voltage 21 vin1 ch1 vga inverting input 22 vip1 ch1 vga noninverting input 23 com1 ch1 lna ground 24 lop1 ch1 lna noninverting output 25 lon1 ch1 lna inverting output 26 vps1 ch1 lna supply 5 v 27 inh1 ch1 lna input 28 lmd1 ch 1 lna midsupply pin; connect a capacitor for midsupply hf bypass table 5. 32-lead lfcsp pin function description (ad8332) pin no. mnemonic description 1 lon1 ch1 lna inverting output 2 vps1 ch1 lna supply 5 v 3 inh1 ch1 lna input 4 lmd1 ch 1 lna midsupply pin; connect a capacitor for midsupply hf bypass 5 lmd2 ch 2 lna midsupply pin; connect a capacitor for midsupply hf bypass 6 inh2 ch2 lna input 7 vps2 ch2 lna supply 5 v 8 lon2 ch2 lna inverting output 9 lop2 ch2 lna noninverting output 10 com2 ch2 lna ground 11 vip2 ch2 vga noninverting input 12 vin2 ch2 vga inverting input 13 vcm2 ch2 common-mode voltage 14 mode gain slope logic input 15 gain gain control voltage 16 rclmp output clamping level input 17 comm vga ground 18 voh2 ch2 noninverting vga output 19 vol2 ch2 inverting vga output 20 nc no connect 21 vpsv vga supply 5 v 22 vol1 ch1 inverting vga output 23 voh1 ch1 noninverting vga output 24 comm vga ground 25 enbv vga enable 26 enbl lna enable 27 hilo vga gain range select (hi or lo) 28 vcm1 ch1 common-mode voltage 29 vin1 ch1 vga inverting input 30 vip1 ch1 vga noninverting input 31 com1 ch1 lna ground 32 lop1 ch1 lna noninverting output
ad8331/ad8332/ad8334 rev. g | page 10 of 56 pin 1 indicator 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 com3 com4 inh4 lmd4 nc lon4 lop4 vip4 vin4 vps4 gain34 clmp34 hilo vcm4 vcm3 nc 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 com2 com1 inh1 lmd1 nc lon1 lop1 vip1 vin1 vps1 gain12 clmp12 en12 en34 vcm1 vcm2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 inh2 lmd2 nc lon2 lop2 vip2 vin2 vps2 vps3 vin3 vip3 lop3 lon3 nc lmd3 inh3 com12 voh1 vol1 vps12 vol2 voh2 com12 mode nc com34 voh3 vol3 vps34 vol4 voh4 com34 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ad8334 top view (not to scale) 03199-006 notes 1. the exposed paddle must be soldered to the pcb ground to ensure proper heat dissipation, noise, and mechanical strength benefits. 2. nc = no connect. figure 6. 64-lead lfcsp pin configuration (ad8334) table 6. 64-lead lfcsp pin function description (ad8334) pin no. nemonic description 1 inh2 ch2 lna input. 2 lmd2 ch 2 lna midsupply pin; connect a capacitor for midsupply hf bypass. 3 nc not connected. 4 lon2 ch2 lna feedback output (for r iz ). 5 lop2 ch2 lna output. 6 vip2 ch2 vga positive input. 7 vin2 ch2 vga negative input. 8 vps2 ch2 lna supply 5 v. 9 vps3 ch3 lna supply 5 v. 10 vin3 ch3 vga negative input. 11 vip3 ch3 vga positive input. 12 lop3 ch3 lna positive output. 13 lon3 ch3 lna feedback output (for r iz ). 14 nc not connected. 15 lmd3 ch 3 lna midsupply pin; connect a capacitor for midsupply hf bypass. 16 inh3 ch3 lna input. 17 com3 ch3 lna ground. 18 com4 ch4 lna ground. 19 inh4 ch4 lna input. 20 lmd4 ch 4 lna midsupply pin; connect a capacitor for midsupply hf bypass. 21 nc not connected. 22 lon4 ch4 lna feedback output (for r iz ). 23 lop4 ch4 lna positive output. 24 vip4 ch4 vga positive input. 25 vin4 ch4 vga negative input. 26 vps4 ch4 lna supply 5 v.
ad8331/ad8332/ad8334 rev. g | page 11 of 56 pin no. mnemonic description 27 gain34 gain control voltage for ch3 and ch4. 28 clmp34 output clamping level input for ch3 and ch4. 29 hilo gain select for postamp 0 db or 12 db. 30 vcm4 ch4 common-mode voltageac bypass. 31 vcm3 ch3 common-mode voltageac bypass. 32 nc no connect. 33 com34 vga ground ch3 and ch4. 34 voh4 ch4 positive vga output. 35 vol4 ch4 negative vga output. 36 vps34 vga supply 5 v ch3 and ch4. 37 vol3 ch3 negative vga output. 38 voh3 ch3 positive vga output. 39 com34 vga ground ch3 and ch4. 40 nc no connect. 41 mode gain control slope, logic input, 0 = positive. 42 com12 vga ground ch1 and ch2. 43 voh2 ch2 positive vga output. 44 vol2 ch2 negative vga output. 45 vps12 ch2 vga supply 5 v ch1 and ch2. 46 vol1 ch1 negative vga output. 47 voh1 ch1 positive vga output. 48 com12 vga ground ch1 and ch2. 49 vcm2 ch2 common-mode voltageac bypass. 50 vcm1 ch1 common-mode voltageac bypass. 51 en34 shared lna/vga enable ch3 and ch4. 52 en12 shared lna/vga enable ch1 and ch2. 53 clmp12 output clamping level input ch1 and ch2. 54 gain12 gain control voltage ch1 and ch2. 55 vps1 ch1 lna supply 5 v. 56 vin1 ch1 vga negative input. 57 vip1 ch1 vga positive input. 58 lop1 ch1 lna positive output. 59 lon1 ch1 lna feedback output (for r iz ). 60 nc not connected. 61 lmd1 ch 1 lna midsupply pin; connect a capacitor for midsupply hf bypass. 62 inh1 ch1 lna input. 63 com1 ch1 lna ground. 64 com2 ch2 lna ground. epad the exposed paddle must be soldered to the pc b ground to ensure proper heat dissipation, noise, and mechanical strength benefits.
ad8331/ad8332/ad8334 rev. g | page 12 of 56 typical performance characteristics t a = 25c, v s = 5 v, r l = 500 , r s = r in = 50 , r iz = 280 , c sh = 22 pf, f = 10 mhz, r clmp = , c l = 1 pf, vcm pin floating, ?4.5 db to +43.5 db gain (hilo = lo), and differential output voltage, unless otherwise specified. 60 50 40 30 20 10 0 ?10 0 0.2 0.4 0.6 0.8 1.0 1.1 gain (db) v gain (v) 03199-007 hilo = hi hilo = lo ascending gain mode descending gain mode (where available) figure 7. gain vs. v gain and mode (mode available on ru package) 2.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 0 0.2 0.4 0.6 0.8 1.0 1.1 gain error (db) v gain (v) 03199-008 +25c ?40c +85c figure 8. absolute gain error vs. v gain at three temperatures 2.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 0 0.2 0.4 0.6 0.8 1.0 1.1 gain error (db) v gain (v) 03199-009 1mhz 30mhz 10mhz 70mhz 50mhz figure 9. absolute gain error vs. v gain at various frequencies 50 40 30 20 10 0 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 percent of units (%) gain error (db) 03199-010 sample size = 80 units v gain = 0.5v figure 10. gain error histogram 03199-011 25 v gain = 0.7v 0 5 15 20 25 10 0 5 10 20 15 ?0.17 ?0.15 ?0.13 ?0.11 ?0.09 ?0.07 ?0.05 ?0.03 ?0.01 0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19 0.21 percent of units (%) channel to channel gain match (db) sample size = 50 units v gain = 0.2v figure 11. gain match histogram for v gain = 0.2 v and 0.7 v 50 40 30 20 10 0 ?20 ?10 100k 1m 10m 100m 500m gain (db) frequency (hz) 03199-012 v gain = 1v v gain = 0.8v v gain = 0.6v v gain = 0.4v v gain = 0.2v v gain = 0v figure 12. frequency response for various values of v gain
ad8331/ad8332/ad8334 rev. g | page 13 of 56 60 50 40 30 20 10 0 ?10 100k 1m 10m 100m 500m gain (db) frequency (hz) 03199-013 v gain = 1v v gain = 0.8v v gain = 0.6v v gain = 0.4v v gain = 0.2v v gain = 0v figure 13. frequency response for various values of v gain , hilo = hi 30 20 ?30 ?20 ?10 0 10 100k 1m 10m 100m 500m gain (db) frequency (hz) 03199-014 r in = r s = 50 ? r in = r s = 75 ? r in = r s = 100 ? r in = r s = 200 ? r in = r s = 500 ? r in = r s = 1k ? v gain = 0.5v figure 14. frequency response for various matched source impedances 30 ?30 ?20 ?10 0 10 20 100k 1m 10m 100m 500m gain (db) frequency (hz) 03199-015 v gain = 0.5v r iz = figure 15. frequency respon se, unterminated lna, r s = 50 0 ?120 ?100 ?80 ?60 ?40 ?20 100k 1m 10m 100m crosstalk (db) frequency (hz) 03199-016 v out = 1v p-p v gain = 1.0v v gain = 0.7v v gain = 0.4v ad8332 ad8334 figure 16. channel-to-channel crosstalk vs. frequency for various values of v gain 50 0 5 10 15 20 25 30 35 40 45 100k 1m 10m 100m group delay (ns) frequency (hz) 03199-017 0.1f coupling 1f coupling figure 17. group delay vs. frequency for two values of ac coupling 03199-018 20 ?20 ?10 0 10 20 ?20 ?10 0 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 offset voltage (mv) v gain (v) t = +85c t = +25c t = ?40c t = +85c t = +25c t = ?40c hi gain lo gain figure 18. representative differential output offset voltage vs. v gain at three temperatures
ad8331/ad8332/ad8334 rev. g | page 14 of 56 03199-019 35 sample size = 100 0.2v < v gain < 0.7v 0 5 10 15 20 25 30 49.6 50.5 50.4 50.350.250.150.049.949.849.7 % total gain scaling factor figure 19. gain scaling factor histogram 03199-020 100 10 1 0.1 100k 100m 10m 1m output impedance ( ? ) frequency (hz) single ended, pin voh or pin vol r l = figure 20. output im pedance vs. frequency 03199-021 10k 1k 100 10 100k 100m 10m 1m input impedance ( ? ) frequency (hz) r iz = 6.65k ? , c sh = 0pf r iz = 3.01k ? , c sh = 0pf r iz = 1.1k ? , c sh = 1.2pf r iz = 549 ? , c sh = 8.2pf r iz = 412 ? , c sh = 12pf r iz = 270 ? , c sh = 22pf r iz = , c sh = 0pf figure 21. lna input impedance vs. frequency for various values of r iz and c sh r in = 50 ? , r iz = 270 ? r in = 75 ? , r iz = 412 ? r in = 100 ? , r iz = 549 ? r in = 200 ? , r iz = 1.1k ? r in = 6k ? , r iz = 0 ? 17? 100j 50j ?50j ?100j 25j ?25j f = 100khz 03199-022 figure 22. smith chart, s11 vs. frequency, 0.1 mhz to 200 mhz for various values of r iz 20 15 10 5 0 ?15 ?10 ?5 100k 1m 10m 100m 500m gain (db) frequency (hz) 03199-023 v in = 10mv p-p r in = 50 ? r in = 75 ? r in = 100 ? r in = 200 ? r in = 500 ? r in = 1k ? figure 23. lna frequency response, si ngle-ended, for various values of r in 20 15 10 5 0 ?15 ?10 ?5 100k 1m 10m 100m 500m gain (db) frequency (hz) 03199-024 r iz = figure 24. frequency response for unterminated lna, single-ended
ad8331/ad8332/ad8334 rev. g | page 15 of 56 500 400 300 200 100 0 0 0.2 0.4 0.6 0.8 1.0 output-referred noise (nv/ hz) v gain (v) 03199-025 hi gain lo gain ad8332 ad8334 ad8331 f = 10mhz figure 25. output-referred noise vs. v gain 2.5 2.0 1.5 1.0 0.5 100k 1m 10m 100m frequency (hz) 03199-026 r s = 0, r iz = , v gain = 1v, hilo = lo or hi input-referred noise (nv/ hz) figure 26. short-circuit, inpu t-referred noise vs. frequency 100 10 1 0.1 0 0.2 0.4 0.6 0.8 1.0 v gain (v) 03199-027 r s = 0, r iz = , hilo = lo or hi, f = 10mhz input-referred noise (nv/ hz) figure 27. short-circuit, input-referred noise vs. v gain 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 ?50 ?30 ?10 10 30 50 70 90 input-referred noise (nv/ hz) temperature (c) 03199-028 r s = 0, r iz = , v gain = 1v, f = 10mhz figure 28. short-circuit, input- referred noise vs. temperature 10 1 0.1 1 10 100 1k source resistance ( ? ) 03199-029 f = 5mhz, r iz = , v gain = 1v r s thermal noise alone input-referred noise (nv/ hz) figure 29. input-referred noise vs. r s 7 6 5 4 3 2 1 0 50 100 1k noise figure (db) source resistance ( ? ) 03199-030 includes noise of vga r in = 50 ? r in = 75 ? r in = 100 ? r in = 200 ? r iz = simulated results figure 30. noise figure vs. r s for various values of r in
ad8331/ad8332/ad8334 rev. g | page 16 of 56 35 30 25 20 15 10 5 0 0 0.10.20.30.40.50.60.70.80.91.01.1 noise figure (db) v gain (v) 03199-031 f = 10mhz, r s = 50 ? preamp limited hilo = lo, r in = 50 ? hilo = lo, r iz = hilo = hi, r in = 50 ? hilo = hi, r iz = figure 31. noise figure vs. v gain 30 25 20 15 10 5 0 10 15 20 25 30 35 40 45 50 55 60 noise figure (db) gain (db) 03199-032 f = 10mhz, r s = 50 ? hilo = lo, r in = 50 ? hilo = lo, r fb = hilo = hi, r in = 50 ? hilo = hi, r fb = figure 32. noise figure vs. gain 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 1m 10m 100m harmonic distortion (dbc) frequency (hz) 03199-113 g = 30db v out = 1vp-p hilo = hi, hd2 hilo = hi, hd3 hilo = lo, hd2 hilo = lo, hd3 figure 33. harmonic distortion vs. frequency ? 30 ?40 ?50 ?60 ?70 ?80 ?90 0 2000 1800 1600 1400 1200 1000 800 600400200 harmonic distortion (dbc) r load ( ? ) 03199-034 hilo = lo, hd2 hilo = lo, hd3 hilo = hi, hd2 hilo = hi, hd3 f = 10mhz, v out = 1v p-p figure 34. harmonic distortion vs. r load ? 40 ?50 ?60 ?70 ?80 ?90 0 10203040 harmonic distortion (dbc) c load (pf) 03199-035 50 f = 10mhz, v out = 1v p-p hilo = lo, hd2 hilo = lo, hd3 hilo = hi, hd2 hilo = hi, hd3 figure 35. harmonic distortion vs. c load ? 20 ?40 ?60 ?80 ?100 01234 harmonic distortion (dbc) v out (v p-p) 03199-036 f = 10mhz, gain = 30db hilo = lo, hd2 hilo = lo, hd3 hilo = hi, hd2 hilo = hi, hd3 figure 36. harmonic distortion vs. differential output voltage
ad8331/ad8332/ad8334 rev. g | page 17 of 56 0 ?20 ?40 ?60 ?80 ?120 ?100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 distortion (dbc) v gain (v) 03199-037 v out = 1v p-p input range limited when hilo = lo hilo = lo, hd2 hilo = lo, hd3 hilo = hi, hd2 hilo = hi, hd3 figure 37. harmonic distortion vs. v gain , f = 1 mhz 0 ?20 ?40 ?60 ?80 ?120 ?100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 distortion (dbc) v gain (v) 03199-038 v out = 1v p-p input range limited when hilo = lo hilo = lo, hd2 hilo = lo, hd3 hilo = hi, hd2 hilo = hi, hd3 figure 38. harmonic distortion vs. v gain , f = 10 mhz 10 ?10 0 ?20 ?30 ?40 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ip1db compression (dbm) v gain (v) 03199-039 f = 10mhz hilo = hi hilo = lo figure 39. ip1db compression vs. v gain 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 1m 10m 100m imd3 (dbc) frequency (hz) 03199-040 v out = 1v p-p composite ( f 1 + f 2 ) g = 30db hilo = lo hilo = hi figure 40. imd3 vs. frequency 40 35 30 25 20 15 10 5 0 01 0.90.80.7 0.6 0.50.4 0.3 0.20.1 output ip3 (dbm) v gain (v) 03199-041 . 0 v out = 1v p-p composite ( f 1 + f 2 ) 1mhz hilo = hi 10mhz hilo = hi 1mhz hilo = lo 10mhz hilo = lo figure 41. output third-order intercept (ip3) vs. v gain 2mv 50mv 10ns 100 90 10 0 0 3199-042 figure 42. small signal pulse response, g = 30 db, top: input, bottom: output voltage, hilo = hi or lo
ad8331/ad8332/ad8334 rev. g | page 18 of 56 20mv 500mv 10ns 100 90 10 0 0 3199-043 figure 43. large signal pulse response, g = 30 db, hilo = hi or lo, top: input, bottom: output voltage 2 ?2 ?1 0 1 ?50 5040302010 0 ?10?20?30?40 v out (v) time (ns) 03199-044 g = 30db input input is not to scale c l = 0pf c l = 10pf c l = 22pf c l = 47pf figure 44. large signal pulse response for various capacitive loads, c l = 0 pf, 10 pf, 20 pf, 50 pf 500mv 200mv 400ns 0 3199-045 figure 45. pin gain transient response, top: v gain , bottom: output voltage 5.0 4.0 3.0 2.0 1.0 4.5 3.5 2.5 1.5 0.5 0 05 4540353025201510 5 v out (v p-p) r clmp (k ? ) 03199-046 0 hilo = hi hilo = lo figure 46. clamp level vs. r clmp 4 ?4 ?3 ?2 ?1 0 1 2 3 ?30?20?100 1020304050607080 v out (v) time (ns) 03199-047 g = 40db input r clmp = 48.1k ? r clmp = 16.5k ? r clmp = 7.15k ? r clmp = 2.67k ? figure 47. clamp level pulse response for four values of r clmp 200mv 100ns 100 90 10 0 0 3199-048 figure 48. lna overdrive recovery, v inh 0.05 v p-p to 1 v p-p burst, v gain = 0.27 v vga output shown
ad8331/ad8332/ad8334 rev. g | page 19 of 56 1v 100ns 100 90 10 0 0 3199-049 figure 49. vga overdrive recovery, v inh 4 mv p-p to 70 mv p-p burst, v gain = 1 v vga output shown attenuated by 24 db 1v 100ns 100 90 10 0 0 3199-050 figure 50. vga overdrive recovery, v inh 4 mv p-p to 275 mv p-p burst, v gain = 1 v vga output shown attenuated by 24 db 2v 200mv 1ms 0 3199-051 figure 51. enable response, top: v enb , bottom: v out , v inh = 30 mv p-p 2v 1v 1ms 0 3199-052 figure 52. enable response, large signal, top: v enb , bottom: v out , v inh = 150 mv p-p 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100k 1m 10m 100m psrr (db) frequency (hz) 03199-053 vps1, v gain = 0.5v vpsv, v gain = 0.5v vps1, v gain = 0v figure 53. psrr vs. frequency (no bypass capacitor) 140 130 120 110 100 90 80 70 60 50 40 30 20 ?40 100 80 60 40 20 0 ?20 quiescent supply current (ma) temperature (c) 03199-054 v gain = 0.5v ad8334 ad8332 ad8331 figure 54. quiescent supply current vs. temperature
ad8331/ad8332/ad8334 rev. g | page 20 of 56 test circuits measurement considerations figure 55 through figure 68 show typical measurement configurations and proper interface values for measurements with 50 conditions. short-circuit input noise measurements are made as shown in figure 62 . the input-referred noise level is determined by dividing the output noise by the numerical gain between point a and point b and accounting for the noise floor of the spectrum analyzer. the gain should be measured at each frequency of interest and with low signal levels because a 50 load is driven directly. the generator is removed when noise measurements are made. 0 3199-055 lmd 18nf 22pf fb* 120nh * ferrite bead in out 0.1f dut network analyze r 0.1f 28 ? 237? 28? 1:1 50? 50? 270 ? inh 237? 0.1f 0.1f figure 55. test circuitgain and bandwidth measurements 10k ? 10k ? 03199-056 lmd 18nf 22pf fb* 120nh *ferrite bead in out 0.1f vgn dut network analyzer 0.1f 28? 237 ? 28 ? 1:1 50? 50 ? inh 237 ? 0.1f 0.1f figure 56. test circuitfrequency response for various matched source impedances 03199-057 lmd 22pf fb* 120nh *ferrite bead in out 0.1f vgn dut network analyzer 0.1f 28 ? 237? 28? 1:1 50 ? 50? inh 237? 0.1f 0.1f figure 57. test circui tfrequency response fo r unterminated lna, r s = 50
ad8331/ad8332/ad8334 rev. g | page 21 of 56 03199-058 18nf 22pf in out network analyzer 28 ? 237? 28? 1:1 50 ? 50 ? 0.1f or 1f 237? 10k ? vga fb* 120nh *ferrite bead lmd 0.1f lna 0.1f or 1f inh 0.1f or 1f 0.1f 0.1f figure 58. test circuitgroup delay vs. frequency for two values of ac coupling 03199-059 18nf 22pf 28 ? 237? 28? 0.1f 237? 50? 1:1 out network analyzer 50? 270? fb* 120nh *ferrite bead lmd 0.1f dut 0.1f 0.1f inh figure 59. test circuitlna input impedance vs. frequency in standard and smith chart (s11) formats 03199-060 22pf 28 ? 237 ? 28? 1:1 0.1f 0.1f 237 ? in out network analyzer 50? 50 ? vga lna fb* 120nh *ferrite bead lmd 0.1f 0.1f inh 0.1f 0.1f 0.1f figure 60. test circuitfr equency response for unterminated lna, single-ended 03199-061 18nf 22pf 28? 237 ? 28 ? 0.1f inh 237 ? 1:1 in networ k analyzer 50? 270? fb* 120nh * ferrite bead lmd 0.1f dut 0.1f 0.1f figure 61. test circuitshort- circuit, input-referred noise
ad8331/ad8332/ad8334 rev. g | page 22 of 56 03199-062 22pf signal generator to measure gain disconnect for noise measurement gain 1:1 0.1f in spectrum analyzer 50? b a 49.9 ? 50? 1 ? ferrite bead 120nh inh lmd 0.1f 0.1f 0.1f dut figure 62. test circuitnoise figure 03199-063 22pf ad8332 1:1 0.1f in spectrum analyzer 50? 50? signal generator ?6db ?6db 28? 28? 1k? 1k? 18nf 270? lpf inh lmd 0.1f 0.1f 0.1f dut figure 63. test circuitharmonic distortion vs. load resistance 03199-114 22pf ad8332 1:1 0.1f in spectrum analyzer 50? 50? signal generator ?6db ?6db 28? 28? 18nf 270? lpf inh lmd 0.1f 0.1f 0.1f dut 237 ? 237 ? figure 64. test circuitharmonic distortion vs. load capacitance 03199-065 inh 0.1f spectrum analyzer input 50? 22pf ?6db signal generators combiner ?6db 50? ?6db 50? ?6db +22db +22db fb* 120nh *ferrite bead 18nf 28? 237 ? 237 ? 28 ? 274? lmd 0.1f dut 0.1f 0.1f 1:1 figure 65.test circuitimd3 vs. frequency
ad8331/ad8332/ad8334 rev. g | page 23 of 56 0 3199-066 inh 0.1f oscilloscope in 50? 22pf 50? fb* 120nh *ferrite bead 18nf 28? 237? 28? 237? 1:1 270 ? lmd 0.1f dut 0.1f 0.1f figure 66. test circuitpulse response measurements 03199-067 inh diff probe 0.1f oscilloscop e ch1 ch2 22pf 18nf 270? rf signal generator to pin gain or pin enxx 50? 50 ? pulse generator 9.5db fb* 120nh *ferrite bead 255? 255? lmd 0.1f dut 0.1f 0.1f figure 67. test circuitgain and enable transient response 03199-068 inh diff probe 0.1f 22pf rf signal generator 50 ? probe power 50? network analyzer in out 50? fb* 120nh *ferrite bead 18nf 270? 255? 255 ? lmd 0.1f 0.1f 0.1f to power pins dut figure 68. test circuitpsrr vs. frequency
ad8331/ad8332/ad8334 rev. g | page 24 of 56 theory of operation 03199-071 clamp lna 2 lna 1 inh1 lon1 lop1 v ip1 v in1 en12 inh2 lon2 lop2 vip2 pa2 ? attenuator ?48db + vga bias and interpolator + attenuator ?48db ? gain up/ down v mid1 clamp gain int voh1 clmp12 vol1 vol2 gain12 hilo voh2 vin2 mode v cm1 v mid2 v mid3 vcm2 vcm3 v mid4 lna 4 lna 3 inh3 lon3 lop3 lmd3 lmd4 inh4 vcm bias vcm bias pa3 pa4 ? attenuator ?48db + vga bias and interpolator + attenuator ?48db ? gain int voh3 vol3 vol4 gain34 voh4 clmp34 21db 21db 21db 21db vip3 vin3 vcm4 en34 vin4 vip4 lon4 lop4 ad8334 lmd1 lmd2 pa1 overview the ad8331 / ad8332/ ad8334 operate in the same way. figure 69 , figure 70 , and figure 71 are functional block diagrams of the three devices 03199-069 vol voh lna attenuator ?48db ? + inh v in v ip lop lon enbv gain ad8331 + ? mode hilo 3.5db/ 15.5db rclmp v mid v cm vga bias and interpolator enbl gain int vcm bias pa 21db clamp lmd figure 69. ad8331 functional block diagram 03199-070 lna 2 lna 1 +19db inh1 lon1 lop1 lon2 lop2 vip1 vip2 vin1 vin2 lmd1 lmd2 inh2 lna v mid pa1 pa2 ? attenuator ?48db + vga bias and interpolator + attenuator ?48db ? 3.5db/ 15.5db enb gain int voh1 vol1 voh2 vol2 gain rclmp hilo ad8332 v mid vcm1 v mid vcm2 clamp 21db 21db figure 71. ad8334 functional block diagram each channel contains an lna that provides user-adjustable input impedance termination, a differential x-amp vga, and a pro- grammable gain postamp with adjustable output voltage limiting. figure 72 shows a simplified block diagram with external components. figure 70. ad8332 functional block diagram 03199-072 lna vol voh hilo inh lmd lop lon preamplifier 19db postamp 3.5db/15.5db signal path bias and interpolator vin vip rclmp 21db vcm v mid clamp 48db attenuator gain interface gain vcm bias figure 72. simplified block diagram
ad8331/ad8332/ad8334 rev. g | page 25 of 56 the linear-in-db, gain control interface is trimmed for slope and absolute accuracy. the gain range is +48 db, extending from ?4.5 db to +43.5 db in lo gain and +7.5 db to +55.5 db in hi gain mode. the slope of the gain control interface is 50 db/v, and the gain control range is 40 mv to 1 v. equation 1 and equation 2 are the expressions for gain. gain (db) = 50 (db/v) v gain ? 6.5 db, ( hilo = lo ) (1) or gain (db) = 50 (db/v) v gain + 5.5 db, ( hilo = hi ) (2) the ideal gain characteristics are shown in figure 73 . 60 50 40 30 20 10 0 ?10 0 0.2 0.4 0.6 0.8 1.0 1.1 gain (db) v gain (v) 03199-073 hilo = hi hilo = lo ascending gain mode descending gain mode (where available) figure 73. ideal gain control characteristics the gain slope is negative with mode pulled high (where available), as follows: gain (db) = ?50 (db/v) v gain + 45.5 db, ( hilo = lo ) (3) or gain (db) = ?50 (db/v) v gain + 57.5 db, ( hilo = hi ) (4) the lna converts a single-ended input to a differential output with a voltage gain of 19 db. if only one output is used, the gain is 13 db. the inverting output is used for active input impedance termination. each of the lna outputs is capacitively coupled to a vga input. the vga consists of an attenuator with a range of 48 db followed by an amplifier with 21 db of gain for a net gain range of ?27 db to +21 db. the x-amp, gain interpolation technique results in low gain error and uniform bandwidth, and differential signal paths minimize distortion. the final stage is a logic programmable amplifier with gains of 3.5 db or 15.5 db. the lo and hi gain modes are optimized for 12-bit and 10-bit adc applications, in terms of output-referred noise and absolute gain range. output voltage limiting can be programmed by the user. low noise amplifier (lna) good noise performance in the ad8331/ ad8332 / ad8334 relies on a proprietary ultralow noise preamplifier at the beginning of the signal chain, which minimizes the noise contribution in the following vga. active impedance control optimizes noise per- formance for applications that benefit from input matching. a simplified schematic of the lna is shown in figure 74 . inh is capacitively coupled to the source. a bias generator establishes dc input bias voltages of 3.25 v and centers the output common- mode levels at 2.5 v. a capacitor c lmd (can be the same value as the input coupling capacitor c inh ) is connected from the lmd pin to ground to decouple the lmd bus. the lmd pin is not useable for configuring the lna as a differential input amplifier. 03199-074 r s c inh c sh i 0 i 0 i 0 i 0 q1 q2 vpos vcm bias lop inh 3.25v 3.25v ?a ?a lon to vga 2.5v 2.5v c lmd lmd c iz r iz 60? 40? 80? figure 74. simplified lna schematic the lna supports differential output voltages as high as 5 v p-p, with positive and negative excursions of 1.25 v, about a common-mode voltage of 2.5 v. because the differential gain magnitude is 9, the maximum input signal before saturation is 275 mv or +550 mv p-p. overload protection ensures quick recovery time from large input voltages. because the inputs are capacitively coupled to a bias voltage near midsupply, very large inputs can be handled without interacting with the esd protection. low value feedback resistors and the current-driving capability of the output stage allow the lna to achieve a low input-referred voltage noise of 0.74 nv/hz. this is achieved with a current consumption of only 11 ma per channel (55 mw). on-chip resistor matching results in precise single-ended gains of 4.5 (9 differential), critical for accurate impedance control. the use of a fully differential topology and negative feedback minimizes distortion. low hd2 is particularly important in second harmonic ultrasound imaging applications. differential signaling enables smaller swings at each output , further reducing third-order distortion.
ad8331/ad8332/ad8334 rev. g | page 26 of 56 active impedance matching the lna supports active impedance matching through an external shunt feedback resistor from pin lon to pin inh. the input resistance, r in , is given in equation 5, where a is the single- ended gain of 4.5, and 6 k is the unterminated input impedance. iz iz iz in r r a r r + = + = k 33 k 6 k 6 1 (5) c iz is needed in series with r iz because the dc levels at pin lon and pin inh are unequal. expressions for choosing r iz in terms of r in and for choosing c iz are found in the applications information section. c sh and the ferrite bead enhance stability at higher frequencies, where the loop gain is diminished, and prevent peaking. frequency response plots of the lna are shown in figure 23 and figure 24 . the bandwidth is approximately 130 mhz for matched input impedances of 50 to 200 and declines at higher source impedances. the unterminated bandwidth (when r iz = ) is approximately 80 mhz. each output can drive external loads as low as 100 in addition to the 100 input impedance of the vga (200 differential). capacitive loading up to 10 pf is permissible. all loads should be ac-coupled. typically, pin lop output is used as a single-ended driver for auxiliary circuits, such as those used for doppler ultrasound imaging. pin lon drives r iz . alternatively, a differential external circuit can be driven from the two outputs in addition to the active feedback termination. in both cases, important stability considerations discussed in the applications information section should be carefully observed. the impedance at each lna output is 5 . a 0.4 db reduction in open circuit gain results when driving the vga, and a 0.8 db reduction results with an additional 100 load at the output. the differential gain of the lna is 6 db higher. if the load is less than 200 on either side, a compensating load is recommended on the opposite output. lna noise the input-referred voltage noise sets an important limit on system performance. the short-circuit input voltage noise of the lna is 0.74 nv/hz or 0.82 nv/hz (at maximum gain), including the vga noise. the open circuit, current noise is 2.5 pa/hz. these measurements, taken without a feedback resistor, provide the basis for calculating the input noise and noise figure performance of the configurations in figure 75 . figure 76 and figure 77 show simulations extracted from these results and the 4.1 db noise figure (nf) measurement with the input actively matched to a 50 source. unterminated (r iz = ) operation exhibits the lowest equivalent input noise and noise figure. figure 76 shows the noise figure vs. source resistance, rising at low r s , where the lna voltage noise is large compared to the source noise, and again at high r s due to current noise. the vga input-referred voltage noise of 2.7 nv/hz is included in all of the curves. v out unterminated + ? v in r in r s v out resistive termination + ? v in r in r s r s v out active impedance match - r s = r in + ? v in r in r iz r iz 1 + 4.5 r s r in = 03199-075 figure 75. input configurations 7 6 5 4 3 2 1 0 50 100 1k noise figure (db) r s ( ? ) 03199-076 includes noise of vga resistive termination (r s = r in ) active impedance match unterminated simulation figure 76. noise figure vs. r s for resistive, active match, and unterminated inputs 7 6 5 4 3 2 1 0 50 100 1k noise figure (db) r s ( ? ) 03199-077 includes noise of vga r in = 50 ? r in = 75 ? r in = 100 ? r in = 200 ? r iz = (simulated results) figure 77. noise figure vs. r s for various fixed values of r in , actively matched
ad8331/ad8332/ad8334 rev. g | page 27 of 56 the primary purpose of input impedance matching is to improve the system transient response. with resistive termination, the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the lna input voltage noise generator. with active impedance matching, however, the contributions of both are smaller than they would be for resistive termination by a factor of 1/(1 + lna gain ). figure 76 shows their relative nf performance. in this graph, the input impedance is swept with r s to preserve the match at each point. the noise figures for a source impedance of 50 are 7.1 db, 4.1 db, and 2.5 db, respectively, for the resistive, active, and unterminated configurations. the noise figures for 200 are 4.6 db, 2.0 db, and 1.0 db, respectively. figure 77 is a plot of nf vs. r s for various values of r in , which is helpful for design purposes. the plateau in the nf for actively matched inputs mitigates source impedance variations. for comparison purposes, a preamp with a gain of 19 db and noise spectral density of 1.0 nv/hz, combined with a vga with 3.75 nv/hz, yields a noise figure degradation of approximately 1.5 db (for most input impedances), significantly worse than the ad8331 / ad8332/ ad8334 performance. the equivalent input noise of the lna is the same for single- ended and differential output applications. the lna noise figure improves to 3.5 db at 50 without vga noise, but this is exclusive of noise contributions from other external circuits connected to lop. a series output resistor is usually recom- mended for stability purposes when driving external circuits on a separate board (see the applications information section). in low noise applications, a ferrite bead is even more desirable. variable gain amplifier the differential x-amp vga provides precise input attenuation and interpolation. it has a low input-referred noise of 2.7 nv/hz and excellent gain linearity. a simplified block diagram is shown in figure 78 . 03199-078 vip gain r 6db 2r 2 00 ? 48db vin g m postamp postamp + ? gain interpolator (both channels) figure 78. simplified vga schematic x-amp vga the input of the vga is a differential r-2r ladder attenuator network with 6 db steps per stage and a net input impedance of 200 differential. the ladder is driven by a fully differential input signal from the lna and is not intended for single-ended operation. lna outputs are ac-coupled to reduce offset and isolate their common-mode voltage. the vga inputs are biased through the center tap connection of the ladder to vcm, which is typically set to 2.5 v and is bypassed externally to provide a clean ac ground. the signal level at successive stages in the input attenuator falls from 0 db to ?48 db in +6 db steps. the input stages of the x-amp are distributed along the ladder, and a biasing interpolator, controlled by the gain interface, determines the input tap point. with overlapping bias currents, signals from successive taps merge to provide a smooth attenuation range from 0 db to ?48 db. this circuit technique results in excellent linear-in-db gain law conformance and low distortion levels and deviates 0.2 db or less from the ideal. the gain slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply. the x-amp inputs are part of a gain-of-12 feedback amplifier that completes the vga. its bandwidth is 150 mhz. the input stage is designed to reduce feedthrough to the output and to ensure excellent frequency response uniformity across gain setting (see figure 12 and figure 13 ). gain control position along the vga attenuator is controlled by a single-ended analog control voltage, v gain , with an input range of 40 mv to 1.0 v. the gain control scaling is trimmed to a slope of 50 db/v (20 mv/db). values of v gain beyond the control range saturate to minimum or maximum gain values. both channels of the ad8332 are controlled from a single gain interface to preserve matching. gain can be calculated using equation 1 and equation 2. gain accuracy is very good because both the scaling factor and absolute gain are factory trimmed. the overall accuracy relative to the theoretical gain expression is 1 db for variations in temperature, process, supply voltage, interpolator gain ripple, trim errors, and tester limits. the gain error relative to a best-fit line for a given set of conditions is typically 0.2 db. gain matching between channels is better than 0.1 db ( figure 11 shows gain errors in the center of the control range). when v gain < 0.1 or > 0.95, gain errors are slightly greater. the gain slope can be inverted, as shown in figure 73 (except for the ad8332 ar models). the gain drops with a slope of ?50 db/v across the gain control range from maximum to minimum gain. this slope is useful in applications such as automatic gain control, where the control voltage is proportional to the measured output signal amplitude. the inverse gain mode is selected by setting the mode pin to hi gain mode. gain control response time is less than 750 ns to settle within 10% of the final value for a change from minimum to maximum gain.
ad8331/ad8332/ad8334 rev. g | page 28 of 56 vga noise in a typical application, a vga compresses a wide dynamic range input signal to within the input span of an adc. while the input-referred noise of the lna limits the minimum resolvable input signal, the output-referred noise, which depends primarily on the vga, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. this limit is set in accordance with the quantization noise floor of the adc. output- and input-referred noise as a function of v gain are plotted in figure 25 and figure 27 for the short circuited input conditions. the input noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range. the output-referred noise is flat over most of the gain range because it is dominated by the fixed output-referred noise of the vga. values are 48 nv/hz in lo gain mode and 178 nv/hz in hi gain mode. at the high end of the gain control range, the noise of the lna and the noise of the source prevail. the input- referred noise reaches its minimum value near the maximum gain control voltage, where the input-referred contribution of the vga becomes very small. at lower gains, the input-referred noise, and thus noise figure, increases as the gain decreases. the instantaneous dynamic range of the system is not lost, however, because the input capacity increases with it. the contribution of the adc noise floor has the same dependence as well. the important relationship is the magnitude of the vga output noise floor relative to that of the adc. with its low output-referred noise levels, these devices ideally drive low voltage adcs. the converter noise floor drops 12 db for every two bits of resolution and drops at lower input full- scale voltages and higher sampling rates. adc quantization noise is discussed in the applications information section. the preceding noise performance discussion applies to a differential vga output signal. although the lna noise performance is the same in single-ended and differential applications, the vga performance is not. the noise of the vga is significantly higher in single-ended usage because the contribution of its bias noise is designed to cancel in the differential signal. a transformer can be used with single-ended applications when low noise is desired. gain control noise is a concern in very low noise applications. thermal noise in the gain control interface can modulate the channel gain. the resultant noise is proportional to the output signal level and usually only evident when a large signal is present. its effect is observable only in lo gain mode where the noise floor is substantially lower. the gain interface includes an on-chip noise filter, which reduces this effect significantly at frequencies above 5 mhz. care should be taken to minimize noise impinging at the gain input. an external rc filter can be used to remove v gain source noise. the filter bandwidth should be sufficient to accommodate the desired control bandwidth. common-mode biasing an internal bias network connected to a midsupply voltage establishes common-mode voltages in the vga and postamp. an externally bypassed buffer maintains the voltage. the bypass capacitors form an important ac ground connection because the vcm network makes a number of important connections internally, including the center tap of the vga differential input attenuator, the feedback network of the vga fixed gain amplifier, and the feedback network of the postamp in both gain settings. for best results, use a 1 nf capacitor and a 0.1 f capacitor in parallel, with the 1 nf capacitor nearest to the vcm pin. separate vcm pins are provided for each channel. for dc coupling to a 3 v adc, the output common-mode voltage is adjusted to 1.5 v by biasing the vcm pin. postamplifier the final stage has a selectable gain of 3.5 db (1.5) or 15.5 db (6), set by the hilo logic pin. figure 79 is a simplified block diagram. 0 3199-079 gm2 + ? gm1 voh vol vcm gm1 gm2 f1 f2 figure 79. postamplifier block diagram separate feedback attenuators implement the two gain settings. these are selected in conjunction with an appropriately scaled input stage to maintain a constant 3 db bandwidth between the two gain modes (~150 mhz). the slew rate is 1200 v/s in hi gain mode and 300 v/s in lo gain mode. the feedback networks for hi and lo gain modes are factory trimmed to adjust the absolute gains of each channel. noise the topology of the postamp provides constant input-referred noise with the two gain settings and variable output-referred noise. the output-referred noise in hi gain mode increases (with gain) by four. this setting is recommended when driving converters with higher noise floors. the extra gain boosts the output signal levels and noise floor appropriately. when driving circuits with lower input noise floors, the lo gain mode optimizes the output dynamic range. although the quantization noise floor of an adc depends on a number of factors, the 48 nv/hz and 178 nv/hz levels are well suited to the average requirements of most 12-bit and 10-bit converters, respectively. an additional technique, described in the applications information section, can extend the noise floor even lower for possible use with 14-bit adcs.
ad8331/ad8332/ad8334 rev. g | page 29 of 56 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?3 ?2 ?1 0 1 2 3 v oh , v ol (v) v inh (v) 03199-080 r clmp = r clmp = 8.8k ? 8.8k ? 3.5k ? 3.5k ? r clmp = 1.86k ? output clamping outputs are internally limited to a level of 4.5 v p-p differential when operating at a 2.5 v common-mode voltage. the postamp implements an optional output clamp engaged through a resistor from r clmp to ground. tabl e 8 shows a list of recommended resistor values. output clamping can be used for adc input overload protection, if needed, or postamp overload protection when operating from a lower common-mode level, such as 1.5 v. the user should be aware that distortion products increase as output levels approach the clamping levels, and the user should adjust the clamp resistor accordingly. for additional information, see the applications information section. the accuracy of the clamping levels is approximately 5% in lo or hi mode. figure 80 illustrates the output characteristics for a few values of r clmp . figure 80. output clamping characteristics
ad8331/ad8332/ad8334 rev. g | page 30 of 56 applications information lnaexternal components the lmd pin (connected to the bias circuitry) must be bypassed to ground and signal sourced to the inh pin, which is capacitively coupled using 2.2 nf to 0.1 f capacitors (see figure 81 ). the unterminated input impedance of the lna is 6 k. the user can synthesize any lna input resistance between 50 and 6 k. r iz is calculated according to equation 6 or selected from table 7 . () () in in iz r r r C k 6 k 33 = (6) table 7. lna external component values for common source impedances r in () r iz (nearest std 1% value, ) c sh (pf) 50 280 22 75 412 12 100 562 8 200 1.13 k 1.2 500 3.01 k none 6 k none when active input termination is used, a decoupling capacitor (c is ) is required to isolate the input and output bias voltages of the lna. the shunt input capacitor, c sh , reduces gain peaking at higher frequencies where the active termination match is lost due to the gain roll-off of the lna at high frequencies. the value of c sh diminishes as r in increases to 500 , at which point no capacitor is required. suggested values for c sh for 50 r in 200 are shown in table 7 . when a long trace to pin inh is unavoidable, or if both lna outputs drive external circuits, a small ferrite bead (fb) in series with pin inh preserves circuit stability with negligible effect on noise. the bead shown is 75 at 100 mhz (murata blm21 or equivalent). other values can prove useful. figure 82 shows the interconnection details of the lna output. capacitive coupling between the lna outputs and the vga inputs is required because of the differences in their dc levels and the need to eliminate the offset of the lna. capacitor values of 0.1 f are recommended. there is a 0.4 db loss in gain between the lna output and the vga input due to the 5 output resistance. additional loading at the lop and lon outputs affects lna gain. 21 22 23 24 28 25 26 27 15 16 20 17 18 19 8 7 6 5 1 4 3 2 14 13 9 12 11 10 vcm2 rclmp comm vol2 voh2 vip2 gain vin2 lop2 com2 lmd2 lon2 vps2 inh2 com1 lop1 lmd1 lon1 vps1 inh1 voh1 enb vip1 vcm1 vin1 vpsv vol1 hilo 0.1f c iz * c sh * r iz * c lmd 0.1f 1nf 5v 5v 1nf 5v +5v * * vga out vga out 5v 1nf 0.1f lna out 1nf v gain fb 1nf 0.1f 0.1f 0.1f 0.1f 1nf 0.1f *see text 03199-081 lna source figure 81. basic connections for a typical channel ( ad8332 shown) 03199-082 vin vip lop vcm 100 ? 50? 100 ? lon r iz c sh to ext circuit to ext circuit lna decoupling resistor ln a decoupling resistor 50? 5 ? 5 ? lna 3.25v 3.25v 2.5v 2.5v figure 82. interconnections of the lna and vga both lna outputs are available for driving external circuits. pin lop should be used in those instances when a single-ended lna output is required. the user should be aware of stray capacitance loading of the lna outputs, in particular lon. the lna can drive 100 in parallel with 10 pf. if an lna output is routed to a remote pc board, it tolerates a load capacitance up to 100 pf with the addition of a 49.9 series resistor or ferrite 75 /100 mhz bead.
ad8331/ad8332/ad8334 rev. g | page 31 of 56 gain input the gain pin is common to both channels of the ad8332. the input impedance is nominally 10 m, and a bypass capacitor from 100 pf to 1 nf is recommended. parallel connected devices can be driven by a common voltage source or dac. decoupling should take into account any band- width considerations of the drive waveform, using the total distributed capacitance. if gain control noise in lo gain mode becomes a factor, main- taining 15 nv/hz noise at the gain pin ensures satisfactory noise performance. internal noise prevails below 15 nv/hz at the gain pin. gain control noise is negligible in hi gain mode. vcm input the common-mode voltage of pin vcm, pin vol, and pin voh defaults to 2.5 v dc. with output ac-coupled applications, the vcm pin is unterminated; however, it must still be bypassed in close proximity for ac grounding of internal circuitry. the vga outputs can be dc connected to a differential load, such as an adc. common-mode output voltage levels between 1.5 v and 3.5 v can be realized at pin voh and pin vol by applying the desired voltage at pin vcm. dc-coupled operation is not recommended when driving loads on a separate pc board. the voltage on the vcm pin is sourced by an internal buffer with an output impedance of 30 and a 2 ma default output current (see figure 83 ). if the vcm pin is driven from an external source, its output impedance should be <<30 , and its current drive capability should be >>2 ma. if the vcm pins of several devices are connected in parallel, the external buffer should be capable of overcoming their collective output currents. when a common-mode voltage other than 2.5 v is used, a voltage- limiting resistor, r clmp , is needed to protect against overload. 03199-083 vcm new v cm r o << 30 ? 100pf 2ma max 30? 0.1f internal circuitry ac grounding for internal circuitry figure 83. vcm interface logic inputsenb, mode, and hilo the input impedance of all enable pins is nominally 25 k and can be pulled up to 5 v (a pull-up resistor is recommended) or driven by any 3 v or 5 v logic families. the enable pin, enb, powers down the vga; when pulled low, the vga output voltages are near ground. multiple devices can be driven from a common source. consult table 3 , table 4 , table 5 , and table 6 for infor- mation about circuit functions controlled by the enable pins. pin hilo is compatible with 3 v or 5 v cmos logic families. it is either connected to ground or pulled up to 5 v, depending on the desired gain range and output noise. optional output voltage limiting the rclmp pin provides the user with a means to limit the output voltage swing when used with loads that have no provisions for prevention of input overdrive. the peak-to-peak limited voltage is adjusted by a resistor to ground (see table 8 for a list of several voltage levels and corresponding resistor values). unconnected, the default limiting level is 4.5 v p-p. note that third harmonic distortion increases as waveform amplitudes approach clipping. for lowest distortion, the clamp level should be set higher than the converter input span. a clamp level of 1.5 v p-p is recommended for a 1 v p-p linear output range, 2.7 v p-p for a 2 v p-p range, or 1 v p-p for a 0.5 v p-p operation. the best solution is determined experimentally. figure 84 shows third harmonic distortion as a function of the limiting level for a 2 v p-p output signal. a wider limiting level is desirable in hi gain mode. ? 20 ?30 ?40 ?50 ?60 ?70 ?80 1.52.02.53.0 4.0 3.5 4.5 5.0 hd3 (dbc) clamp limit level (v p-p) 03199-084 v gain = 0.75v hilo = lo hilo = hi figure 84. hd3 vs. clamping le vel for 2 v p-p differential input table 8. clamp resistor values clamp level (v p-p) clamp resistor value () ilo lo ilo i 0.5 1.21 1.0 2.74 2.21 1.5 4.75 4.02 2.0 7.5 6.49 2.5 11 9.53 3.0 16.9 14.7 3.5 26.7 23.2 4.0 49.9 39.2 4.4 100 73.2 output decoupling when driving capacitive loads greater than about 10 pf, or long circuit connections on other boards, an output network of resistors and/or ferrite beads can be useful to ensure stability. these components can be incorporated into a nyquist filter such as the one shown in figure 81 . in figure 81 , the resistor value is 84.5 . for example, all the evaluation boards for this series incorporate 100 in parallel with a 120 nh bead. lower value resistors are permissible for applications with nearby loads or
ad8331/ad8332/ad8334 rev. g | page 32 of 56 with gains less than 40 db. the exact values of these components can be selected empirically. an antialiasing noise filter is typically used with an adc. filter requirements are application dependent. when the adc resides on a separate board, the majority of filter components should be placed nearby to suppress noise picked up between boards and to mitigate charge kickback from the adc inputs. any series resistance beyond that required for output stability should be placed on the adc board. figure 85 shows a second-order, low-pass filter with a bandwidth of 20 mhz. the capacitor is chosen in conjunction with the 10 pf input capacitance of the adc. 03199-085 18pf optional backplane 0.1f 0.1f adc 84.5 ? 84.5 ? 158 ? 158 ? 1.5h 1.5h figure 85. 20 mhz second-order, low-pass filter driving adcs the output drive accommodates a wide range of adcs. the noise floor requirements of the vga depend on a number of application factors, including bit resolution, sampling rate, full- scale voltage, and the bandwidth of the noise/antialias filter. the output noise floor and gain range can be adjusted by selecting hi or lo gain mode. the relative noise and distortion performance of the two gain modes can be compared in figure 25 and figure 31 through figure 41 . the 48 nv/hz noise floor of the lo gain mode is suited to converters with higher sampling rates or resolutions (such as 12 bits). both gain modes can accommodate adc full- scale voltages as high as 4 v p-p. because distortion performance remains favorable for output voltages as high as 4 v p-p (see figure 36 ), it is possible to lower the output-referred noise even further by using a resistive attenuator (or transformer) at the output. the circuit in figure 86 has an output full-scale range of 2 v p-p, a gain range of ?10.5 db to +37.5 db, and an output noise floor of 24 nv/hz, making it suitable for some 14-bit adc applications. 03199-086 adc ad6644 187 ? 2:1 187 ? 374? voh vol lpf 4v p-p diff, 48nv/ hz 2v p-p diff, 24nv/ hz figure 86. adjusting the noise floor for 14-bit adcs overload these devices respond gracefully to large signals that overload its input stage and to normal signals that overload the vga when the gain is set unexpectedly high. each stage is designed for clean-limited overload waveforms and fast recovery when gain setting or input amplitude is reduced. signals larger than 275 mv at the lna input are clipped to 5 v p-p differential prior to the input of the vga. figure 48 shows the response to a 1 v p-p input burst. the symmetric overload waveform is important for applications, such as cw doppler ultrasound, where the spectrum of the lna outputs during overload is critical. the input stage is also designed to accommodate signals as high as 2.5 v without triggering the slow-settling esd input protection diodes. both stages of the vga are susceptible to overload. post- amplifier limiting is more common and results in the clean- limited output characteristics found in figure 49 . recovery is fast in all cases. the graph in figure 87 summarizes the combinations of input signal and gain that lead to the different types of overload. 03199-087 gain (db) 1m lo gain mode 15mv ?4.5 25mv lna overload x -amp overload postamp overload x -amp overload postamp overload 29db 43.5 input amplitude (v) 0.2750.1 10m 24.5db gain (db) hi gain mode 4mv 7.5 25mv lna overload 41db 56.5 input amplitude (v) 24.5db 1 1m 0.275 0.1 10m 1 figure 87. overload gain and signal conditions the clamp interface mentioned in the output clamping section controls the maximum output swing of the postamp and its overload response. when the clamp feature is not used, the output level defaults to approximately 4.5 v p-p differential centered at 2.5 v common mode. when other common-mode levels are set through the vcm pin, the value of r clmp should be selected for graceful overload. a value of 8.3 k or less is recommended for 1.5 v or 3.5 v common-mode levels (7.2 k for hi gain mode). this limits the output swing to just above 2 v p-p differential. optional input overload protection applications in which high transients are applied to the lna input can benefit from the use of clamp diodes. a pair of back- to-back schottky diodes can reduce these transients to manageable levels. figure 88 illustrates how such a diode protection scheme can be connected. 03199-088 20 19 4 3 2 lon vpsl inh comm enbl 0.1f fb r sh c iz r iz c sh 2 3 1 optional schottky overload clamp bas40-04 figure 88. input overload clamping
ad8331/ad8332/ad8334 rev. g | page 33 of 56 when selecting overload protection, the important parameters are forward and reverse voltages and t rr (or rr ). the infineon bas40-04 series shown in figure 88 has a rr of 100 ps and a v f of 310 mv at 1 ma. many variations of these specifications can be found in vendor catalogs. layout, grounding, and bypassing due to their excellent high frequency characteristics, these devices are sensitive to their pcb environments. realizing expected performance requires attention to detail critical to good, high speed, board design. a multilayer board with power and ground planes is recom- mended with blank areas in the signal layers filled with ground plane. be certain that the power and ground pins provided for robust power distribution to the device are connected. decouple the power supply pins with surface-mount capacitors as close as possible to each pin to minimize impedance paths to ground. decouple the lna power pins from the vga supply using ferrite beads. together with the capacitors, ferrite beads eliminate undesired high frequencies without reducing the headroom. use a larger value capacitor for every 10 chips to 20 chips to decouple residual low frequency noise. to minimize voltage drops, use a 5 v regulator for the vga array. several critical lna areas require special care. the lon and lop output traces must be as short as possible before connecting to the coupling capacitors connected to pin vin and pin vip. r iz must be placed near the lon pin as well. resistors must be placed as close as possible to the vga output pins, vol and voh, to mitigate loading effects of connecting traces. values are discussed in the output decoupling section. signal traces must be short and direct to avoid parasitic effects. wherever there are complementary signals, symmetrical layout should be employed to maintain waveform balance. pcb traces should be kept adjacent when running differential signals over a long distance. multiple input matching matching of multiple sources with dissimilar impedances can be accomplished as shown in figure 89 . a relay and low supply voltage analog switch can be used to select between multiple sources and their associated feedback resistors. an adg736 dual spdt switch is shown in this example; however, multiple switches are also available and users are referred to the analog devices selection guide for switches and multiplexers. 03199-090 inh lna 5 ? 200 ? 50? lmd lop adg736 lon 0.1f 18nf 280? 1.13k ? ad8332 5 ? select r iz figure 89. accommodating multiple sources disabling the lna where accessible, connection of the lna enable pin to ground powers down the lna, resulting in a current reduction of about half. in this mode, the lna input and output pins can be left unconnected; however, the power must be connected to all the supply pins for the disabling circuit to function. figure 90 illustrates the connections using ad8331 as an example. 03199-089 15 16 20 17 18 19 8 7 6 5 1 4 3 2 9 13 10 comm vip lop coml lmd lon vpsl inh comm enbv enbl gain 0.1f hilo +5v +5v nc voh vol vout vpos +5v 14 11 12 vcm r clmp nc nc nc vin 0.1f ad8331 mode gain mode vcm hilo vin rclmp figure 90. disabling the lna
ad8331/ad8332/ad8334 rev. g | page 34 of 56 ultrasound tgc application the ad8332 ideally meets the requirements of medical and industrial ultrasound applications. the tgc amplifier is a key subsystem in such applications because it provides the means for echo location of reflected ultrasound energy. figure 91 through figure 93 are schematics of a dual, fully differential system using the ad8332 and the ad9238 12-bit high speed adc with conversion speeds as high as 65 msps. high density quad layout the ad8334 is the ideal solution for applications with limited board space. figure 94 represents four channels routed to and away from this very compact quad vga. note that none of the signal paths crosses and that all four channels are spaced apart to eliminate crosstalk. in this example, all of the components shown are 0402 size; however, the same layout is executable at the expense of slightly more board area. the sketch also assumes that both sides of the printed circuit board are available for components and that the bypass and power supply decoupling circuitry is located on the wiring side of the board.
ad8331/ad8332/ad8334 rev. g | page 35 of 56 03199-091 +5vlna voh1 21 25 vin1 lon1 c78 1nf c58 0.1f 17 ad8332aru v in +a 1 c49 0.1f 2 c80 22pf 3 cfb1 18nf c59 0.1f c41 0.1f c74 1nf 4 7 5 c53 0.1f vps1 26 6 com1 23 8 c51 0.1f 27 inh1 s1 e in1 c60 0.1f c79 22pf l13 120nh fb tp6 28 lmd1 c70 0.1f 14 9 c48 0.1f 10 c83 1nf 11 r3 (r clmp ) c54 0.1f c55 0.1f 12 lmd2 inh2 vps2 lon2 vip2 lop2 com2 vin2 comm vcm2 gain rclmp voh2 vol2 13 jp12 vpsv 15 c45 0.1f c85 1nf vol1 c56 0.1f 16 l8 120nf fb 18 enb +5vga 19 hilo 20 vcm1 c43 0.1f c77 1nf 22 24 vip1 lop1 +5vlna vcm1 rfb1 274? rfb2 274 ? c50 0.1f s3 e in2 l12 120nh fb tp5 cfb2 18nf c68 1nf c69 0.1f r27 100? l11 120nh fb jp8 dc2h l10 120nh fb jp7 dc2l r26 100? +5vga enable hi gain disable lo gain l9 120nh fb r24 100? jp9 jp10 jp17 tp2 gain jp5 in2 jp6 in1 tp7 gnd l17 sat l18 sat l19 sat l20 sat c67 sat c66 sat l1 sat l14 sat l15 sat l16 sat c64 sat c65 sat optional 4-pole low-pass filter jp13 vcm1 +5vga jp10 jp16 r25 100 ? c42 0.1f v in ?a tb1 +5v tb2 gnd c46 1f +5vga l7 120nh fb l6 120nh fb tp4 (black) tp3 (red) + +5vlna +5v v in +b v in ?b optional 4-pole low-pass filter figure 91. schematic, tgc, vga section using an ad8332 and ad9238
ad8331/ad8332/ad8334 rev. g | page 36 of 56 1 2 3 17 62 6 7 11 10 14 15 18 63 19 20 60 21 22 16 4 13 64 12 5 8 9 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 vref vin+_a vin?_a vin?_b vin+_b avdd reft_a refb_a sense reft_b refb_b clk_b dcs dfs pdwn_b oeb_b agnd agnd avdd avdd agnd agnd d5_b d4_b d3_b drgnd d2_b d1_b d0_b dnc dnc drvdd d10_a d11_a 61 59 58 57 56 55 54 53 otr_a u1 a/d converter ad9238 d9_a d8_a d6_a d7_a d5_a d4_a d3_a d2_a d1_a d0_a dnc dnc d4_b d3_b d2_b d1_b d0_b dnc dnc otr_b d11_b d10_b d9_b d8_b d7_b d6_b d5_b 20mhz adclk +3.3vclk adclk +3.3vavdd v in ?_b v in +_b + +3.3vaddig sg-636pce 14 3 2 u5 74vhc04 + + tp9 tp 12 4 312 12 13 10 11 u5 74vhc04 u5 74vhc04 u5 74vhc04 u5 74vhc04 u5 74vhc04 spares 8965 tp 13 jp1 3 2 1 v dd out gnd oe jp4 s2 ext clock + jp11 jp3 jp2 shared ref +3.3vaddig y mux_select shared_ref clk_a pdwn_a avdd otr_a d11_a (msb) drgnd d8_a drvdd d7_a d6_a d5_a d4_a d3_a d2_a d1_a d0_a drvdd d10_a drgnd otr_b d9_a d10_b d9_b d8_b d7_b d6_b d11_b (msb) dnc dnc oeb_a ext int v in +_a v in ?_a n data clk vref c11 10f 6.3v c14 0.1f c23 0.1f c25 1nf r14 4.7k ? r11 100? r10 0 ? r15 0 ? c22 0.1f c21 1nf c86 0.1f c47 10f 6.3v adclk c2 10f 6.3v c18 1nf c17 0.1f c52 10nf c57 10nf c61 18pf c40 0.1f r5 33? r6 33? r4 1.5k ? r12 1.5k ? 1.5k ? 1.5k ? c12 10f 6.3v r9 0 ? r8 33? r7 33? c19 1nf c20 0.1f c63 0.1f c26 0.1f c24 1nf c33 10f 6.3v c38 0.1f c16 0.1f c62 18pf c15 1nf c35 0.1f c36 0.1f c37 0.1f r20 4.7k ? r17 49.9 ? r41 4.7k ? +3.3vclk r19 499? r16 5k? r18 499? + +3.3vaddig 3 2 1 c32 0.1f c39 10f c34 10f 6.3v c44 1f c31 0.1f c30 0.1f c29 0.1f c1 0.1f out v r1 adp3339akc-3.3 l2 120nh fb l3 120nh fb l4 120nh fb l5 120nh fb in out gnd 31 2 tab + +5v 03199-092 c13 1nf u6 figure 92. converter schematic, tgc using an ad8332 and ad9238
ad8331/ad8332/ad8334 rev. g | page 37 of 56 19 1 d10_a d11_a 24 39 vcc gnd y1 a1 g1 1 2 3 6 7 10 4 5 8 9 17 11 14 15 18 19 20 + 16 13 12 g2 a8 a7 a6 a5 a4 a3 a2 y8 y7 y6 y5 y4 y3 y2 vcc gnd y1 a1 g1 1 2 3 6 7 10 4 5 8 9 17 11 14 15 18 19 20 + 16 13 12 g2 a8 a7 a6 a5 a4 a3 a2 y8 y7 y6 y5 y4 y3 y2 vcc gnd y1 a1 g1 1 2 3 6 7 10 4 5 8 9 17 11 14 15 18 19 20 ++ 16 13 12 g2 a8 a7 a6 a5 a4 a3 a2 y8 y7 y6 y5 y4 y3 y2 vcc gnd y1 a1 g1 1 2 3 6 7 10 4 5 8 9 17 11 14 15 18 19 20 + 16 13 12 g2 a8 a7 a6 a5 a4 a3 a2 y8 y7 y6 y5 y4 y3 y2 2 3 6 7 10 4 5 8 9 17 11 14 15 18 20 16 13 12 37 21 26 25 30 22 23 28 27 35 29 34 33 38 40 36 31 32 r39 22? dataclka otr_a d9_a d8_a d6_a d7_a d5_a d4_a d3_a d2_a d1_a d0_a dnc dnc otr_b d11_b d10_b d9_b d8_b d7_b d6_b d5_b d4_b d3_b d2_b d1_b d0_b dnc dnc +3.3vdvdd +3.3vdvdd +3.3vdvdd dataclk u3 74vhc541 u10 74vhc541 u7 74vhc541 u2 74vhc541 sam080upm 76 61 79 58 41 80 77 73 72 78 75 74 71 63 69 68 65 64 62 66 67 70 43 59 56 55 52 60 57 54 53 45 51 48 47 44 42 46 49 50 sam080upm rp 9 8 7 6 5 8 7 6 5 1 4 3 2 1 4 3 2 8 7 6 5 8 7 6 5 1 4 3 2 1 4 3 2 8 7 6 5 8 7 6 5 7 6 5 8 7 6 5 4 3 2 1 4 3 2 rp 11 rp 12 rp 13 rp 14 1 4 3 2 1 4 3 2 18 rp 15 rp 16 r40 22? 18 7 6 5 4 3 2 rp 1 18 7 6 5 4 3 2 rp2 18 7 6 5 4 3 2 rp 3 18 7 6 5 4 3 2 rp 4 18 7 6 5 4 3 2 rp 5 1 8 7 6 5 4 3 2 rp 6 18 7 6 5 4 3 2 rp 7 18 7 6 5 4 3 2 rp 8 22 4 22 4 rp 10 22 4 22 4 22 4 22 4 22 4 22 4 header up male no shroud header up male no shroud c3 0.1f c28 10f 6.3v c8 0.1f c10 0.1f c76 10f 6.3v c7 0.1f c9 0.1f c27 10f 6.3v c4 0.1f c5 0.1f c6 0.1f c75 10f 6.3v +3.3vdvdd 22 4 22 4 22 4 22 4 22 4 22 4 22 4 22 4 03199-093 figure 93. interface schematic, tgc using an ad8332 and ad9238
ad8331/ad8332/ad8334 rev. g | page 38 of 56 28 25 26 27 17 18 19 21 22 23 24 15 16 8 7 6 5 1 4 3 2 14 13 9 12 11 10 50 49 56 55 51 54 53 52 35 36 37 38 42 39 40 41 34 33 29 30 31 32 48 47 43 46 45 44 58 57 59 62 61 60 63 64 20 power supply decoupling located on wiring side ad8334 inh2 lmd2 nc lon2 lop2 vip2 vin2 vps2 vps3 vin3 vip3 lop3 lon3 nc lmd3 inh3 nc com12 voh1 vol1 vps12 vol2 voh2 com12 mode com34 voh3 vol3 vps34 vol4 voh4 com34 com3 com4 inh4 lmd4 nc lon4 lop4 vip4 vin4 vps4 gain34 clmp34 hilo vcm4 vcm3 nc com2 com1 inh1 lmd1 nc lon1 lop1 vip1 vin1 vps1 gain12 clmp12 en12 en34 vcm1 vcm2 ch1 lna input ch2 lna input ch3 lna input ch4 lna input ch1 differential output ch2 differential output ch3 differential output ch4 differential output 03199-094 nc = no connect figure 94. compact signal path and board layout for the ad8334
ad8331/ad8332/ad8334 rev. g | page 39 of 56 ad8331 evaluation board 03199-115 general description the ad8331 evaluation board is a platform for testing and evaluating the ad8331 variable gain amplifier (vga). the board is provided completely assembled and tested; the user simply connects an input signal, vgain sources, and a 5 v power supply. the ad8331-evalz is lead free and rohs compliant. figure 95 is a photograph of the board. user-supplied optional components as shown in the schematic in figure 96 , the board provides for optional components. the components shown in black are for typical operation, and the components shown in gray are installed at the users discretion. as shipped, the lna input impedance of the ad8331-evalz is configured for 50 to accommodate most signal generators and network analyzers. input impedances up to 6 k are realized by changing the values of rfb and csh. refer to the theory of operation section for details on this circuit feature. see table 9 for typical values of input impedance and corresponding components. figure 95. photograph of ad8331-evalz measurement setup the basic board connection for measuring bandwidth is shown in figure 97 . a 5 v, 100 ma minimum power supply and a low noise, voltage reference supply for gain are required. table 10 lists jumpers, and figure 97 shows their functions and positions. table 9. lna external component values for common source impedances the preferred signal detection method is a differential probe connected to vo, as shown in figure 97 . single-ended loads can be connected using the board edge sma connector, voh. be sure to take into account the 25.8 db attenuation incurred when using the board in this manner. for connection to an adc, the 270 series resistors can be replaced with 0 or other appropriate values. r in () rfb (, nearest 1% value) csh (pf) 50 274 22 75 412 12 100 562 8 200 1.13 k 1.2 500 3.01 k none 6 k none table 10. jumper functions switch function lna_en enables the lna when in the top position vga_en enables the vga when in the top position w5, w6 connects the ad8331 outputs to the sma connectors gn_slope left = gain increases with v gain right = gain decreases with v gain gn_hi_lo left = high gain right = lo gain the board is designed for 0603 size, surface-mount components. back-to-back diodes can be instal led at location d3 if desired. to evaluate the lna as a standalone amplifier, install optional sma connectors lon and lop and capacitors c1 and c2; typical values are 0.1 f or smaller. at r4 and r8, 0 resistors are installed unless capacitive loads larger than 10 pf are connected to the sma connectors lon and lop (such as coaxial cables). in that event, small value resistors (68 to 100 ) must be installed at r4 and r8 to preserve the stability of the amplifier. board layout the evaluation board circuitry uses four conductor layers. the two inner layers are grounded, and all interconnecting circuitry is located on the outer layers. figure 99 to figure 102 illustrate the copper patterns. a resistor can be inserted at rclmp if output clamping is desired. refer to tabl e 8 for appropriate values.
ad8331/ad8332/ad8334 rev. g | page 40 of 56 ad8331 evaluation board schematics 03199-116 mode vip gain vin lop coml lmd2 lon vps inh voh vol comm comm enbv vpos clmp hilo vcm c2 c1 r4 r8 lna2 +5v lo +5 v +5v gn_slope w5 w6 gnd gnd2 gnd1 dut ad8331arq gnd4 gnd3 + 1 2 3 4 5 6 7 8 9 10 20 18 17 16 15 14 13 12 11 c3 10f 10v l1 120nh fb c inh 0.1f clmd 0.1f l2 120nh fb csh 22pf c6 0.1f lon lop c16 0.1f c14 0.1f gain c34 1nf components in gray are optional and user supplied. l4 120nh fb vo voh t1 1:1 r16 237? r20 237? c24 0.1f c26 0.1f r43 100 ? r44 100 ? l3 120nh fb c17 0.1f c32 0.1f c18 0.1f enb lna_en 19 gn_hi_lo +5v +5v vga_en input clamp diodes 3d1 bat64-04 cfb 0.018f rfb 274f rclmp vcm l5 120nh fb probe rclmp enable disable enable disable hi lo down up figure 96. schematic of the ad8331 evaluation board
ad8331/ad8332/ad8334 rev. g | page 41 of 56 gnd gnd dp8200 precision voltage reference (for vgain) 4395a analyzer 1103 tekprobe power supply e3631a power supply 03199-117 +5v differential probe to vo pins insert jumpers w5 and w6 to use output transformer and voh sma figure 97. ad8331 typical board test connections
ad8331/ad8332/ad8334 rev. g | page 42 of 56 ad8331 evaluation board pcb layers 0 3199-118 figure 98. ad8331-evalz assembly 03199-199 figure 99. primary side copper 03199-200 figure 100. secondary side copper 03199-201 figure 101. internal layer ground 03199-202 figure 102. power plane 03199-119 figure 103. top silkscreen
ad8331/ad8332/ad8334 rev. g | page 43 of 56 ad8332 evaluation board general description the ad8332-evalz is a platform for the testing and evaluation of the ad8332 variable gain amplifier (vga). the board is shipped assembled and tested, and users need only connect the signal and vgain sources to a single 5 v power supply. figure 104 is a photograph of the component side of the board, and figure 105 shows the schematic. the ad8332-evalz is lead free and rohs compliant. 03199-131 figure 104.photograph of the ad8332-evalz user-supplied optional components the board is built and tested using the components shown in black in figure 105 . provisions are made for optional components (shown in gray) that can be installed for testing at user discretion. the default lna input impedance is 50 to match various signal generators and network analyzers. input impedances up to 6 k are realized by changing the values of rfbx and cshx. for reference, tabl e 11 lists the common input impedance values and corresponding adjustments. the board is designed for 0603 size, surface-mount components. table 11. lna external component values for common source impedances r in () rfb1, rfb2 ( std 1% value) csh1, csh2 (pf) 50 274 22 75 412 12 100 562 8 200 1.13 k 1.2 500 3.01 k none 6 k none sma connectors, s2, s3, s6, and s7, are provided for access to the lna outputs or the vga inputs. if the lna is used alone, 0.1 f coupling capacitors can be installed at the c5, c9, c23, and c24 locations. resistors of 68 to 100 may be required if the load capacitances, as seen by the lna outputs, are larger than approximately 10 pf. a resistor can be inserted at rclmp if output clamping is desired. the peak-to-peak clamping level is adjusted by installing one of the standard 1% resistor values listed in table 8 . a high frequency differential probe connected to the 2-pin headers, vox, is the preferred method to observe a waveform at the vga output. a typical setup is shown in figure 106 . single-ended loads can be connected directly via the board edge sma connectors. note that the ad8332 output amplifier is buffered with 237 resistors; therefore, be sure to compensate for attenuation if low impedances are connected to the output smas. measurement setup the basic board connections for measuring bandwidth are shown in figure 106 . a 5 v, 100 ma (minimum) power supply is required, and a low noise voltage reference supply is required for vgain. board layout the evaluation board circuitry uses four conductor layers. the two inner layers are power and ground planes, and all interconnecting circuitry is located on the outer layers. figure 108 to figure 111 illustrate the copper patterns.
ad8331/ad8332/ad8334 rev. g | page 44 of 56 evaluation board schematics vcm2 rclmp comm vol2 voh2 vip2 gain vin2 lop2 com2 lmd2 lon2 vps2 inh2 com1 lop1 lmd1 lon1 vps1 inh1 voh1 enb vip1 vcm1 vin1 vpsv vol1 hilo +5v lo w9 c24 c23 r9 r11 r12 r10 c5 c9 +5vlna lna2 +5v w8 rclmp +5 v w4 +5v hi +5vlna w5 w12 w13 w10 w11 gnd gnd4 gnd3 gnd2 gnd1 ad8332aruz + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 28 27 26 25 24 23 22 21 20 19 18 17 16 c25 10f l1 120nh fb c4 0.1f csh2 22pf c2 0.1f l8 120nh fb cal2 cfb2 18nf c6 0.1f rfb2 274 ? s6 lon2 s7 lop2 c16 0.1f c14 0.1f c10 0.1f vcm2 gain c8 1nf tp3 clamp c20 0.1f l3 120nh fb r7 100 ? r8 100 ? l4 120nh fb voh2 t2 1:1 r13 237? c11 0.1f w6 vo2 r14 237? c12 0.1f components in gray are optional and user supplied. c22 0.1f l7 120nh fb l5 120nh fb w7 vo1 voh1 t1 1:1 r15 237 ? r16 237 ? c19 0.1f c18 0.1f r6 100? r5 100? l6 120nh fb enable disable c17 0.1f vcm1 c15 0.1f c13 0.1f s3 lop1 s2 lon1 rfb1 274 ? c7 0.1f cal1 cfb1 18nf lna1 l2 120nh fb c3 0.1f csh1 22pf c1 0.1f 0 3199-096 +5v figure 105. schematic of the ad8332 evaluation board
ad8331/ad8332/ad8334 rev. g | page 45 of 56 vgain supply network analyzer 1103 tekprobe power supply differential probe 03199-120 figure 106. ad8332 typical board test connections
ad8331/ad8332/ad8334 rev. g | page 46 of 56 ad8332 evaluation board pcb layers 03199-121 figure 107. ad8332-evalz assembly 03199-099 figure 108. prim ary side copper 03199-100 figure 109. secondary side copper 03199-101 figure 110. ground plane 0 3199-102 figure 111. power plane 03199-103 figure 112. component side silkscreen
ad8331/ad8332/ad8334 rev. g | page 47 of 56 ad8334 evaluation board general description the ad8334-evalz is a platform for the testing and evaluation of the ad8334 variable gain amplifier (vga). the board is shipped assembled and tested, and users need only connect the signal and vgain sources and a single 5 v power supply. figure 113 is a photograph of the board. the ad8334-evalz is lead free and rohs compliant. 03199-122 figure 113. ad8334-evalz top view
ad8331/ad8332/ad8334 rev. g | page 48 of 56 configuring the input impedance the board is built and tested using the components shown in black in figure 115 . provisions are made for optional components (shown in gray) that can be installed at user discretion. as shipped, the input impedances of the low noise amplifiers (lnas) are configured for 50 to match the output impedances of most signal generators and network analyzers. input impedances up to 6 k can be realized by changing the values of the feedback resistors, r fb1 , r fb2, r fb3 , r fb4 , and shunt capacitors, c6, c8, c10, and c12. for reference, table 12 lists standard values of 1% resistors for some typical values of input impedance. of course, if the user has determined that the source impedance falls between these values, the feedback resistor value can be calculated accordingly. note that the board is designed to accept standard surface-mount, size 0603 components. table 12. lna external component values for common source impedances r in () rfb1, rfb2, rfb3, rfb4 (, 1%) c6, c8, c10, c12 (pf) 50 274 22 75 412 12 100 562 8 200 1.13 k 1.2 500 3.01 k no capacitor 6 k no resistor no capacitor driving the vga from an exte rnal source or using the lna to drive an external load appropriate components can be installed if the user wants to drive the vga directly from an external source or to evaluate the lna output. if the lna is used to drive off-board loads or cables, small value series resistors (47 to 100 ) are recommended for lna decoupling. these can be installed in the r10, r11, r14, r15, r18, r19, r22, and r23 spaces. provisions are made for surface-mount sma connectors that can be used for driving from either direction. if the lna is not used, it is recommended that the capacitors, c16, c17, c21, c22, c26, c27, c31, and c32, be carefully removed to avoid driving the outputs of the lnas. using the clamp circuit the board is shipped with no resistors installed in the spaces provided for clamp-circuit operation. note that each pair of channels shares a clamp resistor. if the output clamping is desired, the resistors are installed in r49 and r50. the peak-to- peak clamping level is application dependent. viewing signals the preferred signal detector is a high impedance differential probe, such as the tektronix p6247, 1 ghz differential probe, connected to the 2-pin headers (vo1, vo2, vo3, or vo4), as shown in figure 116 . the low capacitance of this probe has the least effect on the performance of the device of any detection method tried. the probe can also be used for monitoring input signals at in1, in2, in3, or in4. it can be used for probing other circuit nodes; however, be aware that the 200 k input impedance can affect certain circuits. differential-to-single-ended transformers are provided for single-ended output connections. note that series resistors are provided to protect against accidental output overload should a 50 load be connected to the connector. of course, the effect of these resistors is to limit the bandwidth. if the load connected to the sma is >500 , the 237 series resistors, rx1, rx2, rx3, rx4, rx5, rx6, rx7, and rx8, can be replaced with 0 values. 03199-123 figure 114. ad8334-evalz assembly measurement setup the basic board connections for measuring bandwidth are shown in figure 116 . a 5 v, 200 ma (minimum) power supply is required, and a low noise voltage reference supply is required for vgain. board layout the evaluation board circuitry uses four conductor layers. the two inner layers are ground, and all interconnecting circuitry is located on the outer layers. figure 117 to figure 120 illustrate the copper patterns.
ad8331/ad8332/ad8334 rev. g | page 49 of 56 evaluation board schematics com34 vol2 voh2 voh1 vol1 com12 vps 34 comm34 lm d 2 lo n2 inh2 voh3 voh4 vol3 vol4 vp sv2 com12 25 26 27 17 18 19 21 22 23 24 15 16 8 7 6 5 1 4 3 2 14 13 9 12 11 10 50 4 9 56 55 51 54 53 52 35 36 37 38 42 39 40 41 34 33 30 31 32 48 47 43 46 45 44 58 57 59 62 61 60 vps 2 vip2 vin2 lo p2 vps 3 vip3 vin3 lm d 3 lo n3 inh3 lo p3 nc com3 com4 lmd4 in h4 vcm4 vcm3 hilo clmp34 lon4 vps4 vip4 vin4 lop4 nc nc 3 nc 3 mode lmd1 lon1 vps1 in h1 com1 63 lop1 vip1 vin1 en12 vcm1 com2 gain12 vcm2 clmp12 en34 nc 64 20 c7 0.1 f inh2 in2 c8 22 pf l7 120 nh cf b 2 18 nf c2 0.1 f lo2 1 r15 1 0 ? r14 1 0 ? rfb2 27 4 ? c69 0.1 f l2 12 0 nh c71 0.1 f l3 12 0 nh c3 0.1f c9 0.1 f inh3 c10 22 pf l6 12 0 nh cfb3 18 nf lo3 1 r18 1 r19 1 rfb3 274 ? c26 0.1 f c27 0.1 f c21 0.1 f c22 0.1 f in3 cfb4 18 nf c11 0.1 f l8 12 0 nh c12 22 pf c4 0.1 f rfb4 274 ? c32 0.1 f c31 0.1 f lo4 1 r23 1 r22 1 +5v c1 3 0.1 f l4 12 0 nh c62 0.1 f c6 4 0.1 f r50 4.02k ? c55 0.1 f +5v vo2 l1 3 120 nh l1 1 120 nh rx4 100 ? rx3 100 ? vo 1 l10 12 0 nh l9 12 0 nh rx2 100 ? rx1 100 ? c75 0.1 f l12 120 nh fb +5v vo 3 l14 12 0 nh l15 12 0 nh rx5 100 ? rx6 100 ? vo 4 l16 12 0 nh l17 12 0 nh rx7 100 ? rx8 10 0 ? l34 120 nh +5 v c77 0.1 f +5v cfb1 18 nf c5 0.1 f inh1 l5 12 0 nh c6 22 pf c1 0.1 f rfb1 274 ? c17 0.1 f c16 0.1 f lo1 1 r11 1 r1 0 1 +5 v l1 12 0 nh c67 0.1 f clmp12 r49 4. 02k ? c53 0.1 f c8 2 1nf c59 0.1 f c57 0.1 f in4 in1 hi lo slope d u e d e d c8 0 1nf +5 v +5 v 28 29 gain 34 gain34 +5 v en34 en12 hil o +5v + c14 10 f gnd1 gnd2 gnd3 gnd6 gnd5 gnd4 icr4 cr 4 12 3 icr3 cr3 12 3 icr2 cr2 1 2 3 icr1 cr1 12 3 clmp34 notes 1 components in gray are optional user supplied. 2 nc = no connect. 03199-124 ad8334 nc figure 115. ad8334-evalz schematic
ad8331/ad8332/ad8334 rev. g | page 50 of 56 03199-125 network analyzer precision voltage reference (for vgain) gnd gnd gain control voltage signal input differential probe power supply +5v probe power supply figure 116. ad8334 typical board test connections (one channel shown)
ad8331/ad8332/ad8334 rev. g | page 51 of 56 ad8334 evaluation board pcb layers 03199-126 figure 117. ad8334-evalz primary side copper 0 3199-127 figure 118. ad8334-evalz secondary side copper 0 3199-128 figure 119. ad8334-evalz inner layer 1copper 03199-129 figure 120. ad8334-evalz inner layer 2 copper
ad8331/ad8332/ad8334 rev. g | page 52 of 56 03199-130 figure 121. ad8334-evalz component side silkscreen
ad8331/ad8332/ad8334 rev. g | page 53 of 56 outline dimensions compliant to jedec standards mo-153-ae 28 15 14 1 8 0 seating plane c oplanarit y 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 figure 122. 28-lead thin shrink small outline package (tssop) (ru-28) dimensions shown in millimeters compliant to jedec standards mo-137-ad 081908-a controlling dimensions are in inches; millimeters dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 20 11 10 1 seating plane 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0.025 (0.64) bsc 0.041 (1.04) ref 0.010 (0.25) 0.006 (0.15) 0.050 (1.27) 0.016 (0.41) 0.020 (0.51) 0.010 (0.25) 8 0 coplanarity 0.004 (0.10) 0.065 (1.65) 0.049 (1.25) 0.069 (1.75) 0.053 (1.35) 0.345 (8.76) 0.341 (8.66) 0.337 (8.55) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) figure 123. 20-lead shrink small outline package (qsop) (rq-20) dimensions shown in inches and (millimeters
ad8331/ad8332/ad8334 rev. g | page 54 of 56 compliant to jedec standards mo-220-vhhd-2 011708-a 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indi c ator top view 5.00 bsc sq 4.75 bsc sq 3.25 3.10 sq 2.95 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 124. 32-lead lead frame chip scale package (lfcsp_vq) 5 mm 5 mm body, very thin quad (cp-32-2) dimensions shown in millimeters pin 1 indicator top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max * 4.85 4.70 sq 4.55 exposed pad (bottom view) * compliant to jedec standards mo-220-vmmd-4 except for exposed pad dimension 082908-b seating plane pin 1 indicator 0.30 0.25 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 125. 64-lead lead frame chip scale package (lfcsp_vq) 9 mm 9 mm body, very thin quad (cp-64-1) dimensions shown in millimeters
ad8331/ad8332/ad8334 rev. g | page 55 of 56 ordering guide model 1 temperature range package description package option ad8331arq C40c to +85c 20-lead shrink small outline package (qsop) rq-20 ad8331arq-reel C40c to +85c 20-lead shrink small outline package (qsop) rq-20 ad8331arq-reel7 C40c to +85c 20-lead shrink small outline package (qsop) rq-20 ad8331arqz C40c to +85c 20-lead shrink small outline package (qsop) rq-20 AD8331ARQZ-RL C40c to +85c 20-lead shrink small outline package (qsop) rq-20 ad8331arqz-r7 C40c to +85c 20-lead shrink small outline package (qsop) rq-20 ad8331-evalz evaluation board with ad8331arq ad8332acp-r2 C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-2 ad8332acp-reel C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-2 ad8332acp-reel7 C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-2 ad8332acpz-r2 C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-2 ad8332acpz-r7 C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-2 ad8332acpz-rl C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-2 ad8332aru C40c to +85c 28-lead thin shrink small outline package (tssop) ru-28 ad8332aru-reel C40c to +85c 28-lead thin shrink small outline package (tssop) ru-28 ad8332aru-reel7 C40c to +85c 28-lead thin shrink small outline package (tssop) ru-28 ad8332aruz C40c to +85c 28-lead thin shrink small outline package (tssop) ru-28 ad8332aruz-r7 C40c to +85c 28-lead thin shrink small outline package (tssop) ru-28 ad8332aruz-rl C40c to +85c 28-lead thin shrink small outline package (tssop) ru-28 ad8332-evalz evaluation board with ad8332aru ad8334acpz C40c to +85c 64-lead lead frame chip scale package (lfcsp_vq) cp-64-1 ad8334acpz-reel C40c to +85c 64-lead lead frame chip scale package (lfcsp_vq) cp-64-1 ad8334acpz-reel7 C40c to +85c 64-lead lead frame chip scale package (lfcsp_vq) cp-64-1 ad8334-evalz evaluation board with ad8334acp 1 z = rohs compliant part.
ad8331/ad8332/ad8334 rev. g | page 56 of 56 notes ?2003C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d03199-0-10/10(g )

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