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cmos 16-bit single chip microcomputer description the CXP974F096 is a cmos 16-bit microcomputer integrating on a single chip an a/d converter, serial interface, i 2 c bus interface, timer, pwm output circuit, programmable pattern generator, remote control receive circuit, parallel interface, flash rom interface, and as well as basic configurations like a 16-bit cpu, flash eeprom, ram, and i/o port. this lsi also provides the sleep/stop functions that enable lower power consumption. features an efficient instruction set as a controller ?direct addressing, numerous abbreviated forms, multiplication and division instructions instruction sets for c language and rtos ?highly quadratic instruction system, general- purpose register of 16-bit 8-pin 16-bank configuration minimum instruction cycle 58.8ns at 34mhz operation (3.0 to 3.6v) 66.7ns at 30mhz operation (2.7 to 3.6v) incorporated flash eeprom capacity 384k bytes incorporated ram capacity 23.5k bytes peripheral functions ?a/d converter 8-bit 12-analog input, successive approximation system, 3-stage fifo (conversion time: 1.55s at 40mhz) ?serial interface asynchronous serial interface (uart) 128-byte buffer ram, 3 channels ?i 2 c bus interface 64-byte buffer ram (supports master/slave and automatic transfer mode) ?timers 8-bit timer/counter, 2 channels (with timing output) 16-bit capture timer/counter (with timing output) 16-bit timer, 4 channels, watchdog timer ?pwm output circuit 14-bit pwm, 4 channels (2-channel of binary output switch function by ppg) ?programmable pattern generator 16-bit output, 64-byte buffer ram, 1 channel ?remote control receive circuit 8-bit pulse measurement counter, 10-stage fifo ?parallel interface external register interface (8-bit parallel bus), 4-chip select interruption 33 factors, 33 vectors, multi-interruption and priority selection possible standby mode sleep/stop package 100-pin plastic qfp 100-pin plastic lqfp piggy/evaluation chip cxp971000 mask rom cxp974096 structure silicon gate cmos ic ?1 e00z18-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP974F096 100 pin qfp (plastic) 100 pin lqfp (plastic) perchase of sony's i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips.
?2 CXP974F096 block diagram pa0 to pa7 pb0 to pb7 pc0 to pc7 pd0 to pd7 pe0 to pe7 pf0 to pf5 pf6, pf7 ph0, ph1, ph6, ph7 pi0 to pi7 pj0 to pj7 scs0 so0 si0 sck0 si1 scs1 sck1 so1 scs2 so2 si2 sck2 t1 pwm0 ec0 rmc port a 16-bit capture timer/counter (ch2) buffer ram i 2 c bus interface unit buffer ram serial interface unit (ch2) buffer ram serial interface unit (ch1) buffer ram serial interface unit (ch0) 8 8 20 port b 8 port c 8 port d 8 pg4 to pg7 4 ph2 to ph5 4 port e 8 port f 6 2 pg0 to pg3 4 4 port g pk0 to pk4 5 pk5 to pk6 2 port k port h port i port j 8 8 spc970 cpu core clock generator/ system controller flash eeprom 384k bytes ram 23.5k bytes pwm1 pwm2 pwm3 t2 prescaler/ time-base timer ec2 cint scl sda txd rxd int0 to int7 ks0 to ks19 nmi rst extal v pp xtal v dd v ss 16 a/d converter 12 8 remocon fifo 2ch 14-bit pwm (ppg) 2ch 14-bit pwm 4ch 16-bit timer uart interrupt controller an0 to an11 ppo00 to ppo15 16 d0 to d7 a0 to a15 adten adtrg xcs3 xcs2 xcs1 xcs0 xrd xwr av ss av ref av dd 8-bit timer/counter (ch0) 8-bit timer (ch1) 2 4 2 3 2 programable patteern generator ext. registers interface buffer ram fifo watchdog timer
3 CXP974F096 pin assignment 1 (top view) 100-pin qfp package 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 pe7/int7/cint pf0/ec0 pf1/ec2 pf2/scs1/nmi pf3/si1 pf4/so1 pf5/sck1 pf6/t1 pf7/t2 rst v ss xtal extal v dd pg0/pwm0 pg1/pwm1 pg2/pwm2 pg3/pwm3 pg4/scs0 pg5/si0 ph0/sda pk6/teta pk5/tetb pk4/adtrg pk3/adten pk2 pk1 pk0 av dd av ref av ss pj7/an11/ks11 pj6/an10/ks10 pj5/an9/ks9 pj4/an8/ks8 pj3/an7/ks7 pj2/an6/ks6 pj1/an5/ks5 pj0/an4/ks4 pi7/an3/ks3 pi6/an2/ks2 pi5/an1/ks1 pi4/an0/ks0 vss pi3/sck2 51 52 53 54 55 56 pi2/so2 pi1/si2 pi0/scs2 pg7/sck0 pg6/so0 pb2/ppo02/a10 pb3/ppo03/a11 pb4/ppo04/a12 pb5/ppo05/a13 pb6/ppo06/a14 pb7/ppo07/a15 pc0/ppo08 pc1/ppo09 pc2/ppo10 pc3/ppo11 pc4/ppo12/xcs3 pc5/ppo13/xcs2 pc6/ppo14/xcs1 pc7/ppo15/xcs0 v ss pd0/d0/ks12 pd1/d1/ks13 pd2/d2/ks14 pd3/d3/ks15 pd4/d4/ks16 pd5/d5/ks17 pd6/d6/ks18 pd7/d7/ks19 pe0/int0 25 26 27 28 29 pe1/int1 pe2/int2 pe3/int3 pe4/int4 pe5/int5 30 pe6/int6 pb1/ppo01/a9 pb0/ppo00/a8 pa7/a7 pa6/a6 pa5/a5 pa4/a4 pa3/a3 pa2/a2 pa1/a1 pa0/a0 v ss v dd v pp ph7/xrd ph6/xwr ph5/tetc ph4/rmc ph3/txd ph2/rxd ph1/scl 100 note) 1. v pp (pin 88) must be connected to nc for mask rom. 2. vss and avss (pins 15, 41, 57, 70 and 90) must be connected to gnd. 3. v dd and av dd (pins 44, 72 and 89) must be connected to v dd .
4 CXP974F096 pin assignment 2 (top view) 100-pin lqfp package 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 pe7/int7/cint pf0/ec0 pf1/ec2 pf2/scs1/nmi pf3/si1 pf4/so1 pf5/sck1 pf6/t1 pf7/t2 rst v ss xtal extal v dd pg0/pwm0 pg1/pwm1 pg2/pwm2 pg3/pwm3 pg4/scs0 pg5/si0 ph0/sda pk6/teta pk5/tetb pk4/adtrg pk3/adten pk2 pk1 pk0 av dd av ref av ss pj7/an11/ks11 pj6/an10/ks10 pj5/an9/ks9 pj4/an8/ks8 pj3/an7/ks7 pj2/an6/ks6 pj1/an5/ks5 pj0/an4/ks4 pi7/an3/ks3 pi6/an2/ks2 pi5/an1/ks1 pi4/an0/ks0 vss pi3/sck2 51 52 53 54 55 56 pi2/so2 pi1/si2 pi0/scs2 pb4/ppo04/a12 pb5/ppo05/a13 pb6/ppo06/a14 pb7/ppo07/a15 pc0/ppo08 pc1/ppo09 pc2/ppo10 pc3/ppo11 pc4/ppo12/xcs3 pc5/ppo13/xcs2 pc6/ppo14/xcs1 pc7/ppo15/xcs0 v ss pd0/d0/ks12 pd1/d1/ks13 pd2/d2/ks14 pd3/d3/ks15 pd4/d4/ks16 pd5/d5/ks17 pd6/d6/ks18 pd7/d7/ks19 pe0/int0 25 26 27 28 29 pe1/int1 pe2/int2 pe3/int3 30 pe4/int4 pe5/int5 pe6/int6 pb1/ppo01/a9 pb2/ppo02/a10 pb3/ppo03/a11 pb0/ppo00/a8 pa7/a7 pa6/a6 pa5/a5 pa4/a4 pa3/a3 pa2/a2 pa1/a1 pa0/a0 v ss v dd v pp ph7/xrd ph6/xwr ph5/tetc ph4/rmc ph3/txd ph2/rxd ph1/scl 100 pg7/sck0 pg6/so0 note) 1. v pp (pin 86) must be connected to nc for mask rom. 2. vss and avss (pins 13, 39, 55, 68 and 88) must be connected to gnd. 3. v dd and av dd (pins 42, 70 and 87) must be connected to v dd .
5 CXP974F096 pin functions symbol i/o functions pa0/a0 to pa7/a7 pb0/ppo00/ a8 to pb7/ppo07/ a15 pc0/ppo08 to pc3/ppo11 pc4/ppo12/ xcs3 to pc7/ppo15/ xcs0 pd0/d0/ ks12 to pd7/d7/ ks19 pe0/int0 to pe6/int6 pe7/int7/ cint pf0/ec0 pf1/ec2 pf2/scs1/ nmi pf3/si1 pf4/so1 pf5/sck1 pf6/t1 pf7/t2 pg0/pwm0 to pg1/pwm1 pg2/pwm2 pg3/pwm3 pg4/scs0 pg5/si0 pg6/so0 pg7/sck0 output / output output / output / output i/o / output i/o / output / output i/o / i/o / input i/o / input i/o / input / input input / input input / input / input input / input input / output input / i/o output / output output / output output / output output / output i/o / input i/o / input i/o / output i/o / i/o (port a) 8-bit output port. (8 pins) (port b) 8-bit output port. ppo value and or output. (8 pins) (port c) 8-bit i/o port. i/o can be specified in 1-bit units. ppo value and or output. (8 pins) (port d) 8-bit i/o port. i/o can be specified in 1-bit units. (8 pins) (port e) 8-bit i/o port. i/o can be specified in 1-bit units. (8 pins) (port f) 8-bit port. lower 6 bits are for input; upper 2 bits are for output. (8 pins) (port g) 8-bit port. lower 4 bits are for output; upper 4 bits are for i/o. upper 4 bits can be specified in 1-bit units. (8 pins) external register interface address bus port output data value and or output. (8 pins) programmable pattern generator outputs. (16 pins) external register interface data bus. (8 pins) external interrupt inputs. (8 pins) external event inputs for 8-bit timer/counter. (2 pins) serial chip select (ch1) input. serial data (ch1) input. serial data (ch1) output. serial clock (ch1) i/o. 8-bit timer/counter output. 16-bit capture timer/counter timing output. 14-bit pwm output with output value switch control by programmable pattern generator. (2 pins) 14-bit pwm output. (2 pins) serial chip select (ch0) input. serial data (ch0) input. serial data (ch0) output. serial clock (ch0) i/o. external register interface address bus. address width can be extended in 1-bit units. (8 pins) external register interface chip select signal. chip select signal output function can be selected in 1-bit units. (4 pins) external capture input for 16-bit capture timer/counter. standby release input function can be specified in 1-bit units. (8 pins) non-maskable external interrupt input.
6 CXP974F096 symbol i/o functions ph0/sda ph1/scl ph2/rxd ph3/txd ph4/rmc ph5/tetc ph6/xwr ph7/xrd pi0/scs2 pi1/si2 pi2/so2 pi3/sck2 pi4/an0/ ks0 to pi7/an3/ ks3 pj0/an4/ ks4 to pj7/an11/ ks11 pk0 to pk2 pk3/adten pk4/adtrg pk5/tetb pk6/teta extal xtal rst av dd av ref avss v pp v dd vss output / i/o output / i/o i/o / input i/o / output i/o / input i/o / input output / output output / output i/o / input i/o / input i/o / output i/o / i/o i/o / input / input i/o / input / input i/o i/o / input i/o / input output / input output / input input input input (port h) 8-bit port. lower 2 bits are for large current n-ch open drain outputs; medium 4 bits are for i/o; upper 2 bits are for output. medium 4 bits can be specified in 1-bit units. (8 pins) (port i) 8-bit i/o port. i/o can be specified in 1-bit units. (8 pins) (port j) 8-bit i/o port. i/o can be specified in 1-bit units. (8 pins) (port k) 7-bit port. lower 5 bits are for i/o; upper 2 bits are for output. lower 5 bits can be specified in 1-bit units. (7 pins) connects a crystal for main clock oscillation. (when the clock is supplied externally, input it to extal and input an opposite phase clock to xtal.) system reset. active at "l" level. positive power supply for a/d converter. (must be the same voltage with v dd .) reference voltage input for a/d converter. (must be the same voltage with v dd .) gnd for a/d converter. positive power supply for flash eeprom rewrite. positive power supply. (connect both v dd pins to positive power supply.) gnd (connect all four vss pins to gnd.) i 2 c bus interface data i/o. i 2 c bus interface clock i/o. uart reception data input. (common with data reception during on-board rewrite boot mode) uart transmission data output. (common with data transmission during on-board rewrite boot mode) remote control signal input. on-board rewrite boot mode setting. (total 3 pins) external register interface write signal. external register interface read signal. serial chip select (ch2) input. serial data (ch2) input. serial data (ch2) output. serial clock (ch2) i/o. analog input for a/d converter. (12 pins) a/d converter operation enable input by external trigger. external trigger input for a/d converter. on-board rewrite boot mode setting. (total 3 pins) standby release input function can be specified in 1-bit units. (12 pins)
7 CXP974F096 i/o circuit format for pins pin circuit format after a reset pa0/a0 to pa7/a7 hi-z pb0/ppo00/a8 to pb7/ppo07/ a15 hi-z pc0/ppo08 to pc3/ppo11 hi-z a0 to a7 rd pa register pa register write (undefined after a reset) reset internal data bus q s r a8 to a15 ppo00 to ppo07 rd pb register pb register write address width setting (undefined after a reset) ("0" after a reset) reset internal data bus q s r 1 mpx 0 ppo08 to ppo11 rd pc register input protection circuit ("0" after a reset) internal data bus pcd register ("0" after a reset) ip
8 CXP974F096 pc4/ppo12/ xcs3 to pc7/ppo15/ xcs0 hi-z pd0/d0/ks12 to pd7/d7/ ks19 hi-z pe0/int0 to pe7/int7/ cint hi-z xcs3 to xcs0 ppo12 to ppo15 xcs output setting 1 mpx 0 rd pc register pcd register internal data bus ("0" after a reset) ("0" after a reset) ("0" after a reset) ip rd pd register pdd register external register i/f external register i/f wr (external register area) internal data bus internal data bus internal data bus external register operation enable standby release ("0" after a reset) ("0" after a reset) rd (external register area) external register operation enable ip clr clr ? large current drive 5ma (v dd = 2.7 to 3.6v) ? rd pe register ped register internal data bus int0 to int7/cint (undefined after a reset) ("0" after a reset) cmos schmitt input ip pin circuit format after a reset
9 CXP974F096 pf0/ec0 pf1/ec2 hi-z pf2/scs1/ nmi hi-z pf3/si1 hi-z pf4/so1 hi-z pf5/sck1 hi-z internal data bus ec0, ec2 rd cmos schmitt input ip pfsl register ("0" after a reset) nmi input enable ("0" after a reset) internal data bus rd cmos schmitt input scs1 nmi ip pfsl register ("0" after a reset) internal data bus rd cmos schmitt input si1 ip rd pfsl register ("0" after a reset) so1 output enable so1 internal data bus ip rd cmos schmitt input pfsl register ("0" after a reset) sck1 output enable sck1 internal data bus ip sck1 pin circuit format after a reset
10 CXP974F096 pf6/t1 "h" level pf7/t2 "h" level ("h" level at on resistance of pull-up transistor by a reset.) pg0/pwm0 to pg3/pwm3 hi-z t1 rd pfsl register ("1" after a reset) ("0" after a reset) internal data bus 1 0 mpx pf register pf register write reset q s r t2 rd pfsl register ("1" after a reset) ("0" after a reset) internal data bus 1 0 mpx pf register ? ? pull-up transistor approximately 150k ? (v dd = 2.7 to 3.6v) pg register write reset q s r pwm0 to pwm3 rd pgsl register (undefined after a reset) ("0" after a reset) internal data bus 1 0 mpx pg register pin circuit format after a reset
11 CXP974F096 pg4/scs0 hi-z pg5/si0 hi-z pg6/so0 hi-z rd pgd register pgsl register internal data bus scs0 ("0" after a reset) pg register (undefined after a reset) ("0" after a reset) ip cmos schmitt input rd pgd register pgsl register internal data bus si0 ("0" after a reset) pg register (undefined after a reset) ("0" after a reset) ip cmos schmitt input rd pg register pgsl register internal data bus (undefined after a reset) ("0" after a reset) pgd register ("0" after a reset) so0 output enable so0 ip 1 mpx 0 1 mpx 0 pin circuit format after a reset
12 CXP974F096 pg7/sck0 hi-z ph0/sda ph1/scl hi-z ph2/rxd hi-z rd pg register pgsl register internal data bus (undefined after a reset) ("0" after a reset) pgd register ("0" after a reset) sck0 output enable cmos schmitt input sck0 sck0 ip 1 mpx 0 1 mpx 0 cmos schmitt input rd phsl register internal data bus ("0" after a reset) ph register ("1" after a reset) sda, scl sda, scl ip 1 mpx 0 ? large current drive 5ma (v dd = 2.7 to 3.6v) ? cmos schmitt input rd phl register phd register internal data bus rxd (undefined after a reset) ("0" after a reset) ip pin circuit format after a reset
13 CXP974F096 ph3/txd hi-z ph4/rmc hi-z ph5/tetc hi-z ph6/xwr ph7/xrd hi-z rd ph register internal data bus (undefined after a reset) phd register ("0" after a reset) txd output enable txd ip 1 mpx 0 cmos schmitt input rd ph register phd register internal data bus rmc (undefined after a reset) ("0" after a reset) ip cmos schmitt input rd ph register phd register internal data bus (undefined after a reset) ("0" after a reset) ip xwr, xrd rd ph register ph register write phsl register (undefined after a reset) ("0" after a reset) reset internal data bus q s r 1 mpx 0 pin circuit format after a reset
14 CXP974F096 pi0/scs2 hi-z pi1/si2 hi-z pi2/so2 hi-z rd pid register pisl register internal data bus scs2 ("0" after a reset) pi register (undefined after a reset) ("0" after a reset) ip cmos schmitt input rd pid register pisl register internal data bus si2 ("0" after a reset) pi register (undefined after a reset) ("0" after a reset) ip cmos schmitt input rd pi register pisl register internal data bus (undefined after a reset) ("0" after a reset) pid register ("0" after a reset) so2 output enable so2 ip 1 mpx 0 1 mpx 0 pin circuit format after a reset
15 CXP974F096 pi3/sck2 hi-z pi4/an0/ks0 to pi7/an3/ ks3 hi-z pj0/an4/ks4 to pj7/an11/ ks11 hi-z rd pi register pisl register internal data bus (undefined after a reset) ("0" after a reset) pid register ("0" after a reset) sck2 output enable cmos schmitt input sck2 sck2 ip 1 mpx 0 1 mpx 0 rd pid register pisl register internal data bus standby release a/d converter ("0" after a reset) pi register (undefined after a reset) ("0" after a reset) ip input multiplexer rd pjd register pjsl register internal data bus standby release a/d converter ("0" after a reset) pj register (undefined after a reset) ("0" after a reset) ip input multiplexer pin circuit format after a reset
16 CXP974F096 pk0 to pk2 hi-z pk3/adten pk4/adtrg hi-z pk5/tetb "h" level pk6/teta "h" level ("h" level at on resistance of pull-up transistor by a reset.) rd pk register pkd register internal data bus (undefined after a reset) ("0" after a reset) ip rd pk register pkd register internal data bus adten, adtrg (undefined after a reset) ("0" after a reset) cmos schmitt input ip rd ("1" after a reset) internal data bus pk register pk register write reset q s r rd ("1" after a reset) internal data bus pk register ? pull-up transistor approximately 150k ? (v dd = 2.7 to 3.6v) ? pin circuit format after a reset
17 CXP974F096 xtal extal oscillation rst "l" level (during a reset) oscillation stop control timing generator diagram shows circuit configuration during oscillation. feedback resistor is reoved during standby stop mode, and xtal is driven at "h" level. ip extal xtal ? pull-up transistor approximately 30k ? (v dd = 2.7 to 3.6v) ? ip rst mask option cmos schmitt input op internal reset circuit pin circuit format after a reset
18 CXP974F096 absolute maximum ratings (vss = 0v reference) item supply voltage input voltage output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd av dd av ref av ss v in v out i oh i oh i ol i olc i ol topr tstg p d 0.3 to +4.6 av ss to +4.6 ? 1 av ss to +4.6 ? 1 0.3 to +0.3 0.3 to +4.6 ? 2 0.3 to +4.6 ? 2 5.0 50 15.0 20.0 130 30 to +85 55 to +150 600 380 v v v v v v ma ma ma ma ma c c mw output (value per pin) total for all output pins all pins excluding large current output pins (value per pin) large current output pins ? 3 (value per pin) total for all output pins qfp-100p-l01 lqfp-100p-l01 symbol rating unit remarks ? 1 av dd and av ref must be the same voltage with v dd . ? 2 v in and v out excluding ph0 and ph1 must not exceed v dd + 0.3v. ? 3 the large current drive transistor is n-ch transistor of pd and ph0, ph1. note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsi.
19 CXP974F096 item supply voltage v dd av dd av ref v ih v ihs v ihex v il v ils v ilex topr tpwe high level input voltage low level input voltage symbol min. 2.7 2.0 2.7 2.7 0.7v dd 0.8v dd v dd 0.4 0 0 0.3 30 0 3.6 3.6 3.6 3.6 v dd v dd v dd + 0.2 0.2v dd 0.2v dd 0.4 +85 +50 v v v v v v v v v c c guaranteed data hold range during stop mode ? 1 ? 1 ? 2 cmos schmitt input ? 3 extal ? 4 cmos schmitt input ? 3 extal ? 4 recommended operating range of flash eeprom rewrite operation max. unit remarks ? 1 av dd and av ref must be the same voltage with v dd . ? 2 pc, pd, pf4, pg6, ph3, pi2, pi4 to pi7, pj, pk0 to pk2, pwe for normal input port. ? 3 rst, pe, pf0 to pf3, pf5, pg4, pg5, pg7, ph0 to ph2, ph4, ph5, pi0, pi1, pi3, pk3 and pk4. ? 4 specified only during self-oscillation. recommended operating conditions (vss = 0v reference) operating temperature
20 CXP974F096 electrical characteristics dc characteristics 1 (topr = 30 to +85 c, vss = 0v reference) item symbol pins conditions min. typ. max. unit v dd = 3.0v, i oh = 0.15ma v dd = 2.7v, i oh = 0.15ma v dd = 3.0v, i oh = 0.5ma v dd = 2.7v, i oh = 0.5ma v dd = 3.0v, i oh = 1.5ma v dd = 2.7v, i oh = 1.5ma i ol = 1.2ma i ol = 1.6ma i ol = 2.0ma i ol = 3.0ma i ol = 5.0ma v dd = 3.6v, v ih = 3.6v v dd = 3.6v, v il = 0.3v v dd = 3.6v, v il = 0.3v v dd = 3.6v, v i = 0, 3.6v v dd = 3.6v, v ih = 3.6v v oh v ol i ihe i ile i ilr i iz i loh high level output voltage low level output voltage input current i/o leakage current open drain output leakage current (n-ch tr. off-state) pd to pe, pf6, pf7, pg0 to pg5, ph2, ph4, ph5, pi to pj, pk0 to pk6 pa to pc, pf4, pf5, pg6, pg7, ph3, ph6, ph7, pi2, pi3 pe, pf6, pf7, pg0 to pg5, ph2, ph4, ph5, pi0, pi1, pi4 to pi7, pj, pk0 to pk6 pa to pc, pf4, pf5, pg6, pg7, ph3, ph6, ph7, pi2, pi3 pd, ph0, ph1 extal rst ? 1 pa to pj, pk0 to pk6, rst ? 1 ph0, ph1 2.70 2.40 2.30 2.00 2.30 2.00 0.3 0.3 0.9 0.30 0.50 0.30 0.50 1.00 61 61 250 31 31 v v v v v v v v a a a a a ? 1 rst specifies the input current when pull-up resistor has been selected; the leakage current when no resistor has been selected.
21 CXP974F096 item symbol pins conditions min. typ. max. unit clock 1mhz, 0v for all pins excluding measured pins clock 1mhz, 0v for all pins excluding measured pins clock 1mhz, 0v for all pins excluding measured pins c in c out c i/o input capacitance output capacitance i/o capacitance pf0 to pf3, extal, rst pa to pb, pf6, pf7, pg0 to pg3, ph6, ph7, pk5, pk6, xtal pc to pe, pf4, pf5, pg4 to pg7, ph0 to ph5, pi to pj, pk0 to pk4 10 10 10 20 20 20 pf pf pf i/o capacitance item symbol pins conditions min. typ. max. unit v dd = 3.3 0.3v, f ex = fsrc = 40mhz, external clock operation a/d off state, pll off state v dd = 3.3 0.3v, f ex = fsrc = 40mhz, external clock operation a/d off state, pll off state, sleep mode v dd = 3.6v, stop mode ? 2 i dd1 ? 2 i dds2 i dds3 supply current ? 1 v dd , v ss v dd , v ss v dd , v ss 65 26 75 30 500 350 100 ma ma a dc characteristics 2 (topr = 30 to +85 c, vss = 0v reference) 85 c or less 75 c or less 50 c or less ? 1 when all output pins are open. ? 2 when the upper two bits (pck1, pck0) of the clock control register (clc: 0002feh) are set to "00" and the lsi is operated in high-speed mode (1/2 frequency dividing clock).
22 CXP974F096 ac characteristics (1) clock timing (topr = 30 to +85 c, v dd = 2.7 to 3.6 v, vss = 0v reference) item main clock base oscillation frequency main clock base oscillation input pulse width main clock base oscillation input rise time, fall time main clock duty extal, xtal extal, xtal extal, xtal xtal f ex = 40.0mhz fig.1, fig.2 external clock drive f ex = 33.86mhz fig.1, fig.2 external clock drive f ex = 20.0mhz fig.1, fig.2 external clock drive f ex = 40.0mhz fig.1, fig.2 external clock drive f ex = 33.86mhz fig.1, fig.2 external clock drive f ex = 20.0mhz fig.1, fig.2 external clock drive fig.1, fig.2 1/2 v dd point 9.5 9.5 9.5 9.5 9.5 9.5 4.0 4.0 11 40 34.5 31.0 35.5 32.5 38.5 35.0 8.5 10.5 14 60 mhz mhz mhz ns ns ns ns ns ns % symbol pins conditions min. max. 50 typ. unit note) t sys indicates the four values below according to the upper two bits (pck1, pck0) of the clock control register (clc: 0002feh). tsys [ns] = 2/f ex (pck1, pck0 = 00), 4/f ex (pck1, pck0 = 01), 8/f ex (pck1, pck0 = 10, 16/f ex (pck1, pck0 = 11) f ex t xh t xl t xh t xl t xh t xl t xr t xf t xr t xf t xr t xf duty v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v fig.1, fig.2 fig.1, fig.2 30 to +75 c fig.1, fig.2 30 to +50 c
23 CXP974F096 extal xtal 1/f ex t xh t xf t xl t xr v dd 0.4v 0.4v xtal duty = tx/t ex ; t ex = 1/f ex t ex t x 1/2v dd fig. 2. oscillator connection and clock applied conditions extal xtal (iii) oscillator connection example of main oscillation circuit connection example (1) of external clock connection example (2) of external clock extal xtal (ii) (i) extal xtal fig. 1. clock timing
24 CXP974F096 fig. 3. event count input timing ec0 ec2 t eh t el 0.8v dd 0.2v dd (2) event count input (topr = 30 to +85 c, v dd = 2.7 to 3.6v, vss = 0v reference) item event count input clock pulse width t eh , t el ec0, ec2 fig. 3 t sys + 100 ns symbol pins conditions min. max. unit fig. 4. interruption input timing 0.2v dd t ih t il 0.8v dd nmi int0 to int7 ks0 to ks19 0.2v dd rst t rst fig. 5. reset input timing (3) interruption and reset input (topr = 30 to +85 c, v dd = 2.7 to 3.6v, vss = 0v reference) item external interruption high, low level width t ih , t il t rst nmi, int0 to int7, ks0 to ks19 int4 to int7 rst main mode sleep mode fig. 4 noise filter selected fig. 4 fig. 5 ps4 ps6 ns ns t sys + 100 2 t sys + 100 32/f ex + 100 128/f ex + 100 50/f ex reset input low level width symbol pins conditions min. max. unit
25 CXP974F096 conversion time sampling time reference input voltage analog input voltage av ref current t conv t samp v ref i ref i refs av ref v dd = av dd = av ref = 3.0v ? 1 ? 1 v dd = av dd = av ref linearity error absolute error resolution 3.6 av ref 2.1 1.7 12 34 t sys 62 t sys 10 t sys 20 t sys 2.7 0 main mode adc off state ? 2 stop mode item symbol pins conditions min. typ. max. unit bits (4) a/d converter characteristics (topr = 30 to +85 c, v dd = av dd = av ref = 2.7 to 3.6v, vss = avss = 0v reference) 8 1 lsb lsb ns ns ns ns v v ma ma a 3 1.5 1.2 av ref an0 to an11 fig. 6. definition of a/d converter terms ffh feh 01h 00h analog input linearity error digital conversion value ffh (100h) feh 01h 00h analog input digital conversion value absolute error av ref v ft ? 2 v zt ? 1 ? 1 v zt : value at which the digital conversion value changes from 00h to 01h and vice versa. ? 2 v ft : value at which the digital conversion value changes from feh to ffh and vice versa. absolute error ? 1 when bit 6 (adck) of a/d control status register (adcs: 000132h) is specified to "1". ? 2 when bit 5 (adpc) of a/d control status register (adcs: 000132h) is specified to "1". note) av dd and av ref must be the same voltage with v dd . v dd = 3.3 0.3v f src = 40mhz v dd = 3.3 0.3v f src = 20mhz
26 CXP974F096 sck0, sck1, sck2 sck0, sck1, sck2 so0, so1, so2 scs0, scs1, scs2 scs0, scs1, scs2 sck0, sck1, sck2 sck0, sck1, sck2 si0, si1, si2 si0, si1, si2 so0, so1, so2 sck0, sck1, sck2 note) the load condition for the sck output mode and so output delay time is 100pf. (5) serial transfer (ch0, ch1, ch2) (topr = 30 to +85 c, v dd = 2.7 to 3.6v, vss = 0v reference) item cs sck delay time cs sck float delay time cs so delay time cs so float delay time cs high level width sck cycle time sck high, low pulse width si input data setup time (for sck ) si input data hold time (for sck ) sck so delay time minimum interval time t dcsk t dskf t dcso t dcsof t whcs t kcy t kh , t kl t sik t ksi t kso t int symbol pins min. 2 t sys + 150 2 t sys + 160 100 110 2 t sys + 200 2 t sys + 210 16/f ex 16/f ex t sys + 100 t sys + 110 8/f ex 100 8/f ex 110 100 110 200 210 2 t sys + 100 2 t sys + 110 100 110 3 t sys + 100 3 t sys + 110 8/f ex 100 8/f ex 110 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns max. unit conditions external start transfer mode (sck = output mode) external start transfer mode input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v v dd = 3.3 0.3v v dd = 3.0 0.3v t sys + 100 t sys + 110 1.5 t sys + 200 1.5 t sys + 210 1.5 t sys + 200 1.5 t sys + 210 1.5 t sys + 200 1.5 t sys + 210 1.5 t sys + 200 1.5 t sys + 210 ns ns ns ns ns ns ns ns ns ns
27 CXP974F096 sck0 sck1 sck2 si0 si1 si2 so0 so1 so2 scs0 scs1 scs2 sck0 sck1 sck2 t int 0.8v dd 0.2v dd 0.8v dd t dcsof 0.2v dd 0.8v dd t sik t ksi 0.2v dd 0.8v dd 0.2v dd 0.8v dd t kh t dcskf t whcs t kl t dcsk t kcy t kso output data input data t dcso fig. 7. serial transfer ch0, ch1, ch2 timing
28 CXP974F096 ? 1 due to the total capacitance of the bus. (6) i 2 c bus (topr = 30 to +85 c, v dd = 2.7 to 3.6v, vss = 0v reference) sck clock frequency bus free time between stop and start conditions hold time under (resend) start condition hold time in scl clock low state hold time in scl clock high state setup time under (resend) start condition data hold time data setup time scl, sda signal output rise time scl, sda signal output fall time setup time under stop condition scl sda sda, scl scl scl sda, scl sda, scl sda, scl sda, scl sda, scl sda, scl t scl t buf t hd;sta t low t high t su;sta t hd;dat t su;dat t rd , t rc t fd , t fc t su;sto 400 0.9 300 300 1.3 0.6 1.3 0.6 0.6 0 100 20 + ? 1 20 + ? 1 0.6 khz s s s s s s ns ns ns s 100 1000 300 4.7 4.0 4.7 4.0 4.7 0 250 4.0 item symbol pins min. standard mode high-speed mode max. min. max. unit sda scl t buf t su;dat t hd;sta t scl t fd t rd t rc t fc t low t hd;sta t hd;dat t high t su;sta t su;sto fig. 8. i 2 c bus timing
29 CXP974F096 (7) remote control reception (topr = 30 to +85 c, v dd = 2.7 to 3.6v, vss = 0v reference) item remote control receive high, low level width t rmc rmc main mode ps5 selected ps7 selected ps9 selected ns 128/f ex + 100 512/f ex + 100 2048/f ex + 100 symbol pins conditions typ. max. unit 0.8v dd rmc 0.2v dd t rmc t rmc fig. 9. remote control signal input timing
30 CXP974F096 (8) external register interface (vss = 0v reference) item symbol min. max. min. max. min. max. 3.3 0.3v topr = 20 to +75 c 3.3 0.3v topr = 30 to +85 c 3.0 0.3v topr = 30 to +85 c unit chip select pulse width 1 chip select pulse width 2 chip select pulse width 3 chip select pulse width 4 chip select pulse width 5 chip select pulse width 6 chip select pulse width 7 read/write strobe pulse width 1 read/write strobe pulse width 2 read/write strobe pulse width 3 address setting time 1 address setting time 2 address hold time read data setting request time read data hold request time write data setting time 1 write data setting time 2 write data hold time t cs1 t cs2 t cs3 t cs4 t cs5 t cs6 t cs7 t rw1 t rw2 t rw3 t as1 t as2 t ah t ds1 t dh1 t ds2 t ds3 t dh2 1.5 t sys 20 2.5 t sys 20 2.5 t sys 20 3.5 t sys 20 2.5 t sys 20 3.5 t sys 20 4.5 t sys 20 t sys 25 2 t sys 25 2 t sys 25 t sys/2 25 1.5 t sys 25 t sys/2 25 15 0 1.5 t sys 25 2.5 t sys 25 t sys/2 25 1.5 t sys 16.5 t sys 32.5 t sys 33.5 t sys 17.5 t sys 18.5 t sys 34.5 t sys t sys 16 t sys 32 t sys t sys/2 1.5 t sys 1.5 t sys 16.5 t sys t sys/2 +30 1.5 t sys 20 2.5 t sys 20 2.5 t sys 20 3.5 t sys 20 2.5 t sys 20 3.5 t sys 20 4.5 t sys 20 t sys 25 2 t sys 25 2 t sys 25 t sys/2 25 1.5 t sys 25 t sys/2 25 15 0 1.5 t sys 25 2.5 t sys 25 t sys/2 25 1.5 t sys 16.5 t sys 32.5 t sys 33.5 t sys 17.5 t sys 18.5 t sys 34.5 t sys t sys 16 t sys 32 t sys t sys/2 1.5 t sys 1.5 t sys 16.5 t sys t sys/2 +30 1.5 t sys 30 2.5 t sys 30 2.5 t sys 30 3.5 t sys 30 2.5 t sys 30 3.5 t sys 30 4.5 t sys 30 t sys 35 2 t sys 35 2 t sys 35 t sys/2 35 1.5 t sys 35 t sys/2 35 20 0 1.5 t sys 35 2.5 t sys 35 t sys/2 35 1.5 t sys 16.5 t sys 32.5 t sys 33.5 t sys 17.5 t sys 18.5 t sys 34.5 t sys t sys 16 t sys 32 t sys t sys/2 1.5 t sys 1.5 t sys 16.5 t sys t sys/2 +30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
31 CXP974F096 read timing t1 t cs1 t ah t as1 t rw1 t2 a15 to a0 xcs3 to xcs0 xrd d7 to d0 t ds1 t dh1 fig. 10. byte read (without programmable wait) t ds1 t dh1 t cs2 t ah t as1 t rw2 t1 t2 or tw t3 or t w + 1 a15 to a0 xcs3 to xcs0 xrd d7 to d0 fig. 11. byte read (with programmable wait)
32 CXP974F096 t ds1 t dh1 t cs3 even add. odd add. t ah t as1 t rw3 t1 t2 t3 a15 to a0 xcs3 to xcs0 xrd d7 to d0 t ds1 fig. 12. word read (no strobe mode, without programmable wait) t ds1 t dh1 t dh1 t cs4 even add. odd add. t ah t as1 t ah t as1 t rw1 t rw1 t1 t2 t3 t4 a15 to a0 xcs3 to xcs0 xrd d7 to d0 t ds1 fig. 13. word read (strobe mode, without programmable wait)
33 CXP974F096 write timing t1 t cs5 t ah t ds2 t as2 t rw1 t2 t3 a15 to a0 xcs3 to xcs0 xwr d7 to d0 t dh2 fig. 14. byte write (without programmable wait) t1 t cs6 t ah t ds3 t as2 t rw2 t2 t3 or tw t4 or t w + 1 a15 to a0 xcs3 to xcs0 xwr d7 to d0 t dh2 fig. 15. byte write (with programmable wait)
34 CXP974F096 t dh2 t cs7 even add. odd add. t ah t ah t as1 t rw1 t rw1 t1 t2 t3 t4 t5 a15 to a0 xcs3 to xcs0 xwr d7 to d0 t ds2 t dh2 t ds2 fig. 16. word write (without programmable wait)
35 CXP974F096 extal xtal c 1 c 2 rd extal xtal c 1 c 2 rd extal (i) main oscillation circuit (ii) main oscillation circuit (iii) main oscillation circuit xtal c 1 c 2 rd l c 3 fig. 17. recommended oscillation circuit appendix spc970 series recommended oscillation circuit and oscillator murata mfg co., ltd. river eletec co., ltd. hc-49/u03 csa6.00mg040 csa8.00mtz csa10.0mtz csa12.0mtz csa16.00mxz040 csa20.00mxz040 csa24.00mxz040 cst6.00mgw040 ? cst8.00mtw ? cst10.0mtw ? cst12.0mtw ? cst16.00mxw0c3 ? 6.0 8.0 10.0 12.0 16.0 20.0 24.0 6.0 8.0 10.0 12.0 16.0 6.0 8.0 10.0 12.0 100 30 30 30 15 10 7 100 30 30 30 15 18 15 10 10 100 30 30 30 15 10 7 100 30 30 30 15 18 15 10 10 0 0 0 0 0 0 0 0 0 0 0 0 560 330 330 220 (i) (ii) ? indicates types with on-chip grounding capacitor (c 1 , c 2 ). cl: load capacitor (i) cl = 13.5pf cl = 12pf cl = 9.5pf cl = 10pf manufacturer model f ex (mhz) c 1 (pf) c 2 (pf) rd ( ? ) circuit example remarks
36 CXP974F096 product list type product name flash eeprom capacitance ram capacitance package main clock base oscillation frequency reset pin pull-up resistor flash eeprom incorporated version CXP974F096q-1, CXP974F096r-1 384k byte 23.5k byte 100-pin plastic qfp, 100-pin plastic lqfp 40mhz existent 6.0 8.0 10.0 12.0 16.0 20.0 24.0 28.0 32.0 36.0 40.0 6.0 12.0 16.0 28.0 40.0 15 15 10 12 12 12 12 1 3 3 1 36 (20%) 20 (20%) 10 (20%) 10 (20%) 5 15 15 10 12 12 12 12 1 0.01f 0.01f 0.01f 36 (20%) 20 (20%) 10 (20%) 10 (20%) 5 5.6k 3.0k 1.8k 1.0k 470 390 200 100 0 0 0 0 0 0 0 0 cl = 16pf cl = 12pf (i) (ii) (iii) ? indicates types with on-chip grounding capacitor (c 1 , c 2 ). ccr ??? : surface mounted type ceramic oscillator cl: load capacitor (i) c3 = 10pf, l = 2.7h c3 = 5pf, l = 2.7h c3 = 3pf, l = 3.3h kinseki ltd. hc-49/u-s hc-49/u tdk corporation ccr6.0mc5 ? ccr12.0msc5 ? ccr16.0msc6 ? ccr28.0msc6 ? ccr40.0ms6 manufacturer model f ex (mhz) c 1 (pf) c 2 (pf) rd ( ? ) circuit example remarks
37 CXP974F096 notes on pk6 usage flash eeprom incorporated pk6 is also used as flash mode setting function. note the followings: 1. "h" is output to pk6 during a reset. that is driven at comparatively high impedance (approximately 150k ? ), and take care that v oh should not fall under 0.7v dd by the partial pressure with external circuit load impedance. 2. when using software reset functions, pk6 may not rise enough during a reset. switching pk6 to "h" output prior to software reset execution or connecting pull-up resistor is recommended. mask rom and piggy/evaluation chip do not have flash mode setting function. considering that flash eeprom incorporated type is used, above countermeasure should be performed. keep pk6 above 0.7v dd during this period. rst pk6 flash mode normal operation limits on usage of flash eeprom incorporated type the main clock doubler circuit is not guaranteed to operate.
38 CXP974F096 characteristics curve 60 66 72 54 48 42 36 30 24 18 6 0 2.1 2.4 2.7 3.3 3 3.6 3.9 12 60 66 72 54 48 42 36 30 24 18 12 6 2.1 2.4 2.7 3 3.3 3.6 3.9 0 60 66 72 54 48 42 36 30 24 18 12 6 010203040 0 60 66 72 54 48 42 36 30 24 18 12 6 10 20 30 40 0 0 i dd supply current [ma] v dd supply voltage [v] i dd vs. v dd (f ex = 40mhz, topr = 25 c, typical) i dd supply current [ma] v dd supply voltage [v] i dd vs. v dd (f ex = 40mhz, topr = 25 c, typical) i dd supply current [ma] f ex main clock base oscillation frequency [mhz] i dd vs. f ex (v dd = 3v, topr = 25 c, typical) i dd supply current [ma] f ex main clock base oscillation frequency [mhz] i dd vs. f ex (v dd = 3v, topr = 25 c, typical) sleep mode (1/2 frequency dividing mode) sleep mode (1/4 frequency dividing mode) sleep mode (1/8 frequency dividing mode) sleep mode (1/16 frequency dividing mode) 1/4 frequency dividing mode 1/2 frequency dividing mode 1/8 frequency dividing mode 1/16 frequency dividing mode 1/4 frequency dividing mode 1/2 frequency dividing mode 1/8 frequency dividing mode 1/16 frequency dividing mode sleep mode (1/2 frequency dividing mode) sleep mode (1/4 frequency dividing mode) sleep mode (1/8 frequency dividing mode) sleep mode (1/16 frequency dividing mode)
39 CXP974F096 package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 23.9 0.4 qfp-100p-l01 100pin qfp (plastic) 20.0 0.1 + 0.4 0.15 0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 0.1 + 0.4 2.75 0.15 + 0.35 a 0.65 m 0.13 qfp100-p-1420 1.7g 1 100 81 80 51 50 31 30 0.3 0.1 + 0.15 detail a 0 ? to 10 ? 0.8 0.2 (16.3) 0.15 0.1 0.05 + 0.2 lead specifications item lead material alloy 42 lead treatment sn-pb 10% lead treatment thickness 5-18 m spec.
40 CXP974F096 package outline unit: mm 100pin lqfp (plastic) 25 26 51 50 75 76 1 100 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy package structure detail a lqfp-100p-l01 p-lqfp100-14x14-0.5 16.0 0.2 14.0 0.1 0.5 b (0.22) a 1.5 ?0.1 + 0.2 0.5 0.2 (15.0) 0? to 10? 0.1 0.1 0.5 0.2 0.1 note: dimension " ? " does not include mold protrusion. 0.7g 0.13 m b = 0.18 ?0.03 ( 0.18 ) (0.127) + 0.08 0.127 ?0.02 + 0.05 detail b ? b sony corporation lead specifications item lead material alloy 42 lead treatment sn-pb 10% lead treatment thickness 5-18 m spec.

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