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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. ad1838 2 adc, 6 dac, 96 khz, 24-bit - codec features 5 v stereo audio system with 3.3 v tolerant digital interface supports up to 96 khz sample rates 192 khz sample rate available on one dac supports 16-/20-/24-bit word lengths multibit - modulators with perfect differential linearity restoration for reduced idle tones and noise floor data directed scrambling dacs?east sensitive to jitter differential output for optimum performance adcs: ?5 db thd + n, 105 db snr and dynamic range dacs: ?5 db thd + n, 108 db snr and dynamic range on-chip volume controls per channel with 1024 step linear scale dac and adc software controllable clickless mutes digital de-emphasis processing supports 256 f s , 512 f s, and 768 f s master mode clocks power-down mode plus soft power-down mode flexible serial data port with right-justified, left- justified, i 2 s compatible, and dsp serial port modes tdm interface mode supports 8 in/8 out using a single sharc sport 52-lead mqfp plastic package functional block diagram outlp1 outln1 control port clock filtd filtr adclp adcln adcrp adcrn dlrclk dbclk dsdata1 dsdata2 dsdata3 dauxdata mclk asd ata abclk alrclk odvdd d vdd av d d av d d d vdd a gnd agnd a gnd a gnd dgnd dgnd cin clatch cclk cout digital filter pd / rst m /s - adc vo lume serial data i/o port digital filter - dac v ref outrp1 outrn1 vo lume outlp2 outln2 vo lume digital filter - dac outrp2 outrn2 vo lume outlp3 outln 3 vo lume digital filter - dac outrp3 outrn3 vo lume digital filter - adc aauxd ata 3 ad1838 product overview the ad1838 is a high performance single-chip codec featuring three stereo dacs and one stereo adc. each dac comprises a high performance digital interpolation filter, a multibit - modulator featuring analog devices?patented technology, and a continuous-time voltage out analog section. each dac has independent volume control and clickless mute functions. the adc comprises two 24-bit conversion channels with multibit - modulators and decimation filters. the ad1838 also contains an on-chip reference with a nominal value of 2.25 v. the ad1838 contains a flexible serial interface that allows for glueless connection to a variety of dsp chips, aes/ebu receiv- ers, and sample rate converters. the ad1838 can be configured in left-justified, right-justified, i 2 s, or dsp compatible serial modes. control of the ad1838 is achieved by means of an spi compatible serial port. while the ad1838 can be operated from a single 5 v supply, it also features a separate supply pin for its digital interface that allows the device to be interfaced to other devices using 3.3 v power supplies. the ad1838 is available in a 52-lead mqfp package and is specified for the industrial temperature range of ?0? to +85?. applications dvd video and audio players home theater systems automotive audio systems audio/visual receivers digital audio effects processors
rev. a ? ad1838?pecifications test conditions supply voltages (av dd , dv dd ) 5.0 v ambient temperature 25 c input clock 12.288 mhz, (256 f s mode) dac input signal 1.0078125 khz, 0 dbfs (full scale) adc input signal 1.0078125 khz, ? dbfs (full scale) input sample rate (f s ) 48 khz measurement bandwidth 20 hz to 20 khz word width 24 bits load capacitance 100 pf load impedance 47 k ? performance of all channels is identical (exclusive of the interchannel gain mismatch and interchannel phase deviation specific ations). parameter min typ max unit analog-to-digital converters adc resolution 24 bits dynamic range (20 hz to 20 khz, ?0 db input) no filter 100 103 db a-weighted 101 105 db total harmonic distortion + noise (thd+n) ?5 ?8.5 db interchannel isolation 100 db interchannel gain mismatch 0.025 db analog inputs differential input range ( full scale) ?.828 +2.828 v common-mode input voltage 2.25 v input impedance 4 k ? input capacitance 15 pf v ref 2.25 v dc accuracy gain error 5% gain drift 35 ppm/? digital-to-analog converters dac resolution dynamic range (20 hz to 20 khz, ?0 dbfs input) no filter 103 105 db with a-weighted filter 105 108 db total harmonic distortion + noise ?5 ?0 db interchannel isolation 110 db dc accuracy gain error 4% interchannel gain mismatch 0.025 db gain drift 200 ppm/ c interchannel phase deviation 0.1 degrees volume control step size (1023 linear steps) 0.098 % volume control range (max attenuation) 60 db mute attenuation ?00 db de-emphasis gain error 0.1 db full-scale output voltage at each pin (single-ended) 1.0 (2.8) v rms (v p-p) output resistance at each pin 180 ? common-mode output voltage 2.25 v adc decimation filter, 48 khz * pass band 20 khz pass-band ripple 0.01 db stop band 24 khz stop-band attenuation 120 db group delay 910 s
rev. a ad1838 ? parameter min typ max unit adc decimation filter, 96 khz * pass band 40 khz pass-band ripple 0.01 db stop band 48 khz stop-band attenuation 120 db group delay 460 s dac interpolation filter, 48 khz * pass band 20 khz pass-band ripple 0.01 db stop band 24 khz stop-band attenuation 55 db group delay 340 s dac interpolation filter, 96 khz * pass band 37.5 khz pass-band ripple 0.01 db stop band 55.034 khz stop-band attenuation 55 db group delay 160 s dac interpolation filter, 192 khz * pass band 89.954 khz pass-band ripple 0.01 db stop band 104.85 khz stop-band attenuation 80 db group delay 110 s digital i/o input voltage high 2.4 v input voltage low 0.8 v output voltage high odv dd ?0.4 v output voltage low 0.4 v leakage current 10 a power supplies supply voltage (av dd and dv dd ) 4.5 5.0 5.5 v supply voltage (odv dd ) 3.0 dv dd v supply current i analog 84 95 ma supply current i analog , power-down 55 67 ma supply current i digital 64 74 ma supply current i digital , power-down 1 4.5 ma dissipation operation, both supplies 740 mw operation, analog supply 420 mw operation, digital supply 320 mw power-down, both supplies 280 mw power supply rejection ratio 1 khz, 300 mv p-p signal at analog supply pins ?0 db 20 khz, 300 mv p-p signal at analog supply pins ?5 db * guaranteed by design. specifications subject to change without notice.
rev. a ? ad1838 timing specifications parameter min max unit comments master clock and reset t mh mclk high 15 ns t ml mclk low 15 ns t pdr pd / rst low 20 ns spi port t cch cclk high 40 ns t ccl cclk low 40 ns t ccp cclk period 80 ns t cds cdata setup 10 ns to cclk rising t cdh cdata hold 10 ns from cclk rising t cls clatch setup 10 ns to cclk rising t clh clatch hold 10 ns from cclk rising t coe cout enable 15 ns from clatch falling t cod cout delay 20 ns from cclk falling t cots cout three-state 25 ns from clatch rising dac serial port normal mode (slave) t dbh dbclk high 60 ns t dbl dbclk low 60 ns f db dbclk frequency 64 f s t dls dlrclk setup 10 ns to dbclk rising t dlh dlrclk hold 10 ns from dbclk rising t dds dsdata setup 10 ns to dbclk rising t ddh dsdata hold 10 ns from dbclk rising packed 256 modes (slave) t dbh dbclk high 15 ns t dbl dbclk low 15 ns f db dbclk frequency 256 f s t dls dlrclk setup 10 ns to dbclk rising t dlh dlrclk hold 5 ns from dbclk rising t dds dsdata setup 10 ns to dbclk rising t ddh dsdata hold 10 ns from dbclk rising adc serial port normal mode (master) t abd abclk delay 25 ns from mclk rising edge t ald alrclk delay low 5 ns from abclk falling edge t abdd asdata delay 10 ns from abclk falling edge normal mode (slave) t abh abclk high 60 ns t abl abclk low 60 ns f ab abclk frequency 64 f s t als alrclk setup 5 ns to abclk rising t alh alrclk hold 15 ns from abclk rising packed 256 mode (master) t pabd abclk delay 20 ns from mclk rising edge t pald lrclk delay 5 ns from abclk falling edge t pabdd asdata delay 10 ns from abclk falling edge
rev. a ad1838 ? parameter min max unit comments tdm256 mode (master) t tbd bclk delay 20 ns from mclk rising t fsd fstdm delay 5 ns from bclk rising t tabd asdata delay 10 ns from bclk rising t tdds dsdata1 setup 15 ns to bclk falling t tddh dsdata1 hold 15 ns from bclk falling tdm256 mode (slave) f ab bclk frequency 256 f s t tbch bclk high 15 ns t tbcl bclk low 15 ns t tfs fstdm setup 10 ns to bclk falling t tfh fstdm hold 10 ns from bclk falling t tbdd asdata delay 10 ns from bclk rising t tdds dsdata1 setup 15 ns to bclk falling t tddh dsdata1 hold 15 ns from bclk falling auxiliary interface t axds aauxdata setup 10 ns to auxbclk rising t axdh aauxdata hold 10 ns from auxbclk rising t dxd dauxdata delay 15 ns from auxbclk falling f abp auxbclk frequency 64 f s slave mode t axbh auxbclk high 15 ns t axbl auxbclk low 15 ns t axls auxlrclk setup 10 ns to auxbclk rising t axlh auxlrclk hold 10 ns from auxbclk rising master mode t auxlrclk auxlrclk delay 5 ns from auxbclk falling t auxbclk auxbclk delay 15 ns from mclk rising specifications subject to change without notice. mclk t mh p d / rst t ml t pdr t mclk figure 1. mclk and pd / rst timing
rev. a ? ad1838 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1838 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. temperature range parameter min typ max unit specifications guaranteed 25 c functionality guaranteed ?0 +85 c storage ?5 +150 c absolute maximum ratings * (t a = 25 c, unless otherwise noted.) av dd , dv dd , odv dd to agnd, dgnd . . ?.3 v to +6.0 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v digital i/o voltage to dgnd . . . . . ?.3 v to odv dd + 0.3 v analog i/o voltage to agnd . . . . . . ?.3 v to av dd + 0.3 v operating temperature range industrial (a version) . . . . . . . . . . . . . . . . . . ?0 c to +85 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature package package model range description option AD1838AS ?0 o c to +85 o c 52-lead mqfp s-52 AD1838AS-reel ?0 o c to +85 o c 52-lead mqfp s-52 eval-ad1838eb evaluation board
rev. a ad1838 ? pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 agnd avdd outrp2 outrn2 outlp2 outln2 outrp1 outrn1 outlp1 outln1 pd / rst cin clatch dvdd outln3 outlp3 dgnd 52 51 50 49 48 47 46 45 44 43 42 41 40 filtd filtr agnd dauxdata agnd avdd adcln adclp adcrn adcrp agnd dgnd cclk cout asdata odvdd mclk alrclk abclk aauxdata3 dsdata3 dsdata2 dsdata1 ad1838 top view (not to scale ) outrn3 outrp3 nc nc nc agnd agnd dlrclk dbclk 27 28 29 30 31 32 33 34 35 36 37 38 39 m /s dvdd avdd 14 15 16 17 18 19 20 21 22 23 24 25 26 pin function descriptions input/ pin no. mnemonic output description 1, 39 dvdd digital power supply. connect to digital 5 v supply. 2c latch i latch input for control data. 3 cin i serial control input. 4 pd / rst i power-down/reset. 5, 10, 16, 24, 30, 34 agnd analog ground. 6, 12, 25 outlnx o dacx left channel negative output. 7, 13, 26 outlpx o dacx left channel positive output. 8, 14, 27 outrnx o dacx right channel negative output. 9, 15, 28 outrpx o dacx right channel positive output. 11, 19, 29 avdd analog power supply. connect to analog 5 v supply. 17 filtd filter capacitor connection. recommended 10 f/100 nf. 18 filtr reference filter capacitor connection. recommended 10 f/100 nf. 20 adcln i adc left channel negative input. 21 adclp i adc left channel positive input. 22 adcrn i adc right channel negative input. 23 adcrp i adc right channel positive input. 31?3 nc not connected. 35 m /s i adc master /slave select. 36 dauxdata i auxiliary dac input data. 37 dlrclk i/o dac lr clock. 38 dbclk i/o dac bit clock. 40, 52 dgnd digital ground. 41?3 dsdatax i dacx input data (left and right channels). 44 aauxdata3 i auxiliary adc3 digital input. 45 abclk i/o adc bit clock. 46 alrclk i/o adc lr clock. 47 mclk i master clock input. 48 odvdd digital output driver power supply. 49 asdata o adc serial data output. 50 cout o output for control data. 51 cclk i control clock input for control data.
rev. a ? ad1838?ypical performance characteristics frequency (normalized to f s ) 05 magnitude (db) 10 ?50 15 ?00 ?0 0 tpc 1. adc composite filter response frequency (hz) ?0 020 5 magnitude (db) 10 15 ?5 ?0 ?5 ?0 ? 0 5 tpc 2. adc high-pass filter response, f s = 48 khz frequency (normalized to f s ) ?50 0 2.0 0.5 magnitude (db) 1.0 1.5 0 ?00 ?0 tpc 3. adc composite filter response (pass-band section) frequency (hz) ?0 020 5 magnitude (db) 10 15 ?5 ?0 ?5 ?0 ? 0 5 tpc 4. adc high-pass filter response, f s = 96 khz frequency (khz) 0 ?0 ?50 magnitude (db) ?00 0 200 50 100 150 tpc 5. dac composite filter response, f s = 48 khz 0 ?0 ?50 ?00 0 200 50 100 150 frequency (khz) magnitude (db) tpc 6. dac composite filter response, f s = 96 khz
rev. a ad1838 ? 0 ?0 0 200 50 100 150 ?00 ?50 frequency (khz) magnitude (db) tpc 7. dac composite filter response, f s = 192 khz 0.10 0.05 ?.10 020 51015 0 ?.05 frequency (khz) magnitude (db) tpc 8. dac composite filter response, f s = 48 khz (pass-band section) 0.2 0.1 ?.2 050 10 20 30 40 0 ?.1 frequency (khz) magnitude (db) tpc 9. dac composite filter response, f s = 96 khz (pass-band section) 0.10 0.05 ?.10 0 100 20 40 60 80 0 ?.05 frequency (khz) magnitude (db) tpc 10. dac composite filter response, f s = 192 khz (pass-band section)
rev. a ?0 ad1838 terminology dynamic range the ratio of a full-scale input signal to the integrated input noise in the pass band (20 hz to 20 khz), expressed in decibels (db). dynamic range is measured with a ?0 db input signal and is equal to (s/[thd + n]) + 60 db. note that spurious harmon- ics are below the noise with a ?0 db input, so the noise level es tablishes the dynamic range. the dynamic range is specified with and without an a-weight filter applied. signal-to-(total harmonic distortion + noise) [s/(thd + n)] the ratio of the root-mean-square (rms) value of the fundamental input signal to the rms sum of all other spectral components in the pass band, expressed in decibels (db). pass band the region of the frequency spectrum unaffected by the attenu- ation of the digital decimator? filter. pass-band ripple the peak-to-peak variation in amplitude response from equal- amplitude input signal frequencies within the pass band, expressed in decibels. stop band the region of the frequency spectrum attenuated by the digital decimator? filter to the degree specified by stop-band attenuation. gain error with identical near full-scale inputs, the ratio of actual output to ex pected output, expressed as a percentage. interchannel gain mismatch with identical near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels. gain drift change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per c. crosstalk (eiaj method) ratio of response on one channel with a grounded input to a full-scale 1 khz sine wave input on the other channel, expressed in decibels. power supply rejection with no analog input, signal present at the output when a 300 mv p-p signal is applied to power supply pins, expressed in decibels of full scale. group delay intuitively, the time interval required for an input pulse to appear at the converter? output, expressed in milliseconds (ms). more precisely, the derivative of radian phase with respect to radian frequency at a given frequency. group delay variation the difference in group delays at different input frequencies. specified as the difference between the largest and the smallest group delays in the pass band, expressed in microseconds ( s). acronyms adc?nalog-to-digital converter dac?igital-to-analog converter dsp?igital signal processor imclk?nternal master clock signal used to clock the adc and dac engines mclk?xternal master clock signal applied to the ad1838
rev. a ad1838 ?1 functional overview adcs there are two adc channels in the ad1838, configured as a stereo pair. each adc has fully differential inputs. the adc section can operate at a sample rate of up to 96 khz. the adcs include on-board digital decimation filters with 120 db stop- band attenuation and linear phase response, operating at an over- sampling ratio of 128 (for 48 khz operation) or 64 (for 96 khz operation). adc peak level information for each adc may be read from the adc peak 0 and adc peak 1 registers. the data is sup plied as a 6-bit word with a maximum range of 0 db to ?3 db and a resolution of 1 db. the registers will hold peak inform ation until read; after reading, the registers are reset so that new peak inform ation can be acquired. refer to the register description for details of the format. the two adc channels have a common serial bit clock and a left-right framing clock. the clock signals are all synchronous with the sample rate. the adc digital pins, abclk and alrclk, can be set to operate as inputs or outputs by connecting the m /s pin to odvdd or dgnd, respectively. when the pins are set as outputs, the ad1838 will generate the timing signals. when the pins are set as inputs, the timing must be generated by the external audio controller. dacs the ad1838 has six dac channels arranged as three indepen- dent stereo pairs, with six fully differential analog outputs for improved noise and distortion performance. each channel has its own independently programmable attenuator, adjustable in 1024 linear steps. digital inputs are supplied through three serial data input pins (one for each stereo pair) and a common frame (dlrclk) and bit (dbclk) clock. alternatively, one of the packed data modes may be used to access all six channels on a single tdm data pin. a stereo replicate feature is included w here the dac data sent to the first dac pair is also sent to the other dacs in the part. the ad1838 can accept dac data at a sample rate of 192 khz on dac 1 only. the stereo replicate feature can then be used to copy the audio data to the other dacs. each set of differential output pins sits at a dc level of v ref and swings 1.4 v for a 0 db digital input signal. a single op amp third order external low-pass filter is recommended to remove high frequency noise present on the output pins, as well as to provide differential-to-single-ended conversion. note that the use of op amps with low slew rate or low bandwidth may cause high frequency noise and tones to fold down into the audio band; care should be exercised in selecting these components. the filtd pin should be connected to an external grounded capacitor. this pin is used to reduce the noise of the internal dac bias circuitry, thereby reducing the dac output noise. in some cases, this capacitor may be eliminated with little effect on performance. dac and adc coding the dac and adc output data stream is in a twos complement encoded format. the word width can be selected from 16-bit, 20-bit, or 24-bit. the coding scheme is detailed in table i. table i. coding scheme code level 01111......1111 +fs 00000......0000 0 (ref level) 10000......0000 ?s clock signals the dac and adc engines in the ad1838 are designed to operate from a 24.576 mhz internal master clock (imclk). this clock is used to generate 48 khz, and 96 khz sampling on the adc and 48 khz, 96 khz, and 192 khz on the dac, al though the 192 khz option is available only on one dac pair. the stereo replicate feature can be used to copy this dac data to the other dacs if required. to facilitate the use of the different mclk values, the ad1838 provides a clock scaling feature. the mclk scaler can be pro- grammed via the spi port to scale the mclk by a factor of 1 (pass through), 2 (doubling), or 2/3. the default setting of the mclk scaler is 2, which will generate 48 khz sampling from a 12.288 mhz mclk. additional sam ple rates can be achieved by changing the mclk value. for example, the cd standard sampling frequency of 44.1 khz can be achieved using an 11.2896 khz mclk. figure 2 shows the internal con figura- tion of the clock scaler and converter engines. dac engine cl ock scaling 1 2/3 mclk 12.288mhz dac input in terpolation fi lter - modulator dac 48khz/96khz/192khz adc output 48khz/96khz a nalog ou tput a nalog input imclk = 24.576mhz adc engine o ptional hpf de cimator/ fi lter - modulator 2 figure 2. modulator clocking scheme
rev. a ?2 ad1838 to maintain the highest performance possible, it is recomm ended that the clock jitter of the master clock signal be limited to less than 300 ps rms, measured using the edge-to-edge technique. even at these levels, extra noise or tones may appear in the dac outputs if the jitter spectrum contains large spectral peaks. it is highly recommended that the master clock be generated by an independent crystal oscillator. in addition, it is especially important that the clock signal should not be passed through an fpga or other large digital chip before being applied to the ad1838. in most cases, this will induce clock jitter due to the fact that the clock signal is sharing common power and ground connections with other unrelated digital output signals. reset and power-down pd / rst will power down the chip and set the control registers to their default settings. after pd / rst is deasserted, an initial- ization routine will run inside the ad1838 to clear all memories to zero. this initialization lasts for approximately 20 lrclk intervals. during this time, it is recommended that no spi writes occur. power supply and voltage reference the ad1838 is designed for 5 v supplies. separate power supply pins are provided for the analog and digital sections. these pins should be bypassed with 100 nf ceramic chip capacitors as close to the pins as possible, to minimize noise pickup. a bulk aluminum electrolytic capacitor of at least 22 f should also be provided on the same pc board as the codec. for critical applications, improved performance will be obtained with separate supplies for the analog and digital sections. if this is not possible, it is recommended that the analog and digital supplies be isolated by means of two ferrite beads in series with the bypass capacitor of each supply. it is important that the analog supply be as clean as possible. the internal voltage reference is brought out on the filtr pin and should be bypassed as close as possible to the chip, with a parallel combination of 10 f and 100 nf. the reference voltage may be used to bias external op amps to the common-mode voltage of the analog input and output signal pins. the current drawn from the filtr pin should be limited to less than 50 a. serial control port the ad1838 has an spi compatible control port to permit programming the internal control registers for the adcs and dacs, and to read the adc signal levels from the internal peak detectors. the spi control port is a 4-wire serial control port. the format is similar to the motorola spi format except the input data-word is 16 bits wide. the maximum serial bit clock frequency is 12.5 mhz and may be completely asynchronous to the sample rate of the adcs and dacs. figure 3 shows the format of the spi signal. serial data ports?ata format the adc serial data output mode defaults to the popular i 2 s format, where the data is delayed by 1 bclk interval from the edge of the lrclk. by changing bits 6 to 8 in adc control register 2, the serial mode can be changed to right-justified (rj), left-justified dsp (dsp), or left-justified (lj). in the rj mode, it is necessary to set bits 4 and 5 to define the width of the data-word. the dac serial data input mode defaults to i 2 s. by changing bits 5, 6, and 7 in dac control register 1, the mode can be changed to rj, dsp, lj, or packed mode 256. the word width defaults to 24 bits but can be changed by reprogramming bits 3 and 4 in dac control register 1. packed modes the ad1838 has a packed mode that allows a dsp or other controller to write to all dacs and read all adcs using one input data pin and one output data pin. packed mode 256 refers to the number of bclks in each frame. the lrclk is low while data from a left channel dac or adc is on the data pin, and high while data from a right channel dac or adc is on the data pin. dac data is applied on the dsdata1 pin, and adc data is available on the asd ata pin. figures 7 to 10 show the timing for the packed mode. packed mode is available only for 48 khz (based on mclk = 12.288 mhz) and when the m /s pin is low. auxiliary (tdm) mode a special auxiliary mode is provided to allow three external stereo adcs and one external stereo dac to be interfaced to the ad1838 to provide 8-in/8-out operation. in addition, this mode supports glueless interface to a single sharc dsp serial port, allowing a sharc dsp to access all eight channels of analog i/o. in this special mode, many pins are redefined; see table ii for a list of redefined pins. the auxiliary and the tdm interfaces are independently configurable to operate as masters or slaves. when the auxiliary interface is set as a master, by programming the aux mode bit in adc control register 2, auxlrclk and auxbclk are generated by the ad1838. when the auxiliary interface is set as a slave, the auxlrclk and auxbclk need to be generated by an external adc as shown in figure 13. the tdm interface can be set to operate as a master or slave by connecting the m /s pin to dgnd or odvdd, respectively. in master mode, the fstdm and bclk signals are outputs and are generated by the ad1838. in slave mode, the fstdm and bclk are inputs and should be generated by the sharc. slave mode operation is available for 48 khz and 96 khz opera- tion (based on a 12.288 mhz or 24.576 mhz mclk), and master mode operation is available for 48 khz only.
rev. a ad1838 ?3 clatch cclk cin cout d0 d8 d0 d15 d14 d9 d8 t cch t ccl d9 t cds t cdh t cls t clh t cod t cots t ccp t coe figure 3. format of spi timing lrclk bclk sdata lrclk bclk sdata lrclk bclk sdata lrclk bclk sdata left channel right channel left channel right channel left channel right channel msb msb msb msb msb msb msb msb lsb lsb lsb lsb lsb lsb lsb lsb left-justified mode16 bits to 24 bits per channel i 2 s mode16 bits to 24 bits per channel right-justified modes elect number of bits per channel dsp mode16 bits to 24 bits per channel 1/ f s notes 1. dsp mode does not identify channel. 2. lrclk normally operates at f s except for dsp mode which is 2 f s . 3. bclk frequency is normally 64 lrclk but may be operated in burst mode. figure 4. stereo serial modes
rev. a ?4 ad1838 t als abclk alrclk asdata le ft-justified mode asdata r ight-justified mode lsb asdata i 2 s mode t abh t abp t abl msb msb 1 msb t alh msb figure 5. adc serial mode timing t dls dbclk dlrclk dsdata le ft-justified mode dsdata r ight-justified mode lsb dsdata i 2 s mode t dbh t dbl t dds msb msb 1 t ddh t dds msb t ddh t dds t dds t ddh t ddh msb t dlh figure 6. dac serial mode timing
rev. a ad1838 ?5 lrclk bclk adc data slot 1 left slot 2 slot 5 right slot 6 msb msb ?1 msb ?2 32 bclks 256 bclks slot 3 slot 4 slot 7 slot 8 figure 7. adc packed mode 256 lrclk bclk dac data slot 1 left 1 slot 5 right 1 msb msb ?1 msb ?2 32 bclks 256 bclks slot 2 left 2 slot 3 left 3 slot 4 slot 6 right 2 slot 7 right 3 slot 8 figure 8. dac packed mode 256 abclk alrclk asdata msb msb 1 figure 9. adc packed mode timing dbclk dlrclk dsdata msb msb 1 figure 10. dac packed mode timing
rev. a ?6 ad1838 table ii. pin function changes in auxiliary mode pin name i 2 s mode aux mode asdata (o) i 2 s data out, internal adc tdm data out to sharc dsdata1 (i) i 2 s data in, internal dac1 tdm data in from sharc dsdata2 (i)/aauxdata1 (i) i 2 s data in, internal dac2 aux-i 2 s data in 1 (from ext. adc) dsdata3 (i)/aauxdata2 (i) i 2 s data in, internal dac3 aux-i 2 s data in 2 (from ext. adc) aauxdata3 (i) not connected aux-i 2 s data in 3 (from ext. adc) alrclk (o) lrclk for adc tdm frame sync out to sharc (fstdm) abclk (o) bclk for adc tdm bclk out to sharc dlrclk (i)/auxlrclk(i/o) lrclk in/out internal dacs aux lrclk in/out. driven by ext. lrclk from adc in slave mode. in master mode, driven by mclk/512. dbclk (i)/auxbclk(i/o) bclk in/out internal dacs aux bclk in/out. driven by ext. bclk from adc in slave mode. in master mode, driven by mclk/8. dauxdata(o) not connected aux-i 2 s data out (to ext. dac) fstdm internal adc l1 aux_adc l2 aux_adc l3 aux_adc l4 internal adc r1 aux_adc r2 aux_adc r3 aux_adc r4 internal dac l1 internal dac l2 internal dac l3 internal dac r1 internal dac r2 internal dac r3 msb tdm 1st ch left right i 2 s msb right i 2 s msb left bclk tdm asdata1 tdm (out) asdata dsdata1 tdm (in) dsdata1 aux lrclk i 2 s (from aux adc 1) aux bclk i 2 s (from aux adc 1) aauxdata1 (in) (from aux adc 1) aauxdata2 (in) (from aux adc 2) aauxdata3 (in) (from aux adc 3) aux bclk frequency is 64 frame rate; tdm bclk frequency is 256 frame rate. tdm interface aux i 2 s in terface msb tdm 8th ch 32 32 msb tdm 1st ch msb tdm 8th ch i 2 s msb right i 2 s msb left i 2 s msb right i 2 s msb left aux dac l4 aux dac r4 figure 11. aux-mode timing
rev. a ad1838 ?7 30mhz 12.288mhz sharc is always running in slave mode (interrupt driven). fsync-tdm (rfs) rxclk rxdata tfs (nc) txclk txdata asdata fstdm bclk dsdata1 lrclk bclk data mclk adc 1 slave sharc ad1838 master mclk dsdata3/aauxdata2 dsdata2/aauxdata1 dlrclk/auxlrclk lrclk bclk data mclk adc 2 slave lrclk bclk data mclk adc 1 slave aauxdata3 dbclk/auxbclk lrclk bclk data mclk dac 1 slave dauxdata figure 12. aux-mode connection to sharc (master mode) 30mhz 12.288mhz sharc is always running in slave mode (interrupt driven). fsync-tdm (rfs) rxclk rxdata tfs (nc) txclk txdata asdata fstdm bclk dsdata1 lrclk bclk data mclk adc 1 slave sharc ad1838 slave mclk dsdata3/aauxdata2 dsdata2/aauxdata1 dlrclk/auxlrclk lrclk bclk data mclk adc 2 slave lrclk bclk data mclk adc 1 master aauxdata3 dbclk/auxbclk lrclk bclk data mclk dac 1 slave dauxdata figure 13. aux-mode connection to sharc (slave mode)
rev. a ?8 ad1838 control/status registers the ad1838 has 13 control registers, 11 of which are used to set the operating mode of the part. the other two registers, adc peak 0 and adc peak 1, are read-only and should not be programmed. each of the registers is 10 bits wide with the ex ception of the adc peak reading registers, which are six bits wide. writing to a control register requires a 16-bit data frame to be transmitted. bits 15 to 12 are the address bits of the re quired register. bit 11 is a read/write bit. bit 10 is reserved and should always be programmed to 0. bits 9 to 0 contain the 10-bit value that is to be written to the register or, in the case of a read operation, the 10-bit register contents. figure 3 shows the format of the spi read and write operation. dac control registers the ad1838 register map has eight registers that are used to con- trol the functionality of the dac section of the part. the function of the bits in these registers is discussed below. sample rate these bits control the sample rate of the dacs. based on a 24.576 mhz imclk, sample rates of 48 khz, 96 khz, and 192 khz are available. the mclk scaling bits in adc con trol 3 should be programmed appropriately, based on the master clock frequency. power-down/reset this bit controls the power-down status of the dac section. by default, normal mode is selected. but by setting this bit, the digital section of the dac stage can be put into a low power mode, thus reducing the digital current. the analog output section of the dac stage is not powered down. dac data-word width these two bits set the word width of the dac data. compact disc (cd) compatibility may require 16 bits, but many modern digital audio formats require 24-bit sample resolution. dac data format the ad1838 serial data interface can be configured to be co mpatible with a choice of popular interface formats, including i 2 s, lj, rj, or dsp modes. details of these interface modes are given in the serial data ports section of this data sheet. de-emphasis the ad1838 provides built-in de-emphasis filtering for the three standard sample rates of 32.0 khz, 44.1 khz, and 48 khz. mute dac each of the six dacs in the ad1838 has its own independent mute control. setting the appropriate bit will mute the dac output. the ad1838 uses a clickless mute function that attenu- ates the output to approximately ?00 db over a number of cycles. stereo replicate setting this bit copies the digital data sent to the stereo pair dac 1 to the three other stereo dacs in the system. this allows all three stereo dacs to be driven by one digital data stream. note that in this mode, dac data sent to the other dacs is ignored. dac volume control each dac in the ad1838 has its own independent volume control. the volume of each dac can be adjusted in 1024 linear steps by programming the appropriate register. the de fault value for this register is 1023, which provides no attenu- ation, i.e., full volume. adc control registers the ad1838 register map has five registers that are used to control the functionality and to read the status of the adcs. the function of the bits in each of these registers is discussed below. adc peak level these two registers store the peak adc result from each channel when the adc peak readback function is enabled. the peak result is stored as a 6-bit number from 0 db to ?3 db in 1 db steps. the value contained in the register is reset once it has been read, allowing for continuous level adjustment as required. note that the adc peak level registers use the six most sign ificant bits in the register to store the results. sample rate this bit controls the sample rate of the adcs. based on a 24.576 mhz imclk, sample rates of 48 khz and 96 khz are available. the mclk scaling bits in adc control 3 should be programmed appropriately based on the master clock fre quency. adc power-down this bit controls the power-down status of the adc section and operates in a similar manner to the dac power-down. high-pass filter the adc signal path has a digital high-pass filter. enabling this filter will remove the effect of any dc offset in the analog input signal from the digital output codes. adc data-word width these two bits set the word width of the adc data. adc data format the ad1838 serial data interface can be configured to be co mpatible with a choice of popular interface formats, including i 2 s, lj, rj, or dsp modes. master/slave auxiliary mode when the ad1838 is operating in the auxiliary mode, the auxil iary adc control pins, auxbclk and auxlrclk, which connect to the external adcs, can be set to operate as a master or slave. if the pins are set in slave mode, one of the external adcs should provide the lrclk and bclk signals. adc peak readback setting this bit enables adc peak reading. see the adc section for more information.
rev. a ad1838 ?9 table iii. control register map register register reset address name description type width setting (hex) 0000 dacctrl1 dac control 1 r/ w 10 000 0001 dacctrl2 dac control 2 r/ w 10 000 0010 dacvol1 dac volume?eft 1 r/ w 10 3ff 0011 dacvol2 dac volume?ight 1 r/ w 10 3ff 0100 dacvol3 dac volume?eft 2 r/ w 10 3ff 0101 dacvol4 dac volume?ight 2 r/ w 10 3ff 0110 dacvol5 dac volume?eft 3 r/ w 10 3ff 0111 dacvol6 dac volume?ight 3 r/ w 10 3ff 1000 res reserved r/ w 10 reserved 1001 res reserved r/ w 10 reserved 1010 adcpeak0 adc left peak r 6 000 1011 adcpeak1 adc right peak r 6 000 1100 adcctrl1 adc control 1 r/ w 10 000 1101 adcctrl2 adc control 2 r/ w 10 000 1110 adcctrl3 adc control 3 r/ w 10 000 1111 reserved reserved r/ w 10 reserved table iv. dac control 1 function dac data dac data- power-down address r/ w res de-emphasis format word width reset sample rate 15, 14, 13, 12 11 10 9, 8 7, 6, 5 4, 3 2 1, 0 0000 0 0 00 = none 000 = i 2 s 00 = 24 bits 0 = normal 00 = 48 khz 01 = 44.1 khz 001 = rj 01 = 20 bits 1 = power-down 01 = 96 khz 10 = 32.0 khz 010 = dsp 10 = 16 bits 10 = 192 khz 11 = 48.0 khz 011 = lj 11 = reserved 11 = 48 khz 100 = pack mode 256 101 = reserved 110 = reserved 111 = reserved table v. dac control 2 function stereo mute dac address r/ w res reserved replicate reserved reserved outr3 outl3 outr2 outl2 outr1 outl1 15, 14, 13, 12 11 10 9 8 7 6 543210 0001 0 0 0 0 = off 0 0 0 = on 0 = on 0 = on 0 = on 0 = on 0 = on 1 = replicate 1 = mute 1 = mute 1 = mute 1 = mute 1 = mute 1 = mute
rev. a ?0 ad1838 table vi. dac volume control function address r/ w res dac volume 15, 14, 13, 12 11 10 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 0010 = dacl1 0 0 0000000000 = mute 0011 = dacr1 0000000001 = 1/1023 0100 = dacl2 0000000010 = 2/1023 0101 = dacr2 1111111110 = 1022/1023 0110 = dacl3 1111111111 = 1023/1023 0111 = dacr3 table vii. adc peak function four fixed address r/ w res six data bits bits 15, 14, 13, 12 11 10 9, 8, 7, 6, 5, 4 3, 2, 1, 0 1010 = left adc 1 0 000000 = 0.0 dbfs 0000 1011 = right adc 000001 = ?.0 dbfs 000010 = ?.0 dbfs t hese four bits are always zero. 111111 = ?3.0 dbfs table viii. adc control 1 function adc sample address r/ w res res filter power-down rate reserved 15, 14, 13, 12 11 10 9 8 7 6 5, 4, 3, 2, 1, 0 1100 0 0 0 0 = all pass 0 = normal 0 = 48 khz 0, 0, 0, 0, 0, 0 1 = high-pass 1 = power-down 1 = 96 khz 0, 0, 0, 0, 0, 0 table ix. adc control 2 function r/ w master/slave adc adc data- adc mute address res res aux mode data format word width auxdata reserved right left 15, 14, 13, 12 11 10 9 8, 7, 6 5,4 3 2 1 0 1101 0 0 0 = slave 000 = i 2 s 00 = 24 bits 0 = disabled 0 0 = on 0 = on 1 = master 001 = rj 01 = 20 bits 1 = enabled 1 = mute 1 = mute 010 = dsp 10 = 16 bits 011 = lj 11 = reserved 100 = packed 256 101 = reserved 110 = auxiliary 256 111 = reserved table x. adc control 3 function r/ w imclk adc dac adc address res res reserved clocking scaling peak readback test mode test mode 15, 14, 13, 12 11 10 9, 8 7, 6 5 4, 3, 2 1, 0 1110 0 0 0, 0 00 = mclk 20 = disabled peak readback 000 = normal mode 00 = normal mode 01 = mclk 1 = enabled peak readback all others reserved all others reserved 10 = mclk 2/3 11 = mclk 2
rev. a ad1838 ?1 5.76k 100pf npo a udio input 600z + 47 f 5.76k v ref op275 120pf npo 5.76k 5.76k 750k 237 1nf npo 237 1nf npo 100pf npo adcxp adcxn v ref op275 figure 14. typical adc input filter circuit 3.01k 11k 270pf npo 560pf npo 68pf npo 11k 150pf npo 1.5k 5.62k 5.62k 604 2.2nf npo outlpx a udio output op275 outlnx figure 15. typical dac output filter circuit
rev. a ?2 ad1838 outline dimensions 52-lead metric quad flat package [mqfp] (s-52) dimensions shown in millimeters seating plane view a 0.23 0.11 2.45 max 1.03 0.88 0.73 top view (pins down) 1 39 40 13 14 27 26 52 pin 1 0.65 bsc 13.45 13.20 sq 12.95 7.80 ref 10.20 10.00 sq 9.80 0.40 0.22 view a rotated 90 ccw 7 0 2.20 2.00 1.80 0.13 min coplanarity compliant to jedec standards ms-022-ac
rev. a ad1838 ?3 revision history location page 8/03?ata sheet changed from rev. 0 to rev. a. changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 changes to figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 replaced figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 changes to table iv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 changes to table ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 changes to figure 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
c02954??/03(a) ?4

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