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sdram as4sd8m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 as4sd8m16 rev. 1.0 3/00 features ? single 3.3v power supply ? fully synchronous to positive clock edge ? sdram cas latency = 2 (66 mhz), 3 (75 mhz or 83 mhz) ? burst operation sequential or interleave burst length = programmable 1, 2, 4, 8 or full page burst read and write multiple burst read and single write ? data mask control per byte ? auto refresh (cbr) and self refresh 4096 refresh cycles across 64ms ? automatic and controlled precharge commands ? suspend mode and power down mode options marking ? timing 12ns access -12 ? package(s) ? plastic 54-pin tsop dg no. 901 pin assignment (top view) general description the as4sd8m16 is a synchronous, high data rate, 134,217,728 bit dram organized as 4 x 2,097,152 words x 16 bits. the synchronous design allows precise cycle control with the use of system clock, i/o transactions are possible on every clock cycle. range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. the as4sd8m16 comes in a 54 pin tsop package and is tested over the industrial temp range (-40c to +85c) providing a solution for rugged main memory applications. 8m x 16 sdram synchronous dram memory for more products and information please visit our web site at www.austinsemiconductor.com pin description clk clock input cke clock enable ras\ row address strobe cas\ column address strobe we\ write enable ce\ chip select a0-a11 address inputs ba0, ba1 bank select address dq0-dq15 data input/output l(u)dqm data input/output mask v cc power (3.3v) v ccq data output power v ss ground v ssq data output ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 vss nc/rfu udqm clk cke nc a11 a9 a8 a7 a6 a5 a4 vss vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 vdd ldqm we\ cas\ ras\ ce\ ba0 ba1 a10/ap a0 a1 a2 a3 vdd
sdram as4sd8m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 as4sd8m16 rev. 1.0 3/00 input/output functional description symbol type signal polarity function clk input pulse positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke input level active high activates the clk signal when high and deactivates the clk signal when low. by deactivating the clock, cke low initiates the power down mode, suspend mode, or the self refresh mode. ce input pulse active low ce disable or enable device operation by masking or enabling all inputs except ck0, cke and dqm. ras, cas, we input pulse active low when sampled at the positive rising edge of the clock, cas, ras, we define the operation to be executed by the sdram. ba0,ba1 input level --- selects which sdram bank is to be active. during a bank activate command cycle, a0-a11 defines the row address (ra0-ra11) when sampled at the rising clock edge. during a read or write command cycle, a0-a7 defines the column address (ca0-ca7) when sampled at the rising edge of the clock. in additions to the row address, a10/ap is used to invoke autoprecharge operation at the end of the burst read or write cycles. if a10/ap is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if a10/ap is low, autoprecharge is disabled. during a precharge command cycle, a10/ap is used in conjunction with ba0, ba1 to control which bank(s) to precharge. if a10/ap is high, all banks will be precharged regardless of the state of ba0, ba1. if a10/ap is low, then ba0, ba1 is used to define which bank to precharge. dq0-dq15 input output level --- data input/output are multiplexed on the same pins. l(u)dqm input pulse mask active high the data input/output mask places the dq buffers in a high impedance state when sampled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like and output enable. in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if dqm is high. vdd, vss supply power and ground for the input buffers and the core logic. vddq, vssq supply isolated power and ground for the output buffers to improve noise immunity. a0-a11, a10/ap input level ---
sdram as4sd8m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 as4sd8m16 rev. 1.0 3/00 recommended dc operating characteristics voltage referenced to vss = 0v, t a = -40c to +85c capacitance (t a =25c, f=1mhz, vdd = 3.3v to 3.6v) power supply voltage..............................................-1.0v to +4.6v input voltage.............................................................-1.0v to +4.6v output voltage..........................................................-1.0v to +4.6v operating temperature..........................................-40c to +85c storage temperature............................................-55 c to +125 c short circuit output current (per i/o)............................50ma power dissipation .................................................................1.0 w *stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional opera- tion of the device at these or any other conditions above those indicated in the operation section of this specifica- tion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. min. typ. max. vdd supply voltage 3.0 3.3 3.6 v v ih input high voltage 2.0 3.0 vdd + 0.3 v v il input low voltage -0.3 --- 0.8 v v oh output high voltage 2.4 --- --- v i oh = -2ma v ol output low voltage --- --- 0.4 v i ol = 2ma i il input leakage voltage -5 --- 5 a i ol output leakage voltage -5 --- 5 a notes rating symbol parameter units symbol parameter typ max units notes c i1 input capacitance (a0-a12, ba) 4 pf c i2 input capacitance (clk, cke, ras, cas, we, ce, dqm) 4 pf c out input/output capacitance (dq0-dq71) 5 pf absolute maximum ratings *
sdram as4sd8m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 as4sd8m16 rev. 1.0 3/00 operating current characteristics parameter symbol test condition -12 units notes operating current (one bank active) i cc1 burst length = 1 t rc > t rc (min) 125 ma operating current (burst mode) i cc4 page burst, 2 banks active t ccd = 2 clocks 165 ma i cc2 p cke < v il (max), t ck = 15ns 2ma i cc2 ps cke, clk< v il (max) t ck = infinity, inputs stable 2ma i cc1 n cke < v ih , t ck = 15ns input chagne every 30ns 50 ma i cc1 ns cke> v ih (min) t ck = infinity no input change 35 ma i cc3 p cke< v il (max), t ck = 15ns 12 ma i cc3 ps cke< v il (max), t ck = infinity 12 ma i cc2 n cke < v ih , t ck = 15ns input chagne every 30ns 30 ma i cc2 ns cke> v ih (min) t ck = infinity no input change 20 ma refresh current i cc5 t rc > t rc (min) 210 ma 2 self refresh current i cc6 cke< 0.2v 3 ma precharge standby current in power down mode precharge standby current in non- power down mode active standby current in power down mode active standby current in non-power down mode
sdram as4sd8m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 as4sd8m16 rev. 1.0 3/00 recommended ac operating characteristics min max cas latency = 3 12 1000 cas latency = 2 15 1000 t sac --- 8 ns 1,2 t oh 3 --- ns 2 t ch 4.0 --- ns 3 t cl 4.0 --- ns 3 t ss 3 --- ns 3 t sh 1 --- ns 3 t slz 1 --- ns 2 t shz --- 8 ns t rrd 24 --- ns 4 t rcd 26 --- ns 4 t rp 26 --- ns 4 t ras 60 100,000 ns 4 t rc 90 --- ns 4 t rfc 90 --- ns 4,8 t cdl 1 --- clk 5 t rdl 1 --- clk 5 t bdl 1 --- clk 5 t ccd 1 --- clk 6 cas latency = 3 2 --- cas latency = 2 1 --- input hold time clock high pulse width clock low pulse width column address to column address delay last data in to burst stop last data in to row precharge last data in to new column address delay row cycle time (auto refresh) row cycle time (operation) row active time row precharge time notes ns 1 clock to valid output delay parameter symbol units number of valid output data ea output data hold time input set-up time clk to output low-z clk to output high-z -12 t cc clock cycle time 7 row active to row active delay ras\ to cas\ delay notes: 1) parameters depend on programmed cas latency. 2) if clock rise item is longer then 1ns, (t rise /2-0.5)ns should be added to the parameter. 3) assumed input rise and fall time = 1ns. if t rise or t fall are longer than 1ns. ((t rise + t fall )/2)-1ns should be added to the param- eter. 4) the minimum number of clock cycles required is determined by dividing the minimum time required by the clock cycle time and then rounding up to the higher integer. 5) minimum delay is required to complete write. 6) all devices allow every cycle column address changes 7) in case of row precharge interrupt, auto precharge and read burst stop. 8) a new command may be given t rfc after self refresh exit.
sdram as4sd8m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 as4sd8m16 rev. 1.0 3/00 refresh cycle parameters min max t ref refresh period --- 64 ms 1,2 t srex self refresh exit time t rfc --- ns 3 notes -12 symbol parameter units notes: 1) 4,096 cycles 2) any time that the refresh period has been exceeded, a minimum of two auto (cbr) refresh commands must be to wake- up the device. 3) the self refresh in exited by restarting the external clock and then asserting cke high. this must be followed by nops for a minimum time of t rfc before the sdram reaches idle state to begin normal operation. clock frequency and latency parameters (units in number of clocks) t rc t ras t rp t rrd t rcd t ccd t cdl t rdl 90ns 60ns 26ns 24ns 26ns 12ns 12ns 12ns 83mhz (12ns) 3 8 5 3 2 3 1 1 1 75mhz (12ns) 3 7 5 2 2 2 1 1 1 66mhz (15ns) 2 6 4 2 2 2 1 1 1 frequency cas latency
sdram as4sd8m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 as4sd8m16 rev. 1.0 3/00 command truth table previous cycle current cycle mode register set h x l l l l x auto (cbr) refresh h h l l l h x x x x entry self refresh h l l l l h x x x x single bank precharge h x l l h l x ba l x 2 precharge all banks h x l l h l x x h x bank activate h x l l h h x ba 2 write h x l h l l x ba l column 2 write with auto-precharge h x l h l l x ba h column 2 read h x l h l h x ba l column 2 read with auto-precharge h x l h l h x ba h column 2 burst termination h x l h h l x x x x 3 no operation h x l h h h x x x x device deselect h x h x x x x x x x clock suspend/standby mode l x x x x x x x x x 4 data write/output enable h x x x x x l x x x 5 data mask/output disable h x x x x x h x x x 5 power down mode entry x l h x x x x x x x 6 power down mode exit x h h x x x x x x x 6 row address ce cke function op code dqm we cas ras notes a12, a11, a9-a0 a10/ap ba notes: 1) all of the sdram operations are defined by states of ce, we, ras, cas, and dqm at the positive rising edge of the clock. 2) bank select (ba), if ba0, ba1 = 0,0 then bank a is selected; if ba0, ba1 = 1,0 then bank b is selected; if ba0, ba1 = 0,1 then bank c is selected; if ba0, ba1 = 1,1 then bank d is selected, respectively. 3) during a burst write cycle there is a zero clock delay, for a burst read cycle the delay is equal to the cas latency. 4) during normal access mode, cke is held high and clk is enabled. when it is low, it freezes the internal clock and extends data read and write operations. one clock delay is required for mode entry and exit. 5) the dqm has two functions for the data dq read and write operations. during a read cycle, when dqm goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. dqm also provides a data mask function for write cycles. when it activates, the write operation at the clock is prohibited (zero clock latency). 6) all banks must be precharged before entering the power down mode. the power down mode does not preform any refresh operations, therefore the device cant remain in this mode longer than the refresh period (t ref ) of the device. one clock delay is required for mode entry and exit.
sdram as4sd8m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 as4sd8m16 rev. 1.0 3/00 clock enable (cke0) truth table previous cycle current cycle ce ras cas we ba a12-a0 h x x x x x x x invalid 1 lhhxxxxx exit self refresh with device deselect 2 lhlhhhxx exit self refresh with no operation 2 l h l h h l x x illegal 2 l h l h l x x x illegal 2 l h l l x x x x illegal 2 l l x x x x x x maintain self refresh h x x x x x x x invalid 1 lhhxxxxx power down mode exit, all banks idle 2 l h l x x x x x illegal 2 l l x x x x x x maintain power down mode hhhxxx 3 hhlhxx 3 hhllhx 3 h h l l l h x x cbr refresh h h l l l l mode register set 4 hlhxxx 3 hllhxx 3 hlllhx 3 h l l l l h x x entry self refresh 4 h l l l l l mode register set l x x x x x x x power down 4 hhxxxxxx refer to operations in the current state truth table hlxxxxxx begin clock suspend next cycle 5 l h x x x x x x exit clock suspend next cycle l l x x x x x x maintain clock suspend notes self refresh power down all banks idle refer to the idle state section of the current state truth table cke command current state action any state other than listed above op code op code refer to the idle state section of the current state truth table notes: 1) for the given current state cke must be low in the previous cycle. 2) when cke has a low to high transition, the clock and other inputs are re-enabled asynchronously. the minimum setup time for cke (t cks ) must be satisfied before any command other than exit is issued. 3) the address inputs (a12-a0) depend on the command that is issued. see the idle state section of the current state truth tab le for more information. 4) the power down mode, self refresh mode, and the mode register set can only be entered from the all banks idle state. 5) must be a legal command as defined in the current state truth table.
sdram as4sd8m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 as4sd8m16 rev. 1.0 3/00 current state truth table ce ras cas we ba a12, a11 a10/ap-a0 description l l l l mode register set set the mode register 1 l l l h x x auto or self refresh start auto or self refresh 2 l l h l x x precharge no operation 2 l l h h ba row address bank activate activate the specified bank and row 2 l h l l ba column write w/o precharge illegal 2 l h l h ba column read w/o precharge illegal 2 l h h l x x burst termination no operation l h h h x x no operation no operation 1 h x x x x x device deselect no operation or power down 2 l l l l mode register set illegal 2 l l l h x x auto or self refresh illegal l l h l x x precharge precharge 3 l l h h ba row address bank activate illegal 3 l h l l ba column write start write; determine if auto precharge 3 l h l h ba column read start read; determine if auto precharge l h h l x x burst termination no operation 4 l h h h x x no operation no operation 3 h x x x x x device deselect no operation 3 l l l l mode register set illegal 3 l l l h x x auto or self refresh illegal 4 l l h l x x precharge terminate burst; start the precharge l l h h ba row address bank activate power down 4 l h l l ba column write terminate burst; start the write cycle l h l h ba column read terminate burst; start a new read cycle 5 l h h l x x burst termination terminate the burst l h h h x x no operation continue the burst h x x x x x device deselect continue the burst idle row active read op code op code op code notes current state action command
sdram as4sd8m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 as4sd8m16 rev. 1.0 3/00 current state truth table (continued) ce ras cas we ba a12, a11 a10/ap-a0 description l l l l mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge terminate burst; start the precharge l l h h ba row address bank activate illegal 4 l h l l ba column write terminat burst; start a new write cycle 8, 9 l h l h ba column read terminate burst; start the read cycle 8, 9 l h h l x x burst termination terminate the burst l h h h x x no operation continue the burst h x x x x x device deselect continue the burst l l l l mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge illegal 4 l l h h ba row address bank activate illegal 4 l h l l ba column write illegal l h l h ba column read illegal lhhlx x burst termination illegal l h h h x x no operation continue the burst h x x x x x device deselect continue the burst l l l l mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge illegal 4 l l h h ba row address bank activate illegal 4 l h l l ba column write illegal l h l h ba column read illegal l h h l x x burst termination illegal l h h h x x no operation continue the burst h x x x x x device deselect continue the burst write read with auto precharge write with auto precharge op code op code op code notes current state action command
sdram as4sd8m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 11 as4sd8m16 rev. 1.0 3/00 current state truth table (continued) ce ras cas we ba a12, a11 a10/ap-a0 description l l l l mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge no operation; bank(s) idle after t rp l l h h ba row address bank activate illegal 4 l h l l ba column write illegal 4 l h l h ba column read illegal 4 l h h l x x burst termination no operation; bank(s) idle after t rp l h h h x x no operation no operation; bank(s) idle after t rp h x x x x x device deselect no operation; bank(s) idle after t rp l l l l mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge illegal 4 l l h h ba row address bank activate illegal 4, 10 l h l l ba column write illegal 4 l h l h ba column read illegal 4 lhhlx x burst termination no operation; bank(s) idle after t rcd l h h h x x no operation no operation; bank(s) idle after t rcd h x x x x x device deselect no operation; bank(s) idle after t rcd l l l l mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge illegal 4 l l h h ba row address bank activate illegal 4 l h l l ba column write start write; determine if auto precharge 9 l h l h ba column read start read; determine if auto precharge 9 lhhlx x burst termination no operation; bank(s) idle after t dpl l h h h x x no operation no operation; bank(s) idle after t dpl h x x x x x device deselect no operation; bank(s) idle after t dpl precharging row activating write recovering op code op code op code notes current state action command
sdram as4sd8m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 12 as4sd8m16 rev. 1.0 3/00 current state truth table (continued) ce ras cas we ba a12, a11 a10/ap-a0 description l l l l mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge illegal 4 l l h h ba row address bank activate illegal 4 l h l l ba column write illegal 4, 9 l h l h ba column read illegal 4, 9 l h h l x x burst termination no operation; bank(s) idle after t dpl l h h h x x no operation no operation; bank(s) idle after t dpl h x x x x x device deselect no operation; bank(s) idle after t dpl l l l l mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge illegal l l h h ba row address bank activate illegal l h l l ba column write illegal l h l h ba column read illegal l h h l x x burst termination no operation; bank(s) idle after t rc l h h h x x no operation no operation; bank(s) idle after t rc h x x x x x device deselect no operation; bank(s) idle after t rc l l l l mode register set illegal l l l h x x auto or self refresh illegal l l h l x x precharge illegal l l h h ba row address bank activate illegal l h l l ba column write illegal l h l h ba column read illegal l h h l x x burst termination illegal l h h h x x no operation no operation; idle after two clock cycles h x x x x x device deselect no operation; idle after two clock cycles write recovering with auto precharge refreshing mode register accessing op code op code op code notes current state action command notes on following page.
sdram as4sd8m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 13 as4sd8m16 rev. 1.0 3/00 notes: 1) cke is assumed to be active (high) in the previous cycle for all entries. the current state is the state of the bank that t he command is being applied to. 2) all banks must be idle otherwise it is an illegal action. 3) if cke is active (high) the sdram starts the auto (cbr) refresh operation, if cke is inactive (low) then the self refresh mode is entered. 4) the current state refers only to one of the banks, if ba0, ba1 selects this bank then the action is illegal. if ba0, ba1 selects the bank not being referenced by the current state then the action may be legal depending on the state of that bank. 5) if cke is inactive (low) then the power down mode is entered, otherwise there is a no operation. 6) the minimum and maximum active time (t ras ) must be satisfied. 7) the ras to cas delay (t rcd ) must occur before the command is given. 8) address a10 is used to determine if the auto precharge function is activated. 9) the command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10) the command is illegal if the minimum bank to bank delay time (t rrd ) is not satisfied. mechanical definitions* asi case #901 (package designator dg) * all measurements are in inches (millimeters), max unless noted otherwise. package width and length do not include mold protrusion (0.25mm allowable per side). min .403(10.24) .397(10.08) .008(0.20) .002(0.05)
sdram as4sd8m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 14 as4sd8m16 rev. 1.0 3/00 ordering information *available processes it = industrial temperature range -40 o c to +85 o c device number package type speed ns process as4sd8m16 dg - 12 /* example: as4sd8m16dg-12/it

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