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?1 CXB1583Q e96501-st 266mbaud fibre channel transceiver ic description the CXB1583Q is a transceiver ic with the built-in plls into a single chip. for receiver, the 265.625mbaud serial data is received and it is output as a 10-bit parallel data; for transmitter, the 265.625mbaud 10-bit parallel data is received and it is output as a serial data after conversion. features transmitter/receiver into a single chip conforms to ansi x3t11 fibre channel standard pll for a clock synthesizing and for clock recovery single 3.3v power supply low power consumption: 860mw (typ.) 80-pin plastic package comma signal detector test pattern (k28.5) generation circuit loop-back circuit supports data rage of 200mbaud pin configuration applications 265.625mbaud fibre channel structure bipolar silicon monolithic ic sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 sdout sdout * v cc e v ee e txsin txsin * lol v ee g v cc g eckenb * v ee g v cc g lpbk altenb * tpgen * txser refclk v ee t v cc g v ee g ms1 ms0 cdetenb v cc t por * txlkdt rxlkdt v ee t v ee g pclkout0 pclkout1 v ee g v cc g cdet pdo9 pdo8 v ee t v cc g lckref * lpfd lpfc v ee p2 lpfb lpfa v cc g txsout * txsout v ee e v cc e sdin * sdin tjmon rext eck * eck v ee p1 v cc p v ee g pdi1 pdi5 pdi7 pdi4 pdi2 pdi3 pdi6 pdi9 pdi0 pdi8 pdo6 pdo0 pdo1 v ee t pdo2 v cc t pdo3 pdo4 v ee t pdo5 pdo7 v cc t 80 pin qfp (plastic)
?2 CXB1583Q absolute maximum ratings (v ee e, v ee t, v ee g, v ee p = 0v) item unit v v v v ma ma ma ? ? 4 5.5 v cc 2 0 20 0 70 150 ?.3 ?.5 v cc ?2 ? ?0 0 ?0 ?5 ?5 v cc v i _t v i _e v is _e i oh _t i ol _t i o _e ta tstg power supply ttl dc input voltage ecl dc input voltage ecl differential input voltage ttl output current (high level) ttl output current (low level) ecl output current operating ambient temperature storage temperature max. typ. min. symbol recommended operating conditions (v ee e, v ee t, v ee g, v ee p = 0v) item unit v ? 3.465 70 3.3 3.135 0 v cc ta supply voltage ambient temperature max. typ. min. symbol
?3 CXB1583Q block diagram 10 pclkout0 pclkout1 s/p rx_pll lpfa lpfb rext v ee p cdet pdo (0 to 9) pdi (0 to 9) altenb * refclk tx_pll p/s 1 0 dq k28.5 gen. 10 26.6mbps refclk (26.6mhz) rtdata rxclk (266mhz) rpclk (26.6m) 10 26.6mbps txload (266mhz) txclk (26.6mhz) 0 1 sout pin rxlkdt txsin * txsin txser tpgen * txlkdt sdout * sdout txsout * txsout 0 1 lol sdin * sdin lpbk lpfc lpfd lckref * cdetenb
?4 CXB1583Q pin description pin no. symbol type typical pin i/o voltage equivalent circuit description 1 to 10 pdi0 to 9 ttl input ttl level parallel data input. 11, 12, 14, 16, 17, 19, 20, 24, 26, 27 pdo0 to 9 ttl output ttl level parallel data output. 13, 18, 25, 33, 78 v ee t power supply 0v negative power supply for ttl input/output. 15, 23, 37 v cc t power supply 3.3v positive power supply for ttl output. 21, 30, 42, 68, 71, 80 v ee g power supply 0v negative power supply for internal logic gate. 22, 29, 41, 69, 72, 79 v cc g power supply 3.3v positive power supply for internal logic gate. 28 cdet ttl output ttl level byte synchronization output. outputs high level when +comma (0011111) or ?omma (1100000) is detected to the serial data. v ee g v cc g ttl-in v ee t v ee t v cc t ttl-out v ee t v cc t ttl-out
?5 CXB1583Q pin no. symbol type typical pin i/o voltage equivalent circuit description 32 pclkout0 ttl output ttl level receive byte clock 0 output. this clock is used to take the parallel data (pdo0 to 9) at the next-stage system. v ee t v cc t ttl-out 31 pclkout1 ttl output ttl level 34 rxlkdt ttl output ttl level receive byte clock 1 output. pclkout0 inverted clock. rx_pll lock detection signal output. outputs high level when the pll is locked to the serial data or the serial data has no signal; outputs low level when the pll is not locked. rxlkdt output may sporadically go high when the pll starts to lock to the serial data. 35 txlkdt ttl output ttl level tx_pll lock detection signal output. outputs high level when the pll is locked to refclk and operating normally; outputs low level when the pll is not operating normally. v ee t v cc t ttl-out v ee t v cc t ttl-out v ee t v cc t ttl-out
?6 CXB1583Q pin no. symbol type typical pin i/o voltage equivalent circuit description 36 por * ttl output ttl level power-on reset signal output. outputs high level after the power is turned on and low level is held for approximately 100ns. v ee t v cc t ttl-out 38 cdetenb ttl input ttl level byte synchronization enable signal input. when high level is input, +comma (0011111) or ?omma (1100000) is detected and the parallel data is synchronized with this byte. (see the timing chart.) when low level is input, byte synchronization is not performed. v ee g v cc g ttl-in v ee t 39, 40 ms0, ms1 ttl input 3.3 v or ttl high level test pin. connect to vcc. v ee g v cc g ttl-in v ee t 43, 44 sdin sdin * ecl input (differ- ential) ecl level serial data input. 45, 63 v cc e power supply 3.3v positive power supply for ecl input/output. 46, 64 v ee e power supply 0v negative power supply for ecl input/output. v ee e ecl-in * ecl-in v cc e v ee g v cc g v cc e ?1.3v
?7 CXB1583Q pin no. symbol type typical pin i/o voltage equivalent circuit description 47, 48 txsout txsout * ecl output (differ- ential) ecl level parallel/serial conversion output. this output is enabled when txser is high. v cc e v ee e ecl-out ecl-out * 49, 50 eck eck * ecl output (differ- ential) one is left open; another is connected to vcc via 47k w . test pin. connect either of these pins to vcc via a 47k w resistor. 51 v cc p power supply 3.3v positive power supply for internal pll. 52, 53 lpfa lpfb ex- ternal part con- nection rx_pll external loop filter connection. (see fig. 1 of the notes on operation.) 54, 55 v ee p1 v ee p2 power supply 0v negative power supply for internal pll. v ee e ecl-in * ecl-in v cc e v ee g v cc g v cc e ?1.3v v ee p1 v cc p lpf_c lpf_d v ee p2 56 rext ex- ternal part con- nection connects the resistor which determines the vco center frequency. (see fig. 1 of the notes on operation.) v cc p v ee p2 rext
?8 CXB1583Q pin no. symbol type typical pin i/o voltage equivalent circuit description 57 tjmon test pin 0v junction temperature measurement. v cc p v ee e2 tjmon 58, 59 lpfc lpfd ex- ternal part con- nection tx_pll external loop filter connection. (see fig. 1 of the notes on operation.) v ee p1 v cc p lpf_c lpf_d v ee p2 60 lckref * ttl input ttl level lock-to-reference signal input. when this pin is set to low level, rx_pll is forcibly locked to refclk. v cc g v ee g v ee t ttl-in 61, 62 sdout sdout * ecl output (differ- ential) ecl level serial data output for transmission. the serial data order is pdi0 ? pdi9. v cc e v ee e ecl-out ecl-out *
?9 CXB1583Q pin no. symbol type typical pin i/o voltage equivalent circuit description 65, 66 txsin txsin * ecl input (differ- ential) ecl level serial ecl data input. when txser is high, this input signal is output from sdout. v ee e ecl-in * ecl-in v cc e v ee g v cc g v cc e ?1.3v 67 lol ecl input (single phase) open or ecl level lost-of-light signal input. low level when this pin is left open. v ee e ecl-in v cc e v ee g v cc g v cc e ?1.3v 70 eckenb * ttl input 3.3v or ttl high level test pin. v ee g v cc g ttl-in v ee t 73 lpbk ttl input ttl level loop-back enable. if lpbk is set to high, the signal output from sdout when lpbk is low is transmitted to the rx input with the internal connection. in this time, sdout/ sdout * are fixed to low/high respectively and sdin/sdin * are both disabled. v ee g v cc g ttl-in v ee t
?10 CXB1583Q pin no. symbol type typical pin i/o voltage equivalent circuit description 74 altenb * ttl input ttl level alternate disparity test pattern generation enable. when altenb * is set to low with tpgen * low, k28.5 (+k28.5, ?28.5) is generated for the data stream output. when this pin is high, +k28.5 is generated. v ee g v cc g ttl-in v ee t 75 tpgen * ttl input ttl level test pattern generation enable. when this pin is low, +k28.5 (altenb * : high) or k28.5 (altenb * : low) is generated for the data stream output. v ee g v cc g ttl-in v ee t 76 txser ttl input ttl level transmit serial data selector. when this pin is high, the serial data input from txsin is output from sdout and the serialized pdi0 to 9 signals are output from txsout. v ee g v cc g ttl-in v ee t 77 refclk ttl input ttl level transmit byte clock. this clock is used to take the pdi0 to 9 signals in the txpll. the rxpll takes the frequency from refclk when lckref * is low. refclk is necessary after lckref * is set to high and the rxpll is locked to the serial data. v ee g v cc g ttl-in v ee t
?11 CXB1583Q CXB1583Q functions 1. data map to the 8b/10b alphabet notation pdi0 is the start bit. pdi, pdo 0 1 2 3 4 5 6 7 8 9 8b/10b alphabet notation abcde i fghj input txser low low high high lpbk low high low high txsout disabled/static disabled/static serialized pdi serialized pdi sdout serialized pdi disabled/static txsin disabled/static output pdo0 to 9 sdin pdi sdin txsin 2. comma detect when cdetenb is high and the sdin input data row includes k28.5, pdo0 to 9 are synchronized with k28.5 and output. byte synchronization is also performed to comma. serial data pdo0 a +k28.5 comma (positive) comma (negative) ?28.5 0 0 1 1 b 0 0 1 1 c 1 1 0 0 d 1 1 0 0 e 1 1 0 0 i 1 1 0 0 f 1 1 0 0 g 0 x x 1 h 1 x x 0 pdo9 j 0 x x 1 3. txser, lpbk operation modes lckref input level rxpll comparison signal high low sdin, sdin * refclk 4. lckref * operation modes cdetenb input level operation high low byte synchronization with the comma signal byte synchronization function stop 5. cdetenb
?12 CXB1583Q electrical characteristics dc characteristics (under the recommended operating conditions) ttl high level input voltage ttl low level input voltage ttl high level input current ttl low level input current ttl high level output voltage ttl low level output voltage ecl high level input voltage ecl low level input voltage ecl differential input voltage ecl high level output voltage ecl low level output voltage ecl output amplitude current consumption power consumption item v ih _t v il _t i ih _t i il _t v oh _t v ol _t v ih _e v il _e v is _e v oh _e v ol _e v os _e i cc p d symbol 2 0 ?00 2.2 v cc ?1.17 v cc ?1.81 200 v cc ?1.05 v cc ?1.81 650 min. 260 0.86 typ. v v ? ? v v v v mv v v mv ma w unit v ih = v cc v il = 0 i oh = ?.4ma i ol = 2ma ac coupling input 50 w terminated to vcc ?2 v 50 w terminated to vcc ?2 v 50 w terminated to vcc ?2 v output pins open output pins open conditions 5.5 0.8 20 0.5 v cc ?0.88 v cc ?1.48 1000 v cc ?0.81 v cc ?1.55 341 1.18 max.
?13 CXB1583Q ac characteristics (under the recommended operating conditions) pdi rise time pdi fall time refclk rise time refclk fall time ttl output rise time ttl output fall time ecl output rise time ecl output fall time sdin data rate refclk cycle tolerance refclk duty cycle pclkout0 and 1 skew pdi setup time pdi hold time pdo setup time pdo hold time tx deterministic jitter (p-p) tx random jitter (p-p) rx jitter tolerance item tir_pdi tif_pdi tir_rfck tif_rfck tor_t tof_t tor_e tof_e r_sdin ttol_rfck dc_rfck tskew ti_s ti_h to_s to_h dj rj jt symbol 0.375 0.375 190 ?00 40 ? 4 3 10 12 min. 0 typ. ns ns ns ns ns ns ps ps mbaud ppm % ns ns ns ns ns ui ui ui unit 0.8 to 2.0v 2.0 to 0.8v 0.8 to 2.0v 2.0 to 0.8v 0.8 to 2.0v, cl = 10pf 2.0 to 0.8v, cl = 10pf 20 to 80%, cl = 2pf 20 to 80%, cl = 2pf sdin cycle reference refclk reference refclk reference pclkout0 reference pclkout0 reference serial data output serial data output serial data input conditions 10 10 5 5 5 5 500 500 280 200 60 3 0.08 0.15 0.7 max. pll ac characteristics (under the recommended operating conditions) tx/px pll frequency acquisition time rx pll bit synchronization time item tfa tbs symbol min. typ. ? bit unit loop damping capacitance = 0.01f conditions 500 2500 max.
?14 CXB1583Q tir_rfck 2.0v 1.5v 0.8v 2.0v 1.5v 0.8v valid valid ti_h ti_s tir_pdi tif_pdi tif_rfck refclk pdi0 to 9 timing chart for tx timing chart for rx 1.5v tskew pclkout1 2.2v 1.5v 0.6v pclkout0 th_pck 2.2v 0.6v valid valid pdo0 to 9 tl_pck tor_pck tof_pck to_h to_s tor_pdo tof_pdo
?15 CXB1583Q electrical characteristics measurement circuit (see ?ig. 3 power supply circuit?regarding the power supply.) ttl_in v ttl_out measurement device a io_t ii_t vo_t vi_t ttl_in ttl_out measurement device pulse generator oscilloscope cl = 10 pf (including the probe capacitance) probe cl (a) ttl i/o dc characteristics measurement circuit (b) ttl i/o ac characteristics measurement circuit ecl_in ecl_out measurement device 50 w ii_e vo_e vi_te v cc e ?2v v a (c) ecl i/o dc characteristics measurement circuit ecl_in ecl_out measurement device pulse generator oscilloscope 50 w v cc e ?2v v cc e ?2v 50 w 50 w v cc e ?2v v cc e ?2v 50 w ecl_in * ecl_out * c 2 pf (input capacitance of the measurement equipment and floating capacitance) 50 w transmission line (d) ecl i/o ac characteristics measurement circuit sdin sout measurement device pulse pattern generator 50 w v cc e ?2v 50 w sdin * sout * 265.625mbps oscilloscope triger 6.640625mhz 265.625mbps v cc e ?2v (e) jitter characteristics measurement circuit
?16 CXB1583Q notes on operation 1. clock synthesizer (pll) the CXB1583Q has a pll-based clock synthesizer for generating the serial data transfer frequency (transmission bit clock) and clock recovery circuit for recovering the clock from the reception serial data. these circuits require the external loop filters and external resistors which determine the vco center frequency. the external part circuit and recommended constant values are shown in the figure below. the parasitic capacitance attached to the pins which are used to connect external parts should be kept as small as possible in order to obtain the good pll characteristics. r5 56 c2 r4 r3 58 59 c1 r2 r1 52 53 c1 : 0.01f c2 : 0.01f r1 : 1.8k w r2 : 1.8k w r3 : 2.0k w r4 : 2.0k w r5 : 2.2k w fig. 1. external part circuit and recommended constants
?17 CXB1583Q 2. ecl input circuit the ecl differential input pins are biased to v bb (v cc ?1.3 v) via an 18k w resistor in the ic. see the figures below for ecl differential input methods. 18k w 18k w v bb (v cc ?1.3v) v cc = 3.3v, v ee = gnd 82 w 82 w v cc = 3.3v, v ee = gnd v cc = 3.3v 3.3v ecl output buffer ecl differential input buffer (a) ecl differrential signal from 3.3v ecl output buffer 18k w 18k w v bb (v cc ?1.3v) v cc = 3.3v, v ee = gnd 330 w v cc = gnd, v ee = ?.5v v ee 0.01f 0.01f 330 w ecl100k output buffer ecl differential input buffer (b) ecl differrential signal from ecl 100k output buffer 18k w 18k w v bb (v cc ?1.3v) v cc = 3.3v, v ee = gnd 50 w 50 w 50 w trans. line 0.01f 0.01f v tt (v cc ?2v) ecl differential input buffer (c) ecl differrential signal from 50 w transmission line 18k w 18k w v bb (v cc ?1.3v) v cc = 3.3v, v ee = gnd 50 w 50w trans. line 0.01f 0.01f v tt (v cc ?2v) ecl differential input buffer (d) ecl single signal from 50 w transmission line fig. 2. ecl input circuits
?18 CXB1583Q 3. example of power supply circuit 0.1f 22f 0.1f 22f v cc t 0.1f 22f v ee t 3.3v v cc g v cc e v ee g v ee e v cc p v ee p fig. 3. example of power supply circuit 4. power-on reset signal (por * ) the CXB1583Q has the power-on reset signal (por * ). this signal functions as a system reset signal when the power is turned on, the low level of signal is output for approximately 100ns and then the high level results. tpor power on por * output fig. 4. power-on reset signal
?19 CXB1583Q example of representative characteristics example of rj measurement (rx recovered clock, 266mhz operation) tx input (pdi0 to 9): random data rx input (sdin): k28.5 ta = 27? rj = 26.3ps (rms) [ 100mv/div ] [ 100ps/div ] example of rj measurement (rx recovered clock, 200mhz operation) tx input (pdi0 to 9): random data rx input (sdin): k28.5 ta = 27? rj = 36.9ps (rms) [ 100mv/div ] [ 100ps/div ]
?20 CXB1583Q example of rj measurement (sdout, 266mbps operation) tx input (pdi0 to 9): random data ta = 27? rj = 17.6ps (rms) [ 100mv/div ] [ 100ps/div ] example of rj measurement (sdout 200mbps operation) tx input (pdi0 to 9): random data ta = 27? rj = 24.3ps (rms) [ 100mv/div ] [ 100ps/div ]
?21 CXB1583Q eye pattern (tx sdout, 266mbps operation) ta = 27? [ 200mv/div ] [ 1ns/div ] eye pattern (tx sdout, 200mbps operation) ta = 27? [ 200mv/div ] [ 1ns/div ]
?22 CXB1583Q eye pattern (rx retimed data, 266mbps operation) [ 200mv/div ] ta = 27? [ 1ns/div ] eye pattern (rx retimed data, 200mbps operation) [ 200mv/div ] ta = 27? [ 1ns/div ]
?23 CXB1583Q package outline unit: mm sony code eiaj code jedec code package structure package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy qfp-80p-l03 lqfp080-p-1414 0.6g 80pin qfp (plastic) 16.0 0.4 14.0 ?0.1 + 0.4 0.65 0.3 ?0.1 + 0.15 0?to 10 0.5 0.2 0.1 ?0.1 + 0.15 (15.0) 0.127 ?0.05 + 0.1 1.5 ?0.15 + 0.35 40 21 20 1 41 60 61 80 m 0.12 0.1

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