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_______________general description the max796/max797/max799 high-performance, step- down dc-dc converters with single or dual outputs provide main cpu power in battery-powered systems. these buck controllers achieve 96% efficiency by using synchronous rectification and maxim? proprietary idle mode control scheme to extend battery life at full-load (up to 10a) and no-load outputs. excellent dynamic response corrects output transients caused by the latest dynamic-clock cpus within five 300khz clock cycles. unique bootstrap circuitry drives inexpensive n-channel mosfets, reducing system cost and eliminating the crowbar switching currents found in some pmos/nmos switch designs. the max796/max799 are specially equipped with a sec- ondary feedback input (secfb) for transformer-based dual-output applications. this secondary feedback path improves cross-regulation of positive (max796) or nega- tive (max799) auxiliary outputs. the max797 has a logic-controlled and synchronizable fixed-frequency pulse-width-modulating (pwm) operating mode, which reduces noise and rf interference in sensi- tive mobile-communications and pen-entry applications. the skip override input allows automatic switchover to idle-mode operation (for high-efficiency pulse skipping) at light loads, or forces fixed-frequency mode for lowest noise at all loads. the max796/max797/max799 are all available in 16- pin dip and narrow so packages. see the table below to compare these three converters. ________________________applications notebook and subnotebook computers pdas and mobile communicators cellular phones ____________________________features ? 96% efficiency ? 4.5v to 30v input range ? 2.5v to 6v adjustable output ? preset 3.3v and 5v outputs (at up to 10a) ? multiple regulated outputs ? +5v linear-regulator output ? precision 2.505v reference output ? automatic bootstrap circuit ? 150khz/300khz fixed-frequency pwm operation ? programmable soft-start ? 375a typ quiescent current (v in = 12v, v out = 5v) ? 1a typ shutdown current max796/max797/max799 step-down controllers with synchronous rectifier for cpu power ________________________________________________________________ maxim integrated products 1 part max799 main output special feature 3.3v/5v or adj regulates negative secondary voltage (such as -5v) max797 3.3v/5v or adj logic-controlled low-noise mode max796 3.3v/5v or adj regulates positive secondary voltage (such as +12v) idle mode is a trademark of maxim integrated products. ? u.s. and foreign patents pending. 19-0221; rev 4; 9/05 ___________________pin configuration 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 dh lx bst dl gnd ref (secfb) skip ss top view max796 max797 max799 pgnd vl v+ csl ( ) are for max796/ max799. csh fb shdn sync dip/so dice* 16 narrow so 16 plastic dip pin-package temp range 0? to +70? 0? to +70? 0? to +70? max796c/d max796cse max796 cpe part ? 16 cerdip 16 narrow so 16 plastic dip -40? to +85? -40? to +85? -55? to +125? max796mje max796ese max796epe ordering information continued at end of data sheet. *contact factory for dice specifications. _______________ordering information for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visi t maxims website at www.maxim-ic.com. e v a l u a t io n k it a v a il a b l e
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v+ = 15v, gnd = pgnd = 0v, i vl = i ref = 0a, t a = 0? to +70? for max79_c, t a = 0? to +85? for max79_e, t a = -55? to +125? for max79_m, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd .................................................................-0.3v, +36v gnd to pgnd........................................................................?v vl to gnd ...................................................................-0.3v, +7v bst to gnd ...............................................................-0.3v, +36v dh to lx...........................................................-0.3v, bst + 0.3v lx to bst.....................................................................-7v, +0.3v shdn to gnd............................................................-0.3v, +36v sync, ss, ref, fb, secfb, skip , dl to gnd..-0.3v, vl + 0.3v csh, csl to gnd .......................................................-0.3v, +7v vl short circuit to gnd..............................................momentary ref short circuit to gnd ...........................................continuous vl output current ...............................................................50ma continuous power dissipation (t a = +70?) so (derate 8.70mw/? above +70?) ........................696mw plastic dip (derate 10.53mw/? above +70?) .........842mw cerdip (derate 10.00mw/? above +70?) ..............800mw operating temperature ranges max79_c_ _ ......................................................0? to +70? max79_e_ _....................................................-40? to +85? max79_mje .................................................-55? to +125? storage temperature range .............................-65? to +160? lead temperature (soldering, 10s) .....................................+300 rising edge, hysteresis = 25mv rising edge, hysteresis = 15mv shdn = 2v, 0ma < i vl < 25ma, 5.5v < v+ < 30v falling edge, hysteresis = 20mv (max799) csh-csl, negative csh-csl, positive falling edge, hysteresis = 15mv (max796) 6v < v+ < 30v 25mv < (csh-csl) < 80mv 0mv < (csh-csl) < 80mv, fb = vl, 6v < v+ < 30v, includes line and load regulation external resistor divider (csh-csl) = 0v 0mv < (csh-csl) < 80mv conditions v 4.2 4.7 vl/csl switchover voltage v 3.8 4.1 vl fault lockout voltage v 4.7 5.3 vl output voltage -0.05 0 0.05 v 2.45 2.505 2.55 secfb regulation setpoint ma 2.0 ss fault sink current ? 2.5 4.0 6.5 ss source current 5.0 30 v 4.5 30 input supply range -50 -100 -160 mv 80 100 120 current-limit voltage %/v 0.04 0.06 line regulation 1.5 v 4.85 5.10 5.25 5v output voltage (csl) v ref 6 nominal adjustable output voltage range v 2.43 2.505 2.57 feedback voltage % 2.5 load regulation units min typ max parameter max79_c max79_e/m 0mv < (csh-csl) < 80mv, fb = 0v, 4.5v < v+ < 30v, includes line and load regulation v 3.20 3.35 3.46 3.3v output voltage (csl) +3.3v and +5v step-down controllers flyback/pwm controller internal regulator and reference
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power _______________________________________________________________________________________ 3 note 1: since the reference uses vl as its supply, v+ line-regulation error is insignificant. note 2: at very low input voltages, quiescent supply current may increase due to excess pnp base current in the vl linear regulator. this occurs only if v+ falls below the preset vl regulation point (5v nominal). see the quiescent supply current vs. supply voltage graph in the typical operating characteristics . electrical characteristics (continued) (v+ = 15v, gnd = pgnd = 0v, i vl = i ref = 0a, t a = 0? to +70? for max79_c, t a = 0? to +85? for max79_e, t a = -55? to +125? for max79_m, unless otherwise noted.) secfb, 0v or 4v shdn , 0v or 30v shdn , skip sync sync = 0v or 5v no external load (note 1) sync = ref guaranteed by design csh = csl = 6v v+ = 4v, csl = 0v (note 2) sync = 0v or 5v shdn = 0v, v+ = 30v, csl = 0v or 6v falling edge 0? < i ref < 100? sync = ref shdn = 0v, csl = 6v, v+ = 0v or 30v, vl = 0v conditions 0.1 max79_c ? 2.0 max79_e/m input current 2.0 v vl - 0.5 input high voltage % 93 96 89 91 maximum duty cycle khz 190 340 oscillator sync range ns 200 sync rise/fall time ns 200 sync low pulse width ns 200 sync high pulse width 125 150 175 khz 270 300 330 oscillator frequency 2.45 2.55 v 2.46 2.505 2.54 reference output voltage mw 4.8 6.6 quiescent power consumption mw 48 dropout power consumption 15 ? 13 v+ shutdown current v 1.8 2.3 reference fault lockout voltage mv 50 reference load regulation ? 0.1 1 csl shutdown leakage current units min typ max parameter max79_c max79_e/m max79_c max79_e/m fb = csh = csl = 6v, vl switched over to csl 15 ? 13 v+ off-state leakage current dl forced to 2v fb, fb = ref csh, csl, csh = csl = 6v, device not shut down sync, skip a 1 dl sink/source current ?00 50 1.0 shdn , skip sync 0.5 v 0.8 input low voltage dh forced to 2v, bst-lx = 4.5v a 1 dh sink/source current high or low, bst-lx = 4.5v high or low 7 dh on-resistance 7 dl on-resistance oscillator and inputs/outputs na
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power 4 _______________________________________________________________________________________ electrical characteristics (continued) (v+ = 15v, gnd = pgnd = 0v, i vl = i ref = 0a, t a = -40? to +85? for max79_e, unless otherwise noted.) (note 3) note 3: all -40? to +85? specifications above are guaranteed by design. external resistor divider 0mv < (csh - csl) < 80mv, fb = vl, 4.5v < v+ < 30v, includes line and load regulation 0mv < (csh - csl) < 80mv, fb = vl, 6v < v+ < 30v, includes line and load regulation conditions v ref 6.0 nominal adjustable output voltage range v 3.10 3.35 3.56 3.3v output voltage (csl) v 5.0 30 input supply range v 4.70 5.10 5.40 5v output voltage (csl) units min typ max parameter csh - csl, negative (csh-csl) = 0v 6v < v+ < 30v csh - csl, positive -40 -100 -160 current-limit voltage v 2.40 2.60 feedback voltage %/v 0.04 0.06 line regulation mv 70 130 fb = csh = csl = 6v, vl switched over to csl shdn = 0v, v+ = 30v, csl = 0v or 6v rising edge, hysteresis = 25mv no external load (note 1) 0? < i ref < 100? ? 110 v+ off-state leakage current ? 110 v+ shutdown current v rising edge, hysteresis = 15mv shdn = 2v, 0ma < i vl < 25ma, 5.5v < v+ < 30v 4.2 4.7 vl/csl switchover voltage v 2.43 2.505 2.57 reference output voltage falling edge, hysteresis = 15mv (max796) falling edge, hysteresis = 20mv (max799) mv 50 reference load regulation v 3.75 4.05 vl fault lockout voltage v 4.7 5.3 vl output voltage 2.40 2.60 v -0.08 0.08 secfb regulation setpoint sync = ref sync = 0v or 5v 89 91 khz 210 320 oscillator sync range khz sync = ref 120 150 180 oscillator frequency ns 250 sync high pulse width ns 250 sync low pulse width 250 300 350 mw 4.8 8.4 quiescent power consumption high or low, bst - lx = 4.5v high or low sync = 0v or 5v 7 dh on-resistance 7 dl on-resistance % 93 96 maximum duty cycle +3.3v and +5v step-down controllers flyback/pwm controller internal regulator and reference oscillator and inputs/outputs
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power _______________________________________________________________________________________ 5 shdn dh +12v output +5v output input 6v to 30v bst lx dl pgnd csh csl ss ref sync gnd v+ vl fb secfb max796 __________________________________________________typical operating circuits max797 shdn dh +3.3v output input 4.5v to 30v bst lx dl pgnd csh csl ss ref sync gnd skip fb v+ vl
__________________________________________typical operating characteristics (t a = +25?, unless otherwise noted.) 100 50 0.001 1 0.1 0.01 10 efficiency vs. load current, 5v/3a circuit 60 max796-01 load current (a) efficiency (%) 70 80 90 standard max797 5v/3a circuit, figure 1 f = 300khz v in = 6v v in = 30v 100 50 0.001 1 0.1 0.01 10 efficiency vs. load current, 3.3v/3a circuit 60 max796-02 load current (a) efficiency (%) 70 80 90 standard max797 3.3v/3a circuit, figure 1 f = 300khz v in = 12v v in = 30v v in = 5v 100 40 50 60 70 80 90 0.1 1 10 efficiency vs. load current, 3.3v/10a circuit max796-03 load current (a) efficiency (%) skip = low skip = high standard max797 3.3v/10a circuit, figure 1 f = 300khz v in = 5v max796/max797/max799 step-down controllers with synchronous rectifier for cpu power 6 _______________________________________________________________________________________ max799 shdn dh ?v output +5v output input 6v to 30v bst lx dl pgnd csh csl ss ref from ref sync gnd v+ vl fb secfb _____________________________________typical operating circuits (continued)
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power _______________________________________________________________________________________ 7 ____________________________typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) 0 200 400 600 800 14m 15m 16m 0 4 8 121620242832 quiescent supply current vs. supply voltage, 5v/3a circuit in idle mode max796-04 supply voltage (v) supply current (a) standard max797 application configured for 5v skip = low sync = ref 0 0.2 0.4 0.6 0.8 1.2 1.0 1.4 1.6 0 4 8 121620242832 shutdown supply current vs. supply voltage max796-07 supply voltage (v) supply current ( a) device current only shdn = low 0 200 400 600 800 1200 1000 1400 0 4 8 121620242832 max796-05 supply voltage (v) supply current ( a) quiescent supply current vs. supply voltage, 3.3v/3a circuit in idle mode standard max797 3.3v/3a circuit, figure 1 skip = low sync = ref switching not switching (fb forced to 3.5v) 0 10 20 30 0 4 8 121620242832 max796-06 supply voltage (v) supply current (ma) quiescent supply current vs. supply voltage, low-noise mode f = 150khz f = 300khz standard max797 3.3v/3a circuit, figure 1 skip = high 0 0.01 1 10 0.1 dropout voltage vs. load current 200 100 300 400 500 600 700 800 max796-08 load current (a) v in - v out (mv) standard max797 application configured for 5v v out > 4.8v f = 150khz f = 300khz 0 1 100 1000 10 ref load-regulation error vs. load current 5 10 15 20 max796-09 ref load current ( a) load regulation v (mv) 0 200 100 300 400 500 0 20406080 max796-10 vl load current (ma) load regulation v (mv) vl load-regulation error vs. load current 0 50 100 150 200 250 300 350 400 450 0 4 8 121620242832 max796-11 supply voltage (v) maximum secondary current (ma) max796 maximum secondary current vs. supply voltage, 5v/15v circuit i out (main) = 0a i out (main) = 3a circuit of figure 11 transformer = tti5870 v sec > 12.75v 1000 0.1 100 10m 1 switching frequency vs. load current 10 load current (a) switching frequency (khz) 100 1m 100m sync = ref (300khz) skip = low +5v, v in = 7.5v 1 +5v, v in = 30v +3.3v, v in = 7.5v
i load = 100ma, v in = 10v, circuit of figure 1 idle-mode waveforms +5v output 50mv/div 2v/div 200 s/div i load = 1a, v in = 16v, circuit of figure 1 pulse-width-modulation mode waveforms lx voltage 10v/div +5v output voltage 50mv/div 500ns/div v in = 15v, circuit of figure 1 +5v load-transient response +5v output 50mv/div 3a 0a load current 200 s/div max796/max797/max799 step-down controllers with synchronous rectifier for cpu power 8 _______________________________________________________________________________________ 0 150 300 450 600 900 750 1050 0 3 6 9 12 15 18 21 24 max796 maximum secondary current vs. supply voltage, 3.3v/5v circuit max796-12 supply voltage (v) maximum secondary current (ma) i out (main) = 2a i out (main) = 0a circuit of figure 12 transformer = tdk 1.5:1 v sec 4.8v 0 100 200 300 400 600 500 700 800 0 4 8 121620242832 max799 maximum secondary current vs. supply voltage, 5v circuit max796-13 supply voltage (v) maximum secondary current (ma) circuit of figure 13 transformer = tti5926 v sec -5.1v i out (main) = 0a i out (main) = 1a ____________________________typical operating characteristics (continued) (t a = +25?, unless otherwise noted.)
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power _______________________________________________________________________________________ 9 ______________________________________________________________pin description current-sense input, high side. current-limit level is 100mv referred to csl. csh 8 current-sense input, low side. also serves as the feedback input in fixed-output modes. csl 9 battery voltage input (4.5v to 30v). bypass v+ to pgnd close to the ic with a 0.1? capacitor. connects to a linear regulator that powers vl. v+ 10 5v internal linear-regulator output. vl is also the supply voltage rail for the chip. vl is switched to the output voltage via csl (v csl > 4.5v) for automatic bootstrapping. bypass to gnd with 4.7?. vl can supply up to 5ma for external loads. vl 11 power ground. pgnd 12 low-noise analog ground and feedback reference point. gnd 4 oscillator synchronization and frequency select. tie to gnd or vl for 150khz operation; tie to ref for 300khz operation. a high-to-low transition begins a new cycle. drive sync with 0v to 5v logic levels (see the electrical characteristics table for v ih and v il specifications). sync capture range is 190khz to 340khz guaranteed. sync 5 shutdown control input, active low. logic threshold is set at approximately 1v (v th of an internal n-channel mosfet). tie shdn to v+ for automatic start-up. shdn 6 feedback input. regulates at fb = ref (approximately 2.505v) in adjustable mode. fb is a dual-mode tm input that also selects the fixed output voltage settings as follows: ? connect to gnd for 3.3v operation. ? connect to vl for 5v operation. ? connect fb to a resistor divider for adjustable mode. fb can be driven with +5v rail-to-rail logic in order to change the output voltage under system control. fb 7 reference voltage output. bypass to gnd with 0.33? minimum. ref 3 pin secondary winding feedback input. normally connected to a resistor divider from an auxiliary output. dont leave secfb unconnected. ? max796: secfb regulates at vsecfb = 2.505v. tie to vl if not used. ? max799: secfb regulates at vsecfb = 0v. tie to a negative voltage through a high-value current-limit- ing resistor (i max = 100?) if not used. secfb (max796/ max799) 2 soft-start timing capacitor connection. ramp time to full current limit is approximately 1ms/nf. ss 1 function name low-side gate-drive output. normally drives the synchronous-rectifier mosfet. swings 0v to vl. dl 13 boost capacitor connection for high-side gate drive (0.1?). bst 14 switching node (inductor) connection. can swing 2v below ground without hazard. lx 15 high-side gate-drive output. normally drives the main buck switch. dh is a floating driver output that swings from lx to bst, riding on the lx switching-node voltage. dh 16 dual mode is a trademark of maxim integrated products. disables pulse-skipping mode when high. connect to gnd for normal use. dont leave skip unconnected. with skip grounded, the device will automatically change from pulse-skipping operation to full pwm opera- tion when the load current exceeds approximately 30% of maximum. (see table 3.) skip (max797)
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power 10 ______________________________________________________________________________________ ______standard application circuit it is easy to adapt the basic max797 single-output 3.3v buck converter (figure 1) to meet a wide range of applications with inputs up to 28v (limited by choice of external mosfet). simply substitute the appropriate components from table 1. these circuits represent a good set of tradeoffs between cost, size, and efficiency while staying within the worst-case specification limits for stress-related parameters such as capacitor ripple current. each of these circuits is rated for a continuous load current at t a = +85?, as shown. the 1a, 2a and 10a applications can withstand a continuous output short-circuit to ground. the 3a and 5a applications can withstand a short circuit of many seconds duration, but the synchronous-rectifier mosfet overheats, exceed- ing the manufacturer? ratings for junction temperature by 50? or more. if the 3a or 5a circuit must be guaranteed to withstand a continuous output short circuit indefinitely, see the section mosfet switches under selecting other components . don? change the frequency of these cir- cuits without first recalculating component values (par- ticularly inductance value at maximum battery voltage). _______________detailed description the max796 is a bicmos, switch-mode power-supply controller designed primarily for buck-topology regula- tors in battery-powered applications where high effi- ciency and low quiescent supply current are critical. the max796 also works well in other topologies such as boost, inverting, and clk due to the flexibility of its floating high-speed gate driver. light-load efficiency is enhanced by automatic idle-mode operation? vari- able-frequency pulse-skipping mode that reduces max797 csl csh vl sync fb v+ 10 11 5 7 14 q1 q2 16 15 13 d2 cmpsh-3 j1 150khz/300khz jumper note: keep current-sense lines short and close together. see fig. 10 d1 12 8 9 ref 3 gnd 4 +5v at 5ma +3.3v output gnd out bst dh lx dl 2 1 low-noise control pgnd skip ss 6 on/off control shdn input ref output +2.505v at 100 a c5 0.33 f c4 4.7 f c7 0.1 f c6 0.01 f (optional) c1 c2 c3 0.1 f r1 l1 figure 1. standard 3.3v application circuit
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power ______________________________________________________________________________________ 11 table 1. component selection for standard 3.3v applications table 2. component suppliers * distributor losses due to mosfet gate charge. the step-down power-switching circuit consists of two n-channel mosfets, a rectifier, and an lc output filter. the out- put voltage is the average of the ac voltage at the switching node, which is adjusted and regulated by changing the duty cycle of the mosfet switches. the gate-drive signal to the n-channel high-side mosfet must exceed the battery voltage and is provided by a flying capacitor boost circuit that uses a 100nf capaci- tor connected to bst. the max796 contains nine major circuit blocks, which are shown in figure 2. [1] 714-960-6492 (714) 969-2491 matsuo [1] 512-992-3377 (512) 992-7900 irc [1] 310-322-3332 (310) 322-3331 international rectifier [1] 605-665-1627 (605) 668-4131 dale [1] 561-241-9339 (561) 241-7876 coiltronics [1] 847-639-1469 (847) 639-6400 coilcraft [1] 516-435-1824 (516) 435-1110 central semiconductor [1] 803-626-3123 (803) 946-0690 avx factory fax [country code] usa phone manufacturer [1] 864-963-6521 (864) 963-6300 kemet 1.5?, 11a, 3.5m coiltronics ctx03-12357-1 4.7?, 5.5a ferrite coilcraft do3316-472 10?, 3a ferrite sumida cdrh125 33?, 2.2a ferrite dale lpe6562-330mb 47?, 1.2a ferrite or kool-mu sumida cd75-470 l1 inductor 3 x 0.02 irc lr2010-01-r020 (3 in parallel) 0.015 irc lr2010-01-015 0.025 irc lr2010-01-r025 0.039 irc lr2010-01-r039 0.062 irc lr2010-01-r062 r1 resistor 1n5820 niec nsq03a02, or motorola mbrs340t3 1n5821 niec nsq03a04 or motorola mbrs340t3 1n5819 niec ec10qs03 or motorola mbrs130t3 1n5817 niec ec10qs02l or motorola mbrs130t3 1n5817 motorola mbr0502l sod-89 d1 rectifier 4 x 220?, 10v sanyo os-con 10sa220m 3 x 220?, 10v avx tps or sprague 595d 220?, 10v avx tps or sprague 595d 150?, 10v avx tps or sprague 595d 150?, 10v avx tps or sprague 595d c2 output capacitor 2 x 220?, 10v sanyo os-con 10sa220m 4 x 22?, 35v avx tps or sprague 595d 2 x 22?, 35v avx tps or sprague 595d 2 x 22?, 35v avx tps or sprague 595d 22?, 35v avx tps or sprague 595d c1 input capacitor motorola mtd75n03hdl d 2 pak motorola mtd20n03hdl dpak motorola mmsf5n03hd or si9410 motorola 1/2 mmdf3n03hd or 1/2 si9936 international rectifier 1/2 irf7101 q2 low-side mosfet motorola mtd75n03hdl d 2 pak motorola mtd20n03hdl dpak motorola mmsf5n03hd or si9410 motorola 1/2 mmdf3n03hd or 1/2 si9936 international rectifier 1/2 irf7101 q1 high-side mosfet 4.5v to 6v 4.75v to 24v 4.75v to 28v 4.75v to 18v 4.75v to 18v input range {1} 847-390-4405 (847) 390-4461 tdk [81] 3-3607-5144 (847) 956-0666 sumida [1] 603-224-1430 (603) 224-1961 sprague [1] 408-970-3950 (408) 988-8000 (800) 554-5565 siliconix [81] 7-2070-1174 (619) 661-6835 sanyo [81] 3-3494-7414 (805) 867-2555* niec [1] 814-238-0490 (814) 237-1431 (800) 831-9172 murata-erie factory fax [country code] usa phone manufacturer [1] 702-831-3521 (702) 831-0140 transpower technologies [1] 602-994-6430 (602) 303-5454 motorola load current 10a 4a 3a 2a 1a component 300khz 300khz 300khz 300khz 150khz frequency desktop 5v-to-3v high-end notebook notebook sub-notebook pda application
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power 12 ______________________________________________________________________________________ max796 1v csl csh ref gnd 4v fb adj fb 5v fb 3.3v fb sync lpf 60khz pwm comparator out v+ battery voltage 4.5v vl to csl +5v at 5ma bst dh lx dl pgnd secfb main output auxiliary output shdn pwm logic shdn ss on/off +2.505v at 100 a +5v linear regulator +2.505v ref figure 2. max796 block diagram
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power ______________________________________________________________________________________ 13 pwm controller blocks: ? multi-input pwm comparator ? current-sense circuit ? pwm logic block ? dual-mode internal feedback mux ? gate-driver outputs ? secondary feedback comparator bias generator blocks: ? +5v linear regulator ? automatic bootstrap switchover circuit ? +2.505v reference these internal ic blocks aren? powered directly from the battery. instead, a +5v linear regulator steps down the battery voltage to supply both the ic internal rail (vl pin) as well as the gate drivers. the synchronous- switch gate driver is directly powered from +5v vl, while the high-side-switch gate driver is indirectly pow- ered from vl via an external diode-capacitor boost cir- cuit. an automatic bootstrap circuit turns off the +5v linear regulator and powers the ic from its output volt- age if the output is above 4.5v. pwm controller block the heart of the current-mode pwm controller is a multi-input open-loop comparator that sums three sig- nals: output voltage error signal with respect to the ref- erence voltage, current-sense signal, and slope compensation ramp (figure 3). the pwm controller is a direct summing type, lacking a traditional error amplifi- er and the phase shift associated with it. this direct- summing configuration approaches the ideal of cycle-by-cycle control over the output voltage. under heavy loads, the controller operates in full pwm mode. each pulse from the oscillator sets the main pwm latch that turns on the high-side switch for a peri- od determined by the duty factor (approximately v out /v in ). as the high-switch turns off, the synchro- nous rectifier latch is set. 60ns later the low-side switch turns on, and stays on until the beginning of the next clock cycle (in continuous mode) or until the inductor current crosses zero (in discontinuous mode). under fault conditions where the inductor current exceeds the 100mv current-limit threshold, the high-side latch resets and the high-side switch turns off. at light loads ( skip = low), the inductor current fails to exceed the 30mv threshold set by the minimum-current comparator. when this occurs, the controller goes into idle mode, skipping most of the oscillator pulses in order to reduce the switching frequency and cut back gate-charge losses. the oscillator is effectively gated off at light loads because the minimum-current com- parator immediately resets the high-side latch at the beginning of each cycle, unless the feedback signal falls below the reference voltage level. when in pwm mode, the controller operates as a fixed- frequency current-mode controller where the duty ratio is set by the input/output voltage ratio. the current- mode feedback system regulates the peak inductor current as a function of the output voltage error signal. since the average inductor current is nearly the same as the peak current, the circuit acts as a switch-mode transconductance amplifier and pushes the second output lc filter pole, normally found in a duty-factor- controlled (voltage-mode) pwm, to a higher frequency. to preserve inner-loop stability and eliminate regenera- tive inductor current ?taircasing,?a slope-compensa- tion ramp is summed into the main pwm comparator to reduce the apparent duty factor to less than 50%. the relative gains of the voltage- and current-sense inputs are weighted by the values of current sources that bias three differential input stages in the main pwm comparator (figure 4). the relative gain of the voltage comparator to the current comparator is internally fixed at k = 2:1. the resulting loop gain (which is relatively low) determines the 2.5% typical load regulation error. the low loop-gain value helps reduce output filter capacitor size and cost by shifting the unity-gain crossover to a lower frequency. shdn skip load current mode name description low x x shutdown all circuit blocks turned off; supply current = 1? typ high low low, <10% idle pulse-skipping; supply current = 700? typ at v in = 10v; discontinuous inductor current high low medium, <30% idle pulse-skipping; continuous inductor current high low high, >30% pwm constant-frequency pwm; continuous inductor current high high x low noise* (pwm) constant-frequency pwm regardless of load; continuous inductor current even at no load table 3. operating-mode truth table * max796/max799 have no skip pin and therefore can? go into low-noise mode. x = don? care
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power 14 ______________________________________________________________________________________ shoot- through control r q 30mv r q level shift 1 s single-shot 1x main pwm comparator osc level shift current limit vl 24r 1r 2.5v 4 a synchronous rectifier control ref ss shdn ?00mv note 1 csh csl from feedback divider bst dh lx vl dl pgnd s s slope comp n skip (max797 only) ref (max796) gnd (max799) max796, max799 only secfb note 1: comparator input polarities are reversed for the max799. figure 3. pwm controller detailed block diagram
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power ______________________________________________________________________________________ 15 the output filter capacitor c2 sets a dominant pole in the feedback loop. this pole must roll off the loop gain to unity before the zero introduced by the output capacitor? parasitic resistance (esr) is encountered (see design procedure section). a 60khz pole-zero cancellation filter provides additional rolloff above the unity-gain crossover. this internal 60khz lowpass com- pensation filter cancels the zero due to the filter capaci- tor? esr. the 60khz filter is included in the loop in both fixed- and adjustable-output modes. synchronous-rectifier driver (dl pin) synchronous rectification reduces conduction losses in the rectifier by shunting the normal schottky diode with a low-resistance mosfet switch. the synchronous rec- tifier also ensures proper start-up of the boost-gate driv- er circuit. if you must omit the synchronous power mosfet for cost or other reasons, replace it with a small-signal mosfet such as a 2n7002. if the circuit is operating in continuous-conduction mode, the dl drive waveform is simply the complement of the dh high-side drive waveform (with controlled dead time to prevent cross-conduction or ?hoot- through?. in discontinuous (light-load) mode, the syn- chronous switch is turned off as the inductor current falls through zero. the synchronous rectifier works under all operating conditions, including idle mode. the synchronous-switch timing is further controlled by the secondary feedback (secfb) signal in order to improve multiple-output cross-regulation (see secondary feedback-regulation loop section). internal vl and ref supplies an internal regulator produces the 5v supply (vl) that powers the pwm controller, logic, reference, and other blocks within the max796. this +5v low-dropout linear regulator can supply up to 5ma for external loads, with a reserve of 20ma for gate-drive power. bypass vl to gnd with 4.7?. important : vl must not be allowed to exceed 6v. measure vl with the main output fully loaded. if vl is being pumped up above 5.5v, the probable cause is either excessive boost-diode capaci- tance or excessive ripple at v+. use only small-signal diodes for d2 (1n4148 preferred) and bypass v+ to pgnd with 0.1? directly at the package pins. the 2.505v reference (ref) is accurate to ?.6% over temperature, making ref useful as a precision system reference. bypass ref to gnd with 0.33? minimum. ref can supply up to 1ma for external loads. however, if tight-accuracy specs for either vout or ref are essential, avoid loading ref with more than 100?. loading ref reduces the main output voltage slightly, according to the reference-voltage load regulation error. in max799 applications, ensure that the secfb divider doesn? load ref heavily. when the main output voltage is above 4.5v, an internal p- channel mosfet switch connects csl to vl while simul- taneously shutting down the vl linear regulator. this action bootstraps the ic, powering the internal circuitry from the output voltage, rather than through a linear regu- lator from the battery. bootstrapping reduces power dissi- pation caused by gate-charge and quiescent losses by providing that power from a 90%-efficient switch-mode source, rather than from a 50%-efficient linear regulator. fb ref csh csl slope compensation vl i1 r1 r2 to pwm logic output driver uncompensated high-speed level translator and buffer i2 i3 figure 4. main pwm comparator block diagram
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power 16 ______________________________________________________________________________________ it? often possible to achieve a bootstrap-like effect, even for circuits that are set to v out < 4.5v, by powering vl from an external-system +5v supply. to achieve this pseudo-bootstrap, add a schottky diode between the external +5v source and vl, with the cathode to the vl side. this circuit provides a 1% to 2% efficiency boost and also extends the minimum battery input to less than 4v. the external source must be in the range of 4.8v to 6v. another way to achieve a pseudo-bootstrap is to add an extra flyback winding to the main inductor to generate the +5v bootstrap source, as shown in the +3.3v/+5v dual-output application (figure 12). boost high-side gate-driver supply (bst pin) gate-drive voltage for the high-side n-channel switch is generated by a flying-capacitor boost circuit as shown in figure 5. the capacitor is alternately charged from the vl supply and placed in parallel with the high-side mosfet? gate-source terminals. on start-up, the synchronous rectifier (low-side mos- fet) forces lx to 0v and charges the bst capacitor to 5v. on the second half-cycle, the pwm turns on the high-side mosfet by closing an internal switch between bst and dh. this provides the necessary enhancement voltage to turn on the high-side switch, an action that ?oosts?the 5v gate-drive signal above the battery voltage. ringing seen at the high-side mosfet gate (dh) in discontinuous-conduction mode (light loads) is a natur- al operating condition, and is caused by the residual energy in the tank circuit formed by the inductor and stray capacitance at the switching node lx. the gate- driver negative rail is referred to lx, so any ringing there is directly coupled to the gate-drive output. current-limiting and current-sense inputs (csh and csl) the current-limit circuit resets the main pwm latch and turns off the high-side mosfet switch whenever the voltage difference between csh and csl exceeds 100mv. this limiting is effective for both current flow directions, putting the threshold limit at ?00mv. the tolerance on the positive current limit is ?0%, so the external low-value sense resistor must be sized for 80mv/r1 to guarantee enough load capability, while components must be designed to withstand continuous current stresses of 120mv/r1. for breadboarding purposes or very high-current appli- cations, it may be useful to wire the current-sense inputs with a twisted pair rather than pc traces. this twisted pair needn? be anything special, perhaps two pieces of wire-wrap wire twisted together. oscillator frequency and synchronization (sync pin) the sync input controls the oscillator frequency. connecting sync to gnd or to vl selects 150khz operation; connecting sync to ref selects 300khz. sync can also be used to synchronize with an external 5v cmos or ttl clock generator. sync has a guaran- teed 190khz to 340khz capture range. 300khz operation optimizes the application circuit for component size and cost. 150khz operation provides increased efficiency and improved load-transient response at low input-output voltage differences (see low-voltage operation section). low-noise mode (skip pin) the low-noise mode (skip = high) is useful for minimiz- ing rf and audio interference in noise-sensitive appli- cations such as soundblaster hi-fi audio-equipped systems, cellular phones, rf communicating comput- ers, and electromagnetic pen-entry systems. see the summary of operating modes in table 3. skip can be driven from an external logic signal. the max797 can reduce interference due to switching noise by ensuring a constant switching frequency regardless of load and line conditions, thus concentrat- ing the emissions at a known frequency outside the system audio or if bands. choose an oscillator fre- max796 max797 max799 bst vl +5v vl supply battery input vl vl dh lx dl pwm level translator figure 5. boost supply for gate drivers soundblaster is a trademark of creative labs.
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power ______________________________________________________________________________________ 17 quency where harmonics of the switching frequency don? overlap a sensitive frequency band. if necessary, synchronize the oscillator to a tight-tolerance external clock generator. the low-noise mode (skip = high) forces two changes upon the pwm controller. first, it ensures fixed-frequen- cy operation by disabling the minimum-current com- parator and ensuring that the pwm latch is set at the beginning of each cycle, even if the output is in regula- tion. second, it ensures continuous inductor current flow, and thereby suppresses discontinuous-mode inductor ringing by changing the reverse current-limit detection threshold from zero to -100mv, allowing the inductor current to reverse at very light loads. in most applications, skip should be tied to gnd in order to minimize quiescent supply current. supply cur- rent with skip high is typically 10ma to 20ma, depend- ing on external mosfet gate capacitance and switching losses. forced continuous conduction via skip can improve cross regulation of transformer-coupled multiple-output supplies. this second function of the skip pin pro- duces a result that is similar to the method of adding secondary regulation via the secfb feedback pin, but with much higher quiescent supply current. still, improving cross regulation by enabling skip instead of building in secfb feedback can be useful in noise- sensitive applications, since secfb and skip are mutually exclusive pins/functions in the max796 family. adjustable-output feedback (dual-mode fb pin) adjusting the main output voltage with external resis- tors is easy for any of the devices in the max796 family, via the circuit of figure 6. the nominal output voltage (given by the formula in figure 6) should be set approx- imately 2% high in order to make up for the max796? -2.5% typical load-regulation error. for example, if designing for a 3.0v output, use a resistor ratio that results in a nominal output voltage of 3.06v. this slight offsetting gives the best possible accuracy. recommended normal values for r5 range from 5k to 100k . to achieve a 2.505v nominal output, simply connect fb to csl directly. to achieve output voltages lower than 2.5v, use an external reference-voltage source higher than v ref , as shown in figure 7. for best accuracy, this second reference voltage should be much higher than v ref . alternatively, an external op amp could be used to gain-up ref in order to create the second reference source. this scheme requires a minimum load on the output in order to sink the r3/r4 divider current. remote sensing of the output voltage, while not possi- ble in fixed-output mode due to the combined nature of the voltage- and current-sense input (csl), is easy to achieve in adjustable mode by using the top of the external resistor divider as the remote sense point. fixed-output accuracy is guaranteed to be ?% over all conditions. in special circumstances, it may be nec- essary to improve upon this output accuracy. the high- accuracy adjustable-output application (figure 18) provides ?.5% accuracy by adding an integrator-type error amplifier. the breakdown voltage rating of the current-sense inputs (7v absolute maximum) determines the 6v maxi- mum output adjustment range. to extend this output range, add two matched resistor dividers and speed- up capacitors to form a level translator, as shown in figure 8. be sure to set these resistor ratios accurately (using 0.1% resistors), to avoid adding excessive error to the 100mv current-limit threshold. secondary feedback-regulation loop (secfb pin) a flyback winding control loop regulates a secondary winding output (max796/max799 only), improving cross-regulation when the primary is lightly loaded or when there is a low input-output differential voltage. if secfb crosses its regulation threshold (vref for the max796 max797 max799 csl csh gnd fb r4 r5 main output remote sense lines dh dl v out where v ref (nominal) = 2.505v = v ref ( 1 + ) r4 r5 v+ figure 6. adjusting the main output voltage
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power 18 ______________________________________________________________________________________ max796), a 1? one-shot is triggered that extends the low-side switch? on-time beyond the point where the inductor current crosses zero (in discontinuous mode). this causes the inductor (primary) current to reverse, which in turn pulls current out of the output filter capacitor and causes the flyback transformer to operate in the for- ward mode. the low impedance presented by the trans- former secondary in the forward mode dumps current into the secondary output, charging up the secondary capac- itor and bringing secfb back into regulation. the secfb feedback loop does not improve secondary output accu- racy in normal flyback mode, where the main (primary) output is heavily loaded. in this mode, secondary output accuracy is determined, as usual, by the secondary recti- fier drop, turns ratio, and accuracy of the main output voltage. so, a linear post-regulator may still be needed in order to meet tight output accuracy specifications. the secondary output voltage-regulation point is deter- mined by an external resistor divider at secfb. for nega- tive output voltages, the secfb comparator is referenced to gnd (max799); for positive output voltages, secfb regulates at the 2.505v reference (max796). as a result, output resistor divider connections and design equations for the two device types differ slightly (figure 9). ordinarily, the secondary regulation point is set 5% to 10% below the voltage normally produced by the flyback effect. for example, if the output voltage as determined by the turns ratio is +15v, the feedback resistor ratio should be set to produce about +13.5v; otherwise, the secfb one-shot might be triggered unintentionally, caus- ing an unnecessary increase in supply current and output noise. in negative-output (max799) applications, the resistor divider acts as a load on the internal reference, which in turn can cause errors at the main output. avoid overloading ref (see the reference load-regulation error vs. load current graph in the typical operating characteristics ). 100k is a good value for r3 in max799 circuits. soft-start circuit (ss) soft-start allows a gradual increase of the internal cur- rent-limit level at start-up for the purpose of reducing input surge currents, and perhaps for power-supply sequencing. in shutdown mode, the soft-start circuit holds the ss capacitor discharged to ground. when shdn goes high, a 4? current source charges the ss capacitor up to 3.2v. the resulting linear ramp wave- form causes the internal current-limit level to increase proportionally from 20mv to 100mv. the main output capacitor thus charges up relatively slowly, depending on the ss capacitor value. the exact time of the output rise depends on output capacitance and load current and is typically 1ms per nanofarad of soft-start capaci- tance. with no ss capacitor connected, maximum cur- rent limit is reached within 10?. shutdown shutdown mode ( shdn = 0v) reduces the v+ supply current to typically 1?. in this mode, the reference and vl are inactive. shdn is a logic-level input, but it can be safely driven to the full v+ range. connect shdn to v+ for automatic start-up. do not allow slow transitions (slower than 0.02v/?) on shdn . max796 max797 max799 max874 csl csh gnd fb r5 vref2 >>vref (4.096v) r4 main output dh dl v out = v ref - (v ref2 - v ref ) (? r4 r5 v+ figure 7. output voltage less than 2.5v max796 max797 max799 csl csh 0.01 f 0.01 f gnd fb output (8v as shown) dh dl v out r sense divider impedance 5k (each leg) = v ref (1 + ? r3 r4 v+ r1 2.43k r2 1.1k r3 2.43k r4 1.1k figure 8. adjusting the output voltage to greater than 6v
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power ______________________________________________________________________________________ 19 _________________design procedure the five pre-designed standard application circuits (figure 1 and table 1) contain ready-to-use solutions for common applications. use the following design pro- cedure to optimize the basic schematic for different voltage or current requirements. before beginning a design, firmly establish the following: v in(max) , the maximum input (battery) voltage. this value should include the worst-case conditions, such as no-load operation when a battery charger or ac adapter is connected but no battery is installed. v in(max) must not exceed 30v. this 30v upper limit is determined by the breakdown voltage of the bst float- ing gate driver to gnd (36v absolute maximum). v in(min) , the minimum input (battery) voltage. this should be taken at full-load under the lowest battery conditions. if v in(min) is less than 4.5v, a special circuit must be used to externally hold up vl above 4.8v. if the minimum input-output difference is less than 1.5v, the filter capacitance required to maintain good ac load regulation increases. inductor value the exact inductor value isn? critical and can be adjusted freely in order to make tradeoffs among size, cost, and efficiency. although lower inductor values will minimize size and cost, they will also reduce efficiency due to higher peak currents. to permit use of the physi- cally smallest inductor, lower the inductance until the circuit is operating at the border between continuous and discontinuous modes. reducing the inductor value even further, below this crossover point, results in dis- continuous-conduction operation even at full load. this helps reduce output filter capacitance requirements but causes the core energy storage requirements to increase again. on the other hand, higher inductor val- ues will increase efficiency, but at some point resistive losses due to extra turns of wire will exceed the benefit gained from lower ac current levels. also, high induc- tor values can affect load-transient response; see the v sag equation in the low-voltage operation section. the following equations are given for continuous-con- duction operation since the max796 is mainly intended for high-efficiency battery-powered applications. see appendix a in maxim? battery management and dc- dc converter circuit collection for crossover point and discontinuous-mode equations. discontinuous conduc- tion doesn? affect normal idle-mode operation. max799 negative secondary output main output dh v+ secfb r3 r2 1-shot trig dl 0.33 f ref max796 positive secondary output main output dh v+ secfb 2.505v ref r3 r2 1-shot trig dl +v trip where v ref (nominal) = 2.505v = v ref ( 1 + ) r2 r3 -v trip r3 = 100k (recommended) = -v ref ( ) r2 r3 figure 9. secondary-output feedback dividers, max796 vs. max799
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power 20 ______________________________________________________________________________________ three key inductor parameters must be specified: inductance value (l), peak current (i peak ), and dc resistance (r dc ). the following equation includes a constant lir, which is the ratio of inductor peak-to- peak ac current to dc load current. a higher value of lir allows smaller inductance, but results in higher losses and ripple. a good compromise between size and losses is found at a 30% ripple current to load cur- rent ratio (lir = 0.3), which corresponds to a peak inductor current 1.15 times higher than the dc load current. v out (v in(max) - v out ) l = v in(max) x f x i out x lir where: f = switching frequency, normally 150khz or 300khz i out = maximum dc load current lir = ratio of ac to dc inductor current, typically 0.3 the peak inductor current at full load is 1.15 x i out if the above equation is used; otherwise, the peak current can be calculated by: v out (v in(max) - v out ) i peak = i load + 2 x f x l x v in(max) the inductor? dc resistance is a key parameter for effi- ciency performance and must be ruthlessly minimized, preferably to less than 25m at i out = 3a. if a stan- dard off-the-shelf inductor is not available, choose a core with an li 2 rating greater than l x i peak 2 and wind it with the largest diameter wire that fits the winding area. for 300khz applications, ferrite core material is strongly preferred; for 150khz applications, kool-mu (aluminum alloy) and even powdered iron can be acceptable. if light-load efficiency is unimportant (in desktop 5v-to-3v applications, for example) then low- permeability iron-powder cores, such as the micrometals type found in pulse engineering? 2.1? pe-53680, may be acceptable even at 300khz. for high-current applications, shielded core geometries (such as toroidal or pot core) help keep noise, emi, and switching-waveform jitter low. current-sense resistor value the current-sense resistor value is calculated accord- ing to the worst-case-low current-limit threshold voltage (from the electrical characteristics table) and the peak inductor current. the continuous-mode peak inductor- current calculations that follow are also useful for sizing the switches and specifying the inductor-current satu- ration ratings. in order to simplify the calculation, i load may be used in place of i peak if the inductor value has been set for lir = 0.3 or less (high inductor values) and 300khz operation is selected. low-inductance resistors, such as surface-mount metal-film resistors, are preferred. 80mv r sense = i peak input capacitor value place a small ceramic capacitor (0.1?) between v+ and gnd, close to the device. also, connect a low-esr bulk capacitor directly to the drain of the high-side mosfet. select the bulk input filter capacitor accord- ing to input ripple-current requirements and voltage rat- ing, rather than capacitor value. electrolytic capacitors that have low enough esr to meet the ripple-current requirement invariably have more than adequate capacitance values. aluminum-electrolytic capacitors such as sanyo os-con or nichicon pl are preferred over tantalum types, which could cause power-up surge-current failure, especially when connecting to robust ac adapters or low-impedance batteries. rms input ripple current is determined by the input voltage and load current, with the worst possible case occur- ring at v in = 2 x v out : v out (v in - v out ) i rms = i load x v in i rms = i load / 2 when v in is 2 x v out output filter capacitor value the output filter capacitor values are generally deter- mined by the esr (effective series resistance) and volt- age rating requirements rather than actual capacitance requirements for loop stability. in other words, the low- esr electrolytic capacitor that meets the esr require- ment usually has more output capacitance than is required for ac stability. use only specialized low-esr capacitors intended for switching-regulator applications, such as avx tps, sprague 595d, sanyo os-con, or nichicon pl series. to ensure stability, the capacitor must meet both minimum capacitance and maximum esr values as given in the following equations: v ref (1 + v out / v in(min) ) c f > v out x r sense x f r sense x v out r esr < v ref (can be multiplied by 1.5, see note below)
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power ______________________________________________________________________________________ 21 these equations are ?orst-case?with 45 degrees of phase margin to ensure jitter-free fixed-frequency opera- tion and provide a nicely damped output response for zero to full-load step changes. some cost-conscious designers may wish to bend these rules by using less expensive (lower quality) capacitors, particularly if the load lacks large step changes. this practice is tolerable, provided that some bench testing over temperature is done to verify acceptable noise and transient response. there is no well-defined boundary between stable and unstable operation. as phase margin is reduced, the first symptom is a bit of timing jitter, which shows up as blurred edges in the switching waveforms where the scope won? quite sync up. technically speaking, this (usually) harmless jitter is unstable operation, since the switching frequency is now non-constant. as the capacitor quality is reduced, the jitter becomes more pronounced and the load-transient output voltage waveform starts looking ragged at the edges. eventually, the load-transient waveform has enough ringing on it that the peak noise levels exceed the allowable output voltage tolerance. note that even with zero phase margin and gross instability present, the output voltage noise never gets much worse than i peak x r esr (under constant loads, at least). designers of rf communicators or other noise-sensi- tive analog equipment should be conservative and stick to the guidelines. designers of notebook comput- ers and similar commercial-temperature-range digital systems can multiply the r esr value by a factor of 1.5 without hurting stability or transient response. the output voltage ripple is usually dominated by the esr of the filter capacitor and can be approximated as i ripple x r esr . there is also a capacitive term, so the full equation for ripple in the continuous mode is v noise(p-p) = i ripple x (r esr + 1 / (2 x pi x f x c f )). in idle mode, the inductor current becomes discontinuous with high peaks and widely spaced pulses, so the noise can actually be higher at light load compared to full load. in idle mode, the output ripple can be calcu- lated as: 0.02 x r esr v noise(p-p) = + r sense 0.0003 x l x [1 / v out + 1 / (v in - v out )] (r sense ) 2 x c f transformer design (max796/max799 only) buck-plus-flyback applications, sometimes called ?ou- pled-inductor?topologies, need a transformer in order to generate multiple output voltages. the basic electrical design is a simple task of calculating turns ratios and adding the power delivered to the secondary in order to calculate the current-sense resistor and primary induc- tance. however, extremes of low input-output differen- tials, widely different output loading levels, and high turns ratios can complicate the design due to parasitic trans- former parameters such as inter-winding capacitance, secondary resistance, and leakage inductance. for examples of what is possible with real-world transformers, see the graphs of maximum secondary current vs. input voltage in the typical operating characteristics. power from the main and secondary outputs is lumped together to obtain an equivalent current referred to the main output voltage (see inductor l1 for definitions of parameters). set the value of the current-sense resistor at 80mv / i total . p total = the sum of the output power from all outputs i total = p total / v out = the equivalent output cur- rent referred to v out v out (v in(max) - v out ) l(primary) = v in(max) x f x i total x lir v sec + v fwd turns ratio n = v out(min) + v rect + v sense where: v sec is the minimum required rectified sec- ondary-output voltage v fwd is the forward drop across the secondary rectifier v out(min) is the minimum value of the main output voltage (from the electrical characteristics ) v rect is the on-state voltage drop across the synchronous-rectifier mosfet v sense is the voltage drop across the sense resistor in positive-output (max796) applications, the trans- former secondary return is often referred to the main output voltage rather than to ground in order to reduce the needed turns ratio. in this case, the main output voltage must first be subtracted from the secondary voltage to obtain v sec .
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power 22 ______________________________________________________________________________________ ______selecting other components mosfet switches the two high-current n-channel mosfets must be logic-level types with guaranteed on-resistance specifi- cations at v gs = 4.5v. lower gate threshold specs are better (i.e., 2v max rather than 3v max). drain-source breakdown voltage ratings must at least equal the max- imum input voltage, preferably with a 20% derating fac- tor. the best mosfets will have the lowest on-resistance per nanocoulomb of gate charge. multiplying r ds(on) x q g provides a meaningful figure by which to compare various mosfets. newer mos- fet process technologies with dense cell structures generally give the best performance. the internal gate drivers can tolerate >100nc total gate charge, but 70nc is a more practical upper limit to maintain best switching times. in high-current applications, mosfet package power dissipation often becomes a dominant design factor. i 2 r power losses are the greatest heat contributor for both high- and low-side mosfets. i 2 r losses are dis- tributed between q1 and q2 according to duty factor (see the equations below). switching losses affect the upper mosfet only, since the schottky rectifier clamps the switching node before the synchronous rectifier turns on. gate-charge losses are dissipated by the dri- ver- er and don? heat the mosfet. ensure that both mosfets are within their maximum junction tempera- ture at high ambient temperature by calculating the temperature rise according to package thermal-resis- tance specifications. the worst-case dissipation for the high-side mosfet occurs at the minimum battery volt- age, and the worst-case for the low-side mosfet occurs at the maximum battery voltage. pd (upper fet) = i load 2 x r ds(on) x duty v in x c rss + v in x i load x f x ( ?+20ns ) i gate pd (lower fet) = i load 2 x r ds(on) x (1 - duty) duty = (v out + v q2 ) / (v in - v q1 ) where: on-state voltage drop v q_ = i load x r ds(on) c rss = mosfet reverse transfer capacitance i gate = dh driver peak output current capability (1a typically) 20ns = dh driver inherent rise/fall time under output short circuit, the synchronous-rectifier mosfet suffers extra stress and may need to be over- sized if a continuous dc short circuit must be tolerated. during short circuit, q2? duty factor can increase to greater than 0.9 according to: q2 duty (short circuit) = 1 - [v q2 / (v in(max) - v q1 )] where the on-state voltage drop v q = (120mv / r sense ) x r ds(on). rectifier diode d1 rectifier d1 is a clamp that catches the negative induc- tor swing during the 110ns dead time between turning off the high-side mosfet and turning on the low-side. d1 must be a schottky type in order to prevent the lossy parasitic mosfet body diode from conducting. it is acceptable to omit d1 and let the body diode clamp the negative inductor swing, but efficiency will drop one or two percent as a result. use an mbr0530 (500ma rated) type for loads up to 1.5a, a 1n5819 type for loads up to 3a, or a 1n5822 type for loads up to 10a. d1? rated reverse breakdown voltage must be at least equal to the maximum input voltage, preferably with a 20% derating factor. boost-supply diode d2 a signal diode such as a 1n4148 works well for d2 in most applications. if the input voltage can go below 6v, use a small (20ma) schottky diode for slightly improved efficiency and dropout characteristics. don? use large power diodes such as 1n5817 or 1n4001, since high junction capacitance can cause vl to be pumped up to excessive voltages. rectifier diode d3 (transformer secondary diode) the secondary diode in coupled-inductor applications must withstand high flyback voltages greater than 60v, which usually rules out most schottky rectifiers. common silicon rectifiers such as the 1n4001 are also prohibited, as they are far too slow. this often makes fast silicon rectifiers such as the murs120 the only choice. the flyback voltage across the rectifier is relat- ed to the v in -v out difference according to the trans- former turns ratio: v flyback = v sec + (v in - v out ) x n where: n is the transformer turns ratio sec/pri v sec is the maximum secondary dc output voltage v out is the primary (main) output voltage subtract the main output voltage (v out ) from v flyback in this equation if the secondary winding is returned to v out and not to ground. the diode reverse breakdown rating must also accommodate any ringing due to leak- age inductance. d3? current rating should be at least twice the dc load current on the secondary output.
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power ______________________________________________________________________________________ 23 ____________low-voltage operation low input voltages and low input-output differential volt- ages each require some extra care in the design. low absolute input voltages can cause the vl linear regulator to enter dropout, and eventually shut itself off. low input voltages relative to the output (low v in -v out differential) can cause bad load regulation in multi-output flyback applications. see the design equations in the transformer design section. finally, low v in -v out differentials can also cause the output voltage to sag when the load current changes abruptly. the amplitude of the sag is a function of inductor value and maximum duty factor (an electrical characteristics parameter, 93% guaranteed over temper- ature at f = 150khz) as follows: (i step ) 2 x l v sag = 2 x c f x (v in(min) x d max - v out ) the cure for low-voltage sag is to increase the value of the output capacitor. for example, at v in = 5.5v, v out = 5v, l = 10?, f = 150khz, a total capacitance of 660? will prevent excessive sag. note that only the capacitance requirement is increased and the esr requirements don? change. therefore, the added capacitance can be supplied by a low-cost bulk capacitor in parallel with the normal low-esr capacitor. __________applications information heavy-load efficiency considerations the major efficiency loss mechanisms under loads are, in the usual order of importance: ? p(i 2 r), i 2 r losses ? p(gate), gate-charge losses ? p(diode), diode-conduction losses ? p(tran), transition losses ? p(cap), capacitor esr losses ? p(ic), losses due to the operating supply current of the ic inductor-core losses are fairly low at heavy loads because the inductor? ac current component is small. therefore, they aren? accounted for in this analysis. ferrite cores are preferred, especially at 300khz, but powdered cores such as kool-mu can work well. efficiency = p out / p in x 100% = p out / (p out + p total ) x 100% p total = p(i 2 r) + p(gate) + p(diode) + p(tran) + p(cap) + p(ic) p(i 2 r) = (i load ) 2 x (r dc + r ds(on) + r sense ) where r dc is the dc resistance of the coil, r ds(on) is the mosfet on-resistance, and r sense is the current- table 4. low-voltage troubleshooting supply vl from an external source other than v batt , such as the system 5v supply. vl output is so low that it hits the vl uvlo threshold at 4.2v max. low input voltage, <4.5v won? start under load or quits before battery is completely dead use a small 20ma schottky diode for boost diode d2. supply vl from an external source. vl linear regulator is going into dropout and isn? providing good gate-drive levels. low input voltage, <5v high supply current, poor efficiency reduce f to 150khz. reduce secondary impedances?se schottky if possible. stack secondary winding on main output. not enough duty cycle left to initiate forward-mode operation. small ac current in primary can? store energy for flyback operation. low v in -v out differential, v in < 1.3 x v out (main) (max796/max799 only) secondary output won? support a load reduce l value. tolerate the remaining jitter (extra output capacitance helps somewhat). inherent limitation of fixed-fre- quency current-mode smps slope compensation. low v in -v out differential, <1v unstable?itters between two distinct duty factors reduce f to 150khz. reduce mosfet on-resistance and coil dcr. maximum duty-cycle limits exceeded. low v in -v out differential, <1v dropout voltage is too high (v out follows v in as v in decreases) increase bulk output capacitance per formula above. reduce inductor value. limited inductor-current slew rate per cycle. low v in -v out differential, <1.5v sag or droop in v out under step load change solution root cause condition symptom
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power 24 ______________________________________________________________________________________ sense resistor value. the r ds(on) term assumes identi- cal mosfets for the high- and low-side switches because they time-share the inductor current. if the mosfets aren? identical, their losses can be estimat- ed by averaging the losses according to duty factor. p(gate) = gate-driver loss = qg x f x vl where vl is the max796 internal logic supply voltage (5v), and qg is the sum of the gate-charge values for low- and high-side switches. for matched mosfets, qg is twice the data sheet value of an individual mos- fet. if v out is set to less than 4.5v, replace vl in this equation with v batt . in this case, efficiency can be improved by connecting vl to an efficient 5v source, such as the system +5v supply. p(diode) = diode conduction losses = i load x v fwd x t d x f where t d is the diode conduction time (110ns typ) and v fwd is the forward voltage of the schottky. pd(tran) = transition loss = v batt x c rss v batt x i load x f x (?+ 20ns) i gate where c rss is the reverse transfer capacitance of the high-side mosfet (a data sheet parameter), i gate is the dh gate-driver peak output current (1a typ), and 20ns is the rise/fall time of the dh driver (20ns typ). p(cap) = input capacitor esr loss = (i rms ) 2 x r esr where i rms is the input ripple current as calculated in the input capacitor value section of the design procedure. light-load efficiency considerations under light loads, the pwm operates in discontinuous mode, where the inductor current discharges to zero at some point during the switching cycle. this causes the ac component of the inductor current to be high com- pared to the load current, which increases core losses and i 2 r losses in the output filter capacitors. obtain best light-load efficiency by using mosfets with moderate gate-charge levels and by using ferrite, mpp, or other low-loss core material. avoid powdered iron cores; even kool-mu (aluminum alloy) is not as good as ferrite. __pc board layout considerations good pc board layout is required to achieve specified noise, efficiency, and stability performance. the pc board layout artist must be provided with explicit instructions, preferably a pencil sketch of the place- ment of power switching components and high-current routing. see the evaluation kit pc board layouts in the max796 and max797 ev kit manuals for examples. a ground plane is essential for optimum performance. in most applications, the circuit will be located on a multi- layer board and full use of the four or more copper lay- ers is recommended. use the top layer for high-current connections, the bottom layer for quiet connections (ref, ss, gnd), and the inner layers for an uninterrupt- ed ground plane. use the following step-by-step guide. 1) place the high-power components (c1, c2, q1, q2, d1, l1, and r1) first, with their grounds adjacent. priority 1: minimize current-sense resistor trace lengths (see figure 10). priority 2: minimize ground trace lengths in the high-current paths (discussed below). priority 3: minimize other trace lengths in the high- current paths. use >5mm wide traces. c1 to q1: 10mm max length. d1 cathode to q2: 5mm max length lx node (q1 source, q2 drain, d1 cath- ode, inductor): 15mm max length ideally, surface-mount power components are butted up to one another with their ground terminals almost touching. these high-current grounds (c1-, c2-, source of q2, anode of d1, and pgnd) are then connected to each other with a wide filled zone of top-layer copper, so that they don? go through vias. the resulting top-layer ?ub-ground-plane?is connected to the normal inner-layer ground plane at the output ground terminals. this ensures that the analog gnd of the ic is sensing at the output termi- nals of the supply, without interference from ir drops and ground noise. other high-current paths should also be minimized, but focusing ruthlessly on short ground and current-sense connections eliminates about 90% of all pc layout headaches. see the evaluation kit pc board layouts for examples. 2) place the ic and signal components. keep the main switching node (lx node) away from sensitive ana- log components (current-sense traces and ref and ss capacitors). placing the ic and analog compo- nents on the opposite side of the board from the power-switching node is desirable. important: the ic must be no farther than 10mm from the current- sense resistor. keep the gate-drive traces (dh, dl, and bst) shorter than 20mm and route them away from csh, csl, ref, and ss. 3) employ a single-point star ground where the input ground trace, power ground (sub-ground-plane), and normal ground plane all meet at the output ground terminal of the supply.
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power ______________________________________________________________________________________ 25 max796 max797 max799 sense resistor main current path fat, high-current traces figure 10. kelvin connections for the current-sense resistor max796 csl csh fb gnd ref sync secfb vl 10 2 11 7 3 5 14 si9410 si9410 d2 ec11fs1 t1 = transpower tti5870 * = optional, may not be needed 16 15 13 d1 cmpsh -3a 1n5819 12 8 9 v in (6.5v to 18v) +15v at 250ma +5v at 3a bst v+ dh lx dl 6 on/off 1 pgnd shdn ss 0.33 f c2 4.7 f c3 15 f 2.5v 220 f 6.3v 0.1 f 22 f, 35v 0.01 f 20m 22 * 4700pf* t1 15 h 2.2:1 49.9k, 1% 210k, 1% 0.01 f (optional) 18v 1/4 w c2 4.7 f 4 figure 11. +5v/+15v dual-output application (max796) _________________________________________________________application circuits
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power 26 ______________________________________________________________________________________ max796 csl csh secfb gnd ref fb sync v+ vl 10 2 11 43 5 14 q1 t1 = tdk 1:1.5 transformer pc40eem 12.7/13.7 - a160 core bem 12.7/13.7 bobbin primary = 8 turns 24 awg secondary = 12 turns 24 awg design for tight magnetic coupling q1-q2 = si9410 or equivalent q3 = si9955 or equivalent (50v) q2 q3 16 15 13 1n4148 1n5819 mbr0502l 1n5817 12 8 9 7 v in (8v to 18v as shown) +5v at 500ma +3.3v at 2a bst dh lx dl 6 on/off 1 pgnd shdn ss 0.33 f 4.7 f 47 f 330 f 0.1 f 33 f, 35v 10 h 25m t1 1:1.5 100k, 1% 102k 1% 49.9k 1% 33.2k 1% 102k, 1% 0.01 f (optional) figure 12. +3.3v/+5v dual-output application (max796) max799 csl csh vl ss gnd ref secfb 10 32 11 1 4 14 1/2 si9936 1/2 si9936 eq11fs1 t1 = transpower tti5926 16 15 13 1n4148 1n5819 12 8 9 fb 7 v in (9v to 18v) -5.5v out (-5.5v at 200ma) +5v out (+5v at 1a) bst v+ dh lx dl 6 5 on/off pgnd shdn sync 0.01 f (optional) 220 f 10v 0.1 f 22 f, 35v 1 f 22 f 10v 50m t1 15 h 1:1.3 221k, 1% 1000pf 107k, 1% 4.7 f figure 13. ?v dual-output application (max799) ____________________________________________application circuits (continued)
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power ______________________________________________________________________________________ 27 max473 v+ input 4.5v to 30v q1 si9433dy or mmsf4p01 82pf vl (5v) 20pf 1k 100k, 1% 1.5k 16k, 1% ref (2.505v) main 3.3v output (csl) +3.3v main output +2.9v output at 2a standard 3.3v circuit 10 f10 f max797 sanyo os-con figure 14. 2.9v low-dropout linear regulator with fast transient response max797 csl csh vl sync ref gnd v+ q1 fb 100k 100k +5v at 1a bst dh lx dl pgnd 2n7002 optional sync and low-voltage start-up circuit skip shdn v in 2.5v to 5.25v c2 100 f c3 100 f 0.33 f 0.033 0.01 f c1 100 f d1 1n4148 190khz - 340khz 1n4148 +3.3v (external) 33k 4.7 f l1 5 h 0.1 f l1 = sumida cdrh125, 5 h d1 = motorola mbr130 c1 - c3 = avx tps 100 f, 10v q1 = siliconix si9936 (both sections) or motorola mmdf3n03l figure 15. low-noise boost converter for cellular phones ____________________________________________application circuits (continued)
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power 28 ______________________________________________________________________________________ max797 csl csh ss vl sync ref gnd v+ q1 fb 191k 49.9k +12v at 2a bst dh lx pgnd skip shdn vin 4.75v to 6v c2 150 f c3 150 f 0.33 f 0.01 0.01 f c1 220 f d1 4.7 f l1 5 h l1 = 2x sumida cdrh125-100 in parallel d1 = motorola mbr640 q1 = motorola mtd20n03hdl c1 = sanyo os-con 220 f, 10v c2, c3 = sanyo os-con 150 f, 16v figure 16. 5v-to-12v pwm boost converter max797 csl csh vl sync ref gnd v+ q1 t1 q2 fb 200k 200k output +5v at 500ma bst cmpsh-3a dh lx dl pgnd skip hi eff low iq shdn input 3v to 6.5v 4.7 f 0.33 f 33m 220 f 220 f 100 f q1, q2 = si9410dy t1 = coiltronix ctx 10-4 10 h primary, 1:1 start-up supply voltage = 3.5v typ figure 17. 90% efficient, low-voltage pwm flyback converter (4 cells to 5v) ____________________________________________application circuits (continued)
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power ______________________________________________________________________________________ 29 max797 csl csh vl sync ref gnd to vl v+ q1 q2 fb 1000pf r1 63.4k 0.1% r2 200k 0.1% 10k output 3.3v ?.8% remote sense point bst dh lx dl pgnd skip ss shdn input 4.7 f 0.33 f 0.01 f r sense v out use external reference (max872) for better accuracy. adjust range = 2.5v to 4v as shown. omit r2 for v out = 2.5v. = v ref ( 1 + ) r1 r2 l1 max495 51k 5% 200k 5% 51k 5% figure 18. high-accuracy adjustable-output application max797 csl csh vl 1n5819 sync ref gnd v+ si9410 si9410 fb -5v at 1.5a bst dh lx dl pgnd skip input 4.5v to 25v shdn 0.33 f 0.1 f4.7 f 22 f 22 f 1n4148 l1 0.025 150 f 150 f l1 = dale lpe6562-a093 figure 19. negative-output (inverting topology) power supply ____________________________________________application circuits (continued)
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power 30 ______________________________________________________________________________________ max797 csl csh fb vl sync v+ q1 q2 1n4148 1n4148 d1 1n5819 t1 ref gnd +5v output at 3a bst dh lx dl pgnd skip ss shdn input 0.33 f c1 2x 22 f 4.7 f c2 220 f 0.1 f 0.01 f 0.1 f 100k 1% 100k 1% 10 h 1.91 , 1% t1 = 1:70 5mm surface-mount transformer dale lpe-3325-a087 q1, q2 = mmsf5n03 or si9410dy figure 20. buck converter with low-loss smt current-sense transformer ____________________________________________application circuits (continued) max797 max495 csl csh vl sync fb v+ n1 n2 d1 d2 1n5820 ref gnd 1.5v output at 5a dh lx dl pgnd bst skip ss on/off shdn input 4.75v to 5.5v 4.7 f 0.1 f c6 0.01 f c2 2 x 220 f os-con c3 0.1 f c5 0.33 f l1 3.3 h c7 330pf r1 12m r6 49.9k r7 124k r5 150k to vl r3 66.5k 1% r4 100k 1% c1 220 f os-con remote sense line n1 = n2 = mtd20n03hdl l1 = coilcraft do3316-332 figure 21. 1.5v gtl bus termination supply
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power ______________________________________________________________________________________ 31 max797 max495 csl 0.1 f 0.01 f 0.01 f 4.7 f i out 2.5a v in 10.5v to 28v gnd fb v+ 0.33 f 0.33 f l1 10 h 0.025 shdn 9 3 2 6 7 4 sync ss dl 5 74 1 6 13 pgnd 12 lx 15 dh 16 skip 2 bst 14 vl 11 10 ref 3 csh 8 3x 100 f 16v 2x 22 f 35v 1.0k 39k d2 1.7 t1 d1 d3 q1 q2 d1, d3 central semi. cmpsh-3 d2 niec ec10qs02l, schottky rect. l1 dale ihsm-4825 10 h 15% t1 dale lpe-3325-a087, current transformer, 1:70 q1, q2 motorola mmsf5n03hd figure 22. battery-charger current source ____________________________________________application circuits (continued)
max796/max797/max799 step-down controllers with synchronous rectifier for cpu power ___________________chip topography lx shdn csl 0.16o" (4.064mm) 0.085" (2.159mm) fb csh bst dl pgnd vl v+ dh ss gnd sync ref skip (secfb) ( ) are for max796/max799 only. _ordering information (continued) *contact factory for dice specifications. transistor count: 913 substrate connected to gnd maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 32 __________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. part temp range pin-package max797 cpe 0? to +70? 16 plastic dip max797cpe+ 0? to +70? 16 plastic dip max797cse 0? to +70? 16 narrow so max797cse+ 0? to +70? 16 narrow so max797c/d 0? to +70? dice* max797c/d+ 0? to +70? dice* max797epe -40? to +85? 16 plastic dip max797epe+ -40? to +85? 16 plastic dip max797ese -40? to +85? 16 narrow so max797ese+ -40? to +85? 16 narrow so max797mje -55? to +125? 16 cerdip max797mje+ -55? to +125? 16 cerdip max799 cpe 0? to +70? 16 plastic dip max799cse 0? to +70? 16 narrow so max799c/d 0? to +70? dice* max799epe -40? to +85? 16 plastic dip max799ese -40? to +85? 16 narrow so max799mje -55? to +125? 16 cerdip

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