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32-bit tx system risc tx19 family TMP1941AF
mips16, application specific extensions and r3000a are a trademark of mips technologies, inc. the information contained herein is subject to change without notice. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. the products described in this document contain components made in the united states and subject to export control of the u.s. authorities. diversion contrary to the u.s. law is prohibited. toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications ( computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. the products described in this document may include products subject to the foreign exchange and foreign trade laws. ? 2003 toshiba corporation all rights reserved
preface toshiba offers a broad range of microcontrollers targeted for both commercial and industrial applications. the tx system risc tx19 family manual contains the detailed specifications of the tx1941, including the architecture, programming, capabilities, operation, electrical characteristics, packaging and so forth. the tx1941 is a high-performance risc processor based on the r3000a architecture and the mips16 application specific extension pioneered by mips technologies, inc. recently, with the ever-growing market for lightweight portable devices, manufacturers of electronic systems have been seeking cost-effective, single-chip solutions to processor-based applications. toshiba has designed the tx1941 to help customers achieve the best cost performance for their products.

TMP1941AF i contents handling precaution TMP1941AF 1. features ..................................................................................................................... .............................................. 1 2. signal descriptions .......................................................................................................... ....................................... 5 2.1 pin assignment .............................................................................................................. .................................... 5 2.2 pin usage information....................................................................................................... ................................ 6 3. core processor ............................................................................................................... ......................................... 9 3.1 reset operation ............................................................................................................. .................................... 9 4. memory map................................................................................................................... ...................................... 10 5. clock/standby control ........................................................................................................ .................................. 11 5.1 clock generation............................................................................................................ ................................. 12 5.1.1 main system clock......................................................................................................... ........................ 12 5.1.2 subsystem clock........................................................................................................... .......................... 12 5.1.3 clock source block diagrams ............................................................................................... ................. 13 5.2 clock generator (cg) registers.............................................................................................. ........................ 14 5.2.1 system clock control registers............................................................................................ .................. 14 5.2.2 adc conversion clock ...................................................................................................... .................... 16 5.2.3 stop/sleep wake-up interrupt control registers (intcg registers) ............................................... 16 5.2.4 interrupt request clear register.......................................................................................... ................... 18 5.3 system clock control section ................................................................................................ ......................... 19 5.3.1 oscillation stabilization time when switching between normal and slow modes...................... 19 5.3.2 system clock output ....................................................................................................... ....................... 20 5.3.3 reducing the oscillator clock drive capability............................................................................ ......... 20 5.4 prescalar clock control section............................................................................................. ......................... 21 5.5 clock frequency multiplication section (pll)................................................................................ ............... 21 5.6 standby control section ..................................................................................................... ............................. 22 5.6.1 TMP1941AF operation in normal and standby modes.................................................................... 23 5.6.2 cg operation in normal and standby modes .................................................................................. .23 5.6.3 processor and peripheral block operation in standby modes................................................................ 2 3 5.6.4 wake-up signaling......................................................................................................... ......................... 24 5.6.5 stop mode ................................................................................................................. ........................... 26 5.6.6 returning from a standby mode............................................................................................. ................ 26 6. interrupts ................................................................................................................... ............................................ 29 6.1 overview .................................................................................................................... ..................................... 29 6.2 interrupt sources........................................................................................................... ................................... 31 6.3 interrupt detection......................................................................................................... .................................. 33 6.4 resolving interrupt priority................................................................................................ ............................. 33 6.5 register description ........................................................................................................ ................................ 34 6.5.1 interrupt vector register (ivr)........................................................................................... ................... 34 6.5.2 interrupt mode control registers (imcf?imc0) .............................................................................. .... 35 6.5.3 interrupt request clear register (intclr) ................................................................................. .......... 35 7. i/o ports .................................................................................................................... ............................................ 36 7.1 address/data bus bits 0?7 (ad0?ad7)......................................................................................... ................ 40 7.2 address/data bus bits 8?15 (ad8?ad15) / address bus bits 8?15 (a8?a15) ............................................ 40 7.3 address bus bits 16?23 (a16?a23) ............................................................................................ ................... 41 7.4 rd , wr , hwr , wait , busrq , busak , w / r ..................................................................................... 41 7.5 port 37 ..................................................................................................................... ........................................ 43 7.6 port 4 (p40?p44) ............................................................................................................ ................................. 44
TMP1941AF ii 7.7 port 5 (p50?p57) ............................................................................................................ ................................. 47 7.8 port 7 (p70?p77) ............................................................................................................ ................................. 48 7.9 port 8 (p80?p87) ............................................................................................................ ................................. 52 7.10 port 9 (p90?p97) ........................................................................................................... .................................. 55 7.11 port a (pa0?pa7) ........................................................................................................... ................................ 60 7.12 open-drain output control .................................................................................................. ........................... 65 8. external bus interface....................................................................................................... .................................... 66 8.1 address and data buses ...................................................................................................... ............................ 67 8.1.1 supported configurations .................................................................................................. ..................... 67 8.1.2 states of the address bus during on-chip address accesses ............................................................... 67 8.2 external bus operation...................................................................................................... .............................. 68 8.2.1 basic bus operation ....................................................................................................... ........................ 68 8.2.2 wait timing............................................................................................................... ............................. 69 8.2.3 ale pulse width ........................................................................................................... ......................... 71 8.2.4 read recovery time........................................................................................................ ....................... 72 8.3 bus arbitration ............................................................................................................. ................................... 73 8.3.1 bus access control........................................................................................................ ......................... 73 8.3.2 bus arbitration flow ...................................................................................................... ........................ 73 8.3.3 relinquishing the bus..................................................................................................... ......................... 74 9. chip select/wait controller .................................................................................................. ................................ 75 9.1 programming chip select ranges .............................................................................................. ..................... 75 9.1.1 base/mask address registers (bma0?bma3) ................................................................................... .. 75 9.1.2 base address and address mask value calculations .......................................................................... ... 78 9.2 chip select/wait control registers .......................................................................................... ....................... 81 9.3 application example ......................................................................................................... .............................. 83 10. dma controller (dmac)....................................................................................................... .............................. 84 10.1 features................................................................................................................... ......................................... 84 10.2 implementation ............................................................................................................. ................................... 85 10.2.1 on-chip dmac interface................................................................................................... .................... 85 10.2.2 dmac block............................................................................................................... ........................... 86 10.2.3 bus snooping............................................................................................................. ............................. 86 10.3 register description ....................................................................................................... ................................. 87 10.3.1 dma control register (dcr) ............................................................................................... ................. 88 10.3.2 channel control registers (ccrn)......................................................................................... ................ 89 10.3.3 channel status registers (csrn).......................................................................................... .................. 91 10.3.4 source address registers (sarn) .......................................................................................... ................ 92 10.3.5 destination address registers (darn) ..................................................................................... ............. 93 10.3.6 byte count registers (bcrn) .............................................................................................. ................... 94 10.3.7 dma transfer control registers (dtcrn)................................................................................... ......... 95 10.3.8 data holding register (dhr).............................................................................................. ................... 96 10.4 operation .................................................................................................................. ....................................... 97 10.4.1 overview................................................................................................................. ................................ 97 10.4.2 transfer request generation .............................................................................................. .................. 100 10.4.3 dma address modes ........................................................................................................ ................... 101 10.4.4 dma channel operation .................................................................................................... .................. 102 10.4.5 dma channel priority..................................................................................................... ..................... 104 10.4.6 interrupts............................................................................................................... ................................ 104 10.4.7 data packing and unpacking ............................................................................................... ................. 105 10.5 dma transfer timing........................................................................................................ ........................... 106 10.5.1 dual-address mode ........................................................................................................ ...................... 106 10.6 programming example ........................................................................................................ .......................... 108 11. 8-bit timers (tmras)........................................................................................................ ................................ 109 11.1 block diagrams ............................................................................................................. ................................ 110 11.2 timer components ........................................................................................................... ............................. 112
TMP1941AF iii 11.2.1 prescaler................................................................................................................ ................................ 112 11.2.2 up-counters (uc0 and uc1) ................................................................................................ ............... 113 11.2.3 timer registers (ta0reg and ta1reg) ...................................................................................... ..... 113 11.2.4 comparators (cp0 and cp1)................................................................................................ ................. 114 11.2.5 timer flip-flop (ta1ff) .................................................................................................. ................... 114 11.3 register description ....................................................................................................... ............................... 115 11.4 operating modes ............................................................................................................ ............................... 120 11.4.1 8-bit interval timer mode................................................................................................ .................... 120 11.4.2 16-bit interval timer mode............................................................................................... ................... 122 11.4.3 8-bit programmable pulse generation (ppg) mode ........................................................................... . 123 11.4.4 8-bit pwm generation mode................................................................................................ ............... 125 11.4.5 operating mode summary................................................................................................... ................. 128 12. 16-bit timer/event counters (tmrbs)......................................................................................... ..................... 129 12.1 block diagrams ............................................................................................................. ................................ 130 12.2 timer components ........................................................................................................... ............................. 134 12.2.1 prescaler................................................................................................................ ................................ 134 12.2.2 up-counter (uc0) ......................................................................................................... ....................... 135 12.2.3 timer registers (tb0rg0h/l and tb0rg1h/l)................................................................................ 135 12.2.4 capture registers (tb0cp0h/l and tb0cp1h/l) .............................................................................. 136 12.2.5 capture control logic .................................................................................................... ...................... 137 12.2.6 comparators (cp0 and cp1)................................................................................................ ................. 138 12.2.7 timer flip-flop (tb0ff0)................................................................................................. ................... 138 12.3 register description ....................................................................................................... ............................... 139 12.4 operating modes ............................................................................................................ ............................... 149 12.4.1 16-bit interval timer mode ............................................................................................... ................... 149 12.4.2 16-bit event counter mode................................................................................................ .................. 149 12.4.3 16-bit programmable pulse generation (ppg) mode .......................................................................... 150 12.4.4 timing and measurement functions using the capture capability...................................................... 152 13. serial i/o (sio)............................................................................................................ ....................................... 157 13.1 block diagrams ............................................................................................................. ................................ 159 13.2 sio components............................................................................................................. ............................... 163 13.2.1 prescaler................................................................................................................ ................................ 163 13.2.2 baud rate generator...................................................................................................... ....................... 164 13.2.3 serial clock generator................................................................................................... ....................... 167 13.2.4 receive counter.......................................................................................................... .......................... 167 13.2.5 receive controller ....................................................................................................... ......................... 167 13.2.6 receive buffer ........................................................................................................... ........................... 167 13.2.7 transmit counter ......................................................................................................... ......................... 168 13.2.8 transmit controller...................................................................................................... ......................... 168 13.2.9 transmit buffer.......................................................................................................... ........................... 170 13.2.10 parity controller ....................................................................................................... ............................ 170 13.2.11 error flags (uart mode only) ............................................................................................ ................ 170 13.2.12 signal generation timing ................................................................................................ ..................... 171 13.3 register description ....................................................................................................... ............................... 172 13.4 operating modes ............................................................................................................ ............................... 186 13.4.1 mode 0 (i/o interface mode).............................................................................................. .................. 186 13.4.2 mode 1 (7-bit uart mode) ................................................................................................. ............... 189 13.4.3 mode 2 (8-bit uart mode) ................................................................................................. ............... 190 13.4.4 mode 3 (9-bit uart mode) ................................................................................................. ............... 190 14. serial bus interface (sbi) .................................................................................................. ................................. 193 14.1 block diagram.............................................................................................................. ................................. 193 14.2 registers .................................................................................................................. ...................................... 194 14.3 i 2 c bus mode data formats........................................................................................................ .................. 194 14.4 description of the registers used in i 2 c bus mode...................................................................................... 195 14.5 i 2 c bus mode configuration ....................................................................................................... .................. 199
TMP1941AF iv 14.5.1 acknowledgment mode ...................................................................................................... .................. 199 14.5.2 number of bits per transfer.............................................................................................. ................... 199 14.5.3 serial clock............................................................................................................. .............................. 199 14.5.4 slave addressing and address recognition mode ............................................................................ ... 200 14.5.5 configuring the sbi as a master or a slave ............................................................................... ........... 200 14.5.6 configuring the sbi as a transmitter or a receiver ....................................................................... ...... 201 14.5.7 generating start and stop conditions ..................................................................................... ...... 201 14.5.8 asserting and deasserting interrupt requests............................................................................. .......... 202 14.5.9 sbi operating modes ...................................................................................................... ..................... 202 14.5.10 lost-arbitration detection monitor ...................................................................................... ................ 202 14.5.11 slave address match monitor ............................................................................................. ................. 203 14.5.12 general-call detection monitor .......................................................................................... ................. 203 14.5.13 last received bit monitor............................................................................................... ..................... 203 14.5.14 software reset .......................................................................................................... ............................ 204 14.5.15 serial bus interface data buffer register (sbi0dbr)..................................................................... .... 204 14.5.16 i 2 c bus address register (i2c0ar)................................................................................................ ..... 204 14.5.17 baud rate register 1 (sbi0dbr1) ......................................................................................... ............. 204 14.5.18 baud rate register 0 (sbi0br0) .......................................................................................... ............... 204 14.6 programming sequences in i 2 c bus mode.................................................................................................... 205 14.6.1 sbi initialization....................................................................................................... ............................ 205 14.6.2 generating a start condition and a slave address ......................................................................... . 205 14.6.3 transferring a data word ................................................................................................. .................... 206 14.6.4 generating a stop condition .............................................................................................. ................ 210 14.6.5 repeated start condition ................................................................................................. ................ 211 14.7 description of registers used in clock-synchronous 8-bit sio mode ........................................................ 21 2 14.8 clock-synchronous 8-bit sio mode operation ................................................................................. ........... 214 14.8.1 serial clock............................................................................................................. .............................. 214 14.8.2 sio transfer modes....................................................................................................... ....................... 216 15. analog-to-digital converter (adc)........................................................................................... ......................... 221 15.1 register description ....................................................................................................... ............................... 222 15.2 operation .................................................................................................................. ..................................... 227 15.2.1 analog reference voltages................................................................................................ ................... 227 15.2.2 selecting an analog input channel (s).................................................................................... .............. 227 15.2.3 starting an a/d conversion ............................................................................................... ................... 227 15.2.4 conversion modes and conversion-done interrupts .......................................................................... .. 228 15.2.5 conversion time.......................................................................................................... ......................... 229 15.2.6 storing and reading the a/d conversion result............................................................................ ...... 229 15.3 programming examples....................................................................................................... .......................... 231 16. watchdog timer (wdt) ........................................................................................................ ............................. 232 16.1 implementation ............................................................................................................. ................................. 232 16.2 register description ....................................................................................................... ............................... 234 16.2.1 watchdog timer mode register (wdmod) ..................................................................................... .. 234 16.2.2 watchdog timer control register (wdcr) ................................................................................... ..... 234 16.3 operation .................................................................................................................. ..................................... 236 17. real-time clock (rtc) ....................................................................................................... ............................... 237 17.1 implemention............................................................................................................... .................................. 237 18. electrical characteristics.................................................................................................. ................................... 239 18.1 maximum ratings............................................................................................................ .............................. 239 18.2 dc electrical characteristics (1/2) ........................................................................................ ........................ 240 18.3 dc electrical characteristics (2/2) ........................................................................................ ........................ 241 18.4 ac electrical characteristics.............................................................................................. ........................... 242 18.5 adc electrical characteristics ............................................................................................. ......................... 248 18.6 sio timing ................................................................................................................. ................................... 249 18.6.1 i/o interface mode....................................................................................................... ......................... 249
TMP1941AF v 18.7 sbi timing ................................................................................................................. ................................... 250 18.7.1 i 2 c mode......................................................................................................................... ...................... 250 18.7.2 clock-synchronous 8-bit sio mode ......................................................................................... ........... 251 18.8 event counters (ta0in, ta2in, tb0in0, tb0in1, tb2in0)..................................................................... 2 52 18.9 timer capture (tb0in0, tb0in1, tb1in0, tb1in1, tb2in0, tb2in1) .................................................. 252 18.10 general interrupts ........................................................................................................ .................................. 252 18.11 nmi and stop/sleep wake-up interrupts ............................................................................................. ... 252 18.12 scout pin................................................................................................................. ................................... 252 18.13 bus request and bus acknowledge signals................................................................................... ............... 253 19. i/o register summary........................................................................................................ ................................. 254 19.1 i/o ports .................................................................................................................. ...................................... 260 19.2 interrupt controller....................................................................................................... ................................. 262 19.3 chip select/wait controller ................................................................................................ .......................... 274 19.4 clock generator (cg) ....................................................................................................... ............................ 278 19.5 dma controller (dmac) ...................................................................................................... ....................... 280 19.6 8-bit timers (tmras) ....................................................................................................... ........................... 296 19.7 16-bit timer/event counters (tmrbs) ........................................................................................ ................ 297 19.8 serial i/o (sio) ........................................................................................................... .................................. 299 19.9 serial bus interface (sbi)................................................................................................. ............................. 302 19.10 a/d converter (adc) ....................................................................................................... ............................ 303 19.11 watchdog timer (wdt) ...................................................................................................... ......................... 304 19.12 real-time clock (rtc) ..................................................................................................... ........................... 304 20. i/o port equivalent-circuit diagrams........................................................................................ ......................... 305 21. notations, precautions and restrictions ..................................................................................... ......................... 308 21.1 notations and terms........................................................................................................ .............................. 308 21.2 precautions and restrictions............................................................................................... ........................... 308
TMP1941AF vi
handling precautions

1 using toshiba semiconductors safely 1 1. using toshiba semiconductors safely toshiba are continually working to improve the quality and the reliability of their products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a toshiba product could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent products specifications. also, please keep in mind the precautions and conditions set forth in the toshiba semiconductor reliability handbook.
2 safety precautions 2 2. safety precautions this section lists important precautions which users of semiconductor devices (and anyone else) should observe in order to avoid injury and damage to property, and to ensure safe and correct use of devices. please be sure that you understand the meanings of the labels and the graphic symbol described below before you move on to the detailed descriptions of the precautions. [explanation of labels] indicates an imminently hazardous situation which will result in death or serious injury if you do not follow instructions. indicates a potentially hazardous situation which could result in death or serious injury if you do not follow instructions. indicates a potentially hazardous situation which if not avoided, may result in minor injury or moderate injury. [explanation of graphic symbol] graphic symbol meaning indicates that caution is required (laser beam is dangerous to eyes).
2 safety precautions 3 2.1 general precautions regarding semiconductor devices do not use devices under conditions exceeding their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature). this may cause the device to break down, degrade its performance, or cause it to catch fire or explode resulting in injury. do not insert devices in the wrong orientation. make sure that the positive and negative terminals of power supplies are connected correctly. otherwise the rated maximum current or power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to catch fire or explode and resulting in injury. when power to a device is on, do not touch the device?s heat sink. heat sinks become hot, so you may burn your hand. do not touch the tips of device leads. because some types of device have leads with pointed tips, you may prick your finger. when conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment?s electrodes or probes to the pins of the device under test before powering it on. otherwise, you may receive an electric shock causing injury. before grounding an item of measuring equipment or a soldering iron, check that there is no electrical leakage from it. electrical leakage may cause the device which you are testing or soldering to break down, or could give you an electric shock. always wear protective glasses when cutting the leads of a device with clippers or a similar tool. if you do not, small bits of metal flying off the cut ends may damage your eyes.
2 safety precautions 4 2.2 precautions specific to each product group 2.2.1 optical semiconductor devices when a visible semiconductor laser is operating, do not look directly into the laser beam or look through the optical system. this is highly likely to impair vision, and in the worst case may cause blindness. if it is necessary to examine the laser apparatus, for example to inspect its optical characteristics, always wear the appropri ate type of laser protective glasses as stipulated by iec standard iec825-1. ensure that the current flowing in an led device does not exceed the device?s maximum rated current. this is particularly important for resin-packaged led devices, as excessive current may cause the package resin to blow up, scattering resin fragments and causing injury. when testing the dielectric strength of a photocoupler, use testing equipment which can shut off the supply voltage to the photocoupler. if you detect a leakage current of more than 100 2.2.2 power devices never touch a power device while it is powered on. also, after turning off a power device, do not touch it until it has thoroug hly discharged all remaining electrical charge. touching a power device while it is powered on or still charged could cause a severe electric shock, resulting in death or seri ous injury. when conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment?s electrodes or probes to the device under test before powering it on. when you have finished, discharge any electrical charge remaining in the device. connecting the electrodes or probes of testing equipment to a device while it is powered on may result in electric shock, causi ng injury.
2 safety precautions 5 do not use devices under conditions which exceed their absolute maximum ratings (current, voltage, power dissipation, temperature etc.). this may cause the device to break down, causing a large short-circuit current to flow, which may in turn cause it to catch fir e or explode, resulting in fire or injury. use a unit which can detect short-circuit currents and which will shut off the power supply if a short-circuit occurs. if the power supply is not shut off, a large short-circuit current will flow continuously, which may in turn cause the device t o catch fire or explode, resulting in fire or injury. when designing a case for enclosing your system, consider how best to protect the user from shrapnel in the event of the device catching fire or exploding. flying shrapnel can cause injury. when conducting any kind of evaluation, inspection or testing, always use protective safety tools such as a cover for the devic e. otherwise you may sustain injury caused by the device catching fire or exploding. make sure that all metal casings in your design are grounded to earth. even in modules where a device?s electrodes and metal casing are insulated, capacitance in the module may cause the electrostatic potential in the casing to rise. dielectric breakdown may cause a high voltage to be applied to the casing, causing electric shock and injury to anyone touching it. when designing the heat radiation and safety features of a system incorporating high-speed rectifiers, remember to take the device?s forward and reverse losses into account. the leakage current in these devices is greater than that in ordinary rectifiers; as a result, if a high-speed rectifier is use d in an extreme environment (e.g. at high temperature or high voltage), its reverse loss may increase, causing thermal runaway to occur . this may in turn cause the device to explode and scatter shrapnel, resulting in injury to the user. a design should ensure that, except when the main circuit of the device is active, reverse bias is applied to the device gate w hile electricity is conducted to control circuits, so that the main circuit will become inactive. malfunction of the device may cause serious accidents or injuries. when conducting any kind of evaluation, inspection or testing, either wear protective gloves or wait until the device has coole d properly before handling it. devices become hot when they are operated. even after the power has been turned off, the device will retain residual heat which may cause a burn to anyone touching it. 2.2.3 bipolar ics (for use in automobiles) if your design includes an inductive load such as a motor coil, incorporate diodes or similar devices into the design to preven t negative current from flowing in. the load current generated by powering the device on and off may cause it to function erratically or to break down, which could in turn cause injury. ensure that the power supply to any device which incorporates protective functions is stable. if the power supply is unstable, the device may operate erratically, preventing the protective functions from working correctly . if protective functions fail, the device may break down causing injury to the user.
3 general safety precautions and usage considerations 6 3. general safety precautions and usage considerations this section is designed to help you gain a better understanding of semiconductor devices, so as to ensure the safety, quality and reliability of the devices which you incorporate into your designs. 3.1 from incoming to shipping 3.1.1 electrostatic discharge (esd) when handling individual devices (which are not yet mounted on a printed circuit board), be sure that the environment is protected against electrostatic electricity. operators should wear anti-static clothing, and containers and other objects which come into direct contact with devices should be made of anti-static materials and should be grounded to earth via an 0.5- to 1.0-m ? protective resistor. please follow the precautions described below; this is particularly important for devices which are marked ?be careful of static.?. (1) work environment ? when humidity in the working environment decreases, the human body and other insulators can easily become charged with static electricity due to friction. maintain the recommended humidity of 40% to 60% in the work environment, while also taking into account the fact that moisture-proof-packed products may absorb moisture after unpacking. ? be sure that all equipment, jigs and tools in the working area are grounded to earth. ? place a conductive mat over the floor of the work area, or take other appropriate measures, so that the floor surface is protected against static electricity and is grounded to earth. the surface resistivity should be 10 4 to 10 8 ? /sq and the resistance between surface and ground, 7.5 10 5 to 10 8 ? ? cover the workbench surface also with a conductive mat (with a surface resistivity of 10 4 to 10 8 ? /sq, for a resistance between surface and ground of 7.5 10 5 to 10 8 ? ) . the purpose of this is to disperse static electricity on the surface (through resistive components) and ground it to earth. workbench surfaces must not be constructed of low-resistance metallic materials that allow rapid static discharge when a charged device touches them directly. ? pay attention to the following points when using automatic equipment in your workplace: (a) when picking up ics with a vacuum unit, use a conductive rubber fitting on the end of the pick-up wand to protect against electrostatic charge. (b) minimize friction on ic package surfaces. if some rubbing is unavoidable due to the device?s mechanical structure, minimize the friction plane or use material with a small friction coefficient and low electrical resistance. also, consider the use of an ionizer. (c) in sections which come into contact with device lead terminals, use a material which dissipates static electricity. (d) ensure that no statically charged bodies (such as work clothes or the human body) touch the devices.
3 general safety precautions and usage considerations 7 (e) make sure that sections of the tape carrier which come into contact with installation devices or other electrical machinery are made of a low-resistance material. (f) make sure that jigs and tools used in the assembly process do not touch devices. (g) in processes in which packages may retain an electrostatic charge, use an ionizer to neutralize the ions. ? make sure that crt displays in the working area are protected against static charge, for example by a vdt filter. as much as possible, avoid turning displays on and off. doing so can cause electrostatic induction in devices. ? keep track of charged potential in the working area by taking periodic measurements. ? ensure that work chairs are protected by an anti-static textile cover and are grounded to the floor surface by a grounding chain. (suggested resistance between the seat surface and grounding chain is 7.5 10 5 to 10 12 ? .) ? install anti-static mats on storage shelf surfaces. (suggested surface resistivity is 10 4 to 10 8 ? /sq; suggested resistance between surface and ground is 7.5 10 5 to 10 8 ? .) ? for transport and temporary storage of devices, use containers (boxes, jigs or bags) that are made of anti-static materials or materials which dissipate electrostatic charge. ? make sure that cart surfaces which come into contact with device packaging are made of materials which will conduct static electricity, and verify that they are grounded to the floor surface via a grounding chain. ? in any location where the level of static electricity is to be closely controlled, the ground resistance level should be class 3 or above. use different ground wires for all items of equipment which may come into physical contact with devices. (2) operating environment ? operators must wear anti-static clothing and conductive shoes (or a leg or heel strap). ? operators must wear a wrist strap grounded to earth via a resistor of about 1 m ? . ? soldering irons must be grounded from iron tip to earth, and must be used only at low voltages (6 v to 24 v). ? if the tweezers you use are likely to touch the device terminals, use anti-static tweezers and in particular avoid metallic tweezers. if a charged device touches a low-resistance tool, rapid discharge can occur. when using vacuum tweezers, attach a conductive chucking pat to the tip, and connect it to a dedicated ground used especially for anti-static purposes (suggested resistance value: 10 4 to 10 8 ? ). ? do not place devices or their containers near sources of strong electrical fields (such as above a crt).
3 general safety precautions and usage considerations 8 ? when storing printed circuit boards which have devices mounted on them, use a board container or bag that is protected against static charge. to avoid the occurrence of static charge or discharge due to friction, keep the boards separate from one other and do not stack them directly on top of one another. ? ensure, if possible, that any articles (such as clipboards) which are brought to any location where the level of static electricity must be closely controlled are constructed of anti-static materials. ? in cases where the human body comes into direct contact with a device, be sure to wear anti- static finger covers or gloves (suggested resistance value: 10 8 ? or less). ? equipment safety covers installed near devices should have resistance ratings of 10 9 ? or less. ? if a wrist strap cannot be used for some reason, and there is a possibility of imparting friction to devices, use an ionizer. ? the transport film used in tcp products is manufactured from materials in which static charges tend to build up. when using these products, install an ionizer to prevent the film from being charged with static electricity. also, ensure that no static electricity will be applied to the product?s copper foils by taking measures to prevent static occuring in the peripheral equipment. 3.1.2 vibration, impact and stress handle devices and packaging materials with care. to avoid damage to devices, do not toss or drop packages. ensure that devices are not subjected to mechanical vibration or shock during transportation. ceramic package devices and devices in canister-type packages which have empty space inside them are subject to damage from vibration and shock because the bonding wires are secured only at their ends. plastic molded devices, on the other hand, have a relatively high level of resistance to vibration and mechanical shock because their bonding wires are enveloped and fixed in resin. however, when any device or package type is installed in target equipment, it is to some extent susceptible to wiring disconnections and other damage from vibration, shock and stressed solder junctions. therefore when devices are incorporated into the design of equipment which will be subject to vibration, the structural design of the equipment must be thought out carefully. if a device is subjected to especially strong vibration, mechanical shock or stress, the package or the chip itself may crack. in products such as ccds which incorporate window glass, this could cause surface flaws in the glass or cause the connection between the glass and the ceramic to separate. furthermore, it is known that stress applied to a semiconductor device through the package changes the resistance characteristics of the chip because of piezoelectric effects. in analog circuit design attention must be paid to the problem of package stress as well as to the dangers of vibration and shock as described above. vibration
3 general safety precautions and usage considerations 9 3.2 storage 3.2.1 general storage ? avoid storage locations where devices will be exposed to moisture or direct sunlight. ? follow the instructions printed on the device cartons regarding transportation and storage. ? the storage area temperature should be kept within a temperature range of 5c to 35c, and relative humidity should be maintained at between 45% and 75%. ? do not store devices in the presence of harmful (especially corrosive) gases, or in dusty conditions. ? use storage areas where there is minimal temperature fluctuation. rapid temperature changes can cause moisture to form on stored devices, resulting in lead oxidation or corrosion. as a result, the solderability of the leads will be degraded. ? when repacking devices, use anti-static containers. ? do not allow external forces or loads to be applied to devices while they are in storage. ? if devices have been stored for more than two years, their electrical characteristics should be tested and their leads should be tested for ease of soldering before they are used. 3.2.2 moisture-proof packing moisture-proof packing should be handled with care. the handling procedure specified for each packing type should be followed scrupulously. if the proper procedures are not followed, the quality and reliability of devices may be degraded. this section describes general precautions for handling moisture-proof packing. since the details may differ from device to device, refer also to the relevant individual datasheets or databook. (1) general precautions follow the instructions printed on the device cartons regarding transportation and storage. ? do not drop or toss device packing. the laminated aluminum material in it can be rendered ineffective by rough handling. ? the storage area temperature should be kept within a temperature range of 5c to 30c, and relative humidity should be maintained at 90% (max). use devices within 12 months of the date marked on the package seal. @@ humidity: temperature:
3 general safety precautions and usage considerations 10 ? if the 12-month storage period has expired, or if the 30% humidity indicator shown in figure 1 is pink when the packing is opened, it may be advisable, depending on the device and packing type, to back the devices at high temperature to remove any moisture. please refer to the table below. after the pack has been opened, use the devices in a 5 c to 30 c. 60% rh environment and within the effective usage period listed on the moisture-proof package. if the effective usage period has expired, or if the packing has been stored in a high-humidity environment, bake the devices at high temperature. packing moisture removal tray if the packing bears the ?heatproof? marking or indicates the maximum temperature which it can withstand, bake at 125 ? when baking devices, protect the devices from static electricity. ? moisture indicators can detect the approximate humidity level at a standard temperature of 25 c. 6-point indicators and 3-point indicators are currently in use, but eventually all indicators will be 3-point indicators. danger if pink change desiccant read at lavender between pink & blue 10% 20% 30% 40% 50% 60% humidity indicator danger if pink read at lavender between pink & blue 20 30 40 humidity indicator (a) 6-point indicator (b) 3-point indicator figure 1 humidity indicator
3 general safety precautions and usage considerations 11 3.3 design care must be exercised in the design of electronic equipment to achieve the desired reliability. it is important not only to adhere to specifications concerning absolute maximum ratings and recommended operating conditions, it is also important to consider the overall environment in which equipment will be used, including factors such as the ambient temperature, transient noise and voltage and current surges, as well as mounting conditions which affect device reliability. this section describes some general precautions which you should observe when designing circuits and when mounting devices on printed circuit boards. for more detailed information about each product family, refer to the relevant individual technical datasheets available from toshiba. 3.3.1 absolute maximum ratings do not use devices under conditions in which their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature) will be exceeded. a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. the absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. although absolute maximum ratings differ from product to product, they essentially concern the voltage and current at each pin, the allowable power dissipation, and the junction and storage temperatures. if the voltage or current on any pin exceeds the absolute maximum rating, the device?s internal circuitry can become degraded. in the worst case, heat generated in internal circuitry can fuse wiring or cause the semiconductor chip to break down. if storage or operating temperatures exceed rated values, the package seal can deteriorate or the wires can become disconnected due to the differences between the thermal expansion coefficients of the materials from which the device is constructed. 3.3.2 recommended operating conditions the recommended operating conditions for each device are those necessary to guarantee that the device will operate as specified in the datasheet. if greater reliability is required, derate the device?s absolute maximum ratings for voltage, current, power and temperature before using it. 3.3.3 derating when incorporating a device into your design, reduce its rated absolute maximum voltage, current, power dissipation and operating temperature in order to ensure high reliability. since derating differs from application to application, refer to the technical datasheets available for the various devices used in your design. 3.3.4 unused pins if unused pins are left open, some devices can exhibit input instability problems, resulting in malfunctions such as abrupt increase in current flow. similarly, if the unused output pins on a device are connected to the power supply pin, the ground pin or to other output pins, the ic may malfunction or break down. since the details regarding the handling of unused pins differ from device to device and from pin
3 general safety precautions and usage considerations 12 to pin, please follow the instructions given in the relevant individual datasheets or databook. cmos logic ic inputs, for example, have extremely high impedance. if an input pin is left open, it can easily pick up extraneous noise and become unstable. in this case, if the input voltage level reaches an intermediate level, it is possible that both the p-channel and n-channel transistors will be turned on, allowing unwanted supply current to flow. therefore, ensure that the unused input pins of a device are connected to the power supply (vcc) pin or ground (gnd) pin of the same device. for details of what to do with the pins of heat sinks, refer to the relevant technical datasheet and databook. 3.3.5 latch-up latch-up is an abnormal condition inherent in cmos devices, in which vcc gets shorted to ground. this happens when a parasitic pn-pn junction (thyristor structure) internal to the cmos chip is turned on, causing a large current of the order of several hundred ma or more to flow between vcc and gnd, eventually causing the device to break down. latch-up occurs when the input or output voltage exceeds the rated value, causing a large current to flow in the internal chip, or when the voltage on the vcc (vdd) pin exceeds its rated value, forcing the internal chip into a breakdown condition. once the chip falls into the latch-up state, even though the excess voltage may have been applied only for an instant, the large current continues to flow between vcc (vdd) and gnd (vss). this causes the device to heat up and, in extreme cases, to emit gas fumes as well. to avoid this problem, observe the following precautions: (1) do not allow voltage levels on the input and output pins either to rise above vcc (vdd) or to fall below gnd (vss). also, follow any prescribed power-on sequence, so that power is applied gradually or in steps rather than abruptly. (2) do not allow any abnormal noise signals to be applied to the device. (3) set the voltage levels of unused input pins to vcc (vdd) or gnd (vss). (4) do not connect output pins to one another. 3.3.6 input/output protection wired-and configurations, in which outputs are connected together, cannot be used, since this short-circuits the outputs. outputs should, of course, never be connected to vcc (vdd) or gnd (vss). furthermore, ics with tri-state outputs can undergo performance degradation if a shorted output current is allowed to flow for an extended period of time. therefore, when designing circuits, make sure that tri-state outputs will not be enabled simultaneously. 3.3.7 load capacitance some devices display increased delay times if the load capacitance is large. also, large charging and discharging currents will flow in the device, causing noise. furthermore, since outputs are shorted for a relatively long time, wiring can become fused. consult the technical information for the device being used to determine the recommended load capacitance.
3 general safety precautions and usage considerations 13 3.3.8 thermal design the failure rate of semiconductor devices is greatly increased as operating temperatures increase. as shown in figure 2, the internal thermal stress on a device is the sum of the ambient temperature and the temperature rise due to power dissipation in the device. therefore, to achieve optimum reliability, observe the following precautions concerning thermal design: (1) keep the ambient temperature (ta) as low as possible. (2) if the device?s dynamic power dissipation is relatively large, select the most appropriate circuit board material, and consider the use of heat sinks or of forced air cooling. such measures will help lower the thermal resistance of the package. (3) derate the device?s absolute maximum ratings to minimize thermal stress from power dissipation. ja = jc + ca ja = (tj?ta) / p jc = (tj?tc) / p ca = (tc?ta) / p in which ja = thermal resistance between junction and surrounding air (c/w) jc = thermal resistance between junction and package surface, or internal thermal resistance (c/w) ca = thermal resistance between package surface and surrounding air, or external thermal resistance (c/w) tj = junction temperature or chip temperature (c) tc = package surface temperature or case temperature (c) ta = ambient temperature (c) p = power dissipation (w) tc figure 2 thermal resistance of package 3.3.9 interfacing when connecting inputs and outputs between devices, make sure input voltage (v il /v ih ) and output voltage (v ol /v oh ) levels are matched. otherwise, the devices may malfunction. when connecting devices operating at different supply voltages, such as in a dual-power-supply system, be aware that erroneous power-on and power-off sequences can result in device breakdown. for details of how to interface particular devices, consult the relevant technical datasheets and databooks. if you have any questions or doubts about interfacing, contact your nearest toshiba office or distributor.
3 general safety precautions and usage considerations 14 3.3.10 decoupling spike currents generated during switching can cause vcc (vdd) and gnd (vss) voltage levels to fluctuate, causing ringing in the output waveform or a delay in response speed. (the power supply and gnd wiring impedance is normally 50 ? to 100 ? .) for this reason, the impedance of power supply lines with respect to high frequencies must be kept low. this can be accomplished by using thick and short wiring for the vcc (vdd) and gnd (vss) lines and by installing decoupling capacitors (of approximately 0.01 f to 1 f capacitance) as high-frequency filters between vcc (vdd) and gnd (vss) at strategic locations on the printed circuit board. for low-frequency filtering, it is a good idea to install a 10- to 100- f capacitor on the printed circuit board (one capacitor will suffice). if the capacitance is excessively large, however, (e.g. several thousand f) latch-up can be a problem. be sure to choose an appropriate capacitance value. an important point about wiring is that, in the case of high-speed logic ics, noise is caused mainly by reflection and crosstalk, or by the power supply impedance. reflections cause increased signal delay, ringing, overshoot and undershoot, thereby reducing the device?s safety margins with respect to noise. to prevent reflections, reduce the wiring length by increasing the device mounting density so as to lower the inductance (l) and capacitance (c) in the wiring. extreme care must be taken, however, when taking this corrective measure, since it tends to cause crosstalk between the wires. in practice, there must be a trade-off between these two factors. 3.3.11 external noise printed circuit boards with long i/o or signal pattern lines are vulnerable to induced noise or surges from outside sources. consequently, malfunctions or breakdowns can result from overcurrent or overvoltage, depending on the types of device used. to protect against noise, lower the impedance of the pattern line or insert a noise-canceling circuit. protective measures must also be taken against surges. for details of the appropriate protective measures for a particular device, consult the relevant databook. 3.3.12 electromagnetic interference widespread use of electrical and electronic equipment in recent years has brought with it radio and tv reception problems due to electromagnetic interference. to use the radio spectrum effectively and to maintain radio communications quality, each country has formulated regulations limiting the amount of electromagnetic interference which can be generated by individual products. electromagnetic interference includes conduction noise propagated through power supply and telephone lines, and noise from direct electromagnetic waves radiated by equipment. different measurement methods and corrective measures are used to assess and counteract each specific type of noise. difficulties in controlling electromagnetic interference derive from the fact that there is no method available which allows designers to calculate, at the design stage, the strength of the electromagnetic waves which will emanate from each component in a piece of equipment. for this reason, it is only after the prototype equipment has been completed that the designer can take measurements using a dedicated instrument to determine the strength of electromagnetic interference waves. yet it is possible during system design to incorporate some measures for the input/output signals
3 general safety precautions and usage considerations 15 prevention of electromagnetic interference, which can facilitate taking corrective measures once the design has been completed. these include installing shields and noise filters, and increasing the thickness of the power supply wiring patterns on the printed circuit board. one effective method, for example, is to devise several shielding options during design, and then select the most suitable shielding method based on the results of measurements taken after the prototype has been completed. 3.3.13 peripheral circuits in most cases semiconductor devices are used with peripheral circuits and components. the input and output signal voltages and currents in these circuits must be chosen to match the semiconductor device?s specifications. the following factors must be taken into account. (1) inappropriate voltages or currents applied to a device?s input pins may cause it to operate erratically. some devices contain pull-up or pull-down resistors. when designing your system, remember to take the effect of this on the voltage and current levels into account. (2) the output pins on a device have a predetermined external circuit drive capability. if this drive capability is greater than that required, either incorporate a compensating circuit into your design or carefully select suitable components for use in external circuits. 3.3.14 safety standards each country has safety standards which must be observed. these safety standards include requirements for quality assurance systems and design of device insulation. such requirements must be fully taken into account to ensure that your design conforms to the applicable safety standards. 3.3.15 other precautions (1) when designing a system, be sure to incorporate fail-safe and other appropriate measures according to the intended purpose of your system. also, be sure to debug your system under actual board-mounted conditions. (2) if a plastic-package device is placed in a strong electric field, surface leakage may occur due to the charge-up phenomenon, resulting in device malfunction. in such cases take appropriate measures to prevent this problem, for example by protecting the package surface with a conductive shield. (3) with some microcomputers and mos memory devices, caution is required when powering on or resetting the device. to ensure that your design does not violate device specifications, consult the relevant databook for each constituent device. (4) ensure that no conductive material or object (such as a metal pin) can drop onto and short the leads of a device mounted on a printed circuit board. 3.4 inspection, testing and evaluation 3.4.1 grounding ground all measuring instruments, jigs, tools and soldering irons to earth. electrical leakage may cause a device to break down or may result in electric shock.
3 general safety precautions and usage considerations 16 3.4.2 inspection sequence c do not insert devices in the wrong orientation. make sure that the positive and negative electrodes of the power supply are correctly connected. otherwise, the rated maximum current or maximum power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to catch fire or explode, resulting in injury to the user. d when conducting any kind of evaluation, inspection or testing using ac power with a peak voltage of 42.4 v or dc power exceeding 60 v, be sure to connect the electrodes or probes of the testing equipment to the device under test before powering it on. connecting the electrodes or probes of testing equipment to a device while it is powered on may result in electric shock, causing injury. (1) apply voltage to the test jig only after inserting the device securely into it. when applying or removing power, observe the relevant precautions, if any. (2) make sure that the voltage applied to the device is off before removing the device from the test jig. otherwise, the device may undergo performance degradation or be destroyed. (3) make sure that no surge voltages from the measuring equipment are applied to the device. (4) the chips housed in tape carrier packages (tcps) are bare chips and are therefore exposed. during inspection take care not to crack the chip or cause any flaws in it. electrical contact may also cause a chip to become faulty. therefore make sure that nothing comes into electrical contact with the chip. 3.5 mounting there are essentially two main types of semiconductor device package: lead insertion and surface mount. during mounting on printed circuit boards, devices can become contaminated by flux or damaged by thermal stress from the soldering process. with surface-mount devices in particular, the most significant problem is thermal stress from solder reflow, when the entire package is subjected to heat. this section describes a recommended temperature profile for each mounting method, as well as general precautions which you should take when mounting devices on printed circuit boards. note, however, that even for devices with the same package type, the appropriate mounting method varies according to the size of the chip and the size and shape of the lead frame. therefore, please consult the relevant technical datasheet and databook. 3.5.1 lead forming c always wear protective glasses when cutting the leads of a device with clippers or a similar tool. if you do not, small bits of metal flying off the cut ends may damage your eyes. d do not touch the tips of device leads. because some types of device have leads with pointed tips, you may prick your finger. semiconductor devices must undergo a process in which the leads are cut and formed before the devices can be mounted on a printed circuit board. if undue stress is applied to the interior of a device during this process, mechanical breakdown or performance degradation can result. this is attributable primarily to differences between the stress on the device?s external leads and the stress on the internal leads. if the relative difference is great enough, the device?s internal leads, adhesive properties or sealant can be damaged. observe these precautions during the lead- forming process (this does not apply to surface-mount devices):
3 general safety precautions and usage considerations 17 (1) lead insertion hole intervals on the printed circuit board should match the lead pitch of the device precisely. (2) if lead insertion hole intervals on the printed circuit board do not precisely match the lead pitch of the device, do not attempt to forcibly insert devices by pressing on them or by pulling on their leads. (3) for the minimum clearance specification between a device and a printed circuit board, refer to the relevant device?s datasheet and databook. if necessary, achieve the required clearance by forming the device?s leads appropriately. do not use the spacers which are used to raise devices above the surface of the printed circuit board during soldering to achieve clearance. these spacers normally continue to expand due to heat, even after the solder has begun to solidify; this applies severe stress to the device. (4) observe the following precautions when forming the leads of a device prior to mounting. ? use a tool or jig to secure the lead at its base (where the lead meets the device package) while bending so as to avoid mechanical stress to the device. also avoid bending or stretching device leads repeatedly. ? be careful not to damage the lead during lead forming. ? follow any other precautions described in the individual datasheets and databooks for each device and package type. 3.5.2 socket mounting (1) when socket mounting devices on a printed circuit board, use sockets which match the inserted device?s package. (2) use sockets whose contacts have the appropriate contact pressure. if the contact pressure is insufficient, the socket may not make a perfect contact when the device is repeatedly inserted and removed; if the pressure is excessively high, the device leads may be bent or damaged when they are inserted into or removed from the socket. (3) when soldering sockets to the printed circuit board, use sockets whose construction prevents flux from penetrating into the contacts or which allows flux to be completely cleaned off. (4) make sure the coating agent applied to the printed circuit board for moisture-proofing purposes does not stick to the socket contacts. (5) if the device leads are severely bent by a socket as it is inserted or removed and you wish to repair the leads so as to continue using the device, make sure that this lead correction is only performed once. do not use devices whose leads have been corrected more than once. (6) if the printed circuit board with the devices mounted on it will be subjected to vibration from external sources, use sockets which have a strong contact pressure so as to prevent the sockets and devices from vibrating relative to one another. 3.5.3 soldering temperature profile the soldering temperature and heating time vary from device to device. therefore, when specifying the mounting conditions, refer to the individual datasheets and databooks for the devices used.
3 general safety precautions and usage considerations 18 (1) using a soldering iron complete soldering within ten seconds for lead temperatures of up to 260c, or within three seconds for lead temperatures of up to 350c. (2) using medium infrared ray reflow ? heating top and bottom with long or medium infrared rays is recommended (see figure 3). long infrared ray heater (preheating) medium infrared ray heater (reflow) product flow figure 3 heating top and bottom with long or medium infrared rays ? complete the infrared ray reflow process within 30 seconds at a package surface temperature of between 210c and 240c. ? refer to figure 4 for an example of a good temperature profile for infrared or hot air reflow. 210 30 seconds or less time (in seconds) 60-120 seconds (c) 240 160 140 package surface temperature figure 4 sample temperature profile for infrared or hot air reflow (3) using hot air reflow ? complete hot air reflow within 30 seconds at a package surface temperature of between 210c and 240c. ? for an example of a recommended temperature profile, refer to figure 4 above. (4) using solder flow ? apply preheating for 60 to 120 seconds at a temperature of 150c. ? for lead insertion-type packages, complete solder flow within 10 seconds with the temperature at the stopper (or, if there is no stopper, at a location more than 1.5 mm from the body) which does not exceed 260c. ? for surface-mount packages, complete soldering within 5 seconds at a temperature of 250c or
3 general safety precautions and usage considerations 19 less in order to prevent thermal stress in the device. ? figure 5 shows an example of a recommended temperature profile for surface-mount packages using solder flow. 5 seconds or less 60-120 seconds (c) 250 160 140 package surface temperature time (in seconds) figure 5 sample temperature profile for solder flow 3.5.4 flux cleaning and ultrasonic cleaning (1) when cleaning circuit boards to remove flux, make sure that no residual reactive ions such as na or cl remain. note that organic solvents react with water to generate hydrogen chloride and other corrosive gases which can degrade device performance. (2) washing devices with water will not cause any problems. however, make sure that no reactive ions such as sodium and chlorine are left as a residue. also, be sure to dry devices sufficiently after washing. (3) do not rub device markings with a brush or with your hand during cleaning or while the devices are still wet from the cleaning agent. doing so can rub off the markings. (4) the dip cleaning, shower cleaning and steam cleaning processes all involve the chemical action of a solvent. use only recommended solvents for these cleaning methods. when immersing devices in a solvent or steam bath, make sure that the temperature of the liquid is 50c or below, and that the circuit board is removed from the bath within one minute. (5) ultrasonic cleaning should not be used with hermetically-sealed ceramic packages such as a leadless chip carrier (lcc), pin grid array (pga) or charge-coupled device (ccd), because the bonding wires can become disconnected due to resonance during the cleaning process. even if a device package allows ultrasonic cleaning, limit the duration of ultrasonic cleaning to as short a time as possible, since long hours of ultrasonic cleaning degrade the adhesion between the mold resin and the frame material. the following ultrasonic cleaning conditions are recommended: frequency: 27 khz 29 khz ultrasonic output power: 300 w or less (0.25 w/cm 2 or less) cleaning time: 30 seconds or less suspend the circuit board in the solvent bath during ultrasonic cleaning in such a way that the ultrasonic vibrator does not come into direct contact with the circuit board or the device.
3 general safety precautions and usage considerations 20 3.5.5 no cleaning if analog devices or high-speed devices are used without being cleaned, flux residues may cause minute amounts of leakage between pins. similarly, dew condensation, which occurs in environments containing residual chlorine when power to the device is on, may cause between- lead leakage or migration. therefore, toshiba recommends that these devices be cleaned. however, if the flux used contains only a small amount of halogen (0.05w% or less), the devices may be used without cleaning without any problems. 3.5.6 mounting tape carrier packages (tcps) (1) when tape carrier packages (tcps) are mounted, measures must be taken to prevent electrostatic breakdown of the devices. (2) if devices are being picked up from tape, or outer lead bonding (olb) mounting is being carried out, consult the manufacturer of the insertion machine which is being used, in order to establish the optimum mounting conditions in advance and to avoid any possible hazards. (3) the base film, which is made of polyimide, is hard and thin. be careful not to cut or scratch your hands or any objects while handling the tape. (4) when punching tape, try not to scatter broken pieces of tape too much. (5) treat the extra film, reels and spacers left after punching as industrial waste, taking care not to destroy or pollute the environment. (6) chips housed in tape carrier packages (tcps) are bare chips and therefore have their reverse side exposed. to ensure that the chip will not be cracked during mounting, ensure that no mechanical shock is applied to the reverse side of the chip. electrical contact may also cause a chip to fail. therefore, when mounting devices, make sure that nothing comes into electrical contact with the reverse side of the chip. if your design requires connecting the reverse side of the chip to the circuit board, please consult toshiba or a toshiba distributor beforehand. 3.5.7 mounting chips devices delivered in chip form tend to degrade or break under external forces much more easily than plastic-packaged devices. therefore, caution is required when handling this type of device. (1) mount devices in a properly prepared environment so that chip surfaces will not be exposed to polluted ambient air or other polluted substances. (2) when handling chips, be careful not to expose them to static electricity. in particular, measures must be taken to prevent static damage during the mounting of chips. with this in mind, toshiba recommend mounting all peripheral parts first and then mounting chips last (after all other components have been mounted). (3) make sure that pcbs (or any other kind of circuit board) on which chips are being mounted do not have any chemical residues on them (such as the chemicals which were used for etching the pcbs). (4) when mounting chips on a board, use the method of assembly that is most suitable for maintaining the appropriate electrical, thermal and mechanical properties of the semiconductor devices used. * for details of devices in chip form, refer to the relevant device?s individual datasheets.
3 general safety precautions and usage considerations 21 3.5.8 circuit board coating when devices are to be used in equipment requiring a high degree of reliability or in extreme environments (where moisture, corrosive gas or dust is present), circuit boards may be coated for protection. however, before doing so, you must carefully consider the possible stress and contamination effects that may result and then choose the coating resin which results in the minimum level of stress to the device. 3.5.9 heat sinks (1) when attaching a heat sink to a device, be careful not to apply excessive force to the device in the process. (2) when attaching a device to a heat sink by fixing it at two or more locations, evenly tighten all the screws in stages (i.e. do not fully tighten one screw while the rest are still only loosely tightened). finally, fully tighten all the screws up to the specified torque. (3) drill holes for screws in the heat sink exactly as specified. smooth the surface by removing burrs and protrusions or indentations which might interfere with the installation of any part of the device. (4) a coating of silicone compound can be applied between the heat sink and the device to improve heat conductivity. be sure to apply the coating thinly and evenly; do not use too much. also, be sure to use a non-volatile compound, as volatile compounds can crack after a time, causing the heat radiation properties of the heat sink to deteriorate. (5) if the device is housed in a plastic package, use caution when selecting the type of silicone compound to be applied between the heat sink and the device. with some types, the base oil separates and penetrates the plastic package, significantly reducing the useful life of the device. two recommended silicone compounds in which base oil separation is not a problem are yg6260 from toshiba silicone. (6) heat-sink-equipped devices can become very hot during operation. do not touch them, or you may sustain a burn. 3.5.10 tightening torque (1) make sure the screws are tightened with fastening torques not exceeding the torque values stipulated in individual datasheets and databooks for the devices used. (2) do not allow a power screwdriver (electrical or air-driven) to touch devices. 3.5.11 repeated device mounting and usage do not remount or re-use devices which fall into the categories listed below; these devices may cause significant problems relating to performance and reliability. (1) devices which have been removed from the board after soldering (2) devices which have been inserted in the wrong orientation or which have had reverse current applied (3) devices which have undergone lead forming more than once
3 general safety precautions and usage considerations 22 3.6 protecting devices in the field 3.6.1 temperature semiconductor devices are generally more sensitive to temperature than are other electronic components. the various electrical characteristics of a semiconductor device are dependent on the ambient temperature at which the device is used. it is therefore necessary to understand the temperature characteristics of a device and to incorporate device derating into circuit design. note also that if a device is used above its maximum temperature rating, device deterioration is more rapid and it will reach the end of its usable life sooner than expected. 3.6.2 humidity resin-molded devices are sometimes improperly sealed. when these devices are used for an extended period of time in a high-humidity environment, moisture can penetrate into the device and cause chip degradation or malfunction. furthermore, when devices are mounted on a regular printed circuit board, the impedance between wiring components can decrease under high- humidity conditions. in systems which require a high signal-source impedance, circuit board leakage or leakage between device lead pins can cause malfunctions. the application of a moisture-proof treatment to the device surface should be considered in this case. on the other hand, operation under low-humidity conditions can damage a device due to the occurrence of electrostatic discharge. unless damp-proofing measures have been specifically taken, use devices only in environments with appropriate ambient moisture levels (i.e. within a relative humidity range of 40% to 60%). 3.6.3 corrosive gases corrosive gases can cause chemical reactions in devices, degrading device characteristics. for example, sulphur-bearing corrosive gases emanating from rubber placed near a device (accompanied by condensation under high-humidity conditions) can corrode a device?s leads. the resulting chemical reaction between leads forms foreign particles which can cause electrical leakage. 3.6.4 radioactive and cosmic rays most industrial and consumer semiconductor devices are not designed with protection against radioactive and cosmic rays. devices used in aerospace equipment or in radioactive environments must therefore be shielded. 3.6.5 strong electrical and magnetic fields devices exposed to strong magnetic fields can undergo a polarization phenomenon in their plastic material, or within the chip, which gives rise to abnormal symptoms such as impedance changes or increased leakage current. failures have been reported in lsis mounted near malfunctioning deflection yokes in tv sets. in such cases the device?s installation location must be changed or the device must be shielded against the electrical or magnetic field. shielding against magnetism is especially necessary for devices used in an alternating magnetic field because of the electromotive forces generated in this type of environment.
3 general safety precautions and usage considerations 23 3.6.6 interference from light (ultraviolet rays, sunlight, fluorescent lamps and incandescent lamps) light striking a semiconductor device generates electromotive force due to photoelectric effects. in some cases the device can malfunction. this is especially true for devices in which the internal chip is exposed. when designing circuits, make sure that devices are protected against incident light from external sources. this problem is not limited to optical semiconductors and eproms. all types of device can be affected by light. 3.6.7 dust and oil just like corrosive gases, dust and oil can cause chemical reactions in devices, which will adversely affect a device?s electrical characteristics. to avoid this problem, do not use devices in dusty or oily environments. this is especially important for optical devices because dust and oil can affect a device?s optical characteristics as well as its physical integrity and the electrical performance factors mentioned above. 3.6.8 fire semiconductor devices are combustible; they can emit smoke and catch fire if heated sufficiently. when this happens, some devices may generate poisonous gases. devices should therefore never be used in close proximity to an open flame or a heat-generating body, or near flammable or combustible materials. 3.7 disposal of devices and packing materials when discarding unused devices and packing materials, follow all procedures specified by local regulations in order to protect the environment against contamination.
4 precautions and usage considerations specific to each product group 24 4. precautions and usage considerations specific to each product group this section describes matters specific to each product group which need to be taken into consideration when using devices. if the same item is described in sections 3 and 4, the description in section 4 takes precedence. 4.1 microcontrollers 4.1.1 design (1) using resonators which are not specifically recommended for use resonators recommended for use with toshiba products in microcontroller oscillator applications are listed in toshiba databooks along with information about oscillation conditions. if you use a resonator not included in this list, please consult toshiba or the resonator manufacturer concerning the suitability of the device for your application. (2) undefined functions in some microcontrollers certain instruction code values do not constitute valid processor instructions. also, it is possible that the values of bits in registers will become undefined. take care in your applications not to use invalid instructions or to let register bit values become undefined. (3) scratch and puncture wounds by the point of a probe the tips of probes and adaptors used in development tools are individually designed to be compatible with particular devices. probes for some devices have sharp points. when you handle them bare-handed, take care not to suffer a scratch or puncture wound.
4 precautions and usage considerations specific to each product group 25 4.1.2 reliability predictions for microcontroller devices for microcontroller devices, the following junction temperature range is used for reliability predictions: tj = 0 c 85 c an estimation of the chip junction temperature, tj, can be obtained from the equation: tj = ta + q ? ja where: ta = ambient temperature ( c) the assumption is that the ambient temperature is not affected by any heat transfers from the device. q = chip?s average power dissipation (w) ? ja = package thermal resistance ( c/w) note 1: if you use a microcontroller device outside the 0 to 85 c range for long periods of time, contact your nearest toshiba office or authorized toshiba dealer. note 2: for the ? ja value, contact your nearest toshiba office or authorized toshiba dealer.
4 precautions and usage considerations specific to each product group 26
TMP1941AF

TMP1941AF 2003-03-27 TMP1941AF-1 32-bit risc microprocessor tx19 family TMP1941AF 1. features the tx19 is a family of high-performance 32-bit microprocessors that offers the speed of a 32-bit risc solution with the added advantage of a significantly reduced code size of a 16-bit architecture. the instruction set of the tx19 includes as a subset the 32-bit instructions of the tx39, which is based on the mips r3000a tm architecture. additionally, the tx19 supports the mips16 application-specific extensions (ase) for improved code density. the tmp1941 is built on a tx19 core processor and a selection of intelligent peripherals. the tmp1941 is suitable for low-voltage, low-power applications. features of the tmp1941 include the following: (1) tx19 core processor 1) two instruction set architecture (isa) modes: 16-bit isa for code density and 32-bit isa for speed ? the 16-bit isa is object-code compatible with the code-efficient mips16 ase. ? the 32-bit isa is object-code compatible with the high-performance tx39 family. 2) combines high performance with low power consumption. ? high performance ? single clock cycle execution for most instructions ? 3-operand computational instructions for high instruction throughput ? 5-stage pipeline ? on-chip high-speed memory ? dsp function: executes 32-bit x 32-bit multiplier operations with a 64-bit accumulation in a single clock cycle. ? low power consumption ? optimized design using a low-power cell library ? programmable standby modes in which processor clocks are stopped 3) fast interrupt response suitable for real-time control ? distinct starting locations for each interrupt service routine ? automatically generated vectors for each interrupt source ? automatic updates of the interrupt mask level purchase of toshiba i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. 980508 eba1 ? toshiba continually is working to improve the quality and the reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the re sponsibility of the buyer, when utilizing toshiba products, to observe standards of safety, and to avoid situations in which a malfunction o r failure of a toshiba product could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent products specifications. also, please keep in mind the precautions and conditions set forth in the toshiba semiconductor reliability handbook. ? the products described in this document are subject to foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assum ed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others.
TMP1941AF 2003-03-27 TMP1941AF-2 (2) 10-kbyte on-chip ram no on-chip rom (3) external memory expansion ? 16-mbyte off-chip address space for code and data ? external bus interface with dynamic bus sizing for 8-bit and 16-bit data ports (4) 4-channel dma controller ? interrupt- or software-triggered (5) 4-channel 8-bit timer (6) 4-channel 16-bit timer (7) 1-channel real-time counter (rtc) (8) 4-channel general-purpose serial interface two channels support both uart and synchronous transfer modes and the other two channels are solely for uart. (9) 1-channel serial bus interface either i 2 c bus mode or clock-synchronous mode can be selected. (10) 8-channel 10-bit a/d converter (with internal sample/hold) conversion time: 8.6 s @40 mhz (11) watchdog timer (12) 4-channel chip select/wait controller (13) interrupt sources ? 4 cpu interrupts: software interrupt instruction ? 32 internal interrupts: 7 priority levels, with the exception of the watchdog timer interrupt ? 11 external interrupts: 7 priority levels, with the exception of the nmi interrupt (14) 46-pin input/output ports (15) four standby modes ? idle (halt, doze), sleep, stop (16) dual clocks ? clock for low-power operation: low-speed clock (32.768 khz) ? rtc clock: low-speed clock (32.768 khz) (17) clock generator ? on-chip pll (x4) ? clock gear: divides the operating speed of the cpu by 1/2, 1/4 or 1/8 (18) little-endian higher address 31 24 23 16 15 8 7 0 word address 11 10 9 8 8 7654 4 lower address 3 2 1 0 0 ? byte 0 is the lowest-order byte (bits 7-0). ? the address of a word data item is the address of its lowest-order byte (byte 0).
TMP1941AF 2003-03-27 TMP1941AF-3 (19) operating voltage range: 2.7 to 3.6 v (20) operating frequency ? 40 mhz (vcc 3.0 v) ? 28 mhz (vcc 2.7 v) (21) package ? 100-pin qfp (14 x 14 x 1.4 (t) mm, 0.5-mm pitch)
TMP1941AF 2003-03-27 TMP1941AF-4 figure 1.1 TMP1941AF block diagram 8-bit tmra2/3 dmac (4ch) tx19 processor core x1 x2 xt1 (p96) xt2 (p97) scout (p44) plloff reset txd3 (p70) rxd3 (p71) txd4 (p72) rxd4 (p73) int0 (p77) int1-4 (pa0-3) int5-a, (p74-5, p80-1, p83-4) g-bus cg intc i/o bus i/f 10-bit adc sio0 sio1 serial bus i/f (sbi) wdt real-time counter (rtc) sio3 sio4 8-bit tmra0/1 16-bit tmrb0 16-bit tmrb1 16-bit tmrb2 16-bit tmrb3 adtrg (p53) (p50 ? p57) an0 ? an7 avcc, avss vrefh, vrefl txd0 (p90) rxd0 (p91) (p92) sclk0/ cts0 txd1 (p93) rxd1 (p94) (p95) sclk1/ cts1 sck (pa5) so/sda (pa6) si/scl (pa7) tb3out (p86) tb2out (p85) tb2in1/inta (p84) tb2in0/int9 ( p83 ) tb1out (p82) tb1in1/int8 ( p81 ) tb1in0/int7 (p80) tb0out (p76) tb0in1/int6 ( p75 ) tb0in0/int5 (p74) ta3out (p73) ta0in (p70) ta2in (p72) ta1out (p71) tx19 cpu mac 10-kbyte ram ( ): initial pin function after reset nmi wr hwr wait busrq p37 (p40-p43) cs0 - cs3 am0/1 ebif port4 w r/ busak rd port3 ad0-ad7 ad8/a8-ad15/a15 a0/a16-a7/a23
TMP1941AF 2003-03-27 TMP1941AF-5 2. signal descriptions this section contains pin assignments for the TMP1941AF as well as brief descriptions of the TMP1941AF input and output signals. 2.1 pin assignment the following illustrates the TMP1941AF pin assignment. figure 2.1 100-pin lqfp pin assignment 88 p44/scout p51/an1 91 p50/an0 90 85 p42/cs2 86 p43/cs3 87 dvcc dvss 89 p54/an4 94 p53/an3/adtrg 93 p52/an2 92 p57/an7 97 p56/an6 96 p55/an5 95 avss 100 vrefl 99 vrefh 98 p71/ta1out/rxd3 3 p70/ta0in/txd3 2 avcc 1 p74/tb0in0/int5 6 p73/ta3out/rxd4 5 p72/ta2in/txd4 4 p77/int0 9 p76/tb0out 8 p75/tb0in1/int6 7 p82/tb1out 12 p81/tb1in1/int8 11 p80/tb1in0/int7 10 p85/tb2out 15 p84/tb2in1/inta 14 p83/tb2in0/int9 13 p90/txd0 18 p87 17 p86/tb3out/intlv 16 p93/txd1 21 p92/sclk0/cts0 20 p91/rxd0 19 cvcc 25 am0 24 p95/sclk1/cts1 23 p94/rxd1 22 x2 26 am1 29 x1 28 cvss 27 p97/xt2 32 p96/xt1 31 reset 30 pa0/int1 37 fvss 36 test 35 fvcc 34 plloff 33 81 r/w 82 p37/dsu 83 p40/cs0 84 p41/cs1 80 busak 76 wr 77 hwr 78 wait 79 busrq 72 a5/a21 73 a6/a22 74 a7/a23 75 rd 68 a1/a17 69 a2/a18 70 a3/a19 71 a4/a20 64 dvcc 65 ad14/a14 66 ad15/a15 67 a0/a16 60 ad12/a12 61 ad13/a13 62 dvss 63 nmi 58 ad10/a10 59 ad11/a11 54 ad6 55 ad7 56 ad8/a8 57 ad9/a9 49 ad1 48 ad0 50 ad2 51 ad3 52 ad4 53 ad5 46 ale 45 dvss 47 dvcc 43 pa6/so/sda 42 pa5/sck 44 pa7/si/scl 40 pa3/int4 38 pa1/int2 39 pa2/int3 41 pa4/sdao
TMP1941AF 2003-03-27 TMP1941AF-6 2.2 pin usage information table 2.1 lists the input and output pins of the TMP1941AF, including alternate pin names and functions for multi-function pins. table 2.1 pin names and functions pin name # of pins type function ad0?ad7 8 input/output address (lower): bits 0-7 of the address/data bus ad8?ad15 a8?a15 8 input/output output address/data (upper): bits 8-15 of the address/data bus address: bits 8-15 of the address bus a0?a7 a16?a23 8 output output address: bits 0-7 of the address bus address: bits 16-23 of the address bus rd 1 output read strobe: asserted during a read operation from an external memory device wr 1 output write strobe: asserted during a write operation on d0-d7 hwr 1 output higher write strobe: asserted during a write operation on d8-d15 wait 1 i nput wait: causes the cpu to suspend external bus activity busrq 1 input bus request: asserted by an external bus master to request bus mastership busak 1 output bus acknowledge: indicates that the cpu has relinquished the bus in response to busrq . w / r 1 output read/write: indicates the direction of data transfer on the bus: 1 = read or dummy cycle, 0 = write cycle p37 dsu 1 input/output input port 37: programmable as input or output (with internal pull-up resister) dsu enable: if this pin is sampled low at the rising edge of reset , the TMP1941AF enters dsu mode for software debugging using an external real-time debug system. if this pin is sampled as high at the rising edge of reset , the TMP1941AF enters normal mode. p40 0 cs 1 input/output output port 40: programmable as input or output (with internal pull-up resister) chip select 0: asserted low to enable external devices at programmed addresses p41 1 cs 1 input/output output port 41: programmable as input or output (with internal pull-up resister) chip select 1: asserted low to enable external devices at programmed addresses p42 cs2 1 input/output output port 42: programmable as input or output (with internal pull-up resister) chip select 2: asserted low to enable external devices at programmed addresses p43 cs3 1 input/output output port 43: programmable as input or output (with internal pull-up resister) chip select 3: asserted low to enable external devices at programmed addresses p44 scout 1 input/output output port 44: programmable as input or output system clock output: drives out a clock signal at the same frequency as the cpu clock (high-speed or low-speed) p50?p57 an0?an7 adtrg 8 input input input port 5: input-only analog input: input to the on-chip a/d converter a/d trigger: starts an a/d conversion (multiplexed with p53) p70 ta0in txd3 1 input/output input output port 70: programmable as input or output 8-bit timer 0 input: input to timer 0 serial transmit data 3: programmable as a push-pull or open-drain output p71 ta1out rxd3 1 input/output output input port 71: programmable as input or output 8-bit timer 1 output: output from either timer 0 or timer 1 serial receive data 3 p72 ta2in txd4 1 input/output input output port 72: programmable as input or output 8-bit timer 2 input: input to timer 2 serial transmit data 4: programmable as a push-pull or open-drain output p73 ta3out rxd4 1 input/output output input port 73: programmable as input or output 8-bit timer 3 output: output from either timer 2 or timer 3 serial receive data 4 p74 tb0in0 int5 1 input/output input input port 74: programmable as input or output 16-bit timer 0 input 0: count/capture trigger input to 16-bit timer 0 interrupt request 5: programmable to be high-level, low-level, rising-edge or falling- edge sensitive
TMP1941AF 2003-03-27 TMP1941AF-7 pin name # of pins type function p75 tb0in1 int6 1 input/output input input port 75: programmable as input or output 16-bit timer 0 input 1: capture trigger input to 16-bit timer 0 interrupt request 6: programmable to be high-level, low-level, rising-edge or falling- edge sensitive p76 tb0out 1 input/output output port 76: programmable as input or output 16-bit timer 0 output: output from 16-bit timer 0 p77 int0 1 input/output input port 77: programmable as input or output interrupt request 0: programmable to be high-level, low-level, rising-edge or falling- edge sensitive p80 tb1in0 int7 1 input/output input input port 80: programmable as input or output 16-bit timer 1 input 0: count/capture trigger input to 16-bit timer 1 interrupt request 7: programmable to be high-level, low-level, rising-edge or falling- edge sensitive p81 tb1in1 int8 1 input/output input input port 81: programmable as input or output 16-bit timer 1 input 1: capture trigger input to 16-bit timer 1 interrupt request 8: programmable to be high-level, low-level, rising-edge or falling- edge sensitive p82 tb1out 1 input/output output port 82: programmable as input or output 16-bit timer 1 output: output from 16-bit timer 1 p83 tb2in0 int9 1 input/output input input port 83: programmable as input or output 16-bit timer 2 input 0: count/capture trigger input to 16-bit timer 2 interrupt request 9: programmable to be high-level, low-level, rising-edge or falling- edge sensitive p84 tb2in1 inta 1 input/output input input port 84: programmable as input or output 16-bit timer 2 input 1: capture trigger input to 16-bit timer 2 interrupt request a: programmable to be high-level, low-level, rising-edge or falling- edge sensitive p85 tb2out 1 input/output output port 85: programmable as input or output 16-bit timer 2 output: output from 16-bit timer 2 p86 tb3out 1 input/output output port 86: programmable as input or output 16-bit timer 3 output: output from 16-bit timer 3 p87 1 input/output port 87: programmable as input or output this pin is used to select the operating mode during reset. this pin should be pulled down to a logic 0 during a reset sequence. p90 txd0 1 input/output output port 90: programmable as input or output serial transmit data 0: programmable as a push-pull or open-drain output p91 rxd0 1 input/output input port 91: programmable as input or output serial receive data 0 p92 sclk0 0 cts 1 input/output input/output input port 92: programmable as input or output serial clock input/output 0 serial clear-to-send 0 p93 txd1 1 input/output output port 93: programmable as input or output start serial transmit data 1: programmable as a push-pull or open-drain output p94 rxd1 1 input/output input port 94: programmable as input or output serial receive data 1 p95 sclk1 1 cts 1 input/output input/output input port 95: programmable as input or output serial clock input/output 1 serial clear-to-send 1 p96 xt1 1 input/output input port 96: programmable as input or open-drain output connection pin for a low-speed crystal p97 xt2 1 input/output output port 97: programmable as input or open-drain output connection pin for a low-speed crystal pa0?pa3 int1?int4 4 input/output input ports a0?a3: individually programmable as input or output interrupt request 1?4: individually programmable to be high-level, low-level, rising- edge or falling-edge sensitive pa4 1 input/output port a4: programmable as input or output pa5 sck 1 input/output input/output port a5: programmable as input or output clock input/output pin when the serial bus interface is in sio mode
TMP1941AF 2003-03-27 TMP1941AF-8 pin name # of pins type function pa6 so sda 1 input/output output input/output port a6: programmable as input or output data transmit pin when the serial bus interface is in sio mode data transmit/receive pin when the serial bus interface is in i 2 c mode; programmable as a push-pull or open-drain output pa7 si scl 1 input/output input input/output port a7: programmable as input or output data receive pin when the serial bus interface is in sio mode clock input/output pin when the serial bus interface is in i 2 c mode; as an output, programmable as a push-pull or open-drain output ale 1 output address latch enable (this signal is driven out only when external memory is accessed.) nmi 1 input nonmaskable interrupt request: causes an nmi interrupt on the falling edge am1 1 input am1 should be tied to logic 0. am0 1 input am0 should be tied to logic 0 when configuring a 16-bit or mixed 8-/16-bit bus. am0 should be tied to logic 1 when configuring a 8-bit bus. test 1 input test pin: this pin should be left open or tied to ground. plloff 1 input this pin should be tied to logic 1 when the frequency multiplied clock from the pll is used; otherwise, it should be tied to logic 0. reset 1 input reset (with internal pull-up resister): initializes the whole TMP1941AF. vrefh 1 input input pin for high reference voltage for the a/d converter. this pin should be connected to the avcc pin when the a/d converter is not used. vrefl 1 input input pin for low reference voltage for the a/d converter. this pin should be connected to the avss pin when the a/d converter is not used. avcc 1 ? power supply pin for the a/d converter. this pin should always be connected to power supply even when the a/d converter is not used. avss 1 ? ground pin for the a/d converter. this pin should always be connected to ground even when the a/d converter is not used. x1/x2 2 input/output connection pins for a high-speed crystal dvcc, cvcc 5 ? power supply pins dvss, cvss 5 ? ground pins (0 v) note 1: when a dsu ice is used, p37 and a0-a7 function as debug interface signals. note 2: p37 and p87 should be held at the prescribed logic states for one system clock cycle before and after the rising edge of reset , with the reset signal being stable in either logic state. the following shows the dsu interface signals. figure 2.2 dsu interface signals dsu debug interface if the dsu pin is sampled low at the rising edge of reset , the port a pins are configured as interface signals for an external real-time debug system. the dsu pin has an internal pullup resistor. dreset (pa7) i debug reset dreset signal for an external real-time debug system dclk (pa0) o debug clock dclk signal for an external real-time debug system dbge (pa5) i debugger enable dbge signal for an external real-time debug system pcst[2] (pa1) o pc trace status [2] pcts[2] signal for an external real-time debug system pcst[1] (pa2) o pc trace status [1] pcst[1] signal for an external real-time debug system pcst[0] (pa3) o pc trace status [0] pcts[0] signal for an external real-time debug system sdi/ dint (pa6) i serial data input / debug interrupt sdi/ dint signal for an external real-time debug system sdao/tpc (pa4) o serial data and address output / target pc sdao/tpc signal for an external real-time debug system
TMP1941AF 2003-03-27 TMP1941AF-9 3. core processor the TMP1941AF contains a high-performance 32-bit core processor called the tx19. for a detailed description of the core processor, refer to the 32-bit tx system risc tx19 core architecture manual. be sure to read section 21, notations, precautions and restrictions , before using this product. functions unique to the TMP1941AF, which are not covered in the architecture manual, are described below. 3.1 reset operation to reset the TMP1941AF, reset must be asserted for at least 12 system clock periods after the power supply voltage and the internal high-frequency oscillator have stabilized. this time is typically 2.4 s at 40 mhz when the on-chip pll is utilized, and 4.8 s otherwise. after a reset, either the pll-multiplied clock or an external clock is selected, depending on the logic state of the plloff pin. by default, the selected clock is geared down to 1/8 for internal operation. the following occurs as a result of a reset: ? the system control coprocessor (cp0) registers within the tx19 core processor are initialized. for details, refer to the 32-bit tx system risc tx19 core architecture manual. ? the reset exception is taken. program control is transferred to the exception handler at a predefined address. this predefined location is called exception vector, which directly indicates the start of the actual exception handler routine. the reset exception is always vectored to virtual address 0xbfc0_0000 (which is the same as for the nonmaskable interrupt exception). ? all on-chip i/o peripheral registers are initialized. ? all port pins, including those multiplexed with on-chip peripheral functions, are configured as either general-purpose inputs or general-purpose outputs. note: a reset operation does not affect the contents of the on-chip ram.
TMP1941AF 2003-03-27 TMP1941AF-10 4. memory map the mapping of virtual addresses to physical addresses is shown below. figure 4.1 memory map 0xffff_ffff virtual address 16 mbytes reserved kseg1 kseg2 16 mbytes reserved kseg0 kuseg 0xc000_0000 0xa000_0000 0x8000_0000 0x0000_0000 16 mbytes reserved 1 gbytes 0xffff_ffff 0xffff _ 8000 2 gbytes 0x4000_0000 0x0000_0000 512 mbytes inaccessible 16 mbytes reserved physical address 0x2000_0000 on-chip peripherals (reserved) on-chip ram (10 kb) (reserved) reserved for debugging (2 mb) (reserved) 0xffff_e000 0xffff_bfff 0xffff_9800 0xff3f ffff 0xff20 ffff 0xff00 _ 0000 note 1: the on-chip ram is mapped to the addresses from 0xffff_9800 through 0xffff_bfff. note 2: the TMP1941AF has access to only 16 mbytes of external physical address space. the 16-mbyte physical memory can be located anywhere within the cpu?s 3.5-gbyte physical address space through use of programmable chip select signals. however, any address references to the on-chip memory, on-chip peripheral or reserved regions override external memory access. note 3: no instruction should be placed in the last four words of the physical memory available in the user?s system.
TMP1941AF 2003-03-27 TMP1941AF-11 5. clock/standby control the TMP1941AF has two clocking modes: single-clock mode which operates off of the high-speed clock supplied from the x1/x2 pins, and dual-clock mode which operates off of the high-speed clock supplied from the x1/x2 pins and the low-speed clock supplied from the xt1/xt2 pins. figure 5.1 shows the transitions between clocking modes in single-clock mode and dual-clock mode. interrupt instruction instruction interrupt reset normal mode (fc / gear_value) reset released idle mode (cpu halted) (selectable peripheral operation) stop mode (whole chip halted) (a) single-clock mode idle mode (cpu halted) (selectable peripheral operation) normal mode (fc/gear_value) reset reset released instruction interrupt stop mode (whole chip halted) slow mode (fs) inter- rupt instruction interrupt instruction interrupt instruction instruction interrupt interrupt sleep mode (fs only) (only rtc is active.) note 1: before a transition to slow or sleep mode can occur, the low-speed oscillator (fs) must be oscillating stably. note 2: after sleep mode is exited, the TMP1941AF returns to the mode it was in before entering sleep mode. note 3: after stop mode is exited, the TMP1941AF returns to the mode specified by the system control register 0 (syscr0). see section 5.2. (b) dual-clock mode figure 5.1 standby modes flow diagram reset reset normal mode fc = fpll = fosc 4 fsys = fc / 8 fsys = fosc / 2 fperiph = fsys normal mode fc = fosc / 2 fsys = fc / 8 fsys = fosc / 16 fperiph = fsys a. when the pll clock is used b. when the pll is not used reset released plloff = 1 pll used reset released plloff = 0 pll not used fosc: clock frequency supplied via the x1 and x2 pins fs: clock frequency supplied via the xt1 and xt2 pins fpll: pll multiplied clock frequency (x4) fc: clock frequency selected by the plloff pin fgear: clock frequency selected by the gear[1:0] bits in the syscr1 fsys: system clock frequency selected by the sysck bit in the syscr1 fperiph: clock source for the prescalers inside on-chip peripherals figure 5.2 default clock frequencies in normal mode
TMP1941AF 2003-03-27 TMP1941AF-12 5.1 clock generation 5.1.1 main system clock ? a crystal can be connected between x1 and x2, or x1 can be externally driven with a clock. ? the on-chip pll can be enabled or disabled (bypassed) during reset by using the plloff pin. when the pll is enabled, the input clock frequency is multiplied by four. ? the clock gear can be programmed to divide the clock by 2, 4 or 8. (the default is 1/8 on reset.) ? input clock frequency input frequency range fmax fmin pll on (for both crystal and external clock) 4?10 mhz 40 mhz 2 mhz crystal 16?20 mhz 20 mhz 1 mhz 16?20 mhz 20 mhz 1 mhz pll off external clock 20?40 mhz 20 mhz 1 1.25 mhz note 1: the dfosc bit in the syscr1 must be cleared to 0. the default is 0 on reset. 5.1.2 subsystem clock ? a 32.768-khz crystal is connected between xt1 and xt2 (or xt1 can be externally driven with a clock.) ? slow mode: the cpu operates off of the low-speed clock. ? sleep mode: only the real-time counter (rtc) is operational.
TMP1941AF 2003-03-27 TMP1941AF-13 5.1.3 clock source block diagrams fosc 2 2 4 fs fc fpll = fosch 4 real-time counter (rtc) on-chip peripherals: adc, tmra/b, sio, sbi, pio, wdt, rtc fsys fs low- speed oscillator xt1 xt2 x1 x2 syscr0. xten syscr0.wuef syscr2.wupt[1:0] syscr3.luptm warm-up timer lock (pll) timer mux 2 4 8 fperiph (to on-chip peripherals) syscr1.dfosc pll plloff (default setting pin) syscr1.fpsel syscr1.gear[1:0] the default is 1/8 on reset. cpu rom ram dmac intc syscr0. xen fsys fperiph 2 syscr0. prck[1:0] fs syscr3.scosel scout fgear syscr1.sysck high- speed oscillator t0 on-chip peripherals: tmra/b, sio, sbi (prescaler input) 2 4 fadc adcck[1:0] note 1: when the clock gear is used to reduce the system clock frequency (fsys), the prescalars within on-chip peripherals must be programmed so that the prescaler output ( tn) satisfies the following relationship: tn < fsys / 2 descriptions of each peripheral on the following sections include tables showing legal programming alternatives. note 2: when the low-speed clock (fs) is used as the system clock, all on-chip peripherals except the watchdog timer (wdt) and the real-time counter (rtc) must be disabled. note 3: the presclar clock source ( tn) must not be changed while any of the peripherals to which it is supplied are running. figure 5.3 clock source block diagrams
TMP1941AF 2003-03-27 TMP1941AF-14 5.2 clock generator (cg) registers 5.2.1 system clock control registers 76543210 syscr0 name xen xten rxen rxten rsysck wuef prck1 prck0 (0xffff_ee00) read/write r/w reset value10100000 function high-speed oscillator 0: disable 1: enable low-speed oscillator 0: disable 1: enable high-speed oscillator after exiting stop mode 0: disable 1: enable low-speed oscillator after exiting stop mode 0: disable 1: enable clock select after exiting stop mode 0: high-speed 1: low-speed oscillator warm-up period (wup) timer on writes: 0: don?t- care 1: start wup on reads: 0: expired 1: not expired prescaler clock select 00: fperiph/4 01: fperiph/2 10: fperiph 11: reserved 15 14 13 12 11 10 9 8 syscr1 name ?? sysck fpsel dfosc ? gear1 gear0 (0xffff_ee01) read/write ?? r/w r/w reset value ?? 000 ? 11 function system clock (fsys) select 0: high- speed (fgear) 1: low- speed (fs) fperiph select 0: fgear 1: fc high-speed oscillator frequency divide factor 0: divide-by-2 1: divide-by-1 high-speed clock (fc) gear select 00: fc 01: fc/2 10: fc/4 11: fc/8 23 22 21 20 19 18 17 16 syscr2 name drvsoch drvoscl wupt1 wupt0 stby1 stby0 ? drve (0xffff_ee02) read/write r/w ? r/w reset value001011 ? 0 function high-speed oscillator drive capability 0: high 1: low low-speed oscillator drive capability 0: high 1: low oscillator warm-up time 00: reserved 01: 2 8 /input frequency 10: 2 14 /input frequency 11: 2 16 /input frequency standby mode select 00: reserved 01: stop mode 10: sleep mode 11: idle mode 1: pins are driven in stop mode. 31 30 29 28 27 26 25 24 syscr3 name ? scosel ? alesel ?? lupfg luptm (0xffff_ee03) read/write ? r/w ? r/w ?? rr/w reset value ? 0 ? 1 ?? 00 function scout output select 0: fs 1: fsys ale output width select 0: fsys 0.5 1: fsys 1.5 pll lock 0: locked 1: unlocked pll lock time select 0: 2 16 /input frequency 1: 2 12 /input frequency
TMP1941AF 2003-03-27 TMP1941AF-15 note 1: the config register in the cp0 has the doze and halt bits. setting the halt bit puts the TMP1941AF in one of the standby modes, as specified by the stby1-stby0 bits in the syscr2. setting the doze bit puts the TMP1941AF in idle mode, irrespective of the settings of the stby1-stby0 bits. note 2: when the pll is not used, the luptm bit in the syscr3 must be set to 1 (2 12 /input frequency). note 3: the wupt1-wupt0 bits in the syscr2 must not be changed during the oscillator warm-up period. the luptm bit in the syscr3 must not be changed during the pll lock period. note 4: the following considerations relate to consecutive mode changes immediately after a warm-up event (e.g., sleep?normal?sleep). hardware warm-up (with no software intervention) (1) after having transitioned from stop or sleep mode to normal mode ? when the pll is used a transition to a next mode can not occur until the pll locks (syscr3.lupfg=0) and at least five program instructions are executed (including the instruction to check the lupfg flag). ? when the pll is not used ? when the oscillator warm-up time (syscr2.wupt[1:0]) is programmed to 01 (2 8 /input frequency) a transition to a next mode can not occur until the pll locks (syscr3.lupfg=0) and at least five program instructions are executed. ? when the oscillator warm-up time (syscr2.wupt[1:0]) is programmed to either 10 (2 14 /input frequency) or 11 (2 16 /input frequency) a transition to a next mode can not occur until at least five program instructions are executed. (2) after having transitioned from stop or sleep mode to slow mode once in slow mode, a transition to a next mode can occur immediately. software warm-up (1) after having transitioned from slow mode to normal mode ? when the pll is used the normal mode can be entered after the oscillator warm-up period timer has expired (i.e., after the syscr2.wuef bit is cleared). a transition to a next mode can not occur until the pll locks (syscr3.lupfg=0) and at least five program instructions are executed (including the instruction to check the lupfg flag). ? when the pll is not used ? when the oscillator warm-up time (syscr2.wupt[1:0]) is programmed to either 01 (2 8 /input frequency) the normal mode can be entered after the oscillator warm-up period timer has expired (i.e., after the syscr2.wuef bit is cleared). a transition to a next mode can not occur until the pll locks (syscr3.lupfg=0) and at least five program instructions are executed. ? when the oscillator warm-up time (syscr2.wupt[1:0]) is programmed to either 10 (2 14 /input frequency) or 11 (2 16 /input frequency) the normal mode can be entered after the oscillator warm-up timer has expired (i.e., after the syscr2.wuef bit is cleared). a transition to a next mode can not occur until at least five program instructions are executed. (2) after having transitioned from normal mode to slow mode after the oscillator warm-up timer has expired (syscr2.wuef=0), a transition to a next mode can not occur until at least five program instructions are executed.
TMP1941AF 2003-03-27 TMP1941AF-16 5.2.2 adc conversion clock 76543210 adcclk name ?????? adcck1 adcck0 (0xffff_ee04) read/write ?????? r/w r/w reset value ?????? 00 function adc conversion clock (fadc) select 00: fsys/2 01: fsys/4 10: fsys/8 11: don?t use. note: a/d conversion is executed using the clock selected by this register. reduced conversion accuracy occurs unless the conversion time is set to 8.6 s or more. relationships between fsys frequencies and a/d conversion times conversion clock fsys fsys/2 fsys/4 fsys/8 32 mhz don?t use. 10.75 s 21.5 s 20 mhz 8.6 s 17.2 s 34.4 s 16 mhz 10.75 s 21.5 s 43.0 s 10 mhz 17.2 s 34.4 s 68.8 s 8 mhz 21.5 s 43.0 s 86.0 s note: the conversion clock must not be changed while a/d conversion is in progress. 5.2.3 stop/sleep wake-up interrupt control registers (intcg registers) 76543210 imcga0 name ?? emcg01 emcg00 ?? ? int0en (0xffff_ee10) read/write ?? r/w ?? ? r/w reset value ?? 10 ?? ? 0 function wake-up int0 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int0 enable 0: disable 1: enable 15 14 13 12 11 10 9 8 imcga1 name ?? emcg11 emcg10 ?? ? int1en (0xffff_ee11) read/write ?? r/w ?? ? r/w reset value ?? 10 ?? ? 0 function wake-up int1 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int1 enable 0: disable 1: enable 23 22 21 20 19 18 17 16 imcga2 name ?? emcg21 emcg20 ?? ? int2en (0xffff_ee12) read/write ?? r/w ?? ? r/w reset value ?? 10 ?? ? 0 function wake-up int2 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int2 enable 0: disable 1: enable
TMP1941AF 2003-03-27 TMP1941AF-17 31 30 29 28 27 26 25 24 imcga3 name ?? emcg31 emcg30 ?? ? int3en (0xffff_ee13) read/write ?? r/w ?? ? r/w reset value ?? 10 ?? ? 0 function wake-up int3 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int3 enable 0: disable 1: enable 765 43210 imcgb0 name ?? emcg41 emcg40 ?? ? int4en (0xffff_ee14) read/write ?? r/w ?? ? r/w reset value ?? 10 ?? ? 0 function wake-up int4 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int4 enable 0: disable 1: enable 15 14 13 12 11 10 9 8 imcgb1 name ??? ????? (0xffff_ee15) read/write ??? ????? reset value ?? 10 ?? ? 0 function must be set to 10. must be set to 0. 23 22 21 20 19 18 17 16 imcgb2 name ??? ????? (0xffff_ee16) read/write ??? ????? reset value ?? 10 ?? ? 0 function must be set to 10. must be set to 0. 31 30 29 28 27 26 25 24 imcgb3 name ?? emcg71 emcg70 ?? ? intrtcen (0xffff_ee17) read/write ?? r/w ?? ? r/w reset value ?? 10 ?? ? 0 function wake-up intrtc sensitivity 00: don?t use. 01: don?t use. 10: don?t use. 11: rising edge these bits must be set to 11. intrtc enable 0:disable 1: enable note 1: the edge/level sensitivity must be defined for an interrupt pin which is enabled as wake-up signaling to exit stop/sleep mode. note 2: interrupt programming must follow these steps: 1. configure the pin as an interrupt input, if the pin is multiplexed with a general-purpose port. 2. set the active state for the interrupt during initialization. 3. clear any interrupt request. 4. enable the interrupt. note 3: the above steps must be performed with the relevant interrupt pin disabled. note 4: the TMP1941AF has six interrupt sources which can be used for wake-up signaling to exit stop/sleep mode: int0 to int4 (external interrupts) and intrtc (internal rtc interrupt). note 5: when one of these interrupt sources is used for stop/sleep wake-up signaling, its interrupt sensitivity defined in the cg block overrides the setting in the intc block. in the intc block, its senstivity must be set to the high level (which has no effect).
TMP1941AF 2003-03-27 TMP1941AF-18 example: enabling the int0 interrupt imcga0.emcg[01:00] = 10 cg block imcga0.int0en = 1 (set the int0 sensitivity to the falling edge) imc0l.eim[11:10] = 01 intc block imc0l.il[12:10] = 101 (set the interrupt sensitivity to the high level, and the interrupt priority level to 5.) all interrupt sources other than those used for stop/sleep wake-up signaling are controlled by the intc block. 5.2.4 interrupt request clear register 76543210 eicrcg name ????? icrcg2 icrcg1 icrcg0 (0xffff_ee20) read/write ????? w reset value ???????? function clear interrupt request 000: int0 100: int4 001: int1 101: reserved 010: int2 110: reserved 011: int3 111: intrtc note 1: clearing the int0-int4 and intrtc interrupt requests, if programmed for stop/sleep wake- up signaling, requires two register settings: first, the eicrcg register in the cg block, and then the intclr register in the intc block. the clearing of other interrupt sources is controlled through the intclr register alone. note 2: in cases where int0-int4 are not used for stop/sleep wake-up signaling, they are controlled by the intc block in the same way as other interrupt sources. intrtc is controlled by both the cg and intc blocks, regardless of whether it is used for wake-up signaling.
TMP1941AF 2003-03-27 TMP1941AF-19 5.3 system clock control section a system reset initializes the syscr0.xen bit to 1, the syscr0.xten bit to 0 and the syscr1.gear[1:0] bits to 00, putting the TMP1941AF in single-clock mode. if the on-chip pll is enabled, the pll reference clock is always multiplied by four. by default, the system clock frequency (fsys) is geared down to fc/8, where fc = fosc 4 (fosc is the oscillator frequency). for example, if an 8-mhz crystal is connected between the x1 and x2 pins, the fsys clock operates at 4 mhz (8 4 1/8). the pll output clock can be disabled by setting the plloff pin low during reset. regardless of the logic state of the plloff pin, the fsys frequency is, by default, geared down to fc/8. a reset clears the syscr1.dfosc bit to 0, setting fc to fosc/2. therefore, for example, if a 20-mhz crystal is connected between the x1 and x2 pins, fsys becomes 20 1/2 1/8 = 1.25 mhz. alternatively, the x1 pin can be driven with an external clock. since the fsys clock must have a 50% duty cycle, it is recommended to use the default dfosc bit value of 0 (i.e., fc = fosc 1/2). however, the divide- by-2 clock generator may be bypassed by setting the dfosc bit after reset. this causes fc to be equal to fosc; i.e., fsys becomes double the rate available when a crystal is connected between x1 and x2. 5.3.1 oscillation stabilization time when switching betw een normal and slow modes when a crystal is connected between the x1 and x2 pins and/or the xt1 and xt2 pins, the integrated warm-up period timer is used to assure oscillation stability. the warm-up period can be selected through the wupt1?wupt0 bits of the syscr2 to suit the crystal used. the warm-up period timer can be started by software writing a 1 to the wuef bit in the syscr0. this bit is self-clearing; it can be read to ascertain that the timer has expired. table 5.1 shows the warm-up periods required when the clocking is switched between normal and slow modes. note 1: no warm-up is necessary when the TMP1941AF is driven by an external oscillator clock which is already stable. note 2: because the warm-up period timer is clocked by the oscillator clock, any frequency fluctuations will lead to small timer errors. table 5.1 should be considered as approximate values. note 3: ensure that the pll lock flag (syscr3.lupfg) is cleared before starting the warm-up period timer. note 4: when a low-speed crystal is connected between xt1 (port 96) and xt2 (port 97), the following register settings are required to reduce power consumption: when a crystal is connected between xt1 and xt2: p9cr.p96c?p97c = 11 p9.p96?p97 = 00 when xt1 is driven with an external clock: p9cr.p96c?p97c = 11 p9.p96?p97 = 10 table 5.1 warm-up periods warm-up period select syscr2.wupt[1:0] high-speed clock (fosc) low-speed clock (fs) 01 (2 8 / oscillation frequency) 25.6 ( s) 7.8 (ms) 10 (2 14 / oscillation frequency) 1.638 (ms) 500 (ms) 11 (2 16 / oscillation frequency) 6.554 (ms) 2000 (ms) assumption: fosc = 10 mhz, fs = 32.768 khz
TMP1941AF 2003-03-27 TMP1941AF-20 example: switching from normal mode to slow mode syscr2.wupt[1:0] = xx select warm-up period. syscr0.xten = 1 enable low-speed clock (fs) oscillation. syscr0.wuef = 1 start warm-up period (wup) timer. check syscr0.wuef. wait until syscr0.wuef is cleared (i.e., the wup expires.) syscr1.sysck = 1 switch system clock speed to low speed (fs). syscr0.xen = 0 disable high-speed clock (fosc) oscillation. 5.3.2 system clock output either the fsys or fs clock can be driven out from the p44/scout pin. the p44/scout pin is configured as scout (system clock output) by programming the port 4 registers as follows: p4cr.p44c=1 and p4fc.p44f=1. the output clock is selected through the syscr3.scosel bit. table 5.2 shows the pin states in each clocking mode when the p44/scout pin is configured as scout. table 5.2 scout output states standby modes scout select normal/ slow idle sleep stop scosel = 0 the fs clock is driven out. scosel = 1 the fsys clock is driven out. held at either 1 or 0. note: the phase difference between the system clock output signal (scout) and the internal clock signal can not be guaranteed. 5.3.3 reducing the oscillator clock drive capability when a crystal is connected between the x1 and x2 pins and/or between xt1 and xt2 pins, oscillator noise and power consumption can be reduced through the programming of the syscr2. setting the syscr2.drvosch bit reduces the drive capability of the high-speed oscillator. setting the syscr2.drvoscl bit reduces the drive capability of the low-speed oscillator clock. a reset clears both the drvosch and drvoscl bits to 0, providing a high drive capability at power-up. both the high-speed and low-speed oscillator clocks must have a high drive capability (i.e., drvosch=0, drvoscl=0) when clocking modes are changed.
TMP1941AF 2003-03-27 TMP1941AF-21 ? drive capability of the high-speed oscillator crystal c2 c1 oscillation enable x1 pin syscr2.drvosch f osc x2 pin ? drive capability of the low-speed oscillator crystal c2 c1 oscillation enable xt1 pin syscr2.drvoscl f s xt2 pin figure 5.4 oscillator clock drive capabilities 5.4 prescalar clock control section the tmra01, tmra23, tmrb0 to tmrb3, sio0 to sio4 (there is no sio2), and sbi have a clock prescalar. the prescalar clock source ( t0) can be selected from fperiph/4, fperiph/2 and fperiph/1 through the prck[1:0] bits of the syscr0. fperiph can be selected from either fgear or fc through the fpsel bit of the syscr1. the default reset values select fgear as fperiph, and fperiph/4 as t0. 5.5 clock frequency multiplication section (pll) the on-chip pll multiplies the frequency of the high-speed oscillator clock (fosc) by four to generate the fpll clock. at reset, the pll is disabled. to use the pll, the plloff pin must be high when reset is released. note: if the plloff pin is low when reset is released, the pll will be disabled and the oscillator clock will be driven with no frequency multiplication. being an analog circuit, the pll requires a certain duration of time (called lock time) to stabilize, like an oscillator. the oscillator warm-up period (wup) timer is also used as the pll lock timer. the luptm bit in the syscr3 must be programmed so that the following relationship is satisfied: pll lock time oscillator warm-up time at reset, the default lock-up time is 2 16 / input frequency. setting the wup timer control bit (syscr0.wuef) starts the pll lock timer. the syscr3.luptm bit remains set while the pll is out of lock, and is cleared when the pll locks. in real-time applications whose software execution time is critical, once the pll has gone out of lock in a standby mode, software must determine before resuming operation whether the pll has locked (after the oscillator warm-up period timer has expired) in order to assure clock stability.
TMP1941AF 2003-03-27 TMP1941AF-22 there is one thing to remember when changing the clock gear value. the clock gear can be changed by the programming of the gear[1:0] bits of the syscr1. the rf[1:0] bits of the cpu?s config register need not be altered. it takes a few clock cycles for a gear change to take effect. therefore, one or more instructions following the instruction that changed the clock gear value may be executed using the old clock gear value. if subsequent instructions need be executed with a new clock gear value, a dummy instruction (one that executes a write cycle) should be inserted after the instruction that modifies the clock gear value. when the clock gear is used, the prescalars within on-chip peripherals must be programmed so that the prescaler output ( tn) satisfies the following relationship: tn < fsys / 2 5.6 standby control section the TMP1941AF provides support for several levels of power reduction. while in normal mode, setting the halt bit of the config register within the tx19 core processor causes the TMP1941AF to enter one of the standby modes ? idle, sleep or stop ? as specified by the syscr2.stby[1:0] bits. setting the doze bit of the config register causes the TMP1941AF to enter idle (doze) mode, irrespective of the setting of syscr2.stby[1:0]. prior to a transition to any of the standby modes, all interrupts other than those used for wake-up signaling must be disabled through the interrupt controller (intc). the characteristics of the idle, sleep and stop modes are as follows: idle: the cpu stops. on-chip peripherals can be selectively enabled and disabled through use of a register bit in a given peripheral, as shown in table 5.3. table 5.3 idle mode register settings peripheral idle mode bit tmra01 ta01run.i2ta01 tmra23 ta23run.i2ta23 tmrb0 tb0run.i2tb0 tmrb1 tb1run.i2tb1 tmrb2 tb2run.i2tb2 tmrb3 tb3run.i2tb3 sio0 sc0mod1.i2s0 sio1 sc1mod1.i2s1 sio3 sc3mod1.i2s3 sio4 sc4mod1.i2s4 sbi sbi0br1.i2sbi0 adc admod1.i2ad wdt wdmod.i2wdt note 1: in halt mode (i.e., a standby mode entered by setting the halt bit in the config register), the TMP1941AF freezes the tx19 core processor, preserving the pipeline state. in halt mode, the TMP1941AF ignores any external bus requests; so it continues to assume bus mastership. note 2: in doze mode (i.e., a standby mode entered by setting the doze bit in the config register), the TMP1941AF freezes the tx19 core processor, preserving the pipeline state. in doze mode, the TMP1941AF recognizes external bus requests. sleep: only the internal low-speed oscillator and the rtc are operational. stop: the whole TMP1941AF stops.
TMP1941AF 2003-03-27 TMP1941AF-23 5.6.1 TMP1941AF operation in normal and standby modes table 5.4 TMP1941AF operation in normal and standby modes operation mode operating states normal the tx19 core processor and peripherals operate at frequencies specified in the cg block. idle (halt) the processor and dmac operations stop; other on-chip peripherals can be selectively disabled. idle (doze) processor operation stops; the dmac is operational; other on-chip peripherals can be selectively disabled. sleep processor operation stops; of the on-chip peripherals, only the rtc is operational (at fs). stop all processor and peripheral operations stop completely. 5.6.2 cg operation in normal and standby modes table 5.5 cg states in normal and standby modes clock source mode oscillator pll clock supply to peripherals clock supply to cpu crystal normal on on yes yes slow on off partially supplied (see note.) yes idle (halt) on on selectable no idle (doze) on on selectable no sleep fs only off rtc only no stop off off no no external clock normal off on yes yes slow off off partially supplied (see note.) yes idle (halt) off on selectable no idle (doze) off on selectable no sleep off off rtc only no stop off off no no note: the intc, external bus interface (ebif), i/o ports, wdt and rtc can operate in slow mode. 5.6.3 processor and peripheral block operation in standby modes table 5.6 processor and peripheral blocks in standby modes circuit block clock source idle (doze) idle (halt) sleep stop tx19 core processor dmac intc ebif external bus mastership i/o ports off on on on on on off off on on on off off off off off off off off off off off off off adc sio i2c timer counters wdt fsys selectable on a block-by-block basis off off off off off off off off off off rtc fs onononoff cg ? on on on off
TMP1941AF 2003-03-27 TMP1941AF-24 5.6.4 wake-up signaling there are two ways to exit a standby mode: an interrupt request or reset signal. availability of wake- up signaling depends on the settings of the interrupt mask level bits, cmask[15:13], of the cp0 status register and the current standby mode (see table 5.7). ? wake-up via interrupt signaling the operation upon return from a standby mode varies, depending on the interrupt priority level programmed before entering a standby mode. if the interrupt priority level is greater than the processor?s interrupt mask level, execution resumes with the interrupt service routine. upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated the standby mode (i.e., the instruction that set the halt or doze bit in the config register). if the interrupt priority level is equal to or less than the processor?s interrupt mask level, program execution resumes with the instruction that activated the standby mode. the interrupt is left pending. nonmaskable interrupts are always serviced upon return from a standby mode, regardless of the current interrupt mask level. ? wake-up via reset signaling reset signaling always brings the TMP1941AF out of any standby mode. a wake-up from stop mode must allow sufficient time for the oscillator to restart and stabilize (see table 5.1). a reset does not affect the contents of the on-chip ram, but initializes everything else, whereas an interrupt preserves all internal states that were in effect before the standby mode was entered.
TMP1941AF 2003-03-27 TMP1941AF-25 table 5.7 wake-up signaling sources and wake-up operations interrupt masking unmasked interrupt (request_level > mask_level) masked interrupt (request_level mask_level) standby mode idle (programmable) sleep stop idle (programmable) sleep stop nmi 1 1 intwdt ?? ?? int0?4 1 ??? 1 intrtc ? ?? ? int5?a ?? ? ?? intta0?3 ?? ? ?? inttb00?31 inttbof0?3 ?? ? ?? intrx0?4 inttx0?4 ?? ? ?? ints2 ?? ? ?? intad ?? ? ?? interrupts intdma 2 ?? ? ?? wake-up signaling sources reset : execution resumes with the interrupt service routine. ( reset initializes the whole TMP1941AF.) ? : execution resumes with the instruction that activated the standby mode. the interrupt is left pending. ?: cannot be used to exit a standby mode. note 1: the TMP1941AF exits the standby mode after the warm-up period timer expires. note 2: intdma is accepted only in idle (doze) mode. note 3: if the interrupt request level is greater than the mask level, an interrupt signal which is programmed as level- sensitive must be held active until interrupt processing begins. otherwise, the interrupt will not be serviced successfully. note 4: if interrupts are disabled in the cpu, all interrupts other than those used for wake-up signaling must also be disabled in the interrupt controller (intc) before a standby mode is entered. otherwise, any interrupt could take the TMP1941AF out of the standby mode.
TMP1941AF 2003-03-27 TMP1941AF-26 5.6.5 stop mode the stop mode stops the whole TMP1941AF, including the on-chip oscillator. pin states in stop mode depend on the setting of the syscr2.drve bit, as shown in table 5.8. upon detection of wake- up signaling, the warm-up period timer should be activated to allow sufficient time for the oscillator to restart and stabilize before exiting stop mode. after that, the system clock output can restart. on exiting stop mode, the TMP1941AF enters either normal or slow mode, as programmed by the rxen, rxten and rsysck bits of the syscr0. these register bits must be programmed prior to the instruction that activates a standby mode. the warm-up period is chosen through the syscr2.wupt[1:0] bits. 5.6.6 returning from a standby mode (1) mode transitions from normal to stop to normal w-up time select syscr2.wupt[1:0] w-up time (fc) 01 (2 8 /fosc) 25.6 s 10 (2 14 /fosc) 1.638 ms 11 (2 16 /fosc) 6.554 ms fsys (high-speed clock) mode cg (high-speed clock) warm-up (w-up) high-speed clock oscillator started system clock stopped stop normal normal warm-up started warm-up completed when fosc = 10 mhz (2) mode transitions from normal to sleep to normal w-up time select syscr2.wupt[1:0] w-up time (fc) 01 (2 8 /fosc) 25.6 s 10 (2 14 /fosc) 1.638 ms 11 (2 16 /fosc) 6.554 ms low-speed clock (fs) continues oscillation. low-speed clock (fs) continues oscillation. fsys (high-speed clock) mode cg (low-speed clock) warm-up (w-up) high-speed clock oscillator started system clock stopped sleep normal normal cg (high-speed clock) warm-up started warm-up completed when fosc = 10 mhz
TMP1941AF 2003-03-27 TMP1941AF-27 (3) mode transitions from slow to stop to slow w-up time select syscr2.wupt[1:0] w-up time (fc) 01 (2 8 /fosc) 7.8 ms 10 (2 14 /fosc) 500 ms 11 (2 16 /fosc) 2000 ms fsys (low-speed clock) mode cg (low-speed clock) warm-up (w-up) low-speed clock oscillator started system clock stopped stop slow slow warm-up started warm-up completed when fosc = 32.768 khz (4) mode transitions from slow to sleep to slow w-up time select syscr2.wupt[1:0] w-up time (fc) 01 (2 8 /fosc) 7.8 ms 10 (2 14 /fosc) 500 ms 11 (2 16 /fosc) 2000 ms fsys (low-speed clock) mode cg (low-speed clock) warm-up (w-up) low-speed clock continues oscillation. sleep slow slow warm-up started warm-up completed when fosc = 32.768 khz note 1: although the fs clock continues oscillation, a warm-up time must be specified. note 2: for the TMP1941AF with an on-chip flash, when the reset signal is used for stop/ sleep wake-up signaling, it must be held active for at least 500 s for the internal system to stabilize.
TMP1941AF 2003-03-27 TMP1941AF-28 table 5.8 pin states in stop mode, depending on the setting of the syscr2.drve bit pin name type drve = 0drve = 1 ad0~ad7 input/output ?? ad8~ad15 input/output ?? a0~a7/a16 a23 output ? output rd , wr output ? output wait , busrq input pu * input hwr , busak , w / r output pu * output p37 output mode p40?43 input mode output mode pu * pu * input output p44 (scout) input mode output mode ? ? input output p50?57 input pin ?? p70?76 input mode output mode ? ? input output p77 (int0) input mode output mode input mode (int0) ? ? input input output input p80?87 input mode output mode ? ? input output p90?95 input mode output mode ? ? input output p96 (xt1) ? p97 (xt2) input mode output mode xt1, xt2 ? ? ? input output ? pa0?pa3 input mode output mode input mode (int1?int4) ? ? input input output input pa4?pa7 input mode output mode ? ? input output nmi input pin input input ale output pin output low output low reset input pin input input am0, am1 input pin input input x1 input pin ?? x2 output pin output high output high ? : pins configured for input mode and input-only pins are disabled. pins configured for output mode and output-only pins assume the high-impedance state. input: the input gate is active; the input voltage must be held at either the high or low level to keep the input pin from floating. output: pin direction is output. pu*: programmable pull-up. because the input gate is always disabled, no overlap current flows while in high-impedance state.
TMP1941AF 2003-03-27 TMP1941AF-29 6. interrupts 6.1 overview interrupt processing is coordinated bewtween the cp0 status register, the interrupt controller (intc) and the clock generator (cg). the status register contains the interrupt mask level field (cmask[15:13]) and the interrupt enable bit (iec). for interrupt processing, also refer to the 32-bit tx system risc tx19 core architecture manual. the TMP1941AF interrupt mechanism includes the following features: ? 4 cpu internal interrupts (software interrupts) ? 12 external interrupt pins ( nmi , int0 through inta) ? 32 on-chip peripheral interrupts ? vector generation for each interrupt source ? programmable priority for each interrupt source (7 levels) ? dma trigger on interrupt tx19l core processor interrupt request nonmaskable interrupt request intc cg interrupt priority settings interrupt vector generation priority resolver interrupt detection block interrupt detection block interrupt clear register interrupt clear register int0?int4 intrtc internal interrupt signals (dmac, timers, sio, sbi, adc) int5?inta nmi, intwdt 3 66 5 int0?int4 bypass the cg unless used for stop/sleep wake-up signaling note 1: there are interrupt enable and polarity bits in these registers: ? ? ? ? interrupt mode control registers (imcxx) in the intc ? ? ? ? imcgxx registers in the cg note 2: the TMP1941AF provides six interrupt sources, int0?int4 and intrtc, that can be used for stop/sleep wake-up signaling. external interrupts int5?inta cannot function as wake-up signals. figure 6.1 general interrupt mechanism the interrupt detection block monitors interrupt events. each interrupt source can be individually programmed for active polarity and either level or edge sensitivity. the TMP1941AF interrupts are broadly grouped as follows: ? external interrupts int0?int4 and intrtc ? when enabled for stop/sleep wake-up signaling the TMP1941AF awakens from stop or sleep mode, if so programmed, when any of the external interrupts int0?int4 or intrtc is asserted. the emcgxx field in the imcgxx register
TMP1941AF 2003-03-27 TMP1941AF-30 defines the interrupt polarity. the intxen bit in the imcgxx register controls whether these interrupt sources are enabled as wake-up signal sources (1=enable). if enabled, the interrupt polarity (eimxx) field in the intc?s imcxx register has no effect, but must be set to 01, or high level. the ilxx field in the imcxx register determines the action taken after exiting stop/sleep mode; i.e., whether execution resumes with an interrupt service routine. ? when disabled for stop/sleep wake-up signaling if int0?int4 are disabled for stop/sleep wake-up signaling, the intc alone determines the polarity and enabling of these interrupt sources. intrtc is programmed through both the cg and intc, regardless of whether it is used for wake-up signaling. ? external interrupts int5?inta and internal interrupts except intrtc these interrupts are programmable through the intc. the intc collects interrupt events, prioritizes them and presents the highest-priority request to the tx19 core processor. hardware interrupts are summarized below. interrupt programming interrupt sensing int0?int4 imcgxx reg. in cg imcx reg. in intc when enabled for stop/sleep wake-up signaling, the polarity field in the intc has no effect, but must always be set to ?high- level.? the actual sensitivity is programmed in the cg. when disabled for stop/sleep wake-up signaling, interrupt sensitivity is programmed in the intc. in either case, each interrupt source is individually configurable as negative or positive polarity, and as edge-triggered or level-sensitive. intrtc imcgxx reg. in cg imcx reg. in intc in the intc, the polarity must always be set to ?high-level.? the actual sensitivity must be configured as rising-edge triggered in the cg. int0?inta imcx reg. in intc configurable as negative or positive polarity, and as edge- triggered or level-sensitive. on-chip peripherals intdman imcx reg. in intc falling edge other imcx reg. in intc rising edge here are example register settings required to enable and disable the int0 interrupt as a source of the stop/sleep wake-up signal (negative-edge triggered). ? enabling the interrupt imcga0.emcg[01:00] = 10 : configure int0 as negative-edge triggered eicrcg.icrcg[2:0] = 000 : clear int0 request cg block imcga0.int0en = 1 : enable int0 for wake-up signaling imc0l.eim[11:10] = 01 : configure int0 as high-level sensitive intclr.eiclr[5:0] = 000001 : clear int0 request intc block imc0l.il[12:10] = 101 : set int0 priority level to 5 status.iec = 1, status.cmask = xxx tx19 core processor ? disabling the interrupt status.iec = 0 tx19 core processor imc0l.il[12:10] = 000 : disable int0 interrupt intclr.eiclr[5:0] = 000001 : clear int0 request imcga0.int0en = 0 : disable int0 for wake-up signaling eicrcg.icrcg[2:0] = 000 : clear int0 request
TMP1941AF 2003-03-27 TMP1941AF-31 6.2 interrupt sources the TMP1941AF provides a reset interrupt, nonmaskable interrupts, and maskable interrupts: ? reset and nonmaskable interrupts the reset pin causes a reset interrupt. the nmi pin functions as a nonmaskable interrupt. the on-chip watchdog timer (wdt) is also capable of being a source of a nonmaskable interrupt (intwdt). reset and nonmaskable interrupts are always vectored to virtual address 0xbfc0_0000. ? maskable interrupts the TMP1941AF supports two types of maskable interrupts: software and hardware interrupts. maskable interrupts are vectored to virtual addresses 0xbfc0_0210 through 0xbfc0_0260, as shown below. interrupt source virtual vector address reset nonmaskable 0xbfc0_0000 swi0 0xbfc0_0210 swi1 0xbfc0_0220 swi2 0xbfc0_0230 software swi3 0xbfc0_0240 maskable hardware 0xbfc0_0260 note 1: the above table shows the vector addresses when the bev bit in the cp0 status register is set to 1. when bev=1, all exception vectors reside in the on-chip rom space. note 2: software interrupts are posted by setting one of the sw[3:0] bits in the cp0 cause register. software interrupts are distinct from the ?software set? interrupt which is one of the hardware interrupt sources. a software set interrupt is posted from the intc to the tx19 core processor when the il0[2:0] field in the intc?s imc0 register is set to a non-zero value.
TMP1941AF 2003-03-27 TMP1941AF-32 table 6.1 hardware interrupt sources interrupt number ivr[9:0] interrupt source interrupt control register address 0 1 2 3 000 010 020 030 software set int0 pin int1 pin int2 pin imc0l imc0h 0xffff_e000 0xffff_e002 4 5 6 7 8 9 10 11 040 050 060 070 080 090 0a0 0b0 int3 pin int4 pin reserved reserved reserved reserved int5 pin int6 pin imc1l imc1h imc2l imc2h 0xffff_e004 0xffff_e006 0xffff_e008 0xffff_e00a 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 0c0 0d0 0e0 0f0 100 110 120 130 140 150 160 170 180 190 1a0 1b0 1c0 1d0 1e0 1f0 200 210 220 230 240 250 260 270 280 290 2a0 2b0 2c0 2d0 2e0 2f0 300 310 320 330 340 350 int7 pin int8 pin int9 pin inta pin reserved reserved reserved reserved intta0: 8-bit timer 0 intta1: 8-bit timer 1 intta2: 8-bit timer 2 intta3: 8-bit timer 3 reserved reserved reserved reserved inttb00: 16-bit timer 0 (tb0rg0) inttb01: 16-bit timer 0 (tb0rg1) inttb10: 16-bit timer 1 (tb1rg0) inttb11: 16-bit timer 1 (tb1rg1) inttb20: 16-bit timer 2 (tb2rg0) inttb21: 16-bit timer 2 (tb2rg1) inttb30: 16-bit timer 3 (tb3rg0) inttb31: 16-bit timer 3 (tb3rg1) reserved reserved reserved reserved inttbof0: 16-bit timer 0 (overflow) inttbof1: 16-bit timer 1 (overflow) inttbof2: 16-bit timer 2 (overflow) inttbof3: 16-bit timer 3 (overflow) reserved reserved reserved reserved intrx0: sio receive (channel 0) inttx0: sio transmit (channel 0) intrx1: sio receive (channel 1) inttx1: sio transmit (channel 1) ints2: serial bus interface (sbi) reserved imc3l imc3h imc4l imc4h imc5l imc5h imc6l imc6h imc7l imc7h imc8l imc8h imc9l imc9h imcal imcah imcbl imcbh imccl imcch imcdl 0xffff_e00c 0xffff_e00e 0xffff_e010 0xffff_e012 0xffff_e014 0xffff_e016 0xffff_e018 0xffff_e01a 0xffff_e01c 0xffff_e01e 0xffff_e020 0xffff_e022 0xffff_e024 0xffff_e026 0xffff_e028 0xffff_e02a 0xffff_e02c 0xffff_e02e 0xffff_e030 0xffff_e032 0xffff_e034
TMP1941AF 2003-03-27 TMP1941AF-33 interrupt number ivr[9:0] interrupt source interrupt control register address 54 55 56 57 58 59 60 61 62 63 360 370 380 390 3a0 3b0 3c0 3d0 3e0 3f0 intrx3: sio receive (channel 3) inttx3: sio transmit (channel 3) intrx4: sio receive (channel 4) inttx4: sio transmit (channel 4) intrtc: rtc intad: a/d conversion complete intdma0: dma complete (channel 0) intdma1: dma complete (channel 1) intdma2: dma complete (channel 2) intdma3: dma complete (channel 3) imcdh imcel imceh imcfl imcfh 0xffff_e036 0xffff_e038 0xffff_e03a 0xffff_e03c 0xffff_e03e 6.3 interrupt detection when enabled as a stop/sleep wake-up signal, the polarities of int0?int4 are programmed in the emcgxx field of the imcgxx register within the cg; in this case, the eimxx field of the imcx register within the intc has no effect; it must be set to ?high-level sensitive,? though. when disabled as a wake-up singnal, the polarities of int0?int4 are programmed in the eimxx field in the intc?s imcx register. the polarity of intrtc is always programmed in both the cg and the intc. all other interrupts are always programmed in the intc?s imcx register. each interrupt source is individually configurable as negative or positive polarity, and as edge-triggered or level-sensitive. when a selected transition is detected, an interrupt request is issued to the intc (except for the nmi and intwdt interrupts, which are directly delivered to the tx19 core processor). it is the responsibility of software (an interrupt handler routine) to determine the cause of an interrupt and to clear the interrupt condition. intrtc and int0?int4 used for stop/sleep wake-up signaling require software access to two registers: the eicrcg register in the cg and the intclr register in the intc. other interrupts can be cleared by writing its ivr[9:4] value to the intclr register located within the intc. for an external interrupt configured as level-sensitive, software must explicitly address the device in question and clear the interrupt condition. a level-sensitive interrupt signal must be held active until the tx19 core processor reads its interrupt vector from the interrupt vector register (ivr). 6.4 resolving interrupt priority (1) seven interrupt priority levels the interrupt mode control registers (imcf?imc0) contain a 3-bit interrupt priority level (ilx) field for each interrupt source, which ranges from level 0 to level 7, with level 7 being the highest priority. level 0 indicates that the interrupt is disabled. (2) interrupt level notification when an interrupt event occurs, the intc sends its priority level to the tx19 core processor. the processor can determine the priority level of an interrupt being requested by reading the il field in the cp0 cause register. (3) interrupt vector (interrupt source notification) whenever an interrupt request is made, the intc automatically sets its vector in the ivr. the tx19 core processor can determine the exact cause of an interrupt by reading the ivr. if multiple interrupt requests occur at the same level, the interrupt with the smallest interrupt number is delivered (see table 6.1). when no interrupt is pending, the ivr[9:4] field in the ivr contains a value of zero. when the tx19 core processor responds to a request with an interrupt acknowledge cycle, the intc forwards the interrupt vector for that interrupt request. at this time, the tx19 core processor saves the priority level value in the cmask field of the cp0 status register.
TMP1941AF 2003-03-27 TMP1941AF-34 6.5 register description table 6.2 intc register map address symbol register name corresponding interrupt number 0xffff_e060 intclr interrupt request clear register all (63 ? 0) 0xffff_e040 ivr interrupt vector register all (63 ? 0) 0xffff_e03c imcf interrupt mode control register f 63 ? 60 0xffff_e038 imce interrupt mode control register e 59 ? 56 0xffff_e034 imcd interrupt mode control register d 55 ? 52 0xffff_e030 imcc interrupt mode control register c 51 ? 48 0xffff_e02c imcb interrupt mode control register b 47 ? 44 0xffff_e028 imca interrupt mode control register a 43 ? 40 0xffff_e024 imc9 interrupt mode control register 9 39 ? 36 0xffff_e020 imc8 interrupt mode control register 8 35 ? 32 0xffff_e01c imc7 interrupt mode control register 7 31 ? 28 0xffff_e018 imc6 interrupt mode control register 6 27 ? 24 0xffff_e014 imc5 interrupt mode control register 5 23 ? 20 0xffff_e010 imc4 interrupt mode control register 4 19 ? 16 0xffff_e00c imc3 interrupt mode control register 3 15 ? 12 0xffff_e008 imc2 interrupt mode control register 2 11 ? 8 0xffff_e004 imc1 interrupt mode control register 1 7 ? 4 0xffff_e000 imc0 interrupt mode control register 0 3 ? 0 6.5.1 interrupt vector register (ivr) this register indicates the vector for the interrupt source when there is an interrupt event. 76543210 ivr name ivrl ???? (0xffff_e040) read/write r reset value00000000 function interrupt vector for the source of the current interrupt 15 14 13 12 11 10 9 8 name ivrh ivrl read/write r/w r reset value00000000 function interrupt vector for the source of the current interrupt 23 22 21 20 19 18 17 16 name ivrm read/write r/w reset value00000000 function 31 30 29 28 27 26 25 24 name ivrm read/write r/w reset value00000000 function
TMP1941AF 2003-03-27 TMP1941AF-35 6.5.2 interrupt mode control registers (imcf?imc0) these registers control the interrupt priority level, active polarity, either level or edge sensitivity, and dma triggering. 76543210 imc0l name ?? eim01 eim00 dm0 il02 il01 il00 (0xffff_e000) read/write ?? r/w reset value ?? 000000 function interrupt sensitivity 00: low level must be set to 00. dma trigger 0: disable 1: enable when dm0 = 0 interrupt number 0 (software set) 000: interrupt disabled. 001?111: priority level (1?7) when dm0 = 1 dmac channel select 000?011: channel number (0?3) 100?111: don?t use. 15 14 13 12 11 10 9 8 name ?? eim11 eim10 dm1 il12 il11 il10 read/write ?? r/w reset value ?? 000000 function interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable when dm0 = 0 interrupt number 1 (int0 pin) 000: interrupt disabled. 001?111: priority level (1?7) when dm0 = 1 dmac channel select 000?011: channel number (0?3) 100?111: don?t use. 23 22 21 20 19 18 17 16 imc0h name ?? eim21 eim20 dm2 il22 il21 il20 (0xffff_e002) read/write ?? r/w reset value ?? 000000 function same as above (int1) same as above (int1) interrupt number 2 (int1 pin) same as above 31 30 29 28 27 26 25 24 name ?? eim31 eim30 dm3 il32 il31 il30 read/write ?? r/w reset value ?? 000000 function same as above (int2) same as above (int2) interrupt number 3 (int2 pin) same as above note 1: interrupt sensitivity must be programmed when interrupts are enabled. note 2: for a complete list of the interrupt mode control registers, see chapter 19. note 3: when an interrupt is used to trigger a dmac channel, that dmac channel must be put in ready state after the programming of the intc. 6.5.3 interrupt request clear register (intclr) loading the eiclr[5:0] field of this register with the ivrl[9:4] value of the ivr causes the corresponding interrupt to be cleared. 76543210 intclr name ?? eiclr5 eiclr4 eiclr3 eiclr2 eiclr1 eiclr0 0xffff_e060) read/write ?? w reset value ???????? function ivrl[9:4] value for an interrupt to be cleared note1: an interrupt request must not be cleared before the tx19 core processor reads the ivr value. note2: follow the steps below to disable a particular interrupt with the interrupt controller (intc). 1. globally disable the acceptance of interrupts by the core processor by clearing the iec bit of the status register. 2. disable a desired interrupt with the intc by clearing the ilx[2:0] field of the imcxx register. 3. execute the sync instruction. 4. enable the acceptance of interrupts by the core processor by setting the iec bit of the status register. example: mtc0 r0, r31 ; _di ( ) ; sb r0, imc** ; imc** = 0 ; sync ; _sync ( ) ; mtc0 $sp, r31 ; _ei ( ) ;
TMP1941AF 2003-03-27 TMP1941AF-36 7. i/o ports the TMP1941AF has 46 i/o port pins. all the port pins except a few share pins with alternate functions. they can be individually programmed as general-purpose i/o or dedicated i/o for the on-chip cpu or peripherals. table 7.1 shows all the i/o port pins available on the TMP1941AF and their shared functions. (there is no port 6.) table 7.2 is a summary of register settings used to control the port pins. table 7.1 programmable i/o ports port pin name # of pins direction pull resistor direction programmability alternate functions port 3 p37 1 in p ut/out p ut pullu p bitwise p40 1 input/output pullup bitwise cs0 p41 1 input/output pullup bitwise cs1 p42 1 input/output pullup bitwise cs2 p43 1 input/output pullup bitwise cs3 port 4 p44 1 input/output ? bitwise scout port 5 p50?p57 8 input ? fixed an0?an7/ adtrg (p53) p70 1 input/output ? bitwise ta0in/txd3 p71 1 input/output ? bitwise ta1out/rxd3 p72 1 input/output ? bitwise ta2in/txd4 p73 1 input/output ? bitwise ta3out/rxd4 p74 1 input/output ? bitwise tb0in0/int5 p75 1 input/output ? bitwise tb0in1/int6 p76 1 input/output ? bitwise tb0out port 7 p77 1 input/output ? bitwise int0 p80 1 input/output ? bitwise tb1in0/int7 p81 1 input/output ? bitwise tb1in1/int8 p82 1 input/output ? bitwise tb1out p83 1 input/output ? bitwise tb2in0int9 p84 1 input/output ? bitwise tb2in1/inta p85 1 input/output ? bitwise tb2out (/ boot in tmp1940fdbf) p86 1 input/output ? bitwise tb3out/intlv port 8 p87 1 input/output ? bitwise p90 1 input/output ? bitwise txd0 p91 1 input/output ? bitwise rxd0 p92 1 input/output ? bitwise sclk0/ cts0 p93 1 input/output ? bitwise txd1 p94 1 input/output ? bitwise rxd1 p95 1 input/output ? bitwise sclk1/ cts1 p96 1 input/output ? bitwise xt1 port 9 p97 1 input/output ? bitwise xt2 pa0?pa3 4 input/output ? bitwise int1?int4 pa4 1 input/output ? bitwise pa5 1 input/output ? bitwise sck pa6 1 input/output ? bitwise so/sda port a pa7 1 input/output ? bitwise si/scl
TMP1941AF 2003-03-27 TMP1941AF-37 table 7.2 i/o port programmability (1/2) i/o register settings port pin name direction / function pn pncr pnfc ad0-ad7 bus input/output n/a n/a n/a ad8-ad15 bus input/output n/a n/a n/a a8-a15 bus output n/a n/a n/a a16-a23 bus output n/a n/a n/a rd output n/a n/a n/a wr output n/a n/a n/a hwr (note 1) output n/a n/a n/a input (with pullup disabled) 0 n/a n/a wait input (with pullup enabled) 1 n/a n/a input (with pullup disabled) 0 n/a n/a busrq input (with pullup enabled) 1 n/a n/a busak output n/a n/a n/a ? w / r (note 1) output n/a n/a n/a input port (with pullup disabled) 0 0 0 port 3 p37 input port (with pullup enabled) 1 0 0 input port (with pullup disabled) 0 0 0 input port (with pullup enabled) 1 0 0 p40?p43 (note 1) output port x 1 0 p40 cs0 output x 1 1 p41 cs1 output x 1 1 p42 cs2 output x 1 1 p43 cs3 output x 1 1 port 4 p44 scout output x 1 1 input port x p50?p57 an[0:7] inputs (note 2) x port 5 p53 adtrg input (note 3) x n/a input port x 0 0 p70?p77 output port x 1 0 ta0in input x 0 1 p70 txd3 output x 1 1 ta1out output x 1 1 p71 rxd3 input x 0 1 ta2in input x 0 1 p72 txd4 output x 1 1 ta3out output x 1 1 p73 rxd4 input x 0 1 tb0in0 input x 0 1 p74 int5 input x 0 setting unneeded tb0in1 input x 0 1 p75 int6 input x 0 setting unneeded p76 tb0out output x 1 1 wake-up int0 input (note 4) x 0 1 port 7 p77 int0 input (no wake-up) x 0 setting unneeded
TMP1941AF 2003-03-27 TMP1941AF-38 table 7.2 i/o port programmability (2/2) i/o register settings port pin name function / direction pn pncr pnfc input port x 0 0 p80?p87 output port x 1 0 tb1in0 input x 0 1 p80 int7 input x 0 setting unneeded tb1in1 input x 0 1 p81 int8 input x 0 setting unneeded p82 tb1out output x 1 1 tb2in0 input x 0 1 p83 int9 input x 0 setting unneeded tb2in1 input x 0 1 p84 inta input x 0 setting unneeded p85 tb2out output x 1 1 port 8 p86 tb3out output x 1 1 input port x 0 0 p90?p95 output port x 1 0 p90 txd0 output x 1 1 p91 rxd0 input x 0 n/a sclk0 output x 1 1 p92 cts0 /sclk0 input x 0 1 p93 txd1 output x 1 1 p94 rxd1 input x 0 n/a sclk1 output x 1 1 p95 cts1 /sclk1 input x 0 1 input port x 0 output port (note 5) x 1 port 9 p96?p97 xt1?xt2 (note 6) x 0 n/a input port x 0 0 pa0?pa7 output port x 1 0 wake-up int1?int4 inputs (note 4) x 0 setting unneeded pa0?pa3 int1?int4 inputs (no wake-up) x 0 sck input x 0 1 pa5 sck output x 1 1 sda input x 0 0 pa6 sda output (note 5)/so output x 1 1 si input/scl input x 0 0 port a pa7 scl output (note 7) x 1 1 x: don?t care pn: port n register, pncr: port n control register, pnfc: port n function register
TMP1941AF 2003-03-27 TMP1941AF-39 note 1: hwr , w / r and p40 to p43 have their internal pullup resistors enabled when the corresponding p4fc register bit is set and when the bus is released. note 2: when p50?p57 are configured as analog channels of the adc, the adch[2:0] field in a/d mode control register 1 (admod1) is used to select a channel(s). see section 15.1. note 3: when p53 is configured as adtrg , the adtrge bit in the admod1 register is used to enable and disable the external trigger input to the adc. note 4: when int0?int4 are enabled for a wake-up from stop mode with the syscr2.drive bit cleared (undriven pins), the corresponding bit in the pnfc must be set. note 5: when p96?p97 are configured as output ports, they function as open-drain outputs. note 6: when p96?p97 are configured as xt1?xt2, the syscr0 register must be programmed to enable oscillation, etc. note 7: when pa6 and pa7 are configured as sda and scl outputs for the sbi, the odea[7:6] field in the open-drain enable (ode) register can be used to configure them as either push-pull or open-drain ouptuts. upon reset, the default is push-pull. see section 7.11.
TMP1941AF 2003-03-27 TMP1941AF-40 7.1 address/data bus bits 0?7 (ad0?ad7) ad0?ad7 function as bits 0?7 of the address/data bus. the address bits 0?7 (a0?a7) and the data bits 0? 7 (d0?d7) are multiplexed onto these pins. data inputs ad0?ad7 internal data bus address/data outputs figure 7.1 address/data bus bits 0?7 (ad0?ad7) 7.2 address/data bus bits 8?15 (ad8?ad15) / address bus bits 8?15 (a8?a15) these pins function as either ad[8:15] bits of the address/data bus or the a[8:15] bits of the address bus, depending on the logic state of the am0 pin. when am0 is at logic 0 (i.e., 16-bit data bus or mixed 8/16-bit data bus), these pins always function as the ad[8:15] bits of the address/data bus. when am0 is at logic 1 (i.e., 8-bit data bus), these pins always function as the a[8:15] bits of the address bus. data inputs ad8?ad15/a8?a15 internal data bus address/data outputs address outputs figure 7.2 address/data bus bits 8?15 (ad8?ad15) / address bus bits 8?15 (a8?a15)
TMP1941AF 2003-03-27 TMP1941AF-41 7.3 address bus bits 16?23 (a16?a23) these pins always function as a[16:23] bits of the address bus. a16?a23 internal data bus address outputs figure 7.3 address bus bits 16?23 (a16?a23) 7.4 rd , wr , hwr , wait , busrq , busak , r/ w these pins always function as bus control signals. upon reset, the internal pullup resistors of the wait and busrq pins are enabled; the pullup resistors can be disabled by clearing the corresponding bits in the p3 register. hwr and r/ w are held at logic 1 while busak =0. rd , wr internal data bus hwr , busak , r/ w internal data bus p-ch figure 7.4 rd , wr , hwr , busak , r/ w
TMP1941AF 2003-03-27 TMP1941AF-42 wait , busrq internal data bus p-ch output latch wait input busrq input (programmable pullup resistor) p3 write figure 7.5 wait / busrq pullup control register 76543210 p3 name ??? rqpup wtpup ??? (0xffff_f018) read/write r/w r/w reset value 1 1 1 function 1 1 (pullup) 1 (pullup) figure 7.6 wait / busrq pullup control register 0: pullup disabled 1: pullup enabled note: the pullup control and p3 registers are physically the same register. bit 7 of this register controls the internal pullup register of port 37.
TMP1941AF 2003-03-27 TMP1941AF-43 7.5 port 37 port 37 functions as a general-purpose i/o pin. port 37 can be configured as an input or an output by programming the p3cr register. upon reset, the output latch p37 is set to 1 and the p37c bit in the p3cr register is cleared, configuring port37 for input mode with pullup. p3 read output buffer direction control (bitwise) p3 write p3cr write reset internal data bus s output latch p37 p-ch programmable pullup resistor figure 7.7 port 37 port 3 register 76543210 p3 name p37 ??????? (0xffff_f018) read/write r/w r/w r/w reset value 1 1 1 functoin 0: pullup disabled 1: pullup enabled port 3 control register 76543210 p3cr name p37 ??????? (0xffff_f01a) read/write w reset value 0 function 0: in 1: out must be written as 1. must be written as 1. must be written as 0. must be written as 0. must be written as 1. figure 7.8 port 37 registers note: the p3 and wait / busrq pullup control registers are physically the same register. bits 3 and 4 control the internal pullup resistors of wait and busrq .
TMP1941AF 2003-03-27 TMP1941AF-44 7.6 port 4 (p40?p44) p40?p43 can be individually programmed to function as either discrete general-purpose i/o pins or programmable chip select ( cs0 ? cs3 ) pins. p44 can be programmed to function as either a general-purpose i/o pin or a system clock output (scout) pin. the p4cr and p4fc registers select the direction and function of the port 4 pins. upon reset, the p4cr and p4fc register bits are cleared, configuring all the port 4 pins as input port pins; p40?p43 have an internal pullup resistor. upon reset, the output latch (p4) is set to all 1s. s output latch direction control (bitwise) p4 read p4 write p4fc write p4cr write reset internal data bus p40 ( cs0 ) p41 ( cs1 ) p42 ( cs2 ) p43 ( cs3 ) programmable pullup resistor cs0 , cs1 , cs2 , cs3 selector output buffer p-ch function control (bitwise) a b s figure 7.9 port 4 (p40?p43)
TMP1941AF 2003-03-27 TMP1941AF-45 s output latch selector function control (bitwise) direction control (bitwise) reset p4cr write p4 read fs clock fsys clock p44 (scout) y s b a p4fc write syscr3.scosel selector y s b a selector y s b a p4 write internal data bus figure 7.10 port 4 (p44)
TMP1941AF 2003-03-27 TMP1941AF-46 port 4 register 76543210 p4 name ??? p44 p43 p42 p41 p40 (0xffff_f01e) read/write ??? r/w reset value ??? input mode ??? 1 1 (pullup) 1 (pullup) 1 (pullup) 1 (pullup) port 4 control register 76543210 p4cr name ??? p44c p43c p42c p41c p40c (0xffff_f020) read/write ??? w reset value ??? 00100 ??? 0: in 1: out port 4 function register 76543210 p4fc name ??? p44f p43f p42f p41f p40f (0xffff_f021) read/write ??? w reset value ??? 00100 function 0: port 0: port 1: scout 1: cs 0 port (p40) 1 cs0 0 port (p41) 1 cs1 0 port (p42) 1 cs2 0 port (p43) 1 cs3 figure 7.11 port 4 registers
TMP1941AF 2003-03-27 TMP1941AF-47 7.7 port 5 (p50?p57) eight port 5 pins are input-only pins shared with the analog input pins of the a/d converter (adc). p53 is also shared with the a/d trigger input pin. ad read port 5 read port 5 p50?p57 (an0?an7) internal data bus channel selector a/d converter a/d conversion result register adtrg (only p53) figure 7.12 port 5 (p50?p57) port 5 register 76543210 p5 bit symbol p57 p56 p55 p54 p53 p52 p51 p50 (0xffff_f025) read/write r after reset input mode figure 7.13 port 5 register note 1: a/d mode control register 1 (admod1) is used to select an a/d converter input channel(s) and to enable the a/d trigger input. see section 15.1. note 2: when p53 is used as the a/d trigger input ( adtrg ) pin, p53 (an3) can not function as an analog input.
TMP1941AF 2003-03-27 TMP1941AF-48 7.8 port 7 (p70?p77) eight port 7 pins can be individually programmed to function as discrete general-purpose or dedicated i/o pins. upon reset, all port 7 pins are configured as input port pins. alternatively, p70 and p72 can each be programmed as either the txd output from an sio channel or the clock input (ta0in or ta2in) to an 8-bit timer. p71 and p73 can each be programmed as either the rxd input to an sio channel or the timer output (ta1out or ta3out) from an 8-bit timer. p74 and p75 can each be programmed as either the clock input (tb0in0 or tb0in1) to a 16-bit timer or an external interrupt request pin (int5 or int6). p76 can be programmed as the timer flip-flop output (tb0out) from a 16-bit timer. p77 can be programmed as an external interrupt request pin (int0). the p7cr and p7fc registers select the direction and function of the port 7 pins. a reset sets the output latch (p7) to all 1s, and clears the p7cr and p7fc register bits, configuring all port 7 pins as input port pins. when int0 is used as a wake-up from stop mode with the syscr2.drve bit cleared, the p7fc.p77f bit must be set to 1. p70 (ta0in/txd3) p72 (ta2in/txd4) reset p7fc write ta0in txd3, txd4 p7 read p7 write p7cr write internal data bus function control (bitwise) selector s output latch ta2in selector configurable as an open-drain output ode.ode70 ode.ode72 s s a b b a direction control (bitwise) figure 7.14 port 7 (p70, p72)
TMP1941AF 2003-03-27 TMP1941AF-49 p71 (ta1out/rxd3) p73 (ta3out/rxd4) reset p7fc write rxd3 timer flip-flop output p7 read p7 write p7cr write internal data bus function control (bitwise) selector direction control (bitwise) output latch rxd4 selector ta1out: from tmra01 ta3out: from tmra23 s a b s s a b p74 (tb0in0/int5) p75 (tb0in1/int6) reset p7fc write tb0in0 tb0in1 p7 read p7 write p7cr write internal data bus function control (bitwise) direction control (bitwise) output latch selector s a b s int5 int6 figure 7.15 port 7 (p71, p73, p74, p75)
TMP1941AF 2003-03-27 TMP1941AF-50 p76 (tb0out) reset p7fc write timer flip-flop output p7 read p7 write p7cr write internal data bus function control (bitwise) selector direction control (bitwise) output latch selector tb0out: from tmrb0 s a s a b b s p77 (int0) reset int0 p7 read p7 write p7cr write direction control (bitwise) output latch selector level/edge sensitivity positive/negative polarity imcga0.emcg[01:00], imcga0.int0en imc0l.eim1 s a b s p7fc write function control (bitwise) (note) internal data bus figure 7.16 port 7 (p76, p77)
TMP1941AF 2003-03-27 TMP1941AF-51 port 7 register 76543210 p7 name p77p76p75p74p73p72p71p70 (0xffff_f02b) read/write r/w reset value input mode (the output latch is set to 1.) 11111111 port 7 control register 76543210 p7cr name p77c p76c p75c p74c p73c p72c p71c p70c (0xffff_f02e) read/write w reset value00000000 function 0: in 1: out port 7 direction settings 0 input 1 output port 7 function register 76543210 p7fc name p77f p76f p75f p74f p73f p72f p71f p70f (0xffff_f02f) read/write w reset value00000000 function 0: port 0: port 0: port 0: port 0: port 0: port 0: port 0: port 1: tb0out 1: tb0in1 1: tb0in0 1: ta3out 1: ta2in 1: ta1out 1: ta0in 1: wake-up int0 1: rxd4 1: txd4 1: rxd3 1: txd3 int0 settings p7fc.p77f 1 p7cr.p77c 0 note: required to exit stop mode, with syscr2.drve cleared. otherwise, unneeded. tb0out settings p7fc.p76f 1 p7cr.p76c 1 tb0in1 settings p7fc.p75f 1 p7cr.p75c 0 tb0in0 settings p7fc.p74f 1 p7cr.p74c 0 rxd4 settings ta3out settings p7fc.p73f 1 p7fc.p73f 1 p7cr.p73c 0 p7cr.p73c 1 ta2in settings txd4 settings p7fc.p72f 1 p7fc.p72f 1 p7cr.p72c 0 p7cr.p72c 1 rxd3 settings ta1out settings p7fc.p71f 1 p7fc.p71f 1 p7cr.p71c 0 p7cr.p71c 1 ta0in settings txd3 settings p7fc.p70f 1 p7fc.p70f 1 p7cr.p70c 0 p7cr.p70c 1 figure 7.17 port 7 registers
TMP1941AF 2003-03-27 TMP1941AF-52 7.9 port 8 (p80?p87) eight port 8 pins can be individually programmed to function as discrete general-purpose or dedicated i/o pins. upon reset, all port 8 pins are configured as input port pins, and the output latch (p8) is set to all 1s. port 8 pins (except p87) can be programmed as clock inputs to 16-bit timers, timer flip-flop outputs from 16- bit timers, or external interrupt request pins (int7 through inta). setting the p8fc register bits configures the port 8 pins for dedicated functions. a reset clears all the p8cr and p8fc register bits, configuring all port 8 pins as input port pins.
TMP1941AF 2003-03-27 TMP1941AF-53 p80 (tb1in0/int7) p81 (tb1in1/int8) p83 (tb2in0/int9) p84 (tb2in1/inta) reset p8fc write tb1in0 tb1in1 tb2in0 tb2in1 p8 read p8 write p8cr write internal data bus function control (bitwise) direction control (bitwise) output latch selector s a b s int7 int8 int9 inta p82 (tb1out) p85 (tb2out) p86 (tb3out) p87 reset p8fc write timer flip-flop output p8 read p8 write p8cr write internal data bus function control (bitwise) selector direction control (bitwise) output latch selector tb1out: from tmrb1 tb2out: from tmrb2 tb3out: from tmrb3 a b s s s b a figure 7.18 port 8 (p80~p87)
TMP1941AF 2003-03-27 TMP1941AF-54 port 8 register 76543210 p8 name p87p86p85p84p83p82p81p80 (0xffff_f030) read/write r/w reset value input mode (the output latch is set to 1.) port 8 control register 76543210 p8cr name p87c p86c p85c p84c p83c p82c p81c p80c (0xffff_f032) read/write w reset value00000000 function 0: in 1: out port 8 direction settings 0 input 1 output port 8 function register 76543210 p8fc name ? p86f p85f p84f p83f p82f p81f p80f (0xffff_f033) read/write w reset value ? 0000000 function must be written as 0. 0: port 1: tb3out 0: port 1: tb2out 0: port 1: tb2in1 0: port 1: tb2in0 0: port 1: tb1out 0: port 1: tb1in1 0: port 1: tb1in0 tb1out settings p8fc.p82f 1 p8cr.p82c 1 tb3out settings tb2out settings p8fc.p86f 1 p8fc.p85f 1 p8cr.p86c 1 p8cr.p85c 1 figure 7.19 port 8 registers
TMP1941AF 2003-03-27 TMP1941AF-55 7.10 port 9 (p90?p97) ? p90?p95 p90?p95 can be individually programmed to function as discrete general-purpose or dedicated i/o pins. upon reset, p90?p95 are configured as input port pins, and the corresponding output latch (p9) bits are set to 1. setting the bits in the p9fc register configures the corresponding pin for sio input or output pins. a reset clears the relevant p9cr and p9fc bits, configuring p90?p95 as input port pins. ? p96?p97 p96 and p97 function as general-purpose i/o pins. as output ports, p96 and p97 are configured as open-drain outputs. upon reset, the relevant output latch (p9) bits are set to 1, and the p9cr register bits are set, causing p96 and p97 to assume the high-impedance state. p96 and p97 can also be used as the xt1 and xt2 pins; in this case, a low-frequency crystal is connected between xt1 and xt2 to provide for dual-clock mode, which is controlled through system clock control registers 0 and 1 (syscr0 and syscr1). (1) p90 (txd0) and p93 (txd1) p90 and p93 can be programmed to function as either general-purpose i/o pins or txd output pins for sio channels. p90 and p93 are configurable as open-drain outputs. internal data bus function control (bitwise) p90 (txd0) p93 (txd1) reset p9fc write txd0, txd1 p9 read p9 write p9cr write selector direction control (bitwise) output latch selector configurable as open-drain outputs ode.ode90 ode.ode93 a b s s s a b figure 7.20 port 9 (p90, p93)
TMP1941AF 2003-03-27 TMP1941AF-56 (2) p91 (rxd0) and p94 (rxd1) p91 and p94 can be programmed to function as either general-purpose i/o pins or rxd input pins for sio channels. p91 (rxd0) p94 (rxd1) reset rxd0, rxd1 p9 read p9 write p9cr write internal data bus output latch direction control (bitwise) selector a b s s figure 7.21 port 9 (p91, p94)
TMP1941AF 2003-03-27 TMP1941AF-57 (3) p92 (sclk0/ cts0 ) and p95 (sclk1/ cts1 ) p92 and p95 can be programmed to function as general-purpose i/o pins, or sclk clock input or output pins or cts input pins for sio channels. p92 (sclk0/ cts0 ) p95 (sclk1/ cts1 ) reset p9fc write cts0 , cts1 sclk0 and sclk1 outputs p9 read p9 write p9cr write internal data bus function control (bitwise) selector direction control (bitwise) output latch sclk0, sclk1 selector a b s s s b a p92 (sclk0/ cts0 ) p95 (sclk1/ cts1 ) figure 7.22 port 9 (p92, p95)
TMP1941AF 2003-03-27 TMP1941AF-58 (4) p96 (xt1) and p97 (xt2) p96 and p97 function as general-purpose i/o pins. alternatively, p96 and p97 can be used as the xt1 and xt2 pins for connecting a low-frequency crystal. reset output buffer (open-drain) output buffer (open-drain) low-frequency clock low-frequency oscillator enable p96 (xt1) (enabled when 1) p97 (xt2) p9 read p9 read p9 write internal data bus p9cr write p9cr write p9 write direction control (bitwise) output latch selector selector output latch direction control (bitwise) a b s s s y s s y a b s figure 7.23 port 9 (p96, p97)
TMP1941AF 2003-03-27 TMP1941AF-59 port 9 register 76543210 p9 name p97p96p95p94p93p92p91p90 (0xffff_f031) read/write r/w output mode input mode reset value 11111111 port 9 control register 76543210 p9cr name p97c p96c p95c p94c p93c p92c p91c p90c (0xffff_f034) read/write w reset value11000000 function 0: in 1: out port 9 direction settings 0 input 1 output port 9 function register 76543210 p9fc name ?? p95f ? p93f p92f ? p90f (0xffff_f035) read/write w reset value ?? 0 ? 00 ? 0 function 0: port 1: sclk1 output or cts1 / sclk1 input 0: port 1: txd1 0: port 1: sclk0 output or 0 cts / sclk0 input 0: port 1: txd0 cts1 /sclk1 input settings sclk1 output settings txd0 output settings p9fc.p95f 1 p9fc.p95f 1 p9fc.p90f 1 p9cr.p95c 0 p9cr.p95c 1 p9cr.p90c 1 txd1 output settings cts1 /sclk0 input settings sclk0 output settings p9fc.p93f 1 p9fc.p92f 1 p9fc.p92f 1 p9cr.p93c 1 p9cr.p92c 0 p9cr.p92c 1 note 1: setting bit 0 of the open-drain enable (ode) register configures thetxd0 pin as an open-drain output. setting bit 1 of the ode register configures the txd1 pin as an open-drain output. see section 7.11. the p91/rxd0 and p94/rxd1 pins do not have bits for selecting pin functions. these pins can be continuously used as shared input port and serial data input pins. note 2: low-speed oscillator consideration when a low-frequency crystal is connected between xt1 (p96) and xt2 (p97), the following register settings are required to reduce power consumption: when a crystal is connected between xt1 and xt2: p9cr.p96c?p97c = 11 p9.p96?p97 = 00 when xt1 is driven with an external clock: p9cr.p96c?p97c = 11 p9.p96?p97 = 10 figure 7.24 port 9 registers
TMP1941AF 2003-03-27 TMP1941AF-60 7.11 port a (pa0?pa7) eight port a pins can be individually programmed to function as discrete general-purpose or dedicated i/o pins. upon reset, all port a pins are configured as input port pins. alternatively, pa0?pa3 can be programmed as external interrupt request pins (int1?int4), and pa5? pa7 as the serial bus interface (sbi) pins. setting the pafc register bits configures the corresponding port 8 pins for dedicated functions. a reset clears all the pacr and pafc register bits, configuring all port a pins as input port pins. when int1?int4 are used as a wake-up from stop mode with the syscr2.drve bit cleared, the corresponding bits in the pafc register must be set to 1. port a can act as an interface to the dsu ice.
TMP1941AF 2003-03-27 TMP1941AF-61 pa0?pa3 (int1?int4) reset int1?int4 pa read pa write pacr write internal data bus direction control (bitwise) output latch selector level/edge sensitivity positive/negative polarity imcgax.emcgx[1:0], imcgax.intxen imcxx.eimx s b a s (note) pafc write function control (bitwise) pa4 reset pa read pa write pacr write internal data bus output latch direction control (bitwise) selector a s s b figure 7.25 port a (pa0?pa4)
TMP1941AF 2003-03-27 TMP1941AF-62 pa5 (sck) reset pafc write sck output pa read pa write pacr write internal data bus function control (bitwise) selector direction control (bitwise) output latch sck input selector a b s s s b a pa6 (so/sda) reset pafc write so output pa read pa write pacr write internal data bus function control (bitwise) selector direction control (bitwise) output latch sda input selector configurable as an open-drain output ode.odea6 a b s a b s s figure 7.26 port a (pa5?pa6)
TMP1941AF 2003-03-27 TMP1941AF-63 pa7 (si/scl) reset pafc write scl output pa read pa write pacr write internal data bus function control (bitwise) selector direction control (bitwise) output latch si input selector configurable as an open-drain output ode.odea7 scl input a b s s b a s figure 7.27 port a (pa7)
TMP1941AF 2003-03-27 TMP1941AF-64 port a register 76543210 pa name pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 (0xffff_f036) read/write r/w reset value input mode (the output latch set to 1.) port a control register 76543210 pacr name pa7c pa6c pa5c pa4c pa3c pa2c pa1c pa0c (0xffff_f038) read/write w reset value00000000 function 0: in 1: out port a direction settings 0 input 1 output port a function register 76543210 pafc name pa7f pa6f pa5f pa4f pa3f pa2f pa1f pa0f (0xffff_f039) read/write w reset value 0 0 0 function 0: port 1: scl output 0: port 1: sda/so output 0: port 1: sck output must be written as 0. 0: port 1: wake-up int4 input 0: port 1: wake-up int3 input 0: port 1: wake-up int2 input 0: port 1: wake- up int1 input wake-up int1?int4 input settings pafc.paxf 1 pacr.paxc 0 note: required to exit stop mode, with syscr2.drve cleared. otherwise, unneeded. sck output settings pafc.pa5f 1 pacr.pa5c 1 sda/so output settings pafc.pa6f 1 scl output settings pacr.pa6c 1 pafc.pa7f 1 pacr.pa7c 1 figure 7.28 port a registers
TMP1941AF 2003-03-27 TMP1941AF-65 7.12 open-drain output control the txd output pins (p70, p72, p90 and p93) of the sio, and the so/sda (pa6) and si/scl (pa7) pins of the serial bus interface (sbi) can be configured as either push-pull or open-drain outputs. open-drain enable register 76543210 ode name ?? ode72 ode70 odea7 odea6 ode93 ode90 (0xffff_f050) read/write ?? r/w reset value ?? 000000 function p72 0: push- pull 1: open- drain p70 0: push- pull 1: open- drain pa7 0: push- pull 1: open- drain pa6 0: push- pull 1: open- drain p93 0: push- pull 1: open- drain p90 0: push- pull 1: open- drain figure 7.29 open-drain enable register
TMP1941AF 2003-03-27 TMP1941AF-66 8. external bus interface the TMP1941AF contains external bus interface logic that handles the transfer of information between the internal busses and the memory or peripherals in the external address space. it consists of the external bus interface (ebif) logic and the chip select/wait controller. the cs/wait controller provides four programmable chip select signals, with variable block sizes. the chip select function supports automatic wait-state generation and data bus sizing (8-bit or 16-bit) for each of the four address blocks and the rest of the external address locations. the ebif logic controls the timing of the external bus, based on the settings of the cs/wait controller. the ebif logic also performs dynamic bus sizing and bus arbitration. (1) wait-state generation individually programmable for each address block ? automatic insertion of up to seven wait cycles ? wait pin (2) data bus width individually programmable (8-bit or 16-bit) for each address block (3) read recovery cycles individually programmable (to up to 2 cycles) for each address block. read recovery cycles are dummy cycles inserted between two consecutive external bus cycles. (4) ale pulse width selectable ale pulse width (0.5 or 1.5 cycles). this setting applies to all the address blocks. (5) bus arbitration ? when am0 = 0 the TMP1941AF has either a mixed 8/16-bit data bus or the 16-bit data bus. the program memory accessed after reset must be connected with the TMP1941AF with a 16-bit data bus. ? when am1 = 1 the TMP1941AF has a 8-bit data bus. when am1 is at logic 1, the data bus width settings in the chip select/wait control registers are ignored.
TMP1941AF 2003-03-27 TMP1941AF-67 8.1 address and data buses 8.1.1 supported configurations for external memory interface, port 0 (ad0?ad7), port 1 (ad8?ad15/a8?a15) and port 2 (a16? a23/a0?a7) pins can be configured as the address and data buses. the TMP1941AF supports the following four bus configurations. when am1 = 0 and am0 = 1, the address and data buses are configured as shown in (1) below. when am1 = 0 and am0 = 0, the address and data buses are configured as shown in (2) below. (1) (2) address lines 24 max (16 mbytes) 24 max (16 mbytes) data lines 8 16 multiplexed address/data lines 816 port 0 ad0?ad7 ad0?ad7 port 1 a8?a15 ad8?ad15 pin functions port 2 a16?a23 a16?a23 timing diagram note 1: because the data bus is multiplxed with the address bus, even in the c and d configurations, address bits also appear on the ad bus prior to the data being accepted or provided. note 2: upon reset, all of ports 0?2 are configured as general-purpose input ports; programming is required to use them as address or data bus pins. note 3: address and data bus configurations are selectable through the programming of the p1cr, p1fc, p2cr and p2fc registers. 8.1.2 states of the address bus during on-chip address accesses while an on-chip address is being accessed, the address bus maintains the previous address externally presented. during this time, the address/data bus assumes the high-impedance state. a23-8 a23-8 ad7-0 ale rd a7-0 d7-0 a23-8 a23-16 ad15-0 ale rd a15-0 d15-0
TMP1941AF 2003-03-27 TMP1941AF-68 8.2 external bus operation this section describes external bus operations. in the timing diagrams which follow, a23?a16 is the address bus, and ad15?ad0 is the address/data bus. this section only provides a functional description of the bus; refer to section 18, ac electrical characteristics , for detailed timing specifications. 8.2.1 basic bus operation while the TMP1941AF provides a total of three clock cycles to perform a read or write, it also allows the bus cycle to be extended by inserting wait states. figure 8.1 shows external bus read timing. figure 8.2 shows external bus write timing. while an on- chip address is being accessed, the external address bus maintains the previous value with the ale pin kept inactive. during this time, the address/data bus assumes the high-impedance state, and bus control signals such as rd and wr remain inactive. a[23:16] ad[15:0] ale rd external access internal access hi-z inactive inactive no change adr data tsys figure 8.1 read cycle timing tsys a[23:16] ad[15:0] ale wr external access internal access hi-z inactive inactive no change adr data figure 8.2 write cycle timing note: tsys is the system clock period.
TMP1941AF 2003-03-27 TMP1941AF-69 8.2.2 wait timing the cs/wait controller provides two ways to insert wait states in a bus cycle. each address block can be programmed either: ? to insert required number of wait state cycles (up to seven cycles), or ? to use the wait pin to insert wait states dynamically on a cycle basis following are bus cycle timing diagrams with wait states. a[23:16] ad[15:0] ale rd upper address upper address adr data adr data 0 wait state 1 wait state wait state tsys figure 8.3 read cycle timing (with zero and one wait state cycle) a[23:16] ad[15:0] ale rd upper address upper address adr data adr data wait states 0 wait state (1 + n wait states; n = 1) wait tsys figure 8.4 read cycle timing (with 1 + n wait states; n=1)
TMP1941AF 2003-03-27 TMP1941AF-70 a[23:16] ad[15:0] ale wr upper address upper address adr data adr data 0 wait state 1 wait state wait state tsys figure 8.5 write cycle timing (with zero and one wait state cycle) a[23:16] ad[15:0] ale wr upper address upper address adr data adr data 0 wait state 1 + n wait states; n = 1 wait states wait tsys figure 8.6 write cycle timing (with 1 + n wait state cycles; n=1)
TMP1941AF 2003-03-27 TMP1941AF-71 8.2.3 ale pulse width the ale pulse width is programmed to 0.5 or 1.5 clock cycles through the alesel bit of the syscr3 register within the cg. the default is 1.5 cycles. this setting applies to the whole external address space. ale (alesel = 0) ad[15:0] ale (alesel = 1) ad[15:0] 0.5 clock cycles 1.5 clock cycles tsys figure 8.7 ale pulse width figure 8.8 shows read cycle timing, with the ale width programmed to 0.5 and 1.5 clock cycles. a[23:16] ad[15:0] ale rd upper address upper address adr data adr data ale = 0. 5 clock cycles ale = 1. 5 clock cycles tsys figure 8.8 read cycle timing (ale = 0.5 and 1.5 clock cycles)
TMP1941AF 2003-03-27 TMP1941AF-72 8.2.4 read recovery time following an external bus read cycle, a certain recovery time may be required before initiating the next external bus cycle. to allow for a read recovery time, one or two dummy cycles can be inserted between back-to-back bus cycles. (dummy cycles can only be inserted immediately after a read.) ? between an external read and an external read: programmable ? between an external read and an external write: programmable ? after an external write: no dummy cycle dummy cycle insertion is programmable in the cs/wait controller. read data rd ad[15:0] ale ale next adr two dummy cycles ad[15:0] read data next adr tsys figure 8.9 read recovery time dummy cycles insert idle cycles between transfers to enable slow off-chip peripherals to remove data from the data bus before the next transfer begins. this provides a sufficient time after the rd strobe for the previous read is deasserted until the address for the next read or write is placed on the address bus. figure 8.10 shows bus cycle timing with one and two dummy cycles inserted into bus cycles. adr ale ad[15:0] upper address data data adr a[23:16] 1 dummy cycle 2 dummy cycles rd tsys dummy dummy figure 8.10 read cycle timing (with dummy cycles inserted)
TMP1941AF 2003-03-27 TMP1941AF-73 8.3 bus arbitration the TMP1941AF provides support for an external bus master to take control of the external bus. two bus arbitration control signals, busrq and busak , are used to determine the bus master. one or more of the external devices on the bus can have the capability of becoming bus master for the external bus, but not the TMP1941AF internal bus. 8.3.1 bus access control external bus masters can gain control of the external bus, but not the TMP1941AF internal bus (g- bus). thus, external bus masters cannot access the TMP1941AF?s on-chip memory and peripherals. the external bus interface (ebif) logic in the TMP1941AF manages the arbitration of the external bus; the cpu and on-chip dmac do not participate in any way in this bus arbitration. during external bus mastership, the cpu and the on-chip dmac can access the internal memory (ram and rom) and registers. once an external device assumes bus mastership, the cpu or the on-chip dmac has no way to regain the bus until the external bus master releases the bus. if the cpu or the on-chip dmac issues an external memory access request, it is forced to wait until the TMP1941AF regains the bus. therefore, should busrq be left asserted for a long time, the TMP1941AF might suffer system lockups. 8.3.2 bus arbitration flow external devices capable of becoming bus masters assert busrq to request the bus. the TMP1941AF samples busrq at the end of each external bus cycle, as seen on its internal bus (g- bus). when the TMP1941AF has made an internal decision to grant the bus, it asserts busak to indicate to the requesting device that the bus is available. at the same time, the TMP1941AF puts the address bus, the data bus and bus control signals in the high-impedance state. a load or store may require multiple bus cycles, depending on the port size of the addressed device (dynamic bus sizing). in that case, the TMP1941AF does not grant the bus until the entire transfer is complete. the TMP1941AF, if so programmed, automatically inserts dummy cycles between back-to-back bus cycles to allow for sufficient read recovery time. in dummy cycles, the TMP1941AF has already internally initiated a bus cycle on the g-bus for the next external access. the TMP1941AF can only accept an external bus request at the boundary of an internal g-bus bus cycle. therefore, if busrq is asserted during a dummy cycle, the TMP1941AF grants the bus after it completes the next external bus cycle. an external bus master must keep busrq asserted until it is granted the bus. a timing diagram of the bus arbitration sequence is shown in figure 8.11.
TMP1941AF 2003-03-27 TMP1941AF-74 12 3 internal address external address busrq busak internal clock TMP1941AF external access TMP1941AF external bus master TMP1941AF TMP1941AF external access figure 8.11 bus arbitration timing diagram 1. busrq is sampled high. 2. the TMP1941AF recognizes the assertion of busrq . 3. the TMP1941AF asserts busak at the completion of the current bus cycle. the external bus master recognizes busak and assumes bus mastership to start a bus transfer. 8.3.3 relinquishing the bus when the external bus master has completed its bus transactions, it deasserts busrq to relinquish the bus to the TMP1941AF. figure 8.12 shows the timing for an external bus master to relinquish the bus. internal address external address busrq busak ?@?a ?b internal clock TMP1941AF external access TMP1941AF external access TMP1941AF external bus masters TMP1941AF 123 figure 8.12 external bus master relinquishing the bus 1. the external bus master has control of the bus. 2. when the external bus master no longer needs the bus, it deasserts busrq . 3. in response to the deassertion of busrq , the TMP1941AF deasserts busak .
TMP1941AF 2003-03-27 TMP1941AF-75 9. chip select/wait controller the TMP1941AF supports direct connections to rom and sram devices. the TMP1941AF provides four programmable chip select signals. programmable features include variable block sizes, data bus width, wait state insertion, and dummy cycle insertion for back-to-back bus cycles. cs0 ? cs3 (multiplexed with p40?p43) are the chip select output pins for the cs0?cs3 address ranges. these chip select signals are generated when the cpu or on-chip dmac issues an address within the programmed ranges. the p40?p43 pins must be configured as cs0 ? cs3 by programming the port a control (p4cr) register and the port 4 function (p4fc) register. chip select address ranges are defined in terms of a base address and an address mask. there is a base/mask address (bman) register for each of the four chip select signals, where n is a number from 0 to 3. there is also a set of three chip select/wait control registers, b01cs, b23cs and bexcs, each of which consists of a master enable bit, a data bus width bit, a wait state field and a dummy cycle field. external memory devices can also use the wait pin to insert wait states and consequently prolong read and write bus cycles. 9.1 programming chip select ranges each of the four chip select address ranges is defined in the bman register. the basic chip select model allows one of the chip select output signals ( cs0 ? cs3 ) to assert when an address on the address bus falls within a particular programmed range. the b01cs register defines specific operations for cs0 and cs1 , and the b23cs register defines specific operations for cs2 and cs3 (see section 9.2). 9.1.1 base/mask address registers (bma0?bma3) the organizations of the bman registers are shown in figure 9.1 and figure 9.2. the base address (ban) field specifies the starting address for a chip select. any set bit in the address mask field (man) masks the corresponding base address bit. the address mask field determines the block size of a particular chip select line. the address is compared on every bus cycle. (1) base address the base address (ban) field specifies the upper 16 bits (a31?a16) of the starting address for a chip select. the lower 16 bits (a15?a0) are assumed to be zero. thus, the base address is any multiple of 64 kbytes starting at 0x0000_0000. figure 9.3 shows the relationships between starting addresses and the bman values. (2) address mask the address mask field defines whether any particular bits of the address should be compared or masked. any set bit masks the corresponding base address bit. the address compare logic uses only the address bits that are not masked (i.e., mask bit cleared to 0) to detect an address match. address bits that can be masked (i.e., supported block sizes) differ for the four chip select spaces as follows: cs0 and cs1 spaces: a29?a14 cs2 and cs3 spaces: a30?a15 the address mask field defines the block size of a particular chip select line. note: use physical addresses in the bman registers.
TMP1941AF 2003-03-27 TMP1941AF-76 base/mask address registers 76543210 bma0 name ma0 (a29 ? a14) (0xffff_e400) read/write r/w reset value11111111 function cs0 block size 0: the address compare logic uses this address bit. 15 14 13 12 11 10 9 8 name ma0 (a29 ? a14) read/write r/w reset value00000011 function must be written as 0. 23 22 21 20 19 18 17 16 name ba0 read/write r/w reset value00000000 function a23?a16 of the starting address for cs0 31 30 29 28 27 26 25 24 name ba0 read/write r/w reset value00000000 function a31?a24 of the starting address for cs0 76543210 bma1 name ma1 (a29 ? a14) (0xffff_e404) read/write r/w reset value11111111 function cs1 block size 0: the address compare logic uses this address bit. 15 14 13 12 11 10 9 8 name ma1 (a29 ? a14) read/write r/w reset value00000011 function must be written as 0. 23 22 21 20 19 18 17 16 name ba1 read/write r/w reset value00000000 function a23?a16 of the starting address for cs1 31 30 29 28 27 26 25 24 name ba1 read/write r/w reset value00000000 function a31?a24 of the starting address for cs1 note: bits 10?15 in the bma0 and bma1 must be written as zeros. the cs0 and cs1 block sizes can vary from 16 kbytes to 1 gbytes. however, the TMP1941AF supports only 16 mbytes of external address space. therefore, bits 10?15 in the bma0 and bma1 must be cleared so that a24?a29 of an address will not be masked. figure 9.1 base/mask address registers (bma0 and bma1)
TMP1941AF 2003-03-27 TMP1941AF-77 76543210 bma2 name ma2 (a30 ? a15) (0xffff_e408) read/write r/w reset value11111111 function cs2 block size 0: the address compare logic uses this address bit. 15 14 13 12 11 10 9 8 name ma2 (a30 ? a15) read/write r/w reset value00000001 function must be written as 0. 23 22 21 20 19 18 17 16 name ba2 read/write r/w reset value00000000 function a23?a16 of the starting address for cs2 31 30 29 28 27 26 25 24 name ba2 read/write r/w reset value00000000 function a31?a24 of the starting address for cs2 76543210 bma3 name ma3 (a30 ? a15) (0xffff_e40c) read/write r/w reset value11111111 function cs3 block size 0: the address compare logic uses this address bit. 15 14 13 12 11 10 9 8 name ma3 (a30 ? a15) read/write r/w reset value00000001 function must be written as 0. 23 22 21 20 19 18 17 16 name ba3 read/write r/w reset value00000000 function a23?a16 of the starting address for cs3 31 30 29 28 27 26 25 24 name ba3 read/write r/w reset value00000000 function a31?a24 of the starting address for cs3 note: bits 9?15 in the bma2 and bma3 must be written as zeros. the cs2 and cs3 block sizes can vary from 32 kbytes to 1 gbytes. however, the TMP1941AF supports only 16 mbytes of external address space. therefore, bits 9?15 in the bma0 and bma1 must be cleared so that a24?a30 of an address will not be masked. figure 9.2 base/mask address registers (bma2 and bma3)
TMP1941AF 2003-03-27 TMP1941AF-78 starting address base address value (ban) 0xffff_0000 0xffff_ffff ffff address 0x0000_0000 64 kbytes 0x0006_0000 0006 0x0005_0000 0005 0x0004_0000 0004 0x0003_0000 0003 0x0002_0000 0002 0x0001_0000 0001 0x0000_0000 0000 figure 9.3 relationships between starting addresses and base address register values 9.1.2 base address and address mask value calculations ? program the bma0 register as follows to cause 0 cs to be asserted in the 64 kbytes of address space starting at 0xc000_0000. 31 16 15 0 ba0 ma0 11000000000000000000000000000011 c0000003 bma0 register value the ba0 field specifies the upper 16 bits of the starting address, or 0xc000. the ma0 field determines whether the a29?a14 bits of the address should be compared or masked. the a31 and a30 bits are always compared. bits 15?10 of the ma0 field must be cleared so that the a29?a24 bits are always compared. when the bma0 register is programmed as shown above, the a31?a16 bits of the address are compared to the value of the ba0 field. consequently, the 64-kbyte address range between 0xc000_0000 and 0xc000_ffff is defined as the cs0 space.
TMP1941AF 2003-03-27 TMP1941AF-79 ? program the bma2 register as follows to cause 2 cs to be asserted in the 512 kbytes of address space starting at 0x1fc8_0000. 31 16 15 0 ba2 ma2 00011111110010000000000000001111 1fc8000f bma2 register value the ba2 field specifies the upper 16 bits of the starting address, or 0x1fc8. the ma2 field determines whether the a30?a15 bits of the address should be compared or masked. the a31 bit is always compared. bits 15?9 of the ma2 field must be cleared so that the a30?a24 bits are always compared. when the bma2 register is programmed as shown above, the a31?a19 bits of the address are compared to the value of the ba2 field. consequently, the 512-kbyte address range between 0x1fc8_0000 and 0x1fcf_ffff is defined as the cs2 space. ? program the bma2 register as follows to cause 2 cs to be asserted in the 1 mbytes of address space starting at 0x1fc8_0000. 31 16 15 0 ba2 ma2 00011111110010000000000000011111 1fc8001f bma2 register value the ba2 field specifies the upper 16 bits of the starting address, or 0x1fc8. the ma2 field determines whether the a30?a15 bits of the address should be compared or masked. the a31 bit is always compared. bits 15?9 of the ma2 field must be cleared so that the a30?a24 bits are always compared. when the bma2 register is programmed as shown above, the a31?a20 bits of the address are compared to the value of the ba2 field. note, however, that the 512-kbyte range between 0x1fc0_0000 and 0x1fc7_ffff is reserved for the on-chip rom. consequently, the 512kbyte address range between 0x1fc8_0000 and 0x1fcf_ffff is defined as the cs2 space. note: the TMP1941AF does not assert any csn signal in the following address ranges: 0xffff_8000 through 0xffff_bfff
TMP1941AF 2003-03-27 TMP1941AF-80 table 9.1 shows the programmable block sizes for cs0 to cs3. even if the user has accidentally programmed more than one chip select line to the same area, only one chip select line is driven because of internal line priorities. cs0 has the highest priority, and cs3 the lowest. example: the starting address of the cs0 space is progammed as 0xc000_0000 with a size of 16 kbytes. the starting address of the cs1 space is programmed as 0xc000_0000 with a size of 64 kbytes. 0xc000_0000 0xc000_3fff 0xc000_0000 0xc000_3fff 0xc000_ffff cs1 space cs0 space when an attempt is made to access the overlapping area, the cs0 area is selected. table 9.1 supported block sizes size (bytes) cs space 16 k 32 k 64 k 128 k 256 k 512 k 1 m 2 m 4 m 8 m 16 m cs0 cs1 cs2 cs3
TMP1941AF 2003-03-27 TMP1941AF-81 9.2 chip select/wait control registers the organizations of the chip select/wait control registers are shown in figure 9.4 to figure 9.5. each of these registers consist of a chip select type field, a master enable bit, a data bus width bit, a wait state field and a dummy cycle field. the b01cs register defines the cs0 and cs1 lines; the b23cs register defines the cs2 and cs3 lines; and the bexcs register defines the access characteristics for the rest of the address locations. chip select/wait control registers 76543210 b01cs name b0om ? b0bus b0w (0xffff_e480) read/write w ? w reset value 0 0 ? 00101 function chip select output waveform 00: rom/ram don?t use any other value. data bus width 0: 16-bit 1: 8-bit number of wait-state cycles 0000: no wait state, 0001: 1 wait state 0010: 2 wait states, 0011: 3 wait states 0100: 4 wait states, 0101: 5 wait states 0110: 6 wait states, 0111: 7 wait states 1111: (1 + n) wait states, as determined by the wait pin don?t use any other value. 15 14 13 12 11 10 9 8 name ???? b0e ? b0rcv read/write ???? w ? w reset value ???? 0 ? 00 function cs0 enable 0: disable 1: enable number of dummy cycles (read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: don?t use. 23 22 21 20 19 18 17 16 name b1om ? b1bus b1w read/write w ? w reset value 0 0 ? 00101 function chip select output waveform 00: rom/ram don?t use any other value. data bus width 0: 16-bit 1: 8-bit number of wait-state cycles 0000: no wait state, 0001: 1 wait state 0010: 2 wait states, 0011: 3 wait states 0100: 4 wait states, 0101: 5 wait states 0110: 6 wait states, 0111: 7 wait states 1111: (1 + n) wait states, as determined by the wait pin don?t use any other value. 31 30 29 28 27 26 25 24 name ???? b1e ? b1rcv read/write ???? w ? w reset value ???? 0 ? 00 function cs1 enable 0: disable 1: enable number of dummy cycles (read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: don?t use. figure 9.4 chip select/wait control registers
TMP1941AF 2003-03-27 TMP1941AF-82 76543210 b23cs name b2om ? b2bus b2w (0xffff_e484) read/write w ? w reset value 0 0 ? 00101 function chip select output waveform 00: rom/ram don?t use any other value. data bus width 0: 16-bit 1: 8-bit number of wait-state cycles 0000: no wait state, 0001: 1 wait state 0010: 2 wait states, 0011: 3 wait states 0100: 4 wait states, 0101: 5 wait states 0110: 6 wait states, 0111: 7 wait states 1111: (1 + n) wait states, as determined by the wait pin don?t use any other value. 15 14 13 12 11 10 9 8 name ???? b2e b2m b2rcv read/write ???? w reset value ???? 1000 function cs2 enable 0: disable 1: enable cs2 space select 0: whole 4-gbyte space 1: cs space number of dummy cycles (read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: don?t use. 23 22 21 20 19 18 17 16 name b3om ? b3bus b3w read/write w ? w reset value 0 0 ? 00101 function chip select output waveform 00: rom/ram don?t use any other value. data bus width 0: 16-bit 1: 8-bit number of wait-state cycles 0000: no wait state, 0001: 1 wait state 0010: 2 wait states, 0011: 3 wait states 0100: 4 wait states, 0101: 5 wait states 0110: 6 wait states, 0111: 7 wait states 1111: (1 + n) wait states, as determined by the wait pin don?t use any other value. 31 30 29 28 27 26 25 24 name ???? b3e ? b3rcv read/write ???? w ? w reset value ???? 0 ? 00 function cs3 enable 0: disable 1: enable number of dummy cycles (read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: don?t use. figure 9.5 chip select/wait control registers
TMP1941AF 2003-03-27 TMP1941AF-83 76543210 bexcs name bexom bexbus bexw (0xffff_e488) read/write w w reset value00 00101 function chip select output waveform 00: rom/ram don?t use any other value. data bus width 0: 16-bit 1: 8-bit sets the number of wait cycles 0000?0111: 0?7 wait states 1111: (1 + n) wait states, as determined by the wait pin don?t use any other value. 15 14 13 12 11 10 9 8 name bexrcv read/write w reset value 00 function number of dummy cycles (read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: don?t use. figure 9.6 chip select/wait control registers 9.3 application example figure 9.7 shows an example usage of the TMP1941AF programmable chip selects. in this example, 128 kbytes of rom and 256 kbytes of ram are connected off-chip through a 16-bit data bus. latch 16 TMP1941AF a15?16 a0?14 oe w r/ ce1 a15?16 a0?14 oe w r/ ce1 lower byte upper byte a15 a0?14 oe ce ram (128 kbits 8) ram (128 kbits 8) i/o1?8 i/o1?8 d0?7 d8?15 a1?15 a16?17 a1?15 a 16?17 le d q am1 am0 cs1 wr rd hwr ale cs2 rom (128 kbits 16) a16 a1?15 ad0?7 ad8?15 a16?17 figure 9.7 external memory connections (rom width = 16 bits, ram width = 16 bits)
TMP1941AF 2003-03-27 TMP1941AF-84 10. dma controller (dmac) the TMP1941AF contains a four-channel dma controller. 10.1 features the TMP1941AF dmac has the following features: (1) four independent dma channels (2) two types of bus requests, with and without bus snooping (3) transfer requests: internal transfer requests: software initiated external transfer requests: hardware signals from on-chip peripherals and external interrupt pins (4) dual-address mode (5) memory-to-memory, memory-to-i/o, and i/o-to-memory transfers (6) transfer width: ? memory: 32-bit (8-bit and 16-bit memory devices are supported through the programming of the cs/wait controller.) ? i/o peripherals: 8-, 16-, and 32-bit (7) address pointers can increment, decrement or remain constant. the user can program the bit positions at which address incrementation or decrementation occurs. (8) fixed channel priority
TMP1941AF 2003-03-27 TMP1941AF-85 10.2 implementation 10.2.1 on-chip dmac interface figure 10.1 shows how the dmac is internally connected with the tx19 core processor and the interrupt controller (intc). tx19 core processor address data bus grant control bus request bus release request busrel ? intdreq[3:0] ? ] 0 : 3 [ dack ? dmac bus grant ackowledge haveit ? interrupt controller (intc) on-chip i/o peripheral interrupt requests? external interrupt requests busreq ? busgnt ? ? internal signals figure 10.1 dmac connections within the TMP1941AF the dmac provides four independently programmable channels. with each dma channel, there are two associated signals: a dma request (intdreqn) and a dma acknowledge ( dackn ), where n is a channel number from 0 to 3. intdreqn is an input to the dmac coming from the intc, and dackn is an output signal from the dmac going to the intc. channel priority is fixed. channel 0 has the highest priority, and channel 3 has the lowest priority. the tx19 core processor supports bus snooping. when snooping is enabled, the tx19 core processor grants the processor data bus to the dmac, so that the dmac can access the on-chip ram connected to the processor. snooping can be enabled and disabled under software control. the dmac bus snooping is discussed in the next subsection in more details. there are two bus request signals from the dmac going to the tx19 core processor, sreq and greq. greq is a bus request without snooping. sreq is a bus request with snooping. note: dma channel priority exists only among those using the same type of bus request signal (sreq or greq). for example, once a given dma channel has acquired bus mastership using sreq, no other dma channel can assume bus mastership using greq until the ongoing dma transaction is completed.
TMP1941AF 2003-03-27 TMP1941AF-86 10.2.2 dmac block the dmac block diagram is shown in figure 10.2. source address register channel 3 channel 2 ?f ?x ?e ?b ?l[ ?v ?? ?? ?a ?h ?? ?x ?? ?w ?x ?^ s ou rce ?a ?h ?? ?x regi su ter byte count ?? ?w ?x ?^ ?` ?? ?l ?? status ?? ?w ?x ?^ ?` ?? ?l ?? ?r ?? ?g ?[ ?? ?? ?w ?x ?^ 31 0 channel 1 destination address register (darn) byte count register (bcrn) channel control register (ccrn) 31 0 channel 0 dma control register (dcr) data holding register (dhr) channel status register (csrn) dma transfer control register (dtcrn) source address re g ister ( sarn ) figure 10.2 dmac block diagram 10.2.3 bus snooping the tx19 core processor supports snoop operations. if snooping is enabled, the tx19 core processor grants the processor data bus to the dmac. because the dmac takes control of the processor data bus, the tx19 stops operating during snoop operations until the dmac relinquishes the bus to the processor. snooping allows the dmac to access the on- chip ram, and thus to use them as a dma source or destination device. the dmac allows the enabling and disabling of the snooping function by software. if snooping is disabled, the dmac can not access the on-chip ram. however, regardless of whether snooping is enabled or disabled, the dmac assumes mastership of the TMP1941AF on-chip bus (g- bus) during dma transfers. therefore, as long as dma transfers are in progress, the tx19 core processor can not access memory or i/o peripherals via the g-bus; any attempt to do so causes the processor pipeline to stall. note: if snooping is disabled, the tx19 core processor does not grant mastership of the processor data bus to the dmac. therefore, if the on-chip ram is specified as a source or destination for dma transfers, a dma acknowledge signal will never be returned, causing bus lockup.
TMP1941AF 2003-03-27 TMP1941AF-87 10.3 register description the dmac has twenty-six 32-bit registers. the dmac register map is shown in table 10.1. table 10.1 dmac registers address symbol register name 0xffff_e200 ccr0 channel control register (ch. 0) 0xffff_e204 csr0 channel status register (ch. 0) 0xffff_e208 sar0 source address register (ch. 0) 0xffff_e20c dar0 destination address register (ch. 0) 0xffff_e210 bcr0 byte count register (ch. 0) 0xffff_e218 dtcr0 dma transfer control register (ch. 0) 0xffff_e220 ccr1 channel control register (ch. 1) 0xffff_e224 csr1 channel status register (ch. 1) 0xffff_e228 sar1 source address register (ch. 1) 0xffff_e22c dar1 destination address register (ch. 1) 0xffff_e230 bcr1 byte count register (ch. 1) 0xffff_e238 dtcr1 dma transfer control register (ch. 1) 0xffff_e240 ccr2 channel control register (ch. 2) 0xffff_e244 csr2 channel status register (ch. 2) 0xffff_e248 sar2 source address register (ch. 2) 0xffff_e24c dar2 destination address register (ch. 2) 0xffff_e250 bcr2 byte count register (ch. 2) 0xffff_e258 dtcr2 dma transfer control register (ch. 2) 0xffff_e260 ccr3 channel control register (ch. 3) 0xffff_e264 csr3 channel status register (ch. 3) 0xffff_e268 sar3 source address register (ch. 3) 0xffff_e26c dar3 destination address register (ch. 3) 0xffff_e270 bcr3 byte count register (ch. 3) 0xffff_e278 dtcr3 dma transfer control register (ch. 3) 0xffff_e280 dcr dma control register (all channels) 0xffff_e28c dhr data holding register (all channels)
TMP1941AF 2003-03-27 TMP1941AF-88 10.3.1 dma control register (dcr) 31 30 16 rst 0 w : read/write 15 0 0 : read/write bits mnemonic field name description 31 rst reset performs a software reset of the dmac. when the rst bit is set to 1, all the dmac internal registers are initialized to their reset values. any transfer requests are removed and all the four dma channels are put in idle state. 0: don?t-care 1: resets the dmac. note 1: when the snoop request is disabled (ccrn.sreq=0), a software reset of the dmac must be performed in the following sequence: 1. disable interrupts. 2. execute nop four times. 3. perform a software reset. 4. perform a software reset again. 5. re-enable interrupts. execute steps 3 and 4 consecutively. note 2: if the software reset command is written to the dcr register immediately after the completion of the last transfer cycle of a dma transaction, the dma-done interrupt will not be cleared. in this case, the software reset only initializes channel registers, etc. note 3: don?t issue a software reset command to the dcr register via a dma transfer. figure 10.3 dma control register (dcr)
TMP1941AF 2003-03-27 TMP1941AF-89 10.3.2 channel control registers (ccrn) 31 30 25 24 23 22 21 20 19 18 17 16 str 0 ? nien ablen ???? big ? w w r/w r/w r/w r/w r/w r/w r/w r/w : read/write 11100010: reset value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? exr pose lev sreq reien sio sac dio dac trsiz dps r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w : read/write 0000000 00 0 00 00 00 : reset value bits mnemonic field name description 31 str channel start reset value: ? enables a dma channel. setting this bit puts the dma channel in ready state. dma transfer starts as soon as a transfer request is received. only a write of 1 is valid, and a write of 0 has no effect on this bit. a 0 is returned on read. 1: enables a dma channel. 24 ? reserved this bit is reserved and must be written as 0. 23 nien normal completion interrupt enable reset value = 1 1: enables an interrupt when the channel finishes a transfer without an error condition. 0: does not enable an interrupt when the channel finishes a transfer without an error condition. 22 abien abnormal termination interrupt enable reset value = 1 1: enables an interrupt when the channel encounters a transfer error. 0: does not enable an interrupt when the channel encounters a transfer error. 21 ? reserved this bit is reserved and must be written as 0. 20 ? reserved this bit is reserved and must be written as 0. 19 ? reserved this bit is reserved and must be written as 0. 18 ? reserved this bit is reserved and must be written as 0. 17 big big-endian reset value = 1 1: the dma channel operates in big-endian mode. 0: the dma channel operates in little-endian mode. in the TMP1941AF, this bit must be cleared to 0. 16 ? reserved this bit is reserved and must be written as 0. 15 ? reserved this bit is reserved and must be written as 0. 14 exr external request mode reset value = 0 selects a transfer request mode. 1: external transfer requests (interrupt-driven) 0: internal transfer requests (software-initiated) 13 pose positive edge reset value = 0 defines the polarity of the internal dma request signal (intdreqn) for the channel. this bit is valid for external transfer requests (i.e., when exr=1), and has no effect on internal transfer requests (i.e., when exr=0). in the TMP1941AF, the pose bit must be cleared, and the lev bit must be set. 12 lev level mode reset value = 0 specifies whether external transfer requests are level-senstiive or edge-triggered. this bit is valid for external transfer requests (i.e., when exr=1), and has no effect on internal transfer requests (i.e., when exr=0). in the TMP1941AF, this bit must be set. figure 10.4 channel control registers (ccrn) (1/2)
TMP1941AF 2003-03-27 TMP1941AF-90 bit mnemonic field name description 11 sreq snoop request reset value = 0 controls whether or not to request bus mastership with snooping. if set, the tx19 core processor?s snoop function becomes valid, allowing the dmac to use the processor?s data bus. if cleared, the snoop function is disabled. 1: the snoop function is enabled (i.e., sreq is used as a bus request signal). 0: the snoop function is disabled (i.e., greq is used as a bus request signal). 10 relen bus release request enable reset value = 0 controls whether or not to respond to the bus release request signal from the tx19 core processor. this bit is valid when the dmac uses greq as a bus request signal. this bit has no meaning or effect when the dmac uses sreq as a bus request signal because, in that case, the tx19 core processor does not have the capability to generate a bus release request signal. 1: the dmac will respond to the bus release request signal from the tx19 core processor, if it has control of the bus. the dmac will relinquish the bus when the current dma bus cycle completes. 0: the dmac will ignore the bus release request signal from the tx19 core processor. 9 sio i/o source reset value = 0 specifies the type of the source device. 1: i/o device 0: memory 8:7 sac source address count reset value = 00 selects the manner in which the source address changes after each cycle. 1x: fixed (remains unchanged) 01: decremented 00: incremented 6 dio i/o destination reset value = 0 specifies the type of the destination device. 1: i/o device 0: memory 5:4 dac destination address count reset value = 00 selects the manner in which the destination address changes after each cycle. 1x: fixed (remains unchanged) 01: decremented 00: incremented 3:2 trsiz transfer size reset value = 00 specifies the amount of data to be transferred in response to a dma request. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) 1:0 dps device port size reset value = 00 specifies the port size of a source or destination i/o device. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) figure 10.4 channel control registers (ccrn) (2/2) note 1: the dps field has no meaning or effect on memory-to-memory transfers. note 2: to access on-chip peripherals, the transfer size (trsiz) must be equal to the device port size (dps). note 3: the ccrn register must be programmed before placing the dmac in ready state.
TMP1941AF 2003-03-27 TMP1941AF-91 10.3.3 channel status registers (csrn) 31 30 24 23 22 21 20 19 18 17 16 act 0 nc abc ? bes sed conf 00 r r/w r/w r/w r r r : read/write 0 000000 : reset value 15 32 0 0 ??? r/w : read/write 00 : reset value bit mnemonic field name description 31 act channel active reset value = 0 indicates whether or not the dma channel is in ready state. 1: the dma channel is in ready state. 0: the dma channel is not in ready state. 23 nc normal completion reset value = 0 if set, the dma channel has terminated by normal completion. if the nien bit in the ccrn is set, an interrupt is generated. the nc bit is cleared by writing a 0 to it. clearing the nc bit causes the interrupt to be cleared. the nc bit must be cleared prior to starting the next transfer. an attempt to set the str bit in the ccrn when nc=1 will cause an error. a write of 1 has no effect on this bit. 1: the dma channel has terminated by normal completion. 0: the dma channel has not terminated by normal completion. 22 abc abnormal completion reset value = 0 if set, the dma channel has terminated with an error. if the abien bit in the ccrn is set, an interrupt is generated. the abc bit is cleared by writing a 0 to it. clearing the abc bit causes the interrupt to be cleared. the abc bit must be cleared prior to starting the next transfer. an attempt to set the str bit in the ccrn when abc=1 will cause an error. a write of 1 has no effect on this bit. 1: the dma channel has terminated with an error. 0: the dma channel has not terminated with an error. 21 ? reserved this bit is reserved and must be written as 0. 20 bes source bus error reset value = 0 1: a bus error has occurred during the source read cycle. 0: a bus error has not occurred during the source read cycle. 19 bed destination bus error reset value = 0 1: a bus error has occurred during the destination write cycle. 0: a bus error has not occurred during the destination write cycle. 18 conf configuration error reset value = 0 1: a configuration error is present. 0: no configuration error is present. 2:0 ? reserved these bits are reserved and must be written as 0s. figure 10.5 channel status registers (csrn)
TMP1941AF 2003-03-27 TMP1941AF-92 10.3.4 source address registers (sarn) 31 16 saddr r/w : read/write 0 : reset value 15 0 saddr r/w : read/write ? : reset value bit mnemonic field name description 31:0 saddr source address reset value: ? contains the physical address of the source device. the address changes as programmed in the sac and trsiz fields in the ccrn and the sacm field in the dtcrn. figure 10.6 source address registers (sarn)
TMP1941AF 2003-03-27 TMP1941AF-93 10.3.5 destination address registers (darn) 31 16 daddr r/w : read/write 0 : reset value 15 0 daddr r/w : read/write ? : reset value bit mnemonic field name description 31:0 daddr destination address reset value: ? contains the physical address of the destination device. the address changes as programmed in the dac and trsiz fields in the ccrn and the dacm field in the dtcrn. figure 10.7 destination address registers (darn)
TMP1941AF 2003-03-27 TMP1941AF-94 10.3.6 byte count registers (bcrn) 31 24 23 16 0bc r/w : read/write ? : reset value 15 0 bc r/w : read/write ? : reset value bit mnemonic field name description 23:0 bc byte count reset value: ? contains the number of bytes left to transfer on a dma channel. the count is decremented by 1, 2 or 4 (as determined by the trsiz field in the ccrn register) for each successful transfer. figure 10.8 byte count registers (bcrn)
TMP1941AF 2003-03-27 TMP1941AF-95 10.3.7 dma transfer control registers (dtcrn) 31 16 0 : read/write : reset value 15 6 5 3 2 0 0dacmsacm r/w r/w : read/write 000 000 : reset value bit mnemonic field name description 5:3 dacm destination address count mode selects the manner in which the destination address is incremented or decremented. 000: counting begins with bit 0 of the darn. 001: counting begins with bit 4 of the darn. 010: counting begins with bit 8 of the darn. 011: counting begins with bit 12 of the darn. 100: counting begins with bit 16 of the darn. 101: reserved 110: reserved 111: reserved 2:0 sacm source address count mode selects the manner in which the source address is incremented or decremented. 000: counting begins with bit 0 of the sarn. 001: counting begins with bit 4 of the sarn. 010: counting begins with bit 8 of the sarn. 011: counting begins with bit 12 of the sarn. 100: counting begins with bit 16 of the sarn. 101: reserved 110: reserved 111: reserved figure 10.9 dma transfer control registers (dtcrn)
TMP1941AF 2003-03-27 TMP1941AF-96 10.3.8 data holding register (dhr) 31 16 dot r/w : read/write ? : reset value 15 0 dot r/w : read/write ? : reset value bit mnemonic field name description 31:0 dot data on transfer reset value: ? contains data read from the source address during a dual-address operation. figure 10.10 data holding register (dhr)
TMP1941AF 2003-03-27 TMP1941AF-97 10.4 operation this section describes the operation of the dmac. 10.4.1 overview the dmac is a high-speed 32-bit dma controller used to quickly move large blocks of data between i/o peripherals and memory without intervention of the tx19 core processor. (1) devices supported for the source and destination the dmac handles data transfers from memory to memory and between memory and i/o peripherals. the device from which data is transferred is referred to as a source device, and the device to which data is transferred is referred to as a destination device. both memory and i/o peripherals can be a source or destination device. the dmac supports data transfers from memory to i/o peripherals, from i/o peripherals to memory, and from memory to memory, but not from i/o peripherals to i/o peripherals. dma protocols for memory and i/o peripherals differ in that when accessing an i/o peripheral, the dmac asserts the dackn (n = channel number) signal to indicate that data is being transferred in response to a previous transfer request. because each dma channel has only one dackn signal, the dmac can not handle data transfers between two i/o peripherals. interrupt requests can be programmed to be a trigger to initiate a dma process instead of requesting an interrupt to the tx19 core processor. if so programmed, the interrupt controller (intc) forwards a dma request to the dmac (see 10.4.6, interrupts ). the dma request coming from the intc is cleared when the intc receives a dackn from the dmac. consequently, a dma request for a transfer to/from an i/o peripheral is cleared after each dma bus cycle (i.e., every time the number of bytes programmed into the ccrn.trsiz field is transferred). on the other hand, during memory-to-memory transfer, the dackn signal is not asserted until the byte count register (bcrn) reaches zero. therefore, memory-to-memory transfer can continuously move large blocks of data in response to a single dma request. for example, data transfers between the TMP1941AF on-chip peripheral and on- or off-chip memory is discontinued after every dma bus cycle. nonetheless, until the bcrn register reaches zero, the dmac remains in ready state to wait for the next transfer request. (2) exchanging bus mastership (bus arbitration) in response to a dma request, the dmac issues a bus request to the tx19 core processor. when the dmac receives a bus grant signal from the tx19 core processor, it assumes bus mastership to service the dma request. there are two bus request signals from the dmac going to the tx19 core processor. one is a bus request without snooping (greq), and the other is a bus request with snooping (sreq). the sreq bit in the ccrn register is used to select a bus request signal to use for each dma channel. while the dmac has control of the bus, the tx19 core processor may issue a bus release request to the dmac. the relen bit of the ccrn register controls whether to honor this request on a channel-by-channel basis. this setting has a meaning only when a dma channel uses greq (i.e., a bus request without snooping). it has no meaning or effect when a dma channel uses sreq (i.e., a bus request with snooping) because, in this case, the tx19 core processor does not have the capability to generate a bus release request. the dmac relinquishes the bus to the tx19 core processor when there is no pending dma request to be serviced. note 1: the nmi interrupt is left pending while the dmac has control of the bus. note 2: don?t place the TMP1941AF in halt powerdown mode while the dmac is operating.
TMP1941AF 2003-03-27 TMP1941AF-98 (3) transfer request generation each dma channel supports two types of request generation methods: internal and external. internal requests are those generated within the dmac. the dma channel is started as soon as the str bit in the ccrn register is set. the channel immediately requests the bus and begins transferring data. if a channel is programmed for external request and the str bit is set, the transfer request signal (intdreqn) must be asserted by the interrupt controller before the channel requests the bus and begins a transfer. although intdreqn can be programmed for level/edge sensitivity, the TMP1941AF requires intdreqn to be low-level sensitive. (4) data transfer modes the TMP1941AF dmac supports dual-address transfers, but not single-address transfers. the dual-address mode allows data to be transferred from memory to memory and between memory and an i/o peripheral. in this mode, the dmac explicitly addresses both the source and destination devices. the dmac also generates a dackn signal when accessing an i/o peripheral. in dual-address mode, a transfer takes place in two dma bus cycles: a source read cycle and a destination write cycle. in the source read cycle, the data being transferred is read from the source address and put into the dmac internal data holding register (dhr). in the destination write cycle, the dmac writes data in the dhr to a destination address. (5) dma channel operation the dmac has four independent dma channels 0 to 3. setting the start (str) bit in the ccrn (n = 0 ? 3) enables a particular channel and puts it in ready state. when a dma request is detected in any of the channels in ready state, the dmac arbitrates for the bus and begins a transfer. when no dma request is pending, the dmac relinquishes the bus to the tx19 core processor and returns to ready state. the channel can terminate by normal completion or from an error of a bus cycle. when a channel terminates, that channel is put in idle state. interrupts can be generated by error termination or by normal channel termination. figure 10.11shows a general state transitions of a dma channel. figure 10.11 dma channel state transitions start transfer done idle ready transfer the dmac assumes bus mastership. the dmac gives up bus mastership. the dmac does not have bus mastership. the dmac has bus mastership.
TMP1941AF 2003-03-27 TMP1941AF-99 (6) summary of transfer modes the dmac can perform data transfers as follows according to the combination of mode settings. transfer request edge/level address mode data flow internal ? dual memory-to-memory memory-to-memory memory-to-i/o external low level dual i/o-to-memory (7) address change options address pointers can increment, decrement or remain constant. the sac and dac fields in the ccrn respectively select address change directions for the source address register (sarn) and the destination address register (darn). while memory addresses can be programmed to increment, decrement or remain constant, i/o addresses must be programmed to remain constant. the sacm and dacm fields in the dtcrn provide options to program bit positions at which the source and destination addresses are incremented or decremented after each transfer. the bit position can be bit 0, 4, 8, 12 or 16. use of bit 0 is the regular increment/decrement mode in which the address changes by 1, 2 or 4, according to the source or destination size. two examples of how other increment/decrement modes affect address changes are show below. example 1: when address bit 0 is selected in the sacm field and address bit 4 is selected in the dacm field sac: programmed to increment the source address dac: programmed to increment the destination address trsiz: programmed to a transfer size of 32 bits source address: 0xa000_1000 destination address: 0xb000_0000 sacm: 000 bit 0 is the source address bit at which address incrementation occurs. dacm: 001 bit 4 is the destination address bit at which address incrementation occurs. source destination 1st transfer 0xa000_1000 0xb000_0000 2nd transfer 0xa000_1004 0xb000_0010 3rd transfer 0xa000_1008 0xb000_0020 4th transfer 0xa000_100c 0xb000_0030 ?? example 2: when address bit 8 is selected in the sacm field and address bit 0 is selected in the dacm field sac: programmed to decrement the address dac: programmed to decrement the address trsiz: programmed to a transfer size of 16 bits source address: 0xa000_1000 destination address: 0xb000_0000 sacm: 010 bit 8 is the source address bit at which address decrementation occurs. dacm: 000 bit 0 is the destination address bit at which address decrementation occurs. source destination 1st transfer 0xa000_1000 0xb000_0000 2nd transfer 0x9fff_ff00 0xafff_fffe 3rd transfer 0x9fff_fe00 0xafff_fffc 4th transfer 0x9fff_fd00 0xafff_fffa ??
TMP1941AF 2003-03-27 TMP1941AF-100 10.4.2 transfer request generation a dma request must be issued for the dmac to initiate a data transfer. each dma channel in the dmac supports two types of request generation method: internal and external. in either request generation mode, once a dma channel is started, a dma request causes the dmac to arbitrate for the bus and begin transferring data. ? internal request generation a channel is programmed for internal request by clearing the exr bit in the ccrn. in internal request generation mode, a transfer request is generated as soon as the str bit in the ccrn is set. an internally generated request keeps a transfer request pending until the transfer is complete. if no transition to a higher-priority dma channel or a bus master occurs, the channel will use 100% of the available bus bandwidth to transfer all data continuously. internally generated requests support only memory-to-memory transfer. ? external request generation a channel is programmed for external request by setting the exr bit in the ccrn. in external request generation mode, setting the str bit in the ccrn puts the channel in ready state. while in ready state, assertion of the intdreqn signal (where n is the channel number) coming from the interrupt controller (intc) causes a transfer request to be generated. externally generated requests support data transfers from memory to memory and between memory and an i/o peripheral. intdreqn can be programmed for either edge or level sensitivity through the pose bit in the ccrn. however, in the TMP1941AF, intdreqn is an active-low, level-sensitive signal. therefore, the pose bit must be cleared to 0. the transfer size, i.e., the amount of data to be transferred in response to a transfer request, is programmed in the trsize field in the ccrn. the transfer size can be 32 bits, 16 bits or 8 bits. a transfer request is removed by assertion of the dackn signal (where n is the channel number). dackn is asserted: 1) when an i/o peripheral bus cycle has completed and 2) when the byte count register (bcrn) has reached zero in memory-to-memory transfer. consequently, a memory-to-i/o or i/o-to-memory transfer request terminates after one dma bus cycle completes, whereas memory-to-memory transfer can continuously move large blocks of data in response to a single dma request. the intc might clear intdreqn before the dmac accepts it and begins a data transfer. it must be noted that, even if that happens, a dma bus cycle might be executed after the interrupt request has been cleared.
TMP1941AF 2003-03-27 TMP1941AF-101 10.4.3 dma address modes the TMP1941AF supports only dual-address mode in which both the source and destination devices are explicitly addressed. in dual-address mode, two bus transfers occur: a read from a source device and a write to the destination device. in the source read cycle, data is read from the source address and placed in the dmac internal data holding register (dhr). then, in the destination write cycle, the data held in the dhr is written to the destination address. figure 10.12 dual-address transfer mode the transfer size programmed into the ccrn.trsiz field determines the amount of data that is transferred from a source device to a destination device in response to a dma request. the transfer size can be 32 bits, 16 bits or 8 bits. the internal dhr is a 32-bit register that serves as a buffer for the data being transferred from a source device to a destination device during dual-address mode. memory accesses occur in a manner to fulfill the ccrn.trsiz setting. remember that the cs/wait controller supports either 16-bit or 8-bit bus accesses for external memory. if the dma transfer size is programmed to 32 bits in ccrn.trsiz, dma read and write cycles each take up to four bus cycles to complete. a 16-bit data bus, as programmed in the cs/wait controller, requires two independent bus cycles to complete a 32-bit transfer. likewise, an 8-bit data bus requires four independent bus cycles to complete a 32-bit transfer. memory-to-i/o and i/o-to-memory dma transfers are governed by the setting of the ccrn.dps field in addition to the setting of ccrn.trsiz. the dps field defines the port size of a source or destination i/o peripheral. the i/o port size can be 32 bits, 16 bits or 8 bits. if the transfer size is equal to the i/o port size, an i/o access takes a single read or single write cycle. if the i/o port size is less than the programmed transfer size, the internal 32-bit dhr serves as a buffer for the data being transferred. for example, assume that the transfer size is programmed to 32 bits. if the source i/o port size is 8 bits and the destination memory width is 32 bits, then four 8-bit read cycles occur, followed by a 32-bit write cycle. (if the destination is an external memory with a 16-bit data bus, dmac destination device data data bus address 1. source read address bus source device 2. desti. write 1. source read 2. desti. write
TMP1941AF 2003-03-27 TMP1941AF-102 the write cycle takes two bus cycles.) the 32 bits of data are buffered in the dhr until the destination write cycle occurs. source and destination addresses can be programmed to increment or decrement after each transfer. the sarn and darn change, if so programmed, after each data transfer, depending on the transfer size, i.e., the programmed trsiz value. the brcn is decremented by trsiz for each data transfer. it is forbidden to program the device port size (dps) to a value greater than the dma transfer size (trsiz). the relationships between trsiz and dps are summarized below. table 10.2 dma transfer sizes and device port sizes (in dual-address mode) trsiz dps # of i/o bus cycles 0x (32 bits) 0x (32 bits) 1 0x (32 bits) 10 (16 bits) 2 0x (32 bits) 11 (8 bits) 4 10 (16 bits) 0x (32 bits) don?t use. 10 (16 bits) 10 (16 bits) 1 10 (16 bits) 11 (8 bits) 2 11 (8 bits) 0x (32 bits) don?t use. 11 (8 bits) 10 (16 bits) don?t use. 11 (8 bits) 11 (8 bits) 1 note: the dmac does not incremnt or decrement the address for i/o peripherals. therefore, if, for example, trsiz is programmed to 16 bits and dps is programmed to 8 bits, both the first and second bus cycles access the lower eight bits of the i/o data bus. 10.4.4 dma channel operation each dma channel is started by setting the str bit in the ccrn to 1. once started, the dmac checks the channel setups for configuration errors. if no configuration error is present, the channel enters ready state. when a dma request is detected while in ready state, the dmac arbitrates for the bus and begins transferring data. the channel can terminate by normal completion or from an error. (1) channel startup a dma channel is started by setting the str bit in the ccrn. once started, the dmac checks the channel setups for configuration errors. if a configuration error is detected, the channel terminates abnormally. if no configuration error is present, the channel enters ready state. once a channel enters ready state, the act bit in the csrn is set to 1. if the channel is programmed for internal request, the channel requests the bus and starts transferring data immediately. if the channel is programmed for external request, intdreqn must be asserted before the channel requests the bus. (2) channel termination a dma channel can terminate by normal completion or from an error. the status of a dma operation can be determined by reading the csrn. a channel terminates abnormally when an attempt is made to set the str bit in the ccrn when the nc or abc bit in the csrn is set.
TMP1941AF 2003-03-27 TMP1941AF-103 normal termination a dma channel terminates by normal completion in the following case. normal completion always occurs at the boundary of transfers programmed into the ccrn.trsize field. ? data transfers have terminated, with the bcrn decremented to 0. abnormal termination the paragraphs that follow summarize the cases in which a dma channel terminates from an error. ? configuration errors a configuration error results when the channel initialization contains inconsistencies or errors. a configuration error is reported before any data transfer takes place; therefore, in case of a configuration error, the sarn, darn and bcrn remain unaltered. when a dma channel has terminated from a configuration error, the abc and conf bits in the csrn are set. a configuration error occurs for the following cases: ? both the ccrn.sio and ccrn.dio bits are set. ? the ccrn.str bit is set when the nc or abc bit in the csrn is set. ? the bcrn contains a value that is not an integer multiple of the transfer size programmed into the ccrn.trsiz field. ? the sarn or darn contains a value that is not an integer multiple of the transfer size programmed into the ccrn.trsiz field. ? the ccrn.trsiz and ccrn.dps fields contain illegal combinations. ? the ccrn.str bit is set when the the bcrn contains a value of zero. ? bus errors when a dma channel has terminated from a bus error, the abc bit and the bes or bed bit in the csrn is set. ? a bus error has been reported during a source read or destination write cycle. note: the contents of the bcrn, sarn and darn are not guaranteed when a channel has terminated due to a bus error. chapter 19 lists the reserved addresses that, if accessed, cause a bus error.
TMP1941AF 2003-03-27 TMP1941AF-104 10.4.5 dma channel priority the dmac provides a fixed priority for the four channels, with channel 0 always having the highest priority and channel 3 the lowest. for example, when transfer requests occur on channels 0 and 1 simultaneously, the channel 0 request is serviced first. the channel 1 request is left pending. so that the channel 1 request is serviced, it must be maintained until data transfer completes on channel 0. remember that the internally generated request is kept until the servicing of the request is finished. external transfer requests come from the interrupt controller (intc). the intc can program any interrupts to be used as a dma trigger instead of as an interrupt request. if such an interrupt is programmed for edge sensitivity, the intc internally maintains a transfer request. however, a level- sensitive interrupt is not held in the intc; thus the interrupt request signal must remain asserted until the servicing of the dma request begins. a higher-priority channel always gets the attention of the dmac. if a transfer request occurs on channel 0 while a request on channel 1 is being serviced, the servicing of the channel 1 request is suspended temporarily in order to service the channel 0 request first. after the channel 0 request has been serviced, channel 1 resumes the remaining data transfer. channel transitions take place at the boundary of a transfer size programmed for the current channel being serviced; that is, after all data in the dhr are written to a destination. note: dma channel priority exists only among those using the same type of bus request signal (sreq or greq). 10.4.6 interrupts the dmac can generate an interrupt request (intdman) to the tx19 core processor on completion of a channel operation: either by normal channel termination or by abnormal termination of a bus cycle. ? normal completion interrupt when a channel operation terminates by normal completion, the nc bit in the csrn is set to 1. at this time, if the nien bit in the ccrn is set, an interrupt request is generated to the tx19 core processor. ? abnormal completion interrupt when a channel operation terminates abnormally, the abc bit in the csrn register is set to 1. at this time, if the abien bit in the ccrn register is set, an interrupt request is generated to the tx19 core processor.
TMP1941AF 2003-03-27 TMP1941AF-105 10.4.7 data packing and unpacking in dual-address mode, the internal 32-bit dhr allows the data to be packed and unpacked by the dmac if the programmed transfer size is not equal to the device port size. for example, if a source i/o peripheral is 8-bits wide and a destination memory device is 32-bits wide, four byte-read cycles occur. the four bytes of data are buffered in the dhr before a destination word-write cycle occurs. the following illustrates the byte ordering for packing and unpacking of data. figure 10.13 data packing and unpacking 4n + 0 4n + 1 4n + 2 4n + 3 i/o device 8 d c b a 0 dhr little-endian 31 dcb a 0
TMP1941AF 2003-03-27 TMP1941AF-106 10.5 dma transfer timing all dmac operations are synchronous to the rising edges of the internal system clock. 10.5.1 dual-address mode ? memory-to-memory transfer figure 10.14 shows a dma cycle from one external 16-bit memory to another, with the transfer size programmed to 16 bits. a block of data is transferred until the bcrn register reaches 0. figure 10.14 memory-to-memory transfer (dual-address mode) ? memory-to-i/o transfer figure 10.15 shows a dma cycle from a 16-bit memory to an 8-bit i/o peripheral, with the transfer size programmed to 16 bits. figure 10.15 memory-to-i/o transfer (dual-address mode) a[23:16] 0 cs rd wr ad[15:0] read write addr 1 cs write tsys data addr data addr data addr a[23:16] 0 cs rd wr / hwr ad [15:0] read write data addr data 1 cs tsys
TMP1941AF 2003-03-27 TMP1941AF-107 ? i/o-to-memory transfer figure 10.16 shows a dma cycle from an 8-bit i/o peripheral to a 16-bit memory, with the transfer size programmed to 16 bits. figure 10.16 i/o-to-memory transfer (dual-address mode) addr read read write tsys a[23:16] 0 cs rd wr ad[15:0] 1 cs data addr data addr data
TMP1941AF 2003-03-27 TMP1941AF-108 10.6 programming example the following illustrates the programming required to transfer data from an sio receive buffer (scnbuf) to the on-chip ram. the assumptions are as follows: dmac settings: ? dma channel used: channel 0 ? source address: sc1buf ? destination address: 0xffff_9800 (physical address) ? number of bytes transferred: 256 sio settings: ? data format: 8 bits, uart ? sio channel used: channel 1 ? transfer rate: 9600 bps dma channel 0 is used for the transfer. the sio1 receive interrupt is used as a trigger to start the dma channel. dma channel 0 settings: dcr 0x8000_0000 / * reset dmac * / imcfl 15 7 0 / * bit positions * / xxxx, xxxx, xx10, x100 / * interrupt level = 4 (arbitrary) * / intclr 0x3c / * ivr[9:4]; clear intdma0 * / dtcr0 0x0000_0000 / * dacm = 000 * / / * sacm = 000 * / sar0 0xffff_f208 / * physical address of sc1buf * / dar0 0xffff_9800 / * physical address of destination * / bcr0 0x0000_00ff / * 256 (number of bytes to be transferred) * / ccr0 0x80c0_5b0f (contents) 31 27 23 19 1000000011000000 15 11 7 3 01011x11x0001111 sio channel 1 settings: imcch 31 16 / * bit positions * / xxxx, xxxx, xx11, 1000 / * use intrx1 as a dma trigger and select dma ch. 0 * / intclr 0x32 / * ivr[9:4]; clear intrx1 * / sc1mod0 0x09 / * uart mode, 8-bit data format, baud rate generator * / sc1cr 0x00 br1cr 0x1d / * @fc = 32 mhz (approx. 9615 bps) * / sc1mod0 0x29 / * enable receiver * /
TMP1941AF 2003-03-27 TMP1941AF-109 11. 8-bit timers (tmras) the TMP1941AF has a four-channel 8-bit timer (tmra0?tmra3), which is comprised of two modules named tmra01 and tmra23. the tmra01 contains the tmra0 and the tmra1, and the tmra23 contains the tmra2 and tmra3. each timer module has the following operating modes: ? 8-bit interval timer mode ? 16-bit interval timer mode ? 8-bit programmable pulse generation (ppg) mode (variable frequency, variable duty cycle) ? 8-bit pulse width modulated (pwm) signal generation mode (fixed frequency, variable duty cycle) figure 11.1 and figure 11.2 are block diagrams of the tmra01 and tmra23 respectively. the main components of a timer channel are an 8-bit up-counter, an 8-bit comparator and an 8-bit timer register. two timer channels share a prescalar and a timer flip-flop. a total of six 8-bit registers provide control over the operating modes and timer flip-flops for the tmra01 and the tmra23 each, which can be independently programmed. the tmra01 and the tmra23 are functionally equivalent. in the following sections, any references to the tmra01 also apply to the tmra23. table 11.1 gives the pins and registers for the two timer modules. table 11.1 pins and registers for the tmra01 and the tmra23 tmra01 tmra23 external clock input ta0in (shared with p70) ta2in (shared with p72) external pins timer flip-flop output ta1out (shared with p71) ta3out (shared with p73) timer run register ta01run (0xffff_f100) ta23run (0xffff_f108) timer registers ta0reg (0xffff_f102) ta1reg (0xffff_f103) ta2reg (0xffff_f10a) ta3reg (0xffff_f10b) timer mode register ta01mod (0xffff_f104) ta23mod (0xffff_f10c) registers (addresses) timer flip-flop control register ta1ffcr (0xffff_f105) ta3ffcr (0xffff_f10d)
TMP1941AF 2003-03-27 TMP1941AF-110 11.1 block diagrams figure 11.1 tmra01 block diagram run/clear prescalar clock source: t0 ta0trg external clock input: ta0in ta01mod. pwm[01:00] selector 8-bit up-counter (uc1) 8-bit comparator (cp1) 8-bit up-counter (uc0) 8-bit timer register ta1reg 8-bit comparator (cp0) match detect ta01run. ta0rde ta01run.ta0run t1 t4 t16 2 n ? 1 overflow tmra0 interrupt output: intta0 ta01mod. ta01m[1:0] tmra0 match output: ta0trg selector t1 t16 t256 internal data bus ta01mod. ta0clk[1:0] ta01mod. ta1clk[1:0] match detect tmra1 interrupt output: intta1 ta01run.ta1run timer flip-flop ta1ff ta1ffcr timer flip-flop output: ta1out 512 256 128 64 32 16 8 4 2 t1 t4 t16 t256 prescaler ta01run.ta01prun internal data bus register buffer 0 8-bit timer register ta0reg
TMP1941AF 2003-03-27 TMP1941AF-111 figure 11.2 tmra23 block diagram run/clear prescalar clock source: t0 ta2trg ta23mod. pwm[21:20] selector 8-bit up-counter (uc3) 8-bit comparator (cp3) 8-bit up-counter (uc2) 8-bit timer register ta3reg 8-bit comparator (cp2) match detect ta23run. ta2rde ta23run.ta2run t1 t4 t16 2 n ? 1 overflow tmra2 interrupt output: intta2 ta23mod. ta23m[1:0] tmra2 match output: ta2trg selector t1 t16 t25 internal data bus ta23mod. ta2clk[1:0] ta23mod. ta3clk[1:0] match detect tmra3 interrupt output: intta3 ta23run.ta3run timer flip-flop ta3ff ta3ffcr timer flip-flop output: ta3out 512 256 128 64 32 16 8 4 2 t1 t4 t16 t256 prescaler ta23run.ta23prun internal data bus external clock input: ta2in register buffer 2 8-bit timer register ta2reg
TMP1941AF 2003-03-27 TMP1941AF-112 11.2 timer components 11.2.1 prescaler the tmra01 has a 9-bit prescalar that slows the rate of a clocking source to the counters. the prescalar clock source ( t0 ) can be selected from fperiph, fperiph/2 and fperiph/4 by programming the prck[1:0] field of the syscr0 located within the cg. fperiph can be selected from fgear (geared clock) and fc (non-geared clock) by programming the fpsel bit of the syscr1 located within the cg. the ta01prun bit in the ta01run register allows the enabling and disabling of the prescalar for the tmra01. a write of 1 to this bit starts the prescalar. a write of 0 to this bit clears and halts the prescalar. prescalar output taps can be divide-by-2 ( ?1) , divide-by-8 ( t4), divide-by-32 ( t16) and divide- by-512 ( t256). table 11.2 shows prescalar output clock resolutions (@fc = 32 mhz). table 11.2 prescalar output clock resolutions @fc = 40 mhz prescalar output clock resolution peripheral clock select syscr1. fpsel clock gear value syscr1. gear[1:0] prescaler clock source syscr0. prck[1:0] t1 t4 t16 t256 00 (fperiph/4) fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 11 (51.2 s) 01 (fperiph/2) fc/2 2 (0.1 s) fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 10 (25.6 s) 00 (fc) 10 (fperiph) ? fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 9 (12.8 s) 00 (fperiph/4) fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.4 s) fc/2 12 (102.4 s) 01 (fperiph/2) fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 11 (51.2 s) 01 (fc/2) 10 (fperiph) ? fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 10 (25.6 s) 00 (fperiph/4) fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 9 (12.8 s) fc/2 13 (204.8 s) 01 (fperiph/2) fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.4 s) fc/2 12 (102.4 s) 10 (fc/4) 10 (fperiph) ? fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 11 (51.2 s) 00 (fperiph/4) fc/2 6 (1.6 s) fc/2 8 (6.4 s) fc/2 10 (25.6 s) fc/2 14 (409.6 s) 01 (fperiph/2) fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 9 (12.8 s) fc/2 13 (204.8 s) 0 (fgear) 11 (fc/8) 10 (fperiph) ? fc/2 6 (1.6 s) fc/2 8 (6.4 s) fc/2 12 (102.4 s) 00 (fperiph/4) fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 11 (51.2 s) 01 (fperiph/2) fc/2 2 (0.1 s) fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 10 (25.6 s) 00 (fc) 10 (fperiph) ? fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 9 (12.8 s) 00 (fperiph/4) fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 11 (51.2 s) 01 (fperiph/2) ? fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 10 (25.6 s) 01 (fc/2) 10 (fperiph) ? fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 9 (12.8 s) 00 (fperiph/4) ? fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 11 (51.2 s) 01 (fperiph/2) ? fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 10 (25.6 s) 10 (fc/4) 10 (fperiph) ?? fc/2 5 (0.8 s) fc/2 9 (12.8 s) 00 (fperiph/4) ? fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 11 (51.2 s) 01 (fperiph/2) ?? fc/2 6 (1.6 s) fc/2 10 (25.6 s) 1 (fc) 11 (fc/8) 10 (fperiph) ?? fc/2 5 (0.8 s) fc/2 9 (12.8 s) note 1: the prescaler's output clock tn must be selected so that tn < fsys/2 is satisfied. note 2: do not change the clock gear value while the timer is running. note 3: the ? character means ?don?t use.?
TMP1941AF 2003-03-27 TMP1941AF-113 11.2.2 up-counters (uc0 and uc1) the timer module contains two 8-bit binary up-counters, each of which is driven by a clock independently selected by the ta01mod register. the clock input to the uc0 is either one of three prescalar outputs ( ?1, t4, t16) or the external clock applied to the ta0in pin. which clock is to use is programmed into the ta0clk[1:0] field of the ta01mod register. possible clock sources for the uc1 depend on the selected operating mode. in 16-bit interval timer mode, the clock input to the uc1 is always the uc0 overflow output. in other operating modes, the clock input to the uc1 is either one of three prescalar outputs ( ?1, t16, t256) or the tmra0 comparator match-detect output. the ta0run and ta1run bits in the ta01run register are used to start counting and to stop and clear the counter. upon reset, the up-counter is set to 00h and the whole timer module is disabled. 11.2.3 timer registers (ta0reg and ta1reg) each timer register is an 8-bit register containing a time constant. when the up-counter reaches the time constant value in the timer register, the comparator block generates a match-detect signal. when the time constant is set to 00h, a match occurs upon a counter overflow. one of the two timer registers, ta0reg, is double-buffered. the double-buffering function can be enabled and disabled through the programming of the ta0rde bit in the ta01run: 0=disable, 1=enable. if double-buffering is enabled, the ta0reg latches a new time constant value from the register buffer. this takes place upon detection of a 2 n ?1 overflow in pwm mode and upon a match between the uc0 and the ta1reg in ppg mode. double-buffering must be disabled in interval timer modes. a reset clears the ta01run.ta0rde bit to 0, disabling the double-buffering function. to use this function, the ta01run.ta0rde bit must be set to1 after loading the ta0reg with a time constant. when ta01run.ta0rde=1, the next time constant can be written to the register buffer. figure 11.13 illustrates the double-buffer structure for the ta0reg. figure 11.3 timer register 0 (ta0reg) structure note: the timer register and the corresponding register buffer are mapped to the same address. when ta01run.ta0rde=0, a time constant value is written to both of the timer register and the register buffer; when ta01run.ta0rde=1, a time constant value is written only to the register buffer. ta1reg match in ppg mode selector write shift trigger write to ta0reg 2 n -1 overflow in pwm mode ta01run.ta0rde up-counter comparator (cp0) timer register 0 (ta0reg) register buffer 0 internal data bus y b a s
TMP1941AF 2003-03-27 TMP1941AF-114 the addresses of the timer registers are as follows: ta0reg: 0xffff_f102 ta1reg: 0xffff_f103 ta2reg: 0xffff_f10a ta3reg: 0xffff_f10b the timer registers are write-only registers. 11.2.4 comparators (cp0 and cp1) the comparator compares the output of the 8-bit up-counter with a time constant value in the 8-bit timer register. when a match is detected, an interrupt (intta0/intta1) is generated and the timer flip-flop is toggled, if so enabled. 11.2.5 timer flip-flop (ta1ff) the timer flip-flop (ta1ff) is toggled, if so enabled, each time the comparator match-detect output is asserted. the toggling of the timer flip-flop can be enabled and disabled through the programming of the taff1ie bit in the ta1ffcr. a reset clears the taff1ie bit, disabling the toggling of the ta1ff. the ta1ff can be initialized to 1 or 0 by writing 01 or 10 to the taff1c[1:0] field in the ta1ffcr. additionally, a write of 00 by software causes the ta1ff to be toggled to the opposite value. the value of the ta1ff can be driven onto the ta1out pin, which is multiplexed with p71. the port 7 registers (p7cr and p7fc) must be programmed to configure the p71/ta1out pin as ta1out.
TMP1941AF 2003-03-27 TMP1941AF-115 11.3 register description tmra01 run register 76543210 name ta0rde ??? i2ta01 ta01prun ta1run ta0run read/write r/w ??? r/w reset value 0 ??? 0000 function double buffering 0: disable 1: enable idle 0: off 1: on prescalar run/stop control 0: stop 1: run timer run/stop control 0: stop & clear 1: run i2ta01: timer on/off in idle mode ta01prun: prescaler ta1run: tmra1 ta0run: tmra0 note: bits 4, 5 and 6 are read as undefined. tmra23 run register 76543210 name ta2rde ??? i2ta23 ta23prun ta3run ta2run read/write r/w ??? r/w reset value 0 ??? 0000 function double buffering 0: disable 1: enable idle 0: off 1: on prescalar run/stop control 0: stop 1: run timer run/stop control 0: stop & clear 1: run i2ta23: timer on/off in idle mode ta23prun: prescaler ta3run: tmra3 ta2run: tmra2 note: bits 4, 5 and 6 are read as undefined. figure 11.4 timer run registers ta01run (0xffff_f100) ta23run (0xffff_f108)
TMP1941AF 2003-03-27 TMP1941AF-116 tmra01 mode register 76543210 name ta01m1 ta01m0 pwm01 pwm00 ta1clk1 ta1clk0 ta0clk1 ta0clk0 read/write r/w reset value 00000000 function operating mode 00: 8-bit interval timer 01: 16-bit interval timer 10: 8-bit ppg 11: 8-bit pwm pwm period 00: reserved 01: 2 6 -1 10: 2 7 -1 11: 2 8 -1 tmra1 clock source 00: ta0trg 01: t1 10: t16 11: t256 tmra0 clock source 00: ta0in input 01: t1 10: t4 11: t16 tmra0 clock source 00 external input (ta0in) 01 t1 (prescaler) 10 t4 (prescaler) 11 t16 (prescaler) tmra1 clock source ta01mod.ta01m[1:0] 01 ta01mod.ta01m[1:0] = 01 00 tmra0 match output 01 t1 10 t16 11 t256 tmra0 overflow output 16-bit timer mode period select in 8-bit pwm mode 00 reserved 01 (2 6 -1) clock source 10 (2 7 -1) clock source 11 (2 8 -1) clock source tmra01 operating mode 00 two 8-bit timers 01 16-bit timer 10 8-bit ppg 11 8-bit pwm generation (tmra0) & 8-bit timer (tmra1) figure 11.5 timer mode register ta01mod (0xffff_f104)
TMP1941AF 2003-03-27 TMP1941AF-117 tmra23 mode register 76543210 name ta23m1 ta23m0 pwm21 pwm20 ta3clk1 ta3clk0 ta2clk1 ta2clk0 read/write r/w reset valu00000000 function operating mode 00: 8-bit interval timer 01: 16-bit interval timer 10: 8-bit ppg 11: 8-bit pwm pwm period 00: reserved 01: 2 6 -1 10: 2 7 -1 11: 2 8 -1 tmra3 clock source 00: ta2trg 01: t1 10: t16 11: t256 tmra2 clock source 00: ta2in 01: t1 10: t4 11: t16 tmra2 clock source 00 external input (ta2in) 01 t1 (prescaler) 10 t4 (prescaler) 11 t16 (prescaler) tmra3 clock source ta23mod.ta23m[1:0] 01 ta23mod.ta23m[1:0] = 01 00 tmra2 match output 01 t1 10 t16 11 t256 tmra2 overflow output 16-bit timer mode period select in 8-bit pwm mode 00 reserved 01 (2 6 -1) clock source 10 (2 7 -1) clock source 11 (2 8 -1) clock source tmra23 operating mode 00 two 8-bit timers 01 16-bit timer 10 8-bit ppg 11 8-bit pwm generation (tmra2) & 8-bit timer (tmra3) figure 11.6 timer mode register ta23mod (0xffff_f10c)
TMP1941AF 2003-03-27 TMP1941AF-118 tmra01 timer flip-flop control register 76543210 name ???? taff1c1 taff1c0 taff1ie taff1is read/write ???? r/w reset value ???? 1100 function 00: toggles ta1ff. (software toggle) 01: sets ta1ff to 1. 10: clears ta1ff to 0. 11: don?t-care this field is always read as 11. ta1ff toggle enable 0: disable 1: enable ta1ff toggle trigger 0: tmra0 1: tmra1 selects a signal to toggle timer flip-flop 1 (ta1ff) (don?t-care in other than 8-bit timer mode) 0 toggled by tmra0 1 toggled by tmra1 note: bits 4 to 7 are read as undefined. figure 11.7 tmra01 flip-flop control register ta1ffcr (0xffff_f105)
TMP1941AF 2003-03-27 TMP1941AF-119 tmra23 flip-flop control register 76543210 name ???? taff3c1 taff3c0 taff3ie taff3is read/write ???? r/w reset value ???? 1100 function 00: toggles ta3ff (software toggle). 01: sets ta3ff to 1 10: clears ta3ff to 0 11: don?t care this field is always read as 11. ta3ff toggle enable 0: disable 1: enable ta3ff trigger 0: tmra2 1: tmra3 selects a signal to toggle timer flip-flop 3 (ta3ff) (don?t-care in other than 8-bit timer mode) 0 toggled by tmra2 1 toggled by tmra3 note: bits 4 to 7 are read as undefined values. figure 11.8 tmra23 flip-flop control register ta3ffcr (0xffff_f10d)
TMP1941AF 2003-03-27 TMP1941AF-120 11.4 operating modes 11.4.1 8-bit interval timer mode the tmra0 and the tmra1 can be independently programmed as 8-bit interval timers. programming these timers should only be attempted when the timers are not running. (1) generating periodic interrupts in the following example, the tmra1 is used to accomplish periodic interrupt generation. first, stop the tmra1 (if it is running). then, set the operating mode, clock source and interrupt interval in the ta01mod and ta1reg registers. then, enable the intta1 interrupt and start the tmra1. example: generating the intta1 interrupt at a 20-s interval (fc = 32 mhz) clocking conditions: system clock: high-speed (fc) prescaler clock: fperiph/4 (fperiph = fsys) msb lsb 76543210 ta01run ?? xx ?? 0 ? stops and clears the tmra1. ta01mod 00xx10xx selects 8-bit interval timer mode and t1 as the clock source (which provides a 0.2- s resolution @fc = 40 mhz.) ta1reg 01010000 sets the time constant value in the ta1reg. 20 s t1 = 80 (50h) imc5lh xx110101 enables intta1 and sets the interrupt level to 5. intta1 must always be programmed to be rising-edge triggered. ta01run ? xxx ? 11 ? starts the tmra1. x = don?t care, ? = no change refer to table 11.2 when selecting a timer clock source. note: the clock inputs to the tmra0 and the tmra1 can be one of the following: tmra0: ta0in input, t1, t4 or t16 tmra1: match-detect signal from the tmra0, t1, t16 or t256
TMP1941AF 2003-03-27 TMP1941AF-121 (2) generating a squarewave with a 50% duty cycle the 8-bit interval timer mode can be used to generate square-wave output. this is accomplished by toggling the timer flip-flop (ta1ff) periodically. the ta1ff state can be driven out to the ta1out pin. both the tmra0 and the tmra1 can be used as square-wave generators. the following shows an example using the tmra1. example: generating square-wave output with a 1.2-s period on the ta1out pin (fc = 40 mhz) clocking conditions: system clock: high-speed (fc) high-speed clock gear: ? 1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) msb lsb 76543210 ta01run ? xxx ?? 0 ? stops and clears the tmra1. ta01mod 00xx01 ?? selects 8-bit interval timer mode and t1 as the clock source (which provides a 0.2- s resolution @fc = 40 mhz). ta1reg 00000011 sets the time constant value in the ta1reg. 1.2 s t1 2 = 3 ta1ffcr xxxx1011 clears the ta1ff to 0 and selects the tmra1 match-detect output as a toggle-trigger signal. p7cr ?????? 1 ? p7fc ?????? 1 ? configures p71 as the ta1out output pin. ta01run ? xxx ? 11 ? starts the tmra1. x = don?t care, ? = no change figure 11.9 square-wave generation (50% duty cycle) 0.6 s @fc = 40 mhz comparator output (match detect) bits 7?2 t1 intta1 up-counter clear ta1ff bit 0 bit 1 ta01run.ta1run up- counter comparator timing ta1out 0 111 2 2 2 3 3 3 0 00
TMP1941AF 2003-03-27 TMP1941AF-122 (3) using the tmra0 match-detect output as a trigger for the tmra1 set the tmra01 in 8-bit interval timer mode. select the tmra0 comparator match-detect output (ta0trg) as the clock source for the tmra1. figure 11.10 using the tmra0 match-detect output as a trigger for the tmra1 11.4.2 16-bit interval timer mode the tmra0 and the tmra1 are cascadable to form a 16-bit interval timer. the tmra01 is put in 16-bit interval timer mode by programming the ta01m[1:0] field in the ta01mod register to 01. in 16-bit interval timer mode, the tmra1 is clocked by the counter overflow output from the tmra0. in this mode, the ta1clk[1:0] bits in the ta01mod register are don?t-cares. the clock input to the tmra0 can be selected from an external clock and one of three prescalar outputs (see table 11.2). write the lower eight bits of a time constant value to the ta0reg and the upper eight bits to the ta1reg. programming these registers should only be attempted when the timers are not running. example: generating the intta1 interrupt at a 0.2-second interval (fc = 40 mhz) clocking conditions: system clock: high-speed (fc) high-speed clock gear: ? 1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) under the above conditions, t16 has a period of 3.2 s @ 40 mhz. when t16 is used as the tmra0 clock source, the required time constant value is calculated as follows: 0.2 s 3.2 s = 62500 = h424h thus, the ta1reg is to be set to f4h and the ta0reg to 24h. every time the up-counter uc0 reaches the value in the ta0reg, the tmra0 comparator generates a match-detect output, but the tmra0 continues counting up. a match between the uc0 and the ta0reg does not cause an intta0 interrupt. every time the up-counter uc1 reaches the value in the ta1reg, the tmra1 comparator generates a match-detect output. when the tmra0 and tmra1 match-detect outputs are asserted simultaneously, both the up-counters (uc0 and uc1) are reset to 00h and an interrupt is generated on intta1. also, if so enabled, the timer flip-flop (ta1ff) is toggled. example: ta1reg = 04h and ta0reg = 80h figure 11.11 timer output in 16-bit interval timer mode 3451 1 22 33 45 2 tmra1 up-counter (when ta1reg = 2) tmra0 up-counter (when ta0reg = 5) 1 12 1 tmra0 comparator match output tmra1 match output 0080h 0180h 0280h 0380h 0480h up-counter values (uc1/uc0) toggled match-detect signal from the tmra0 com p arato r intta1 interrupt 0000h ta1out timer output
TMP1941AF 2003-03-27 TMP1941AF-123 11.4.3 8-bit programmable pulse generation (ppg) mode the 8-bit ppg mode can be used to generate a square wave with any frequency and duty cycle, as shown below. the pulse can be high-going and low-going, as determined by the initial setting of the timer flip-flop (ta1ff). this mode is supported by the tmra0, but not by the tmra1. the square- wave output is driven to the ta1out pin (which is multiplexed with p71). figure 11.12 8-bit ppg output waveform in this mode, a square wave is generated by toggling the timer flip-flop (ta1ff). the ta1ff changes state every time a match is detected between the uc0 and the ta0reg and between the uc0 and the ta1reg. the ta0reg must be set to a value less than the ta1reg value. in this mode, the tmra1 up-counter (uc1) can not be independently used; however, the tmra1 must be put in a running state by setting the ta1run bit in the ta01run register to 1. figure 11.3 shows a functional diagram of 8-bit ppg mode. figure 11.13 functional diagram of 8-bit ppg mode selector
TMP1941AF 2003-03-27 TMP1941AF-124 in 8-bit ppg mode, if the double-buffering function is enabled, the ta0reg value can be changed dynamically by writing a new value into the register buffer. upon a match between the ta1reg and the uc0, the ta0reg latches a new value from the register buffer. the ta0reg can be loaded with a new value upon every match, thus making it easy to generate a square wave with virtually any (and variable) duty cycle. figure 11.14 register buffer operation example: generating a 50-khz square wave with a 25% duty cycle (fc = 40 mhz) clocking conditions: system clock: high-speed (fc) high-speed clock gear: ? 1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) the time constant values to be loaded into the ta0reg and ta1reg are determined as follows: a 50-khz waveform has a period of 20 s. under the above clocking conditions, t1 has a 0.2-s resolution (@fc = 40 mhz). when t1 is used as the timer clock source, the ta1reg should be loaded with: 20 s 0.2 s = 100 (64h) with a 25% duty cycle, the high pulse width is calculated as 20 s 1/4 = 5 s. thus, the ta0reg should be loaded with: 5 s 0.2 s = 25 (19h) msb lsb 76543210 ta01run 0xxx ? 000 stops and clears the tmra0. ta01mod 10xxxx01 selects 8-bit ppg mode and t1 as the clock source. ta0reg 00011001 writes 19h. ta1reg 01100100 writes 64h. ta1ffcr xxxx011x sets the ta1ff to 1 and enables toggling. if these bits are set to 10, a low-going pulse is generated. p7cr ?????? 1 ? p7fc ?????? 1 ? configures p71 as the ta1out output pin. ta01run 1xxx ? 111 starts the tmra0 and the tmra1. x = don?t care, ? = no change shift-trigger for register buffer match between ta0reg and up-counter 0 match between ta1reg and up-counte r ta0reg (compare value) register buffer (up-counter = q 1 ) q 1 write to ta0reg (register buffer). (up-counter = q 2 ) q 2 q 2 q 3 20 s
TMP1941AF 2003-03-27 TMP1941AF-125 11.4.4 8-bit pwm generation mode the tmra0 can be used as a pulse-width modulated (pwm) signal generator with up to 8 bits of resolution. this mode is supported by the tmra0, but not by the tmra1. the pwm signal is driven out on the ta1out pin (which is multiplexed with p71). while the tmra01 is in this mode, the tmra1 is usable as an 8-bit interval timer. however, the tmra0 match-detect output can not be used as a clock source for the tmra1, and the timer output is not available for the tmra1. the timer flip-flop toggles when the up-counter (uc0) reaches the ta0reg value and when a 2 n -1 counter overflow occurs, where n is programmable to 6, 7 or 8 through the pwm[01:00] field in the ta01mod register. the uc0 is reset to 00h upon a 2 n -1 overflow. in 8-bit pwm generation mode, the following must be satisfied: (ta0reg value) < (2 n -1 counter overflow value) (ta0reg value) 0 figure11.15 8-bit pwm signal generation figure 11.16 shows a functional diagram of 8-bit pwm generation mode. figure 11.16 functional diagram of 8-bit pwm generation mode ta1out 2 n -1 overflow (intta0 interrupt) t pwm (pwm cycle) match between ta0reg and up-counter 0 ta01mod. pwm[01:00] ta1ffcr. taff1ie internal data bus shift-trigger clear 8-bit up-counter (uc0) ta01run.ta0run selector t1 t4 t16 ta1ff ta1out comparator ta0reg register buffer selector ta01run.ta0rde toggle ta0reg-wr intta0 ta01mod.ta0clk[1:0] overflow 2 n -1 overflow control
TMP1941AF 2003-03-27 TMP1941AF-126 in 8-bit pwm generation mode, if the double-buffering function is enabled, the ta0reg value (i.e., the duty cycle) can be changed dynamically by writing a new value into the register buffer. upon a 2 n -1 counter overflow, the ta0reg latches a new value from the register buffer. the ta0reg can be loaded with a new value upon every counter overflow, thus generating a pwm signal with variable duty cycle. figure11.17 register buffer operation example: generating a pwm signal as shown below on the ta1out pin (fc = 40 mhz) clocking conditions: system clock: high-speed (fc) high-speed clock gear: ? 1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) under the above conditions, t1 has a 0.2-s period (@fc = 40 mhz). 25.4 s 0.2 s = 127 which is equal to 2 7 ? 1. 14 s 0.2 s = 70 = 46h hence, the time constant value to be programmed into the ta0reg is 48h. msb lsb 76543210 ta01run ? xxx ??? 0 stops and clears the tmra0. ta01mod 1110 ?? 01 selects 8-bit pwm mode (period = 2 7 ? 1) and t1 as the clock source. ta0reg 01000110 writes 46h. ta1ffcr xxxx101x clears the ta1ff to 0 and enables toggling. p7cr ?????? 1 ? p7fc ?????? 1 ? configures p71 as the ta1out output pin. ta01run 1xxx ? 1 ? 1 starts the tmra0. x = don?t care, ? = no change q 2 up-counter = q 2 up-counter = q 1 q 1 q 2 q 3 shift into ta0reg match between ta0reg and up-counter 0 2 n -1 overflo w ta0reg (compare value) register buffer write to ta0reg (register buffer) 14 s 25.4 s
TMP1941AF 2003-03-27 TMP1941AF-127 table 11.3 pwm period @fc = 40 mhz pwm period 2 6 ? 12 7 ? 12 8 ? 1 peripheral clock select syscr1. fpsel clock gear value syscr1. gear[1:0] prescaler clock source syscr0. prck[1:0] t1 t4 t16 t1 t4 t16 t1 t4 t16 00 (fperiph/4) 12.6 s 50.4 s 201.6 s 25.4 s 101.6 s 406.4 s 51 s 204 s 816 s 01 (fperiph/2) 6.3 s 25.2 s 100.8 s 12.7 s 50.8 s 203.2 s 25.5 s 102 s 408 s 00 (fc) 10 (fperiph) ? 12.6 s 50.4 s ? 25.4 s 101.6 s ? 51 s 204 s 00 (fperiph/4) 25.2 s 100.8 s 403.2 s 50.8 s 203.2 s 812.8 s 102 s 408 s 1632 s 01 (fperiph/2) 12.6 s 50.4 s 201.6 s 25.4 s 101.6 s 406.4 s 51 s 204 s 816 s 01 (fc/2) 10 (fperiph) ? 25.2 s 100.8 s ? 50.8 s 203.2 s ? 102 s 408 s 00 (fperiph/4) 50.4 s 201.6 s 806.4 s 101.6 s 406.4 s 1626 s 204 s 816 s 3264 s 01 (fperiph/2) 25.2 s 100.8 s 403.2 s 50.8 s 203.2 s 812.8 s 102 s 408 s 1632 s 10 (fc/4) 10 (fperiph) ? 50.4 s 201.6 s ? 101.6 s 406.4 s ? 204 s 816 s 00 (fperiph/4) 100.8 s 403.2 s 1613 s 203.2 s 812.8 s 3251 s 408 s 1632 s 6528 s 01 (fperiph/2) 50.4 s 201.6 s 806.4 s 101.6 s 406.4 s 1626 s 204 s 816 s 3264 s 0 (fgear) 11 (fc/8) 10 (fperiph) ? 100.8 s 403.2 s ? 203.2 s 812.8 s ? 408 s 1632 s 00 (fperiph/4) 12.6 s 50.4 s 201.6 s 25.4 s 101.6 s 406.4 s 51 s 204 s 816 s 01 (fperiph/2) 6.3 s 25.2 s 100.8 s 12.7 s 50.8 s 203.2 s 25.5 s 102 s 408 s 00 (fc) 10 (fperiph) ? 12.6 s 50.4 s ? 25.4 s 101.6 s ? 51 s 204 s 00 (fperiph/4) 12.6 s 50.4 s 201.6 s 25.4 s 101.6 s 406.4 s 51 s 204 s 816 s 01 (fperiph/2) ? 25.2 s 100.8 s ? 50.8 s 203.2 s ? 102 s 408 s 01 (fc/2) 10 (fperiph) ? 12.6 s 50.4 s ? 25.4 s 101.6 s ? 51 s 204 s 00 (fperiph/4) ? 50.4 s 201.6 s ? 101.6 s 406.4 s ? 204 s 816 s 01 (fperiph/2) ? 25.2 s 100.8 s ? 50.8 s 203.2 s ? 102 s 408 s 10 (fc/4) 10 (fperiph) ?? 50.4 s ?? 101.6 s ?? 204 s 00 (fperiph/4) ? 50.4 s 201.6 s ? 101.6 s 406.4 s ? 204 s 816 s 01 (fperiph/2) ?? 100.8 s ?? 203.2 s ?? 408 s 1 (fc) 11 (fc/8) 10 (fperiph) ?? 50.4 s ?? 101.6 s ?? 204 s note 1: the prescaler's output clock tn must be selected so that tn < fsys/2 is satisfied. note 2: do not change the clock gear value while the timer is running. note 3: the ? character means ?don?t use.?
TMP1941AF 2003-03-27 TMP1941AF-128 11.4.5 operating mode summary table 11.4 shows the settings for the tmra01 for each of the operating modes. table 11.4 register settings for each operating mode register ta01mod ta1ffcr field ta01m[1:0] pwm[01:00] ta1clk[1:0] ta0clk[1:0] taff1is function interval timer mode pwm period uc1 clock source uc0 clock source timer flip-flop toggle-trigger 8-bit timer 2ch 00 ? match output from uc0 t1, t16, t256 (00, 01, 10, 11) external clock, t1, t4, t16 (00, 01, 10, 11) 0: uc0 output 1: uc1 output 16-bit timer mode 01 ?? external clock, t1, t4, t16 (00, 01, 10, 11) ? 8-bit ppg 1ch 10 ?? external clock, t1, t4, t16 (00, 01, 10, 11) ? 8-bit pwm 1ch 8-bit timer 1ch (note) 11 2 6 ? 1, 2 7 ? 1, 2 8 ? 1 (01, 10, 11) t1, t16, t256 (01, 10, 11) external clock, t1, t4, t16 (00, 01, 10, 11) pwm output ? = don?t care note: in 8-bit pwm generation mode, the uc1 can be used as an 8-bit timer. however, the match-detect output from the uc0 can not be used as a clock source for the uc1, and the timer output is not avaialble for the uc1.
TMP1941AF 2003-03-27 TMP1941AF-129 12. 16-bit timer/event counters (tmrbs) the TMP1941AF has a 16-bit timer/event counter consisting of four identical channels (tmrb0?tmrb3). each channel has the following three basic operating modes: ? 16-bit interval timer mode ? 16-bit event counter mode ? 16-bit programmable pulse generation (ppg) mode each channel has the capture capability used to latch the value of the counter. the capture capability allows: ? frequency measurement ? pulse-width measurement ? time difference measurement figure 12.1 to figure 12.4 are block diagrams of the tmrb0 to tmrb3. the main components of a tmrbn block are a 16-bit up-counter, two 16-bit timer registers (one of which is double-buffered), two 16-bit capture registers, two comparators, capture control logic, a timer flip-flop and its associated control logic. each channel is independently programmable and functionally equivalent except that the tmrb3 has no external clock/capture trigger inputs. table 12.1 gives the pins and registers for the four channels. in the following sections, any references to the tmrb0 also apply to all the other channels. table 12.1 pins and registers for the four tmrbn channels tmrb0 tmrb1 tmrb2 tmrb3 tb0in0 (shared with p74) tb1in0 (shared with p80) tb2in0 (shared with p83) external clock / capture trigger inputs tb0in1 (shared with p75) tb1in1 (shared with p81) tb2in1 (shared with p84) ? external pins timer flip-flop output tb0out0 (shared with p76) tb1out0 (shared with p82) tb2out (shared with p85) tb3out (shared with p86) timer run register tb0run (0xffff_f180) tb1run (0xffff_f190) tb2run (0xffff_f1a0) tb3run (0xffff_f1b0) timer mode register tb0mod (0xffff_f182) tb1mod (0xffff_f192) tb2mod (0xffff_f1a2) tb3mod (0xffff_f1b2h timer flip-flop control register tb0ffcr (0xffff_f183) tb1ffcr (0xffff_f193) tb2ffcr (0xffff_f1a3) tb3ffcr (0xffff_f1b3) tb0rg0l (0xffff_f188) tb1rg0l (0xffff_f198) tb2rg0l (0xffff_f1a8) tb3rg0l (0xffff_f1b8) tb0rg0h (0xffff_f189) tb1rg0h (0xffff_f199) tb2rg0h (0xffff_f1a9) tb3rg0h (0xffff_f1b9) tb0rg1l (0xffff_f18a) tb1rg1l (0xffff_f19a) tb2rg1l (0xffff_f1aa) tb3rg1l (0xffff_f1ba) timer registers tb0rg1h (0xffff_f18b) tb1rg1h (0xffff_f19b) tb2rg1h (0xffff_f1ab) tb3rg1h (0xffff_f1bb) tb0cp0l (0xffff_f18c) tb1cp0l (0xffff_f19c) tb2cp0l (0xffff_f1ac) tb3cp0l (0xffff_f1bc) tb0cp0h (0xffff_f18d) tb1cp0h (0xffff_f19d) tb2cp0h (0xffff_f1ad) tb3cp0h (0xffff_f1bd) tb0cp1l (0xffff_f18e) tb1cp1l (0xffff_f19e) tb2cp1l (0xffff_f1ae) tb3cpil (0xffff_fibe) registers (addresses) capture registers tb0cp1h (0xffff_f18f) tb1cp1h (0xffff_f19f) tb2cp1h (0xffff_f1af) tb3cpih (0xffff_fibf)
TMP1941AF 2003-03-27 TMP1941AF-130 12.1 block diagrams figure 12.1 tmrb0 block diagram internal data bus internal data bus run/ clear match detect 16-bit comparator (cp0) 16-bit timer register tb0rg0h/l 16-bit comparator (cp1) register buffer 0 16-bit timer register tb0rg1h/l match detect counter clock tb0mod.tb0clk[1:0] tb0run. tb0rde selector tb0mod. tb0cpm[1:0] prescaler clock source: t0 ta1out tb0in0 tb0in1 t1 t4 t16 tb0run.tb0run tb0mod.tb0cle (from tmra01) capture register 0 tb0cp0h/l tb0mod. tb0cp0 capture register 1 tb0cp1h/l 32 16 8 4 2 t1 t4 t16 tb0run. tb0prun internal data bus internal data bus tb0ff0 timer flip-flop tb0out overflow interrupt inttbof0 timer flip- flop output register 0 inttb00 register 1 inttb01 interrupt output capture & external interrupt control timer flip- flop control 16-bit up-counter (uc0)
TMP1941AF 2003-03-27 TMP1941AF-131 figure 12.2 tmrb1 block diagram internal data bus run/ clear match detect 16-bit comparator (cp0) 16-bit timer register tb1rg0h/l 16-bit up-counter (uc1) 16-bit comparator (cp1) register buffer 0 16-bit timer register tb1rg1h/l match detect coun t clock tb1mod.tb1clk[1:0] tb1run. tb1rde selector tb1mod. tb1cpm[1:0] prescalar clock source: t0 ta1out tb1in0 tb1in1 t1 t4 t16 tb1run.tb1run tb1mod.tb1cle (from tmra01) capture register 0 tb1cp0h/l tb1mod. tb1cp0 capture register 1 tb1cp1h/l 32 16 8 4 2 t1 t4 t16 tb1run. tb1prun internal data bus internal data bus tb1ff0 timer flip-flop tb1out overflow interrupt inttbof1 timer flip- flop output register 0 inttb10 register 1 inttb11 interrupt output capture & external interrupt control timer flip- flop control internal data bus
TMP1941AF 2003-03-27 TMP1941AF-132 figure 12.3 tmrb2 block diagram run/ clear match detect 16-bit comparator (cp0) 16-bit timer register tb2rg0h/l 16-bit comparator (cp1) register buffer 0 16-bit timer register tb2rg1h/l match detect count clock tb2mod.tb2clk[1:0] tb2run. tb2rde selector tb2mod. tb2cpm [ 1:0 ] prescalar clock source: t0 ta1out tb2in0 tb2in1 t1 t4 t16 tb2run.tb2run tb2mod.tb2cle (from tmra01) capture register 0 tb2cp0h/l tb2mod. tb2cp0 capture register 1 tb2cp1h/l 32 16 8 4 2 t1 t4 t16 tb2run. tb2prun internal data bus internal data bus tb2ff0 timer flip-flop tb2out overflow interrupt inttbof2 timer flip- flop output register 0 inttb20 register 1 inttb21 interrupt output capture & external interrupt control timer flip- flop control 16-bit up-counter (uc2) internal data bus internal data bus
TMP1941AF 2003-03-27 TMP1941AF-133 figure 12.4 tmrb3 block diagram internal data bus internal data bus run/ clear match detect 16-bit comparator (cp0) 16-bit timer register tb3rg0h/l 16-bit comparator (cp1) register buffer 0 16-bit timer register tb3rg1h/l match detect count clock tb3mod.tb3clk[1:0] tb3run. tb3rde selector tb3mod. tb3cpm [ 1:0 ] prescalar clock source: t0 ta1out t1 t4 t16 tb3run.tb3run tb3mod.tb3cle (from tmra01) capture register 0 tb3cp0h/l tb3mod. tb3cp0 capture register 1 tb3cp1h/l 32 16 8 4 2 t1 t4 t16 tb3run. tb3prun internal data bus internal data bus tb3ff0 timer flip-flop tb3out overflow interrupt inttbof3 timer flip- flop output register 0 inttb30 register 1 inttb31 interrupt output capture & external interrupt control timer flip- flop control 16-bit up-counter (uc3)
TMP1941AF 2003-03-27 TMP1941AF-134 12.2 timer components 12.2.1 prescaler the tmrb0 has a 5-bit prescalar that slows the rate of a clocking source to the counter. the prescalar clock source ( t0) can be selected from fperiph, fperiph/2 and fperiph/4 by programming the prck[1:0] field of the syscr0 located within the cg. fperiph can be selected from fgear (geared clock) and fc (non-geared clock) by programming the fpsel bit of the syscr1 located within the cg. the tb0run bit in the tb0run register allows the enabling and disabling of the tmrb0 prescalar. a write of 1 to this bit starts the prescalar. a write of 0 to this bit clears and halts the prescalar. prescalar output taps can be divide-by-2 ( t1), divide-by-8 ( t4) and divide-by-32 ( t16). table 12.2 shows prescalar output clock resolutions (@fc = 32 mhz). table 12.2 prescaler output clock resolutions @fc = 40 mhz prescaler output clock resolution peripheral clock select syscr1.fpsel clock gear value syscr1.gear[1:0] prescaler clock source syscr0.prck[1:0] t1 t4 t16 00 (fperiph/4) fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 7 (3.2 s) 01 (fperiph/2) fc/2 2 (0.1 s) fc/2 4 (0.4 s) fc/2 6 (1.6 s) 00 (fc) 10 (fperiph) ? fc/2 3 (0.2 s) fc/2 5 (0.8 s) 00 (fperiph/4) fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.4 s) 01 (fperiph/2) fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 7 (3.2 s) 01 (fc/2) 10 (fperiph) ? fc/2 4 (0.4 s) fc/2 6 (1.6 s) 00 (fperiph/4) fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 9 (12.8 s) 01 (fperiph/2) fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.4 s) 10 (fc/4) 10 (fperiph) ? fc/2 5 (0.8 s) fc/2 7 (3.2 s) 00 (fperiph/4) fc/2 6 (1.6 s) fc/2 8 (6.4 s) fc/2 10 (25.6 s) 01 (fperiph/2) fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 9 (12.8 s) 0 (gear) 11 (fc/8) 10 (fperiph) ? fc/2 6 (1.6 s) fc/2 8 (6.4 s) 00 (fperiph/4) fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 7 (3.2 s) 01 (fperiph/2) fc/2 2 (0.1 s) fc/2 4 (0.4 s) fc/2 6 (1.6 s) 00 (fc) 10 (fperiph) ? fc/2 3 (0.2 s) fc/2 5 (0.8 s) 00 (fperiph/4) fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 7 (3.2 s) 01 (fperiph/2) ? fc/2 4 (0.4 s) fc/2 6 (1.6 s) 01 (fc/2) 10 (fperiph) ? fc/2 3 (0.2 s) fc/2 5 (0.8 s) 00 (fperiph/4) ? fc/2 5 (0.8 s) fc/2 7 (3.2 s) 01 (fperiph/2) ? fc/2 4 (0.4 s) fc/2 6 (1.6 s) 10 (fc/4) 10 (fperiph) ?? fc/2 5 (0.8 s) 00 (fperiph/4) ? fc/2 5 (0.8 s) fc/2 7 (3.2 s) 01 (fperiph/2) ?? fc/2 6 (1.6 s) 1 (fc) 11 (fc/8) 10 (fperiph) ?? fc/2 5 (0.8 s) note 1: the prescaler's output clock tn must be selected so that the relationship tn < fsys/2 is satisfied. note 2: do not change the clock gear value while the timer is running. note 3: the ? character means ?don?t use.?
TMP1941AF 2003-03-27 TMP1941AF-135 12.2.2 up-counter (uc0) the tmrb0 contains a 16-bit binary up-counter, which is driven by a clock selected by the tb0clk[1:0] field in the tb0mod register. the clock input to the uc0 is either one of three prescalar outputs ( ?1, t4, t16) or the external clock applied to the tb0in0 pin. the clock input can be selected through the programming of the tb0clk[1:0] field in the tb0mod register. the tb0run bit in the tb0run register is used to start the uc0 and to stop and clear the uc0. the uc0 is cleared to 0000h, if so enabled, when it reaches the value in the tb0rg1h/l register. the tb0cle bit in the tb0mod register allows the user to enable and disable this clearing. if it is disabled, the uc0 acts as a free-running counter. an overflow interrupt (inttbof0) is generated upon a counter overflow. note: programming the tb0clk[1:0] and tb0cle bits in the tb0mod register should only be attempted when the timer is not running. 12.2.3 timer registers (tb0rg0h/l and tb0rg1h/l) each timer channel has two 16-bit timer registers containing a time constant. when the up-counter reaches the time constant value in each timer register, the associated comparator block generates a match-detect signal. each of the timer registers (tb0rg0h/l, tb0rg1h/l) can be written with either a halfword-store instruction or a series of two byte-store instructions. when byte-store instructions are used, the low- order byte must be stored first, followed by the high-order byte. the 16-bit timer registers are often simply referred to as tb0rg0 and tb0rg1 without the h and l suffix. one of the two timer registers, tb0rg0, is double-buffered. the double-buffering function can be enabled and disabled through the programming of the tb0rde bit in the tb0run: 0=disable, 1=enable. if double-buffering is enabled, the tb0rg0 latches a new time constant value from the register buffer. this takes place when a match is detected between the uc0 and the tb0rg1. upon reset, the contents of the tb0rg0 and tb0rg1 are undefined; thus, they must be loaded with valid values before the timer can be used. a reset clears the tb0run.tb0rde bit to 0, disabling the double-buffering function. to use this function, the tb0run.tb0rde bit must be set to 1 after loading the tb0rg0 and tb0rg1 with time constants. when tb0run.tb0rde=1, the next time constant can be written to the register buffer. note 1: the tb0rg0 and the corresponding register buffer are mapped to the same address (0xffff_f188 thru 0xffff_f189). when tb0run.tb0rde=0, a time constant value is written to both the tb0rg0 and the register buffer; when tb0run.tb0rde=1, a time constant value is written only to the register buffer. therefore, the double-buffering function should be disabled when writing an initial time constant to the timer register. note 2: programming the tb0rde bit should only be attempted when the timer is not running. the following diagram shows the addresses of each timer register.
TMP1941AF 2003-03-27 TMP1941AF-136 12.2.4 capture registers (tb0cp0h/l and tb0cp1h/l) the capture registers are 16-bit registers used to latch the value of the up-counter (uc0). each of the capture registers can be read with either a halfword-load instruction or a series of two byte-load instructions. when byte-load instructions are used, the low-order byte must be read first, followed by the high-order byte. the 16-bit capture registers are often simply referred to as tbncp and tbncp1 without the h and l suffix. the following diagram shows the addresses of each capture register. 8 high-order bits 8 low-order bits tb0rg0 0xffff_f189 0xffff_f188 8 high-order bits 8 low-order bits tb0rg1 0xffff_f18b 0xffff_f18a tmrb0 the timer registers are write-only registers and cannot be read. 8 high-order bits 8 low-order bits tb1rg0 0xffff_f199 0xffff_f198 8 high-order bits 8 low-order bits tb1rg1 0xffff_f19b 0xffff_f19a tmrb1 8 high-order bits 8 low-order bits tb2rg0 0xffff_f1a9 0xffff_f1a8 8 high-order bits 8 low-order bits tb2rg1 0xffff_f1ab 0xffff_f1aa tmrb2 8 high-order bits 8 low-order bits tb3rg0 0xffff_f1b9 0xffff_f1b8 8 high-order bits 8 low-order bits tb3rg1 0xffff_f1bb 0xffff_f1ba tmrb3
TMP1941AF 2003-03-27 TMP1941AF-137 12.2.5 capture control logic the capture control logic controls the capture of an up-counter (uc0) value into the capture registers (tb0cp0 and tb0cp1). the tb0cpm[1:0] field in the tb0mod register selects a capture trigger input to be sensed by the capture control logic. futhermore, a counter value can be captured under software control; a write of 0 to the tb0mod.tb0cp0 bit causes the current uc0 value to be latched into the tb0cp0. to use the capture capability, the prescalar must be running (i.e., tb0run.tb0prun=1). note 1: reading the eight low-order bits of a capture register disables the capture capability. reading the eight high-order bits thereafter re-enables the capture capability. the reading of a whole capture register should be completed during an interval between active transitions on the defined capture trigger input. note 2: don?t stop the timer after only reading the eight low-order bits of a capture register. if this is done, the capture capability continues to remain in the disabled state even after the timer is restarted. note 3: when the tb0in0 pin is selected as a capture trigger input, it can not function as a timer clock source. 8 high-order bits 8 low-order bits tb0cp0 0xffff_f18d 0xffff_f18c 8 high-order bits 8 low-order bits tb0cp1 0xffff_f18f 0xffff_f18e tmrb0 the capture registers are read-only registers and cannot be written by software. 8 high-order bits 8 low-order bits tb1cp0 0xffff_f19d 0xffff_f19c 8 high-order bits 8 low-order bits tb1cp1 0xffff_f19f 0xffff_f19e tmrb1 8 high-order bits 8 low-order bits tb2cp0 0xffff_f1ad 0xffff_f1ac 8 high-order bits 8 low-order bits tb2cp1 0xffff_f1af 0xffff_f1ae tmrb2 8 high-order bits 8 low-order bits tb3cp0 0xffff_f1bd 0xffff_f1bc 8 high-order bits 8 low-order bits tb3cp1 0xffff_f1bf 0xffff_f1be tmrb3
TMP1941AF 2003-03-27 TMP1941AF-138 12.2.6 comparators (cp0 and cp1) the tmrb0 contains two 16-bit comparators. the cp0 block compares the output of the up-counter (uc0) with a time constant value in the tb0rg0. the cp1 block compares the output of the uc0 with a time constant value in the tb0rg1. when a match is detected, an interrupt (inttb00/inttb01) is generated. 12.2.7 timer flip-flop (tb0ff0) the timer flip-flop (tb0ff0) is toggled, if so enabled, upon assertion of match-detect signals from the comparators and latch signals from the capture control logic. the toggling of the tb0ff0 can be enabled and disabled through the programming of the tb0c1t1, tb0c0t1, tb0e1t1 and tb0e0t1 bits in the tb0ffcr register. upon reset, the tb0ff0 assumes an undefined state. the tb0ff0 can be initialized to 1 or 0 by writing 01 or 10 to the tb0ff0c[1:0] field in the tb0ffcr. a write of 01 to this field sets the tb0ff0; a write of 10 to this field clears the tb0ff0. additionally, a write of 00 causes the tb0ff0 to be toggled to the opposite value. the value of the tb0ff0 can be driven onto the tb0out pin, which is multiplxed with p76. the port 7 registers (p7cr and p7fc) must be programmed to configure the p76/tb0out pin as tb0out. note: programming the tb0ff0c[1:0] field should only be attempted when the timer is not running.
TMP1941AF 2003-03-27 TMP1941AF-139 12.3 register description tmrb0 run register 76543210 name tb0rde ??? i2tb0 tb0prun ? tb0run read/write r/w r/w ?? r/w r/w ? r/w reset value 0 0 ?? 00 ? 0 function double buffering 0: disable 1: enable must be written as 0. idle 0: off 1: on prescalar run/stop control 0: stop 1: run run/stop control 0: stop & clear 1: run i2tb0: timer on/off in idle mode tb0prun: prescaler tb0run: tmrb0 note: bits 1, 4 and 5 are read as undefined. tmrb1 run register 76543210 name tb1rde ??? i2tb1 tb1prun ? tb1run read/write r/w r/w ?? r/w r/w ? r/w reset value 0 0 ?? 00 ? 0 function double buffering 0: disable 1: enable must be written as 0. idle 0: off 1: on prescalar run/stop control 0: stop 1: run run/stop control 0: stop & clear 1: run i2tb1: timer on/off in idle mode tb1prun: prescaler tb1run: tmbr1 note: bits 1, 4 and 5 are read as undefined. figure 12.5 timer run registers tb0run (0xffff_f180) tb1run (0xffff_f190)
TMP1941AF 2003-03-27 TMP1941AF-140 tmrb2 run register 76543210 name tb2rde ??? i2tb2 tb2prun ? tb2run read/write r/w r/w ?? r/w r/w ? r/w reset value 0 0 ?? 00 ? 0 function double buffering 0: disable 1: enable must be written as 0. idle 0: off 1: on prescalar run/stop control 0: stop 1: run run/stop control 0: stop & clear 1: run i2tb2: timer on/off in idle mode tb2prun: prescaler tb2run: tmrb2 note: bits 1, 4 and 5 are read as undefined. tmrb3 run register 76543210 name tb3rde ??? i2tb3 tb3prun ? tb3run read/write r/w r/w ?? r/w r/w ? r/w reset value 0 0 ?? 00 ? 0 function double buffering 0: disable 1: enable must be written as 0. idle 0: off 1: on prescalar run/stop control 0: stop 1: run run/stop control 0: stop & clear 1: run i2tb3: timer on/off in idle mode tb3prun: prescaler tb3run: tmrb3 note: bits 1, 4 and 5 are read as undefined. figure 12.6 timer run registers tb2run (0xffff_f1a0) tb3run (0xffff_f1b0)
TMP1941AF 2003-03-27 TMP1941AF-141 tmrb0 mode register 76543210 name ?? tb0cp0 tb0cpm1 tb0cpm0 tb0cle tb0clk1 tb0clk0 read/write r/w w * r/w reset value00100000 function must be written as 00. software capture 0: capture 1: don?t care capture triggers 00: disabled 01: tb0in0 tb0in1 10: tb0in0 tb0in0 11: ta1out ta1out uc0 clear control 0: disable 1: enable tmrb0 clock source 00: tb0in0 input 01: t1 10: t4 11: t16 up-counter (uc0) clear control 0 disabled 1 uc0 is reset upon a match with tb0rg1. capture triggers 00 capture disabled 01 latches uc0 value into tb0cp0 at rising edges of tb0in0 latches uc0 value into tb0cp1 at rising edges of tb0in1. 10 latches uc0 value into tb0cp0 at rising edges of tb0in0. latches uc0 value into tb0cp1 at falling edges of tb0in0. 11 latches uc0 value into tb0cp0 at rising edges of ta1out. latches uc0 value into tb0cp1 at falling edges of ta1out. software capture 0 latches uc0 value into tb0cp0. 1 don?t care figure 12.7 tmrb0 mode register tb0mod (0xffff_f182)
TMP1941AF 2003-03-27 TMP1941AF-142 tmrb1 mode register 76543210 name ?? tb1cp0 tb1cpm1 tb1cpm0 tb1cle tb1clk1 tb1clk0 read/write r/w w * r/w reset value00100000 function must be written as 00. software capture 0: capture 1: don?t care capture triggers 00: disabled 01: tb1in0 tb1in1 10: tb1in0 tb1in0 11: ta1out ta1out uc1 clear control 0: disable 1: enable tmrb1 clock source 00: tb1in0 input 01: t1 10: t4 11: t16 up-counter (uc1) clear control 0 disabled 1 uc1 is reset upon a match with tb1rg1. capture triggers 00 capture disabled 01 latches uc1 value into tb1cp0 at rising edges of tb1in0 latches uc1 value into tb1cp1 at rising edges of tb1in1. 10 latches uc1 value into tb1cp0 at rising edges of tb1in0. latches uc1 value into tb1cp1 at falling edges of tb1in0. 11 latches uc1 value into tb1cp0 at rising edges of ta1out. latches uc1 value into tb1cp1 at falling edges of ta1out. software capture 0 latches uc1 value into tb1cp0. 1 don?t care figure 12.8 tmrb1 mode register tb1mod (0xffff_f192)
TMP1941AF 2003-03-27 TMP1941AF-143 tmrb2 mode register 76543210 name ?? tb2cp0 tb2cpm1 tb2cpm0 tb2cle tb2clk1 tb2clk0 read/write r/w w * r/w reset value00100000 function must be written as 00. software capture 0: capture 1: don?t care capture triggers 00: disabled 01: tb2in0 tb2in1 10: tb2in0 tb2in0 11: ta1out ta1out uc2 clear control 0: disable 1: enable tmrb2 clock source 00: tb2in0 input 01: t1 10: t4 11: t16 up-counter (uc2) clear control 0 disabled 1 uc2is reset upon a match with tb2rg1. capture triggers capture triggers 00 capture disabled 01 latches uc2 value into tb2cp0 at rising edges of tb2in0. latches uc2 value into tb2cp1 at rising edges of tb2in1. 10 latches uc2 value into tb2cp0 at rising edges of tb2in0. latches uc2 value into tb2cp1 at falling edges of tb2in0. 11 latches uc2 value into tb2cp0 at rising edges of ta1out. latches uc2 value into tb2cp1 at falling edges of ta1out. software capture 0 latches uc2 value into tb2cp0. 1 don?t care figure 12.9 tmrb2 mode register tb2mod (0xffff_f1a2)
TMP1941AF 2003-03-27 TMP1941AF-144 tmrb3 mode register 76543210 name ?? tb3cp0 tb3cpm1 tb3cpm0 tb3cle tb3clk1 tb3clk0 read/write r/w w * r/w reset value00100000 function must be written as 00. software capture 0: capture 1: don?t care capture triggers 00: disabled 01: disabled 10: disabled 11: ta1out ta1out uc3 clear control 0: disable 1: enable tmrb3 clock source 00: tb3in0 input 01: t1 10: t4 11: t16 up-counter (uc3) clear control 0 disabled 1 uc3 is reset upon a match with tb3rg1. capture triggers 00 capture disabled 01 capture disabled 10 capture disabled 11 latches uc3 value into tb3cp0 at rising edges of ta1out. latches uc3 value into tb3cp1 at falling edges of ta1out. software capture 0 latches uc3 value into tb3cp0. 1 don?t care figure 12.10 tmrb3 mode register tb3mod (0xffff_f1b2)
TMP1941AF 2003-03-27 TMP1941AF-145 tmrb0 timer flip-flop control register 76543210 name ?? tb0c1t1 tb0c0t1 tb0e1t1 tb0e0t1 tb0ff0c1 tb0ff0c0 read/write w * r/w w * reset value11000011 tb0ff0 toggle-trigger 0: trigger disabled 1: trigger enabled function must be written as 11. * this field is always read as 11. uc0 tb0cp1 uc0 tb0cp0 uc0 = tb0rg1 uc0 = tb0rg0 tb0ff0 control 00: toggle 01: set 10: clear 11: don?t care * this field is always read as 11. timer flip-flop (tb0ff0) control 00 toggles tb0ff0. (software toggle) 01 sets tb0ff0 to 1. 10 clears tb0ff0 to 0. 11 don?t care (read as 11) when uc0 reaches tb0rg0 value. 0 toggle-trigger disabled 1 toggle-trigger enabled when uc0 reaches tb0rg1 value. 0 toggle-trigger disabled 1 toggle-trigger enabled when uc0 value is latched into tb0cp0 (see note). 0 toggle-trigger disabled 1 toggle-trigger enabled when uc0 value is latched into tb0cp1. 0 toggle-trigger disabled 1 toggle-trigger enabled note: capturing the counter value into tb0cp0 via a software capture also generates a toggle-trigger to tb0ff0. figure 12.11 tmrb0 timer flip-flop control register tb0ffcr (0xffff_f183)
TMP1941AF 2003-03-27 TMP1941AF-146 tmrb1 timer flip-flop control register 76543210 name ?? tb1c1t1 tb1c0t1 tb1e1t1 tb1e0t1 tb1ff0c1 tb1ff0c0 read/write w * r/w w * reset value11000011 tb1ff0 toggle-trigger 0: trigger disabled 1: trigger enabled function must be written as 11. * this field is always read as 11. uc1 tb1cp1 uc1 tb1cp0 uc1 = tb1rg1 uc1 = tb1rg0 tb1ff0 control 00: toggle 01: set 10: clear 11: don?t care * this field is always read as 11. timer flip-flop (tb1ff0) control 00 toggles tb1ff0. (software toggle) 01 set tb1ff0 to 1. 10 clears tb1ff0 to 0. 11 don?t care (read as 11) when uc1 reaches tb1rg0 value. 0 toggle-trigger disabled 1 toggle-trigger enabled when uc1 reaches tb1rg1 value. 0 toggle-trigger disabled 1 toggle-trigger enabled when uc1 value is latched into tb1cp0 (see note). 0 toggle-trigger disabled 1 toggle-trigger enabled when uc1 value is latched into tb1cp1. 0 toggle-trigger disabled 1 toggle-trigger enabled note: capturing the counter value into tb1cp0 via a software capture also generates a toggle-trigger to tb1ff0. figure 12.12 tmrb1 timer flip-flop control register tb1ffcr (0xffff_f193)
TMP1941AF 2003-03-27 TMP1941AF-147 tmrb2 timer flip-flop control register 76543210 name ?? tb2c1t1 tb2c0t1 tb2e1t1 tb2e0t1 tb2ff0c1 tb2ff0c0 read/write w * r/w w * reset value11000011 tb2ff0 toggle-trigger 0: trigger disabled 1: trigger enabled function must be written as 11. * this field is always read as 11. uc2 tb2cp1 uc2 tb2cp0 uc2 = tb2rg1 uc2 = tb2rg0 tb2ff0 control 00: toggle 01: set 10: clear 11: don?t care * this field is always read as 11. timer flip-flop (tb2ff0) control 00 toggles tb2ff0. (software toggle) 01 set tb2ff0 to 1. 10 clears tb2ff0 to 0. 11 don?t care (read as 11) when uc2 reaches tb2rg0 value. 0 toggle-trigger disabled 1 toggle-trigger enabled when uc2 reaches tb2rg1 value. 0 toggle-trigger disabled 1 toggle-trigger enabled when uc2 value is latched into tb2cp0 (see note). 0 toggle-trigger disabled 1 toggle-trigger enabled when uc2 value is latched into tb2cp1. 0 toggle-trigger disabled 1 toggle-trigger enabled note: capturing the counter value into tb2cp0 via a software capture also generates a toggle-trigger to tb2ff0. figure 12.13 tmrb2 timer flip-flop control register tb2ffcr (0xffff_f193)
TMP1941AF 2003-03-27 TMP1941AF-148 tmrb3 timer flip-flop control register 76543210 name ?? tb3c1t1 tb3c0t1 tb3e1t1 tb3e0t1 tb3ff0c1 tb3ff0c0 read/write w * r/w w * reset value11000011 tb3ff0 toggle-trigger 0: trigger disabled 1: trigger enabled function must be written as 11. * this field is always read as 11. uc3 tb3cp1 uc3 tb3cp0 uc3 = tb3rg1 uc3 = tb3rg0 tb3ff0 control 00: toggle 01: set 10: clear 11: don?t care * this field is always read as 11. timer flip-flop (tb3ff0) control 00 toggles tb3ff0. (software toggle) 01 set tb3ff0 to 1. 10 clears tb3ff0 to 0. 11 don?t care (read as 11) when uc3 reaches tb3rg0 value. 0 toggle-trigger disabled 1 toggle-trigger enabled when uc3 reaches tb3rg1 value. 0 toggle-trigger disabled 1 toggle-trigger enabled when uc3 value is latched into tb3cp0 (see note). 0 toggle-trigger disabled 1 toggle-trigger enabled when uc3 value is latched into tb3cp1. 0 toggle-trigger disabled 1 toggle-trigger enabled note: capturing the counter value into tb3cp0 via a software capture also generates a toggle-trigger to tb3ff0. figure 12.14 tmrb3 timer flip-flop control register tb3ffcr (0xffff_f1b3)
TMP1941AF 2003-03-27 TMP1941AF-149 12.4 operating modes 12.4.1 16-bit interval timer mode in the following example, the tmrb0 is used to accomplish periodic interrupt generation. the interval time is set in timer register 1 (tb0rg1), and the inttb01 interrupt is enabled. 76543210 tb0run 00xx ? 0x0 stops the tmrb0. imc7ll xx110000 imc7lh xx110100 enables inttb01, sets its priority level to 4 and disables inttb00. tb0ffcr 11000011 disables the timer flip-flop toggle-trigger. tb0mod 001001 ** ( ** = 01, 10, 11) selects a prescalar output clock as the timer clock source and disables the capture function. tb0rg1 ******** sets the interval time. ******** (16 bits) tb0run 00xx ? 1x1 starts the tmrb0. x = don?t care, ? = no change 12.4.2 16-bit event counter mode this mode is used to count events by interpreting the rising edges of the external counter clock (tb0in0) as events. the up-counter (uc0) counts up on each rising clock edge. the counter value is be latched into a capture register under software control. to determine the number of events (i.e., cycles) counted, the value in the capture register must be read. 76543210 tb0run 00xx ? 0x0 stops the tmrb0. p7cr ??? 0 ???? p7fc ??? 1 ???? configures the p74 pin for input mode. imc7ll xx110000 imc7lh xx110100 enables inttb01 (interrupt level = 4) and disables inttb00. tb0ffcr 11000011 disables the timer flip-flop toggle-trigger. tb0mod 00100100 selects the tb0in0 input as the timer clock source. tb0rg1 ******** sets a count value (16 bits). tb0run 00xx ? 1x1 starts the tmrb0. x = don?t care, ? = no change note: even when the timer is used for event counting, the prescaler must be programmed to run (i.e., the tb0run.tb0prun bit must be set to 1).
TMP1941AF 2003-03-27 TMP1941AF-150 12.4.3 16-bit programmable pulse generation (ppg) mode the 16-bit ppg mode can be used to generate a square wave with any frequency and duty cycle. the pulse can be high-going and low-going, as determined by the initial setting of the timer flip-flop (tb0ff0). a square wave is generated by toggling the timer flip-flop every time the up-counter uc0 reaches the values in each timer register (tb0rg0 and tb0rg1). the square-wave output is driven to the tb0out pin. in this mode, the following relationship must be satisfied: (tb0rg0 value) < (tb0rg1 value) figure 12.15 ppg output waveform note: stop the timer when changing the duty cycle in ppg mode. (don?t use the double-buffering function for this purpose.) tb0rg0 match (inttb00 interrupt) tb0rg1 match (inttb01 interrupt) tb0out pin
TMP1941AF 2003-03-27 TMP1941AF-151 figure 12.16 shows a functional diagram of 16-bit ppg mode. figure 12.16 functional diagram of 16-bit ppg mode the following is an example of running the timer in 16-bit ppg mode. 76543210 tb0run 00xx ? 0x0 disables the tb0rg0 double-buffering and stops the tmrb0. tb0rg0 ******** defines the duty cycle (16 bits). tb0rg1 ******** defines the cycle period (16 bits). tb0ffcr xx001110 toggles the tb0ff0 when a match is detected between uc0 and tb0rg0 and between uc0 and tb0rg1. initially clears the tb0ff0 to 0. tb0mod 001001 ** ( ** = 01, 10, 11) selects a prescaler output clock as the timer clock source and disables the capture function. p7cr ? 1 ?????? p7fc ? 1 ?????? configures the p76 pin as tb1out. tb0run 10xx ? 1x1 starts the tmrb0. x = don?t care, ? = no change selector match 16-bit comparator register buffer 0 16-bit up-counter uc0 f/f (tb0ff0) 16-bit comparator internal data bus tb0rg1 tb0in0 t1 t4 t16 tb0out (ppg output) tb0run.tb0run clear
TMP1941AF 2003-03-27 TMP1941AF-152 12.4.4 timing and measurement functions using the capture capability the capture capability of the tmrbn provides versatile timing and measurement functions, including the following: ? one-shot pulse generation using an external trigger pulse ? frequency measurement ? pulse width measurement ? time difference measurement (1) one-shot pulse generation using an external trigger pulse the tmrbn can be used to produce a one-time pulse as follows. the 16-bit up-counter (uc0) is programmed to function as a free-running counter, clocked by one of the prescalar outputs. the tb0in0 pin is used as an active-high external trigger pulse input for latching the counter value into capture register 0 (tb0cp0). the tb0in0 pin is shared with p74 and int5. the interrupt controller (intc) must be programmed to generate an int5 interrupt upon detection of a rising edge on the tb0in0/int5 pin. a one-shot pulse has a delay and width controlled by the values stored in the timer registers (tb0rg0 and tb0rg1). programming the tb0rg0 and tb0rg1 is the responsibility of the int5 interrupt handler. the tb0rg0 is loaded with the sum of the tb0cp0 value (c) plus the pulse delay (d) ? i.e., (c) + (d). the tb0rg1 is loaded with the sum of the tb0rg0 value plus the pulse width (p) ? i.e., (c) + (d) + (p). next, the tb0e1t1 and tb0e0t1 bits in the timer flip-flop control register (tb0ffcr) are set to 11, so that the timer flip-flop (tb0ff0) will toggle when a match is detected between the uc0 and the tb0rg0 and between the uc0 and the tb0rg1. with the tb0ff0 toggled twice, a one-shot pulse is produced. upon a match between the uc0 and the tb0rg1, the tmrb0 generates the inttb01 interrupt, which must disable the toggle-trigger for the tb0ff0. figure 12.17 depicts one-shot pulse generation, with annotations showing (c), (d) and (p). figure 12.17 one-shot pulse generation (with a delay) c + d + p c + d c toggle is disabled for a capture into tb0cp1. toggle is enabled. (p) (d) pulse width delay toggle is enabled. inttb01 is generated. the uc0 value is latched into tb0cp1. int5 is generated. counter clock (internal clock) the counter is free-running. tb0in0 input pin (external trigger pulse) tb0rg0 match tb0rg1 match tb0out (timer output) pin
TMP1941AF 2003-03-27 TMP1941AF-153 example: generating a one-shot pulse with a width of 2 ms and a delay of 3 ms on assertion of an external trigger pulse on the tb0in0 pin clocking conditions: system clock: high-speed (fc) high-speed clock gear: 1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) settings in the main routine 76543210 places the counter in free-running mode. selects t1 as the counter clock source. tb0mod xx101001 tb0ffcr xx000010 latches uc0 value into tb0cp0 at rising edges of the tb0in0 input. clears tb0ff0 to 0. disables the toggle-trigger for tb0ff0. p7cr ? 1 ?????? p7fc ? 1 ?????? configures the p76 pin as tb1out. imc2hl xx110100 imc7ll xx110000 imc7lh xx110000 enables int5 and disables inttb00 and inttb01. tb0run ? 0xx ? 1x1 starts the tmrb0. settings in int5 tb0rg0 tb0cp0 + 3ms/ t1 tb0rg1 tb0rg0 + 2ms/ t1 tb0ffcr xx ?? 11 ?? enables the tb0ff0 toggle-trigger for tb0rg0 and tb0rg1 matches. imc7lh xx110100 enables inttb01. settings in inttb01 tb0ffcr xx ?? 00 ?? disables the tb0ff0 toggle-trigger for tb0rg0 and tb0rg1 matches. imc7lh xx110000 disables inttb01. x = don?t care, ? = no change
TMP1941AF 2003-03-27 TMP1941AF-154 if no delay is necessary, enable the tb0ff0 toggle-trigger for a capture of the uc0 value into the tb0cp0. use the int5 interrupt to load the tb0rg1 with a sum of the tb0cp0 value (c) plus the pulse width (p) and to enable the tb0ff0 toggle-trigger for a match between the uc0 and tb0rg1 values. a match generates the inttb01 interrupt, which then is to disable the tb0ff0 toggle-trigger. figure 12.18 one-shot pulse generation (without a delay) (2) frequency measurement the capture function can be used to measure the frequency of an external clock. frequency measurement requires a 16-bit tmrbn channel running in event counter mode and the 8-bit tmra01. the timer flip-flop (ta1ff) in the tmra01 is used to define the duration during which a measurement is taken. select the tb0in0 pin as the clock source for the tmrb0. set the tb0cpm[1:0] field in the tb0mod to 11 to select the ta1ff output signal from the tmra01 as a capture trigger input. this causes the tmrb0 to latch the 16-bit up-counter (uc0) value into capture register 0 (tb0cp0) on the low-to-high transition of the ta1ff and into capture register 1 (tb0cp1) on the next high-to-low transition of the ta1ff. either the intta0 or intta1 interrupt generated by the 8-bit timer can be used to make a frequency calculation. figure 12.19 frequency measurement for example, if the ta1ff of the 8-bit timer is programmed to be at logic 1 for a period of 0.5 seconds and the difference between the values captured into the tb0cp0 and tb0cp1 is 100, then the tb0in0 frequency is calculated as 100 0.5 s = 200 hz. c2 c1 c2 c1 c2 c1 counter clock (tb0in0 input) ta1out capture into tb0cp0 capture into tb0cp1 intta0/intta1 c + p c toggle is enabled. (p) pulse width the uc0 value is latched into tb0cp0. int5 is generated. counter clock (prescaler output clock) tb0in0 input (external trigger pulse) tb0rg1 match tb0out (timer output) pin the uc0 value is latched into tb0cp1. inttb01 is generated. toggle is enabled for a capture into tb0cp0. toggle is left disabled for a capture into tb0cp1 so that it will not be toggled.
TMP1941AF 2003-03-27 TMP1941AF-155 (3) pulse width measurement the capture function can be used to measure the pulse width of an external clock. the external clock is applied to the tb0in0 pin. the up-counter (uc0) is programmed to operate as a free- running counter, clocked by one of the prescalar outputs. the capture function is used to latch the uc0 value into capture register 0 (tb0cp0) at the clock rising edge and into capture register 1 (tb0cp1) at the next clock falling edge. the tb0in0 input is shared with the int5 input; the interrupt controller (intc) is to be programmed to generate the int5 interrupt at the falling edge of the tb0in0 input. multplying the counter clock period by the difference between the values captured into the tb0cp0 and tb0cp1 gives the high pulse width of the tb0in0 clock. for example, if the prescalar output clock has a period of 0.5 s and the difference between the tb0cp0 and tb0cp1 is 100, the high pulse width is calculated as 0.5 s 100 = 50 s. figure 12.20 pulse width measurement the low pulse width can be measured by the second int5 interrupt. this is accomplished by multiplying the counter clock period by the difference between the tb0cp0 value at the first c2 and the tb0cp1 value at the second c1. c2 c1 c2 c1 c2 c1 prescaler output clock tb0in0 input (external clock) capture into tb0cp0 int5 capture into tb0cp1
TMP1941AF 2003-03-27 TMP1941AF-156 (4) time difference measurement the capture function can be used to measure the time difference between two event occurrences. the 16-bit up-counter (uc0) is programmed to operate as a free-running counter. the uc0 value is latched into capture register 0 (tb0cp0) on the rising edge of tb0in0. the tb0in0 pin is shared with int5; the interrupt controller (intc) is to be programmed to generate the int5 interrupt at this time. then, the uc0 value is latched into capture register 1 (tb0cp1) on the rising edge of tb0in1. the tb0in1 pin is shared with int6; the intc is to be programmed to generate the int6 interrupt at this time. the time difference between the two events that occurred on the tb0in0 and tb0in1 pins is calculated by multiplying the counter clock period by the difference between the tb0cp1 and tb0cp0 values. figure 12.21 time difference measurement time difference c2 c1 tb0in0 input tb0in1 input int5 capture into tb0cp0 int6 capture into tb0cp1 prescaler output clock
TMP1941AF 2003-03-27 TMP1941AF-157 13. serial i/o (sio) the TMP1941AF serial i/o contains four channels named sio0, sio1, sio3 and sio4 (there is not sio2). the sio0 and sio1 provide universal asynchronous receiver/transmitter (uart) mode and synchronous i/o interface mode. the sio2 and sio3 provide only uart mode. ? i/o interface mode mode 0: transmits/receives a serial clock (sclk) as well as data streams for a synchronous clock mode of operation. ? uart mode mode 1: 7 data bits mode 2: 8 data bits mode 3: 9 data bits in mode 1 and mode 2, each character can include a parity bit. in mode 3, an sio channel operates in a wake- up mode for multidrop applications in which a master station is connected to several slave stations through a serial link. figure 13.2 to figure 13.5 are block diagrams of each sio channel. the main components of an sio channel are a clock prescalar, a serial clock generator, a receive buffer, a receive controller, a transimit buffer and a transmit controller. each sio channel is independently programmable, and functionally equivalent with a few exceptions listed below. in the following sections, any references to the sio0 also apply to the other channels. table 13.1 differences between the sio channels sio0 sio1 sio3 sio4 pins used txd0 (p90) rxd0 (p91) 0 cts /sclk0 (p92) txd1 (p93) rxd1 (p94) 1 cts /sclk1 (p95) txd3 (p70) rxd3 (p71) txd4 (p72) rxd4 (p73) i/o interface mode available available not available not available
TMP1941AF 2003-03-27 TMP1941AF-158 ? mode 0 (i/o interface mode) ? mode 1 (7-bit uart mode) ? mode 2 (8-bit uart mode) ? mode 3 (9-bit uart mode) figure 13.1 data formats goes out first 7 bit 0 123456 bit 0 123456 start stop bit 0 123456 start stop (1 bit) parity without parity with parity bit 0 123456 bit 0 123456 start start parity 7 7 7 without parity with parity stop (1 bit) stop (1 bit) bit 0 123 456 start 8 7 bit 0 123456 start stop (wake-up, 1 bit) 8 7 bit 8: address/data bit flag 1: address character (select code) 0: data character stop (1 bit)
TMP1941AF 2003-03-27 TMP1941AF-159 13.1 block diagrams figure 13.2 sio0 block diagram prescaler br0cr. br0ck[1:0] ta0trg (from tmra0) 16 32 64 8 4 2 t2 t8 t32 t0 br0cr. br0s[3:0] br0add. br0k[3:0] selector selector selector divider t0 t2 t8 t32 br0cr. br0adde fsys/2 i/o interface mode 2 selector i/o interface mode sc0cr. ioc sc0mod0. wu receive counter ( 16 for uart) serial channel interrupt control transmit counter ( 16 for uart) transmit control receive control receive buffer 1 (shift register) rb8 receive buffer 2 (sc0buf) error flag sioclk uart mode sc0mod0. sc[1:0] sc0mod0. sm[1:0] tb8 transmit buffer (sc0buf) intrx0 interrupt request internal data bus sc0cr oerr perr ferr txd0 (shared with p90) 0 cts (shared with p92) internal data bus inttx0 interrupt request sc0mod0. ctse rxd0 (shared with p91) pe sc0cr even txdclk sc0mod0. rxe parity control internal data bus serial clock generator sclk0 input (shared with p92) sclk0 output (shared with p92) baud rate generator rxdclk
TMP1941AF 2003-03-27 TMP1941AF-160 figure 13.3 sio1 block diagram prescaler br1cr. br1ck[1:0] ta0trg (from tmra0) 16 32 64 8 4 2 t2 t8 t32 t0 br1cr. br1s[3:0] br1add. br1k[3:0] selector selector selector divider t0 t2 t8 t32 br1cr. br1adde fsys/2 i/o interface mode 2 selector i/o interface mode sc1cr. ioc sc1mod0. wu receive counter ( 16 for uart) serial channel interrupt control transmit counter ( 16 for uart) transmit control receive control receive buffer 1 (shift register) rb8 receive buffer 2 (sc1buf) error flag sioclk uart mode sc1mod0. sc[1:0] sc1mod0. sm[1:0] tb8 transmit buffer (sc1buf) intrx1 interrupt request internal data bus sc1cr oerr perr ferr txd1 (shared with p93) 1 cts (shared with p95) internal data bus inttx1 interrupt request sc1mod0. ctse rxd1 (shared with p94) pe sc1cr even txdclk sc1mod0. rxe parity control internal data bus serial clock generator sclk1 input (shared with p95) sclk1 output (shared with p95) baud rate generator rxdclk
TMP1941AF 2003-03-27 TMP1941AF-161 figure 13.4 sio3 block diagram prescaler br3cr. br3ck[1:0] ta0trg (from tmra0) 16 32 64 8 4 2 t2 t8 t32 t0 br3cr. br3s[3:0] br3add. br3k[3:0] selector selector divider t0 t2 t8 t32 br3cr. br3adde fsys/2 sc3mod0. wu receive counter ( 16 for uart) serial channel interrupt control transmit counter ( 16 for uart) transmit control receive control receive buffer 1 (shift register) rb8 receive buffer 2 (sc3buf) error flag sioclk uart mode sc3mod0. sc[1:0] sc3mod0. sm[1:0] tb8 transmit buffer (sc3buf) intrx3 interrupt request internal data bus sc3cr oerr perr ferr txd3 (shared with p70) internal data bus inttx3 interrupt request rxd3 (shared with p71) pe sc3cr even txdclk sc3mod0. rxe parity control internal data bus serial clock generator baud rate generator rxdclk selector
TMP1941AF 2003-03-27 TMP1941AF-162 figure 13.5 sio4 block diagram prescaler br4cr. br4ck[1:0] ta0trg (from tmra0) 16 32 64 8 4 2 t2 t8 t32 t0 br4cr. br4s[3:0] br4add. br4k[3:0] selector selector divider t0 t2 t8 t32 br4cr. br4adde fsys/2 sc4mod0. wu receive counter ( 16 for uart) serial channel interrupt control transmit counter ( 16 for uart) transmit control receive control receive buffer 1 (shift register) rb8 receive buffer 2 (sc4buf) error flag sioclk uart mode sc4mod0. sc[1:0] sc4mod0. sm[1:0] tb8 transmit buffer (sc4buf) intrx4 interrupt request internal data bus sc4cr oerr perr ferr txd4 (shared with p70) internal data bus inttx4 interrupt request rxd4 (shared with p71) pe sc4cr even txdclk sc4mod0. rxe parity control internal data bus serial clock generator baud rate generator rxdclk selector
TMP1941AF 2003-03-27 TMP1941AF-163 13.2 sio components 13.2.1 prescaler the sio0 has a 6-bit prescalar that slows the rate of a clocking source to the serial clock generator. the prescalar clock source ( t0) can be selected from fperiph, fperiph/2 and fperiph/4 by programming the prck[1:0] field of the syscr0 located within the cg. fperiph can be selected from fgear (geared clock) and fc (non-geared clock) by programming the fpsel bit of the syscr1 located within the cg. the serial clock is selectable from several clocks; the prescalar is only enabled when the baud rate generator output clock is selected as a serial clock. table 13.2 shows prescalar output clock resolutions (@fc = 32 mhz). table 13.2 prescaler output clock resolutions @ fc = 40 mhz prescaler output clock resolution peripheral clock select syscr1. fpsel clock gear value syscr1. gear[1:0] prescaler clock source syscr0.prck[1:0] t0 t2 t8 t32 00 (fperiph/4) fc/2 2 (0.1 s) fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.4 s) 01 (fperiph/2) ? fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 7 (3.2 s) 00 (fc) 10 (fperiph) ? fc/2 2 (0.1 s) fc/2 4 (0.4 s) fc/2 6 (1.6 s) 00 (fperiph/4) fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 9 (12.8 s) 01 (fperiph/2) ? fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.4 s) 01 (fc/2) 10 (fperiph) ? fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 7 (3.2 s) 00 (fperiph/4) fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.4 s) fc/2 10 (25.6 s) 01 (fperiph/2) ? fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 9 (12.8 s) 10 (fc/4) 10 (fperiph) ? fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.4 s) 00 (fperiph/4) fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 9 (12.8 s) fc/2 11 (51.2 s) 01 (fperiph/2) ? fc/2 6 (1.6 s) fc/2 8 (6.4 s) fc/2 10 (25.6 s) 0 (fgear) 11 (fc/8) 10 (fperiph) ? fc/2 5 (0.8 s) fc/2 7 (3.2 s) fc/2 9 (12.8 s) 00 (fperiph/4) fc/2 2 (0.1 s) fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.4 s) 01 (fperiph/2) ? fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 7 (3.2 s) 00 (fc) 10 (fperiph) ? fc/2 2 (0.1 s) fc/2 4 (0.4 s) fc/2 6 (1.6 s) 00 (fperiph/4) ? fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.4 s) 01 (fperiph/2) ? fc/2 3 (0.2 s) fc/2 5 (0.8 s) fc/2 7 (3.2 s) 01 (fc/2) 10 (fperiph) ?? fc/2 4 (0.4 s) fc/2 6 (1.6 s) 00 (fperiph/4) ? fc/2 4 (0.4 s) fc/2 6 (1.6 s) fc/2 8 (6.4 s) 01 (fperiph/2) ?? fc/2 5 (0.8 s) fc/2 7 (3.2 s) 10 (fc/4) 10 (fperiph) ?? fc/2 4 (0.4 s) fc/2 6 (1.6 s) 00 (fperiph/4) ?? fc/2 6 (1.6 s) fc/2 8 (6.4 s) 01 (fperiph/2) ?? fc/2 5 (0.8 s) fc/2 7 (3.2 s) 1 (fc) 11 (fc/8) 10 (fperiph) ??? fc/2 6 (1.6 s) note 1: the prescaler's output clock tn must be selected so that the relationship tn < fsys/2 is satisfied. note 2: do not change the clock gear value while the timer is running. note 3: the ? character means ?don?t use.? prescalar output taps can be divide-by-1 ( t0), divide-by-4 ( t2), divide-by-16 ( t8) and divide-by- 64 ( t32).
TMP1941AF 2003-03-27 TMP1941AF-164 13.2.2 baud rate generator (1) baud rate generator configuration the frequency used to transimit and receive data through the sio0 is derived from the baud rate generator. the clock source for the baud rate generator can be selected from the 6-bit prescalar outputs ( t0, t2, t8, t32) through the programming of the br0ck[1:0] field in the br0cr. the baud rate generator contains a clock divider that can divide the selected clock by 1, n + (m / 16), or 16 (where n is an integer between 2 and 15, and m is an integer between 0 and 15). the clock divisor is programmed into the br0adde and br0s[3:0] bits in the br0cr and the br0k[3:0] bits in the br0add. ? uart mode a. when br0cr.br0adde = 0 when the br0cr.br0adde bit is cleared, the br0add.br0k[3:0] field has no meaning or effect. in this case, the baud rate generator input clock is divided down by a value of n (1 to 16) programmed in the br0cr.br0s[3:0] field. b. when br0cr.br0adde = 1 setting the br0cr.br0adde bit enables the n + (16 ? k) / 16 clock division function. the baud rate generator input clock is divided down according to the value of n (2 to 15) programmed in the br0cr.br0s[3:0] field and the value of k (1 to 15) programmed in the br0add.br0k[3:0] field. note: setting n to 0 or 16 disables the n + (16 ? k) / 16 clock division function. when n = 0 or 16, the br0cr.br0adde bit must be cleared. ? i/o interface mode i/o interface mode can not utilize the n + (16 ? k) / 16 clock division function. the br0cr.br0adde must be cleared, so the baud rate generator input clock is divided down by a value of n (1 to 16) programmed in the br0cr.br0s[3:0] field. (2) baud rate calculations ? uart mode baud rate = divisor generator rate baud clock input generator rate baud 16 when the clock input to the baud rate generator is 8-mhz t0, the maximum baud rate is 500 kbps (with no clock division by the baud rate generator). the baud rate generator can by bypassed if the user wants to use the fsys/2 clock as a serial clock. in this case, the maximum baud rate is 1 mbps @fsys = 32 mhz. ? i/o interface mode baud rate = divisor generator rate baud clock input generator rate baud 2 when the clock input to the baud rate generator is 8-mhz t0, the maximum baud rate is 2 mbps (with the clock divided by 2 by the baud rate generator).
TMP1941AF 2003-03-27 TMP1941AF-165 (3) calculation examples ? integral clock division (divide-by-n) fperiph = 24.576-mhz fc t0 = fperiph/4 baud rate generator input clock: t2 clock divisor n (br0cr.br0s[3:0]) = 10 br0cr.br0adde = 0 clocking conditions system clock: high-speed (fc) high-speed clock gear: ? 1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) the baud rate is determined as follows: baud rate = 10 fc/16 16 = 24.576 10 6 16 10 16 = 9600 (bps) note: clearing the br0cr.br0adde bit to 0 disables the n + (16 ? k) / 16 clock division function. at this time, the br0add.br0k[3:0] field is ignored. ? n + (16 ? k) / 16 clock division (uart mode only) fperiph = 19.2-mhz fc t0 = fperiph/4 baud rate generator input clock: t2 n (br0cr.br0s[3:0]) = 7 k (br0add.br0k[3:0]) = 3 br0cr.br0adde = 1 clocking conditions system clock: high-speed (fc) high-speed clock gear: ? 1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) the baud rate is determined as follows: baud rate = 16 3) - (16 + 7 16 / fc 16 = 19.2 10 6 16 (7 + 16 13 ) 16 = 9600 (bps) table 13.3 and table 13.4 show the uart baud rates obtained with various combinations of clock inputs and clock divisor values. (4) using an external clock as a serial clock the sio0 and sio1 can use an external clock as a serial clock, bypassing the baud rate generator. when an external clock is used, the baud rate is determined as shown below. ? uart mode baud rate = external clock input 16 the external clock period must be greater than or equal to 4/fsys. therefore, when fsys = 40 mhz, the maximum baud rate is 625 kbps (40 4 16).
TMP1941AF 2003-03-27 TMP1941AF-166 ? i/o interface mode baud rate = external clock input clock the external clock period must be greater than 16/fsys. therefore, when fsys = 40 mhz, the maximum baud rate is 2.5 mbps (40 16). for the timing parameters, refer to section 18.6, serial channel timing . table 13.3 uart baud rate selection when the baud rate generator is used and br0cr.br0adde = 0 unit: kbps baud rate generator input clock fc (mhz) divisor n (programmed in br0cr.br0s[3:0]) t0 (fc/4) t2 (fc/16) t8 (fc/64) t32 (fc/256) 1 307.200 76.800 19.200 4.800 2 153.600 38.400 9.600 2.400 4 76.800 19.200 4.800 1.200 8 38.400 9.600 2.400 0.600 19.6608 0 19.200 4.800 1.200 0.300 5 76.800 19.200 4.800 1.200 24.576 a 38.400 9.600 2.400 0.600 1 460.800 115.200 28.800 7.200 2 230.400 57.600 14.400 3.600 3 153.600 38.400 9.600 2.400 4 115.200 28.800 7.200 1.800 6 76.800 19.200 4.800 1.200 29.4912 c 38.400 9.600 2.400 0.600 note: this table assumes: fsys = fc, clock gear = fc/1, prescaler clock source = fperiph/4 table 13.4 uart baud rate selection when the tmra0 timer trigger output is used and the tmra0 input clock is t1 unit: kbps fc (mhz) ta0reg0 29.4912 24.576 24 19.6608 16 12.288 1h 230.4 192 187.5 153.6 125 96 2h 115.2 96 93.75 76.8 62.5 48 3h 76.8 64 62.5 51.2 41.67 32 4h 57.6 48 46.88 38.4 31.25 24 5h 46.08 38.4 37.5 30.72 25 19.2 6h 38.4 32 31.25 25.6 20.83 16 8h 28.8 24 23.44 19.2 15.63 12 ah 23.04 19.2 18.75 15.36 12.5 9.6 10h 14.4 12 11.72 9.6 7.81 6 14h 11.52 9.6 9.38 7.68 6.25 4.8 note 1: i/o interface mode can not utilize the trigger output signal from the 8-bit timer tmra0 as a serial clock. note 2: this table assumes: fsys = fc, clock gear = fc/1, and prescaler clock source = fperiph/4 when the 8-bit timer tmra0 is used to generate a serial clock, the baud rate is determined by the following equation: baud rate = 16 2 ta0reg 0] : k[1 syscr0.prc by selected frequency clock when thetmra0 clock source is t1.
TMP1941AF 2003-03-27 TMP1941AF-167 13.2.3 serial clock generator this block generates a basic clock (sioclk) that controls the transimit and receive circuit. ? i/o interface mode when the sclk0 pin is configured as an output by clearing the sc0cr.ioc bit to 0, the output clock from the baud rate generator is divided by two to generate the sioclk clock. when the sclk0 pin is configured as an input by setting the sc0cr.ioc bit to 1, the external sclk0 clock is used as the sioclk clock; the sc0cr.sclks bit determines the active clock edge. ? uart mode the sioclk clock is selected from a clock produced by the baud rate generator, the system clock (fsys/2), the trigger output signal from the 8-bit timer tmra0, and the external sclk0 clock, according to the setting of the sc0mod0.sc[1:0] field. 13.2.4 receive counter the receive counter is a 4-bit binary up-counter used in uart mode. this counter is clocked by sioclk. the receiver utilizes 16 clocks for each received bit, and oversamples each bit three times around their center (with 7th to 9th clocks). the value of a bit is determined by voting logic which takes the value of the majority of three samples. for example, if the three samples of a bit are 1, 0 and 1, then that bit is interpreted as a 1; if the three samples of a bit are 0, 0 and 1, then that bit is interpreted as a 0. 13.2.5 receive controller ? i/o interface mode if the sclk0 pin is configured as an output by clearing the sc0cr.ioc bit to 0, the receive controller samples the rxd0 input at the rising edge of the shift clock driven out from the sclk0 pin. if the sclk0 pin is configured as an input by setting the sc0cr.ioc bit to 1, the receive controller samples the rxd0 input at either the rising or falling edge of the sclk0 clock, as programmed in the sc0cr.sclks bit. ? uart mode the receive controller contains the start bit detection logic. once a valid start bit is detected, the receive controller begins sampling the incoming data streams. the start bit, each data bit and the stop bit are sampled three times for 2-of-3 majority voting. 13.2.6 receive buffer the receive buffer is double-buffered to prevent overrun errors. received data is serially shifted bit by bit into receive buffer 1. when a whole character (i.e., 7 or 8 bits, as programmed) is loaded into receive buffer 1, it is transferred to receive buffer 2 (sc0buf), and a receive-done interrupt (intrx0) is generated. ? i/o interface mode the double-buffer structure can be used in full-duplex mode, but not in half-duplex mode. for details, refer to section 13.4. ? uart mode the cpu reads a character from receive buffer 2 (sc0buf). receive buffer 1 can accept a new character through the rxd0 pin before the cpu picks up the previous character in receive buffer 2. however, the cpu must read receive buffer 2 before receive buffer 1 is filled with a new character. otherwise, an overrun error occurs, causing the character previouly in receive buffer 1 to be lost. even in that case, the contents of receive buffer 2 and the sc0cr.rb8 bit are preserved.
TMP1941AF 2003-03-27 TMP1941AF-168 the sc0cr.rb8 bit holds the parity bit for an 8-bit uart character and the most-significant bit (i.e., address/data flag) bit for a 9-bit uart character. in 9-bit uart mode, the receiver wake-up feature allows the slave station in a multidrop system to wake up whenever an address character is received. setting the sc0mod0.wu bit enables the wake-up feature. when the sc0cr.rb8 bit has received an address/data flag bit set to 1, the receiver generates the intrx0 interrupt. 13.2.7 transmit counter the transmit counter is a 4-bit binary up-counter used in uart mode. like the receive counter, the transmit counter is also clocked by sioclk. the transmitter generates a transimit clock (txdclk) pulse every 16 sioclk pulses. figure 13.6 transimit clock generation 13.2.8 transmit controller ? i/o interface mode if the sclk0 pin is configured as an output by clearing the sc0cr.ioc bit to 0, the transimit controller shifts out each bit in the transmit buffer to the txd0 pin at the rising edge of the shift clock driven out on the sclk0 pin. if the sclk0 pin is configured as an input by setting the sc0cr.ioc bit to 1, the transimit controller shifts out each bit in the transmit buffer to the txd0 pin at either the rising or falling edge of the sclk0 input, as programmed in the sc0cr.sclks bit. ? uart mode once the cpu loads a character into the transimit buffer, the transmit controller begins transmission at the next rising edge of txdclk, producing a transmit shift clock (txdsft). sioclk txdclk 15 16 12 456 78910 11 12 13 14 15 16 3 1 2
TMP1941AF 2003-03-27 TMP1941AF-169 handshaking the sio0 and sio1 have the clear-to-send ( cts ) pin. if the cts operation is enabled, the cts input must be low in order for the character to be transmitted. this feature can be used for flow control to prevent overrun in the receiver. the sc0mod.ctse bit enables and disables the cts operation. if the cts pin goes high in the middle of a transmission, the transimit controller stops transmission upon completion of the current character until cts again goes low. if so enabled, the transmit controller generates the inttx0 interrupt to notify the cpu that the transmit buffer is empty. after the cpu loads the next character into the transmit buffer, the transmit controller remains in idle state until it detects cts going low. although the sio0 and sio1 do not have the rts pin, any general-purpose port pins can serve as the rts pin. the receiving device uses the rts output to control the cts input of the transmitting device. once the receiving device has received a character, rts should be set to high in the receive- done interrupt handler to temporarily stop the transmitting device from sending the next character. this way, the user can easily implement a two-way handshake protocol. figure 13.7 handshaking signals note 1: when cts goes high in the middle of transmission, the transmitter stops transmission after the current character has been sent. note 2: the transmitter starts tansmission at the first falling edge of the txdclk clock after the cts signal goes low. figure 13.8 clear-to-send ( cts ) signal timing rxd rts ( an y p ort ) receiving device transmitting device txd cts TMP1941AF TMP1941AF cts (note 1) 13 14 15 16 1 2 3 14 15 16 1 2 3 sioclk txdclk txd bit 0 start bit no transmission takes place during this period. write to the transmit buffer (note 2)
TMP1941AF 2003-03-27 TMP1941AF-170 13.2.9 transmit buffer once the cpu loads a character into the transmit buffer (sc0buf), it is shifted out on the txd0 output, with the least-significant bit first, clocked by the transmit shift clock from the transmit controller. when the transmit buffer is empty and ready to be loaded with the next character, the inttx0 interrupt is generated to the cpu. a character can not be written to the transmit buffer in the middle of a transmission. 13.2.10 parity controller for transmit operations, setting the sc0cr.pe enables parity generation in 7- and 8-bit uart modes. the sc0cr.even bit selects either even or odd parity. if enabled, the parity controller automatically generates parity for the character in the transmit buffer (sc0buf). in 7-bit uart mode, the tb7 bit in the sc0buf holds the parity bit. in 8-bit uart mode, the tb8 bit in the sc0mod holds the parity bit. the parity bit is set after the character has been transmitted. the sc0cr.pe and sc0cr.even bits must be programmed prior to a write to the transmit buffer. for receive operations, the parity controller automatically computes the expected parity when a character in receive buffer 1 is transferred to receive buffer 2 (sc0buf). the received parity bit is compared to the sc0buf.rb7 bit in 7-bit uart mode and to the sc0cr.rb8 bit in 8-bit uart mode. if a character is received with incorrect parity, the sc0cr.perr bit is set. 13.2.11 error flags (uart mode only) the sc0cr has the following error flag bits that indicate the status of the received character for improved data reception reliability. ? overrun error (oerr) an overrun error is reported if all bits of a new character are received into receive buffer 1 when receive buffer 2 (sc0buf) still contains a valid character. ? parity error (perr) a parity error is reported when the parity bit attached to a character received on the rxd pin does not match the expected parity computed from the character transferred to receive buffer 2 (sc0buf). ? framing error (ferr) a framing error is reported when a 0 is detected where a stop bit was expected. (the middle three of the 16 samples are used to determine the bit value.) note 1: even if an error is present in a received character, the receive operation for the next character continues normally. note 2: error flags are kept until read.
TMP1941AF 2003-03-27 TMP1941AF-171 13.2.12 signal generation timing (1) uart mode receive operation 9 data bits 8 data bits with parity 8 data bits with no parity 7 data bits with parity 7 data bits with no parity interrupt middle of the stop bit middle of the stop bit middle of the stop bit framing error middle of the stop bit middle of the stop bit middle of the stop bit parity error ? middle of the last bit (i.e., parity bit) middle of the last bit (i.e., parity bit) overrun error middle of the last bit (i.e., bit 8) middle of the last bit (i.e., parity bit) middle of the stop bit transmit operation 9 data bits 8 data bits with parity 8 data bits with no parity 7 data bits with parity 7 data bits with no parity interrupt immediately before the stop bit is shifted out immediately before the stop bit is shifted out immediately before the stop bit is shifted out (2) i/o interface mode sclk output mode immediately after the rising edge of the last sclk pulse (see figure 13.29) transmit interrupt sclk input mode immediately after the rising or falling edge of the last sclk pulse, as programmed (see figure 13.30) sclk output mode when a received character has been transferred to receive buffer 2 (sc0buf) (i.e., immediately after the last sclk pulse) (see figure 13.31) receive interrupt sclk input mode when a received character has been transferred to receive buffer 2 (sc0buf) (i.e., immediately after the last sclk pulse) (see figure 13.32) note 1: don?t modify any control register during transmit or receive operations. note 2: don?t disable receive operations by clearing the sc0mod0.rxe bit while any character is being received.
TMP1941AF 2003-03-27 TMP1941AF-172 13.3 register description 76543210 name tb8 ctse rxe wu sm1 sm0 sc1 sc0 read/write r/w reset value00000000 function bit 8 of a transmitted character handshake control 0: disables cts operation 1: enables cts operation receive control 0: disables receiver 1: enables receiver wake-up function 0: disabled 1: enabled serial transfer mode 00: i/o interface mode 01: 7-bit uart mode 10: 8-bit uart mode 11: 9-bit uart mode serial clock (for uart) 00: ta0trg (timer) 01: baud rate generator 10: internal fsys/2 clock 11: external clock (sclk0 input) wake-up function 9-bit uart mode other modes 0 interrupt on every received character 1 interrupt only when rb8 = 1 don?t care handshake ( cts ) control 0 disable (accepts data streams at all times) 1 enable note: in i/o interface mode, a serial clock is selected by the sio0 control register (sc0cr). figure 13.9 sio0 mode register 0 (sc0mod0) sc0mod0 (0xffff_f202)
TMP1941AF 2003-03-27 TMP1941AF-173 76543210 name tb8 ctse rxe wu sm1 sm0 sc1 sc0 read/write r/w reset value00000000 function bit 8 of a transmitted character handshake control 0: disables cts operation 1: enables cts operation receive control 0: disables receiver 1: enables receiver wake-up function 0: disabled 1: enabled serial transfer mode 00: i/o interface mode 01: 7-bit uart mode 10: 8-bit uart mode 11: 9-bit uart mode serial clock (for uart) 00: ta0trg (timer) 01: baud rate generator 10: internal fsys/2 clock 11: external clock (sclk1 input) wake-up function 9-bit uart mode other modes 0 interrupt on every received character 1 interrupt only when rb8 = 1 don?t care handshake ( cts ) control 0 disable (accepts data streams at all times) 1 enable note: in i/o interface mode, a serial clock is selected by the sio1 control register (sc1cr). figure 13.10 sio1 mode register 0 (sc1mod0) sc1mod0 (0xffff_f20a)
TMP1941AF 2003-03-27 TMP1941AF-174 76543210 name tb8 ? rxe wu sm1 sm0 sc1 sc0 read/write r/w reset value00000000 function bit 8 of a transmitted character must be written as 0. receive control 0: disables receiver 1: enables receiver wake-up function 0: disabled 1: enabled serial transfer mode 00: reserved 01: 7-bit uart mode 10: 8-bit uart mode 11: 9-bit uart mode serial clock (for uart) 00: ta0trg (timer) 01: baud rate generator 10: internal fsys/2 clock 11: don?t care wake-up function 9-bit uart mode other modes 0 interrupt on every received character 1 interrupt only when rb8 = 1 don?t care figure 13.11 sio3 mode register 0 (sc3mod0) sc3mod0 (0xffff_f282)
TMP1941AF 2003-03-27 TMP1941AF-175 76543210 name tb8 ? rxe wu sm1 sm0 sc1 sc0 read/write r/w reset value00000000 function bit 8 of a transmitted character must be written as 0. receive control 0: disables receiver 1: enables receiver wake-up function 0: disabled 1: enabled serial transfer mode 00: reserved 01: 7-bit uart mode 10: 8-bit uart mode 11: 9-bit uart mode serial clock (for uart) 00: ta0trg (timer) 01: baud rate generator 10: internal fsys/2 clock 11: don?t care wake-up function 9-bit uart mode other modes 0 interrupt on every received character 1 interrupt only when rb8 = 1 don?t care figure 13.12 sio4 mode register 0 (sc4mod0) sc4mod0 (0xffff_f28a)
TMP1941AF 2003-03-27 TMP1941AF-176 76543210 name rb8 even pe oerr perr ferr sclks ioc read/write r r/w r (cleared when read) r/w reset value 0000000 1: error has occurred. function bit 8 of a received character parity type 0: odd 1: even parity 0: disabled 1: enabled overrun parity framing 0: sclk0 1: sclk0 0: baud rate generator 1: sclk0 input input clock in i/o interface mode 0 baud rate generator 1 sclk0 input active edge for the sclk0 input 0 data is transmitted/received on the sclk0 rising edge. 1 data is transmitted/received on the sclk0 falling edge. framing error flag parity error flag overrun error flag input clock in i/o interface mode 0 odd parity 1 even parity note 1: all error flags are cleared to 0 when read. note 2: when sclk0 is configured as an output, the sclks bit must be cleared (rising-edge triggered). figure 13.13 sio0 control register (sc0cr) sc0cr (0xffff_f201) these bits are cleared to 0 when read.
TMP1941AF 2003-03-27 TMP1941AF-177 76543210 name rb8 even pe oerr perr ferr sclks ioc read/write r r/w r (cleared when read) r/w reset value 0000000 1: error has occurred. function bit 8 of a received character parity type 0: odd 1: even parity 0: disabled 1: enabled overrun parity framing 0: sclk1 1: sclk1 0: baud rate generator 1: sclk1 input input clock in i/o interface mode 0 baud rate generator 1 sclk1 input active edge for the sclk1 input 0 data is transmitted/received on the sclk1 rising edge. 1 data is transmitted/received on the sclk1 falling edge. framing error flag parity error flag overrun error flag input clock in i/o interface mode 0 odd parity 1 even parity note 1: all error flags are cleared to 0 when read. note 2: when sclk1 is configured as an output, the sclks bit must be cleared (rising-edge triggered). figure 13.14 sio1 control register (sc1cr) these bits are cleared to 0 when read. sc1cr (0xffff_f209)
TMP1941AF 2003-03-27 TMP1941AF-178 76543210 name rb8 even pe oerr perr ferr ?? read/write r r/w r (cleared when read) r/w reset value 0000000 1: error has occurred. function bit 8 of a received character parity type 0: odd 1: even parity 0: disabled 1: enabled overrun parity framing must be written as 00. framing error flag parity error flag overrun error flag parity type 0 odd parity 1 even parity note: all error flags are cleared to 0 when read. figure 13.15 sio3 control register (sc3cr) these bits are cleared to 0 when read. sc3cr (0xffff_f281)
TMP1941AF 2003-03-27 TMP1941AF-179 76543210 name rb8 even pe oerr perr ferr ?? read/write r r/w r (cleared when read) r/w reset value 0000000 1: error has occurred. function bit 8 of a received character parity type 0: odd 1: even parity 0: disabled 1: enabled overrun parity framing must be written as 00. framing error flag parity error flag overrun error flag parity type 0 odd parity 1 even parity note: all error flags are cleared to 0 when read. figure 13.16 sio4 control register (sc4cr) these bits are cleared to 0 when read. sc4cr (0xffff_f289)
TMP1941AF 2003-03-27 TMP1941AF-180 76543210 name ? br0adde br0ck1 br0ck0 br0s3 br0s2 br0s1 br0s0 read/write r/w reset value00000000 function must be written as 0. n + (16?k)/16 function 0: disabled 1: enabled 00: t0 01: t2 10: t8 11: t32 clock divisor value n clock source for baud rate generator 00 internal clock t0 01 internal clock t2 10 internal clock t8 11 internal clock t32 76543210 name ???? br0k3 br0k2 br0k1 br0k0 read/write ???? r/w reset value ???? 0000 function value of k in n+(16?k)/16 clock divisor value for baud rate generator br0cr.br0adde = 1 br0cr.br0adde = 0 br0cr. br0s[3:0] br0add. br0k[3:0] 0000 (n = 16) or 0001 (n = 1) 0010 (n = 2) thru 1111 (n = 15) 0001 (n = 1) (only uart) thru 1111 (n = 15) 0000 (n = 16) 0000 don?t use. don?t use. 0001(k = 1) thru 1111(k = 15) don?t use. divided by n + (16 ? k) / 16 divided by n note 1: the baud rate generator divisor can not be set to 1 in uart mode if the n + (16 ? k) / 16 clock division function is enabled. the divisor should be set to 2 or greater in i/o interface mode. note 2: to use the n + (16 ? k) / 16 clock division function, the value of k must be programmed in the br0add.br0k[3:0] field before setting br0cr.br0adde to 1. however, the n + (16 ? k) / 16 clock division function is not usable when br0cr.br0s[3:0] = 0000 (n = 16) or 0001 (n = 1). note 3: the n + (16 ? k) / 16 clock division function can only be used in uart mode. in i/o interface mode, this must be disabled by clearing br0cr.br0adde to 0. figure 13.17 sio0 baud rate generator control registers (br0cr and br0add) br0add (0xffff_f204) br0cr (0xffff_f203)
TMP1941AF 2003-03-27 TMP1941AF-181 76543210 name ? br1adde br1ck1 br1ck0 br1s3 br1s2 br1s1 br1s0 read/write r/w reset value00000000 function must be written as 0. n + (16?k)/16 function 0: disabled 1: enabled 00: t0 01: t2 10: t8 11: t32 clock divisor value n clock source for baud rate generator 00 internal clock t0 01 internal clock t2 10 internal clock t8 11 internal clock t32 76543210 name ???? br1k3 br1k2 br1k1 br1k0 read/write ???? r/w reset value ???? 0000 function value of k in n+(16?k)/16 clock divisor value for baud rate generator br1cr.br1adde = 1 br1cr.br1adde = 0 br1cr. br1s[3:0] br1add. br1k[3:0] 0000 (n = 16) or 0001 (n = 1) 0010 (n = 2) thru 1111 (n = 15) 0001 (n = 1) (only uart) thru 1111 (n = 15) 0000 (n = 16) 0000 invalid invalid 0001(k = 1) thru 1111(k = 15) invalid divided by n + (16 ? k) / 16 divided by n note 1: the baud rate generator divisor can not be set to 1 in uart mode if the n + (16 ? k) / 16 clock division function is enabled. the divisor should be set to 2 or greater in i/o interface mode. note 2: to use the n + (16 ? k) / 16 clock division function, the value of k must be programmed in the br0add.br0k[3:0] field before setting br0cr.br0adde to 1. however, the n + (16 ? k) / 16 clock division function is not usable when br0cr.br0s[3:0] = 0000 (n = 16) or 0001 (n = 1). note 3: the n + (16 ? k) / 16 clock division function can only be used in uart mode. in i/o interface mode, this must be disabled by clearing br0cr.br0adde to 0. figure 13.18 sio1 baud rate generator control registers (br1cr and br1add) br1add (0xffff_f20c) br1cr (0xffff_f20b)
TMP1941AF 2003-03-27 TMP1941AF-182 76543210 name ? br3adde br3ck1 br3ck0 br3s3 br3s2 br3s1 br3s0 read/write r/w reset value00000000 function must be written as 0. n + (16?k)/16 function 0: disabled 1: enabled 00: t0 01: t2 10: t8 11: t32 clock divisor value n clock source for baud rate generator 00 internal clock t0 01 internal clock t2 10 internal clock t8 11 internal clock t32 76543210 name ???? br3k3 br3k2 br3k1 br3k0 read/write ???? r/w reset value ???? 0000 function value of k in n+(16?k)/16 clock divisor value for baud rate generator br3cr.br3adde = 1 br3cr.br3adde = 0 br3cr. br3s[3:0] br3add. br3k[3:0] 0000 (n = 16) or 0001 (n = 1) 0010 (n = 2) thru 1111 (n = 15) 0001 (n = 1) (only uart) thru 1111 (n = 15) 0000 (n = 16) 0000 invalid invalid 0001(k = 1) thru 1111(k = 15) invalid divided by n + (16 ? k) / 16 divided by n note 1: the baud rate generator divisor can not be set to 1 in uart mode if the n + (16 ? k) / 16 clock division function is enabled. the divisor should be set to 2 or greater in i/o interface mode. note 2: to use the n + (16 ? k) / 16 clock division function, the value of k must be programmed in the br0add.br0k[3:0] field before setting br0cr.br0adde to 1. however, the n + (16 ? k) / 16 clock division function is not usable when br0cr.br0s[3:0] = 0000 (n = 16) or 0001 (n = 1). note 3: the n + (16 ? k) / 16 clock division function can only be used in uart mode. in i/o interface mode, this must be disabled by clearing br0cr.br0adde to 0. figure 13.19 sio3 baud rate generator control registers (br3cr and br3add) br3add (0xffff_f284) br3cr (0xffff_f283)
TMP1941AF 2003-03-27 TMP1941AF-183 76543210 name ? br4adde br4ck1 br4ck0 br4s3 br4s2 br4s1 br4s0 read/write r/w reset value00000000 function must be written as 0. n + (16?k)/16 function 0: disabled 1: enabled 00: t0 01: t2 10: t8 11: t32 clock divisor value n clock source for baud rate generator 00 internal clock t0 01 internal clock t2 10 internal clock t8 11 internal clock t32 76543210 name ???? br4k3 br4k2 br4k1 br4k0 read/write ???? r/w reset value ???? 0000 function value of k in n+(16?k)/16 clock divisor value for baud rate generator br4cr.br4adde = 1 br4cr.br4adde = 0 br4cr. br4s[3:0] br4add. br4k[3:0] 0000 (n = 16) or 0001 (n = 1) 0010 (n = 2) thru 1111 (n = 15) 0001 (n = 1) (only uart) thru 1111 (n = 15) 0000 (n = 16) 0000 invalid invalid 0001(k = 1) thru 1111(k = 15) invalid divided by n + (16 ? k) / 16 divided by n note 1: the baud rate generator divisor can not be set to 1 in uart mode if the n + (16 ? k) / 16 clock division function is enabled. the divisor should be set to 2 or greater in i/o interface mode. note 2: to use the n + (16 ? k) / 16 clock division function, the value of k must be programmed in the br0add.br0k[3:0] field before setting br0cr.br0adde to 1. however, the n + (16 ? k) / 16 clock division function is not usable when br0cr.br0s[3:0] = 0000 (n = 16) or 0001 (n = 1). note 3: the n + (16 ? k) / 16 clock division function can only be used in uart mode. in i/o interface mode, this must be disabled by clearing br0cr.br0adde to 0. figure 13.20 sio4 baud rate generator control registers (br4cr and br4add) br4add (0xffff_f28c) br4cr (0xffff_f28b)
TMP1941AF 2003-03-27 TMP1941AF-184 76543210 tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 (for tranmit) sc0buf (0xffff_f200) 76543210 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 (for receive) figure 13.21 sio0 transmit/receive buffer register (sc0buf) 76543210 name i2s0 fdpx0 ?????? read/write r/w r/w ?????? reset value 0 0 ?????? function sio operation in idle mode 0: off 1: on synchro- nous 0: half- duplex 1: full- duplex figure 13.22 sio0 mode register 1 (sc0mod1) 76543210 tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 (for tranmit) sc1buf (0xffff_f208) 76543210 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 (for receive) figure 13.23 sio1 transmit/receive buffer register (sc1buf) 76543210 name i2s0 fdpx0 ?????? read/write r/w r/w ?????? reset value 0 0 ?????? function sio operation in idle mode 0: off 1: on synchro- nous 0: half- duplex 1: full- duplex figure 13.24 sio1 mode register 1 (sc1mod1) sc0mod1 (0xffff_f205) sc1mod1 (0xffff_f20d)
TMP1941AF 2003-03-27 TMP1941AF-185 76543210 tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 (for tranmit) sc3buf (0xffff_f280) 76543210 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 (for receive) figure 13.25 sio3 transmit/receive buffer register (sc3buf) 76543210 name i2s0 ??????? read/write r/w ??????? reset value 0 ??????? function sio operation in idle mode 0: off 1: on figure 13.26 sio3 mode register 1 (sc3mod1) 76543210 tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 (for tranmit) sc4buf (0xffff_f288) 76543210 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 (for receive) figure 13.27 sio4 transmit/receive buffer register (sc4buf) 76543210 name i2s0 ??????? read/write r/w ??????? reset value 0 ??????? function sio operation in idle mode 0: off 1: on figure 13.28 sio4 mode register 1 (sc4mod1) sc3mod1 (0xffff_f285) sc4mod1 (0xffff_f28d)
TMP1941AF 2003-03-27 TMP1941AF-186 13.4 operating modes 13.4.1 mode 0 (i/o interface mode) mode 0 utilizes a synchronization clock (sclk), which can be configured for either output mode in which the sclk clock is driven out from the TMP1941AF or input mode in which the sclk clock is supplied externally. (1) transmit operations in sclk output mode, each time the cpu writes a character to the transmit buffer, the eight bits of the character is shifted out on the txd0 pin, and the synchronization clock is driven out from the sclk0 pin. when all the bits have been shifted out, the transmit-done interrupt (inttx0) is generated. figure 13.29 transmit operation in i/o interface mode (sclk0 output mode) in sclk0 input mode, the cpu must write a character to the transmit buffer before the sclk0 input is activated. the eight bits of a character in the transmit buffer are shifted out on the txd0 pin, synchronous to the programmed edge of the sclk0 input. when all the bits have been shifted out, the transmit-done interrupt (inttx0) is generated. the cpu must load the next character into the transmit buffer by point a. figure 13.30 transmit operation in i/o interface mode (sclk0 input mode) bit 0 bit 6 bit 7 bit 1 bit 0 transmit data write timing sclk0 output txd0 inttx0 interrupt bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 a sclk0 input (sclks = 0: rising edge) sclk0 input (sclks = 1: falling edge) txd0 inttx0 interrupt transmit data write timing
TMP1941AF 2003-03-27 TMP1941AF-187 (2) receive operations in sclk output mode, each time the cpu picks up the character in receive buffer 2, the synchronization clock is driven out from the sclk0 pin to shift the next character into receive buffer 1. when a whole 8-bit character has been loaded into receive buffer 1, it is transferred to receive buffer 2, and the receive-done interrupt (intrx0) is generated. the sclk output is initiated by setting the sc0mod0.rxe bit to 1. figure 13.31 receive operation in i/o interface mode (sclk0 output mode) in sclk input mode, the cpu must pick up the character in the receive buffer 2 before the sclk0 input is activated to shift the next character into receive buffer 1. when a whole 8-bit character has been loaded into receive buffer 1, it is transferred to receive buffer 2, and the receive-done interrupt (intrx0) is generated. the cpu must read the character in receive buffer 2 by point a. until that is done, the receiver is not ready to accept the next character. in case the cpu reads the character in receiver buffer 2 after point a, reception of the next character begins at that point, causing the received data to be corrupted. for system applications in which the cpu might not be able to keep pace with incoming data streams, handshaking is required. figure 13.32 receive operation in i/o interface mode (sclk0 input mode) note: regardless of whether sclk is in input mode or output mode, the receiver must be enabled by setting the sc0mod.rxe bit to 1 in order to perform receive operations. bit 0 bit 6 bit 7 bit 1 bit 0 sclk0 output rxd0 inttx0 interrupt receive data read timing bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 a sclk0 input ( sclks = 0: risin g ed g e ) rxd0 intrx0 interrupt sclk0 input (sclks = 1: falling edge) receive data read timing
TMP1941AF 2003-03-27 TMP1941AF-188 (3) full-duplex transmit/receive operations setting the sc0mod1.fdpx0 bit enables full-duplex communication. in this mode of operation, the double-buffering is enabled. when receive buffer 1 is filled with an 8-bit character, it is transferred to receive buffer 2 (sc0buf), and the receive-done interrupt (intrx0) is generated. while an 8-bit character is being received, an 8-bit character can be transmitted from the txd0 pin simultaneously. when a whole 8-bit character has been shifted out, the transmit- done interrupt (inttx0) is generated. in sclk output mode, loading the transimit buffer with a character restarts the transmit/receive operation. the cpu must pick up the received character before the next character fills receive buffer 1. otherwise, the latter character is discarded. (the previous character is preserved. transmission proceeds with no error.) figure 13.33 full-duplex transmit/receive operation in i/o interface mode (sclk0 output mode) in sclk input mode, the cpu must write a character to be transmitted into the transmit buffer by point a. no transimi/receive operation occurs until the transmit buffer is filled. in case the transmit buffer is loaded after point a, the transmit/receive operation begins at that point, causing the transimit/receive data to be corrupted. for system applications in which transmit underrun conditions could occur, handshaking is required. figure 13.34 full-duplex transmit/receive operation in i/o interface mode (sclk0 input mode) ? restrictions on sclk configured as an input in i/o interface mode, the cpu may be unable to access the receive or transmit buffer fast enough to support back-to-back transfers. when sclk is configured as an output, one or more wait cycles are automatically inserted to prolong the sclk intervals. however, when sclk is sclk0 output txd0 inttx0 interrupt transmit data write timing intrx0 interrupt rxd0 bit 0 bit 6 bit 7 bit 1 bit 0 bit 5 bit 1 bit 0 bit 6 bit 7 bit 1 bit 0 bit 5 bit 1 receive data read timing bit 0 bit 6 bit 7 bit 1 bit 0 bit 5 bit 1 bit 0 bit 6 bit 7 bit 1 bit 0 bit 5 bit 1 a a sclk0 output txd0 inttx0 interrupt transmit data write timing intrx0 interrupt rxd0 receive data read timing
TMP1941AF 2003-03-27 TMP1941AF-189 configured as an input, the sclk input must be delayed by external hardware so that the cpu can keep pace with the data rate. generally, the wait period is a function of the fsys frequency and the data rate. the following figure gives some indication of the relationsip between sclk and fsys frequencies for different wait periods. in reality, processing load during transfers also affect the maximum sclk frequency. 0 10 20 30 0 0.5 1.0 1.5 2.0 mhz sufficient wait period wait period of one sclk cycle wait period of one-half sclk cycle no wait (free-running sclk) sclk frequency mhz fsys 40 note: the above figure assumes that the dmac is utilized for reads of the receive buffer and writes of the transmit buffer. 13.4.2 mode 1 (7-bit uart mode) setting the sm[1:0] field in the sc0mod0 to 01 puts the sio0 in 7-bit uart mode. in this mode of operation, the parity bit can be added to the transmitted character, and the receiver can perform a parity check on incoming data. parity can be enabled and disabled through the programming of the pe bit in the sc0cr. when pe = 1, the scr0cr.even bit selects even or odd parity. example: transmitting 7-bit uart characters with an even-parity bit clocking conditions: system clock: high-speed (fc) high-speed clock gear: ? 1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) settings in the main routine 76543210 p9cr ??????? 1 p9fc ??????? 1 configures the p90 pin as txd0. sc0mod x0 ? x0101 selects 7-bit uart mode. sc0cr x11xxx00 selects even parity. br0cr 00101010 sets the transfer rate to 2400 bps. imcclh ?? 110100 enables the inttx0 interrupt and sets its priority level to 4. sc0buf ******** loads the transmit buffer with a character. transmit-done interrupt routine intclr xx110001 clears the interrupt request. interrupt processing end of interrupt processing x = don?t care, ? = no change goes out first (transfer rate = 2400 bps @fc = 24.576 mhz) start bit 0 1 2 3 5 46 even parity stop
TMP1941AF 2003-03-27 TMP1941AF-190 13.4.3 mode 2 (8-bit uart mode) setting the sm[1:0] field in the sc0mod0 to 10 puts the sio0 in 8-bit uart mode. in this mode of operation, the parity bit can be added to the transmitted character, and the receiver can perform a parity check on incoming data. parity can be enabled and disabled through the programming of the pe bit in the sc0cr. when pe = 1, the scr0cr.even bit selects even or odd parity. example: transmitting 8-bit uart characters with an odd-parity bit clocking conditions: system clock: high-speed (fc) high-speed clock gear: ? 1 (fc) prescaler clock: fperiph/4 (fperiph = fsys) settings in the main routine 76543210 p9cr ?????? 0 ? configures p91 (rxd0) to be an input. sc0mod ? 01x1001 selects 8-bit uart mode and enables the receiver. sc0cr x01xxx00 selects odd parity. br0cr 00010101 sets the transfer rate to 9600 bps. imccll ?? 110100 enables the intrx0 interrupt and sets its priority level to 4. example of interrupt routine processing 76543210 intclr xx110000 clears the interrupt request. reg. sc0cr and 0x1c if reg. 0 then error checks for errors. reg. sc0buf end of interrupt processing x = don?t care, ? = no change 13.4.4 mode 3 (9-bit uart mode) setting the sm[1:0] field in the sc0mod0 to 11 puts the sio0 in 9-bit uart mode. in this mode, a parity bit cannot be used; thus, parity should be disabled by clearing the sc0cr.pe bit to 0. for transmit operations, the most-significant bit (9th bit) is stored in the tb8 bit in the sc0mod0. for receive operations, the most-significant bit is stored in the rb8 bit in sc0cr. reads and writes of the transmit/receive character must be done with the most-significant bit first, followed by the sc0buf. wake-up feature in 9-bit uart mode, the receiver wake-up feature allows the slave station in a multidrop system to wake up whenever an address character is received. setting the sc0mod0.wu bit enables the wake-up feature. when the sc0cr.rb8 bit has received an address/data flag bit set to 1, the receiver generates the intrx0 interrupt. goes out first (transfer rate = 9600 bps @fc = 24.576 mhz) start bit 0 1 2 3 5 46 odd parity stop
TMP1941AF 2003-03-27 TMP1941AF-191 note: the slave controller?s txd pin must be configured as an open-drain output by programming the ode register. figure 13.35 serial link using the wake-up function protocol (1) put all the master and slave controllers in 9-bit uart mode. (2) enables the receiver in each slave controller by setting the sc0mod0.wu bit to 1. (3) the master controller transmits an address character (i.e, select code) that identifies a slave controller. the address character has the most-significant bit (bit 8) set to 1. (4) each slave controller compares the received address to its station address and clears the wu bit if they match. (5) the master controller transmits data characters or block of data to the selected slave controller (with sc0mod0.wu bit cleared). data characters have the most-significant bit (bit 8) cleared to 0. (6) slave controllers not addressed continue to monitor the data stream, but discard any characters with the most-significant bit (rb8) cleared, and thus does not generate receive-done interrupts (intrx0). the addressed slave controller with its wu bit cleared can transmit data to the master controller to notify that it has successfully received the message. txd master slave 1 slave 2 slave 3 rxd txd rxd txd txd rxd rxd slave controller select code startbit 0123 5 46 stop 78 ?1? data ?0? startbit 0123 5 46 stop 7bit 8
TMP1941AF 2003-03-27 TMP1941AF-192 example: connecting a master station with two slave stations through a serial link using the fsys/2 clock as a serial clock ? master controller settings main routine 76543210 p9cr ?????? 01 p9fc ?????? x1 configures the p90 pin as txd0 and the p91 pin as rxd0 imccll ? ? 110101 enables intrx0 and sets its interrupt level to 5. imcclh ? ? 110100 enables inttx0 and sets its interrupt level to 4. sc0mod0 10101110 selects 9-bit uart mode and selects fsys/2 as a serial clock. sc0buf 00000001 loads the select code for slave 1. interrupt routine (inttx0) intclr xx110001 clears the interrupt request. sc0mod0 0 ??????? clears the tb0 bit to 0. sc0buf ******** loads the transmit data. end of interrupt processing ? slave controller settings main routine 76543210 p9cr ?????? 01 p9fc ?????? x1 ode xx ????? 1 configures the p90 pin as txd (open-drain output) and the p91 pin as rxd. imccll ? ? 110110 enables inttx0 and intrx0. imcclh ? ? 110101 sc0mod0 00111110 selects 9-bit uart mode, selects fsys/2 as the serial clock and and sets the wu bit to 1. interrupt routine (intrx0) intclr xx110000 clears the interrupt request. reg. sc0buf if reg. = select code then sc0mod0 ? ? ? 0 ???? clears the wu bit to 0. txd master slave 1 slave 2 select code 0x0000_0001 rxd txd rxd txd rxd select code 0x0000_1010
TMP1941AF 2003-03-27 TMP1941AF-193 14. serial bus interface (sbi) the TMP1941AF contains a serial bus interface (sbi) channel, which has the following two operating modes: ? i 2 c bus mode (with multi-master capability) ? clock-synchronous 8-bit sio mode in i 2 c bus mode, the sbi is connected to external devices via two pins, pa6 (sda) and pa7 (scl). in clock-synchronous 8-bit sio mode, the sbi is connected to external devices via three pins, pa5 (sck), pa6 (so) and pa7 (si). the following table shows the programming required to put the sbi in each operating mode. ode.odea7 thru ode.odea6 pacr.pa7c thru pacr.pa5c pafc.pa7f thru pafc.pa5f i 2 c bus mode 11 11x 110 clock-synchronous 8-bit sio mode xx 011 010 111 x = don?t care note: with the tmp1940fdbf with flash memory, the sbi is unusable when the dsu feature is enabled. 14.1 block diagram figure 14.1 sbi block diagram i 2 c bus clock synchro- nization / control noise canceller shift register sbi0cr2/ sbi0sr sbi0dbr ints2 interrupt request t0 sbi control register 2 / sbi status register i 2 c bus address register sbi data buffer register sbi control register 1 sbi baud rate registers 0 and 1 sda so si scl sck pa5 pa6 pa7 (sck) (so/sda) (si/scl) sio clock control divider transfer control logic sbi0cr1 sbi0br0/1 i2c0ar noise canceller i 2 c bus data control sio data control input/ output control
TMP1941AF 2003-03-27 TMP1941AF-194 14.2 registers a listing of the registers used to control the sbi follows: ? serial bus interface control register 1 (sbi0cr1) ? serial bus interface control register 2 (sbi0cr2) ? serial bus interface data buffer register (sbi0dbr) ? i 2 c bus address register (i2c0ar) ? serial bus interface status register (sbi0sr) ? serial bus interface baud rate register 0 (sbi0br0) ? serial bus interface baud rate register 1 (sbi0br1) the functions of these registers vary, depending on the mode in which the sbi is operating. for a detailed description of the registers, refer to section 14.5, i 2 c bus mode configuration, and section 14.8, clock-synchronous 8-bit sio mode operation. 14.3 i 2 c bus mode data formats figure 14.2 shows the serial bus interface data formats used in i 2 c bus mode. (a) addressing format (b) addressing format (with repeated start condition) (c) free data format (master-transmitter to slave-receiver) s = start condition r/ w = direction bit ack = acknowledge bit p = stop condition figure 14.2 i 2 c-bus mode data formats s p data 8 bits 1 to 8 bits 1 to 8 bits data data a c k a c k a c k 11 1 once repeated ssp slave address once a c k a c k a c k a c k 8 bits 1 to 8 bits 11 11 8 bits 1 to 8 bits data data slave address repeated once r / w r / w repeated slave address data a c k p 8 bits 1 to 8 bits r / w 1 once repeated 1 to 8 bits a c k a c k data 11 s
TMP1941AF 2003-03-27 TMP1941AF-195 14.4 description of the registers used in i 2 c bus mode this section provides a summary of the registers which control i 2 c bus operation and provide i 2 c bus status information for bus access/monitoring. serial bus interface control register 1 76543210 name bc2 bc1 bc0 ack ? sck2 sck1 sck0/ swrmon read/write w r/w ? wr/w reset value0000 ? 001 function number of bits per transfer (note 1) ack clock pulse 0: no ack 1: ack internal scl output clock frequency (note 2) / software reset monitor on writes: sck[2:0] = internal scl output clock frequency 000 001 010 011 100 101 110 111 n=4 n=5 n=6 n=7 n=8 n=9 n=10 500 khz 278 khz 147 khz 75.8 khz 38.5 khz 19.4 khz 9.73 khz reserved assumptions: system clock: fc (= 40 mhz) clock gear: fc/1 t0 = fperiph/4 (= 10 mhz) frequency = 4 + 2 0 t n (hz) on reads: swrmon = software reset monitor 0 software reset operation is in progress. 1 software reset operation is not in progress. number of bits per transfer ack = 0 ack = 1 bc [2:0] # of clock cycles data length # of clock cycles data length 000 001 010 011 100 101 110 111 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 9 2 3 4 5 6 7 8 8 1 2 3 4 5 6 7 note 1: clear the bc[2:0] field to 000 before switching the operating mode to clock-synchronous 8-bit sio mode. note 2: for details on the scl bus clock frequency, refer to section 14.5.3, serial clock. figure 14.3 i 2 c bus mode registers (1) sbi0cr1 (0x ffff_f240)
TMP1941AF 2003-03-27 TMP1941AF-196 serial bus interface control register 2 76543210 name mst trx bb pin sbim1 sbim0 swrst1 swrst0 read/write w w (note 1) w (note 1) reset value00010000 function master/ slave 0: slave 1: master transmit/ receive 0: receive 1: transmit start / stop generation 0: stop condition 1: start condition ints2 interrupt clear 0: don?t care 1: interrupt clear operating mode (note 2) 00: port mode 01: sio mode 10: i 2 c bus mode 11: reserved software reset a write of 10 followed by a write of 01 operating mode (note 2) 00 port mode (serial bus interface output disabled) 01 clock-synchronous 8-bit sio mode 10 i 2 c bus mode 11 reserved note 1: reading this register causes it to function as a status register (sbi0sr). see the next page. note 2: ensure that the bus is free before switching the operating mode to port mode. ensure that the port is at logic high before switching from port mode to i 2 c bus or sio mode. figure 14.4 i 2 c bus mode registers (2) table 14.1 prescalar output clock ( t0) resolutions @fc = 40 mhz prescalar output clock resolution peripheral clock select syscr1.fpsel clock gear value syscr1.gear[1:0] prescalar clock select syscr0.prck[1:0] t0 00 (fperiph/4) fc/2 2 (0.1 s) 01 (fperiph/2) ? 00 (fc) 10 (fperiph) ? 00 (fperiph/4) fc/2 3 (0.2 s) 01 (fperiph/2) ? 01 (fc/2) 10 (fperiph) ? 00 (fperiph/4) fc/2 4 (0.4 s) 01 (fperiph/2) ? 10 (fc/4) 10 (fperiph) ? 00 (fperiph/4) fc/2 5 (0.8 s) 01 (fperiph/2) ? 0 (fgear) 11 (fc/8) 10 (fperiph) ? 00 (fperiph/4) fc/2 2 (0.2 s) 01 (fperiph/2) ? 00 (fc) 10 (fperiph) ? 00 (fperiph/4) ? 01 (fperiph/2) ? 01 (fc/2) 10 (fperiph) ? 00 (fperiph/4) ? 01 (fperiph/2) ? 10 (fc/4) 10 (fperiph) ? 00 (fperiph/4) ? 01 (fperiph/2) ? 1 (fc) 11 (fc/8) 10 (fperiph) ? note: the ? character means ?don?t use.? sbi0cr2 (0xffff_f243)
TMP1941AF 2003-03-27 TMP1941AF-197 serial bus interface status register 76543210 name mst trx bb pin al aas ad0 lrb read/write r reset value00010000 function master/ slave 0: slave 1: master transmit/ receive 0: receive 1: transmit i 2 c bus status 0: free 1: busy ints2 interrupt status 0: asserted 1: not asserted arbitration lost 0: ? 1: detected addressed as slave 0: ? 1: detected address 0 (general call) 0: ? 1: detected last received bit 0: 0 1: 1 last received bit 0 the last bit received was 0. 1 the last bit received was 1. addressed as slave 0 ? 1 the address on the bus matches the i2coar or general-call address (slave receiver mode only) arbitration lost 0 ? 1 arbitration was lost to another master. note: writing to this register causes it to function as a control register (sbi0cr2). see the previous page. figure 14.5 i 2 c bus mode registers (3) sbi0sr (0xffff_f243)
TMP1941AF 2003-03-27 TMP1941AF-198 serial bus interface baud rate register 0 76543210 name ? i2sbi0 ?????? read/write ? r/w ????? w reset value ? 0 ?????? function idle 0: off 1: on must be written as 0. sbi on/off in idle mode 0off 1on serial bus interface baud rate register 1 76543210 name p4en ??????? read/write r/w ??????? reset value 0 ??????? function internal clock 0: off 1: on controls the iternal baud rate generator 0off 1on serial bus interface data buffer register 76543210 name db7 db6 db5 db4 db3 db2 db1 db0 read/write r (receive) / w (transmit) reset value undefined note: in transmitter mode, data must be written to this register, with bit 7 being the most-significant bit (msb). i 2 c bus address register 76543210 name sa6 sa5 sa4 sa3 sa2 sa1 sa0 als read/write w reset value00000000 function when the sbi is addressed as a slave, this field specifies a 7-bit i 2 c-bus address to which the sbi responds. address recognition mode address recognition mode 0 recognizes the slave address. 1 does not recognize the slave address. figure 14.6 i 2 c bus mode registers (4) sbi0dbr (0xffff_f241) i2c0ar (0xffff_f242) sbi0br0 (0xffff_f244) sbi0br1 (0xffff_f245)
TMP1941AF 2003-03-27 TMP1941AF-199 14.5 i 2 c bus mode configuration 14.5.1 acknowledgment mode setting the sbi0cr1.ack bit selects acknowledge mode. when operating as a master, the sbi generates a clock pulse for acknowledge automatically after each data. as a transmitter, the sbi releases the sda line during this acknowledge cycle so that the receiver of the data transfer can drive the sda line low to acknowledge receipt of the data. as a receiver, the sbi pulls the sda line low during the acknowledge cycle after each data has been received. clearing the sbi0cr1.ack bit selects non-acknowledge mode. when operating as a master, the sbi does not generate acknowledge clock pulses. 14.5.2 number of bits per transfer the sbi0cr1.bc[2:0] field specifies the number of bits of the next data item to be transmitted or received. after a reset, this field is cleared to 000, causing a 7-bit slave address and the data direction ( w / r ) bit to be transferred in a packet of eight bits. at other times, the sbi0cr1.bc[2:0] field keeps a previously programmed value. 14.5.3 serial clock (1) i 2 c bus clock source the sbi0cr1.sck[2:0] field controls the maximum frequency of the scl clock driven out on the scl pin in master mode, as illustrated below. t low = 2 n ? 1 / t0 t high = 2 n ? 1 / t0 + 4/ t0 fscl = 1/(t low + t high ) = 4 2 0 t n + figure 14.7 i 2 c bus clock source t high t low 1/fscl sbi0cr1.sck[2:0] n 000 001 010 011 100 101 110 4 5 6 7 8 9 10
TMP1941AF 2003-03-27 TMP1941AF-200 (2) clock synchronization clock synchronization is performed using the wired-and connection of all i 2 c-bus components to the bus. if two or more masters try to transfer messages on the i 2 c bus, the first to pull its clock line low wins the arbitration, overriding other masters producing a high on their clock lines. clock signals of two or more devices on the i 2 c-bus are synchronized to ensure correct data transfers. figure 14.8 shows a depiction of the clock synchronization mechanism for the i 2 c bus with two masters. figure 14.8 clock synchronization example at point a, master a pulls its internal scl level low, bringing the scl bus line low. the high- to-low transition on the scl bus line causes master b to reset its high-level counter and pulls its internal scl level low. master a completes its low period at point b. however, the low-to-high transition on its internal scl level does not change the state of the scl bus line if master b?s internal scl level is still within its low period. therefore, master a enters a high wait state, where it does not start counting off its high period. when master b has counted off its low period at point c, its internal scl level goes high, releasing the scl bus line (high). there will then be no difference between the internal scl levels and the state of the scl bus line, and both master a and master b start counting off their high periods. this way, a synchronized scl clock is generated with its high period determined by the master with the shortest clock high period and its low period determined by the one with the longest clock low period. 14.5.4 slave addressing and address recognition mode when the sbi is configured to operate as a slave, the sa[6:0] field in the i2c0ar must be loaded with the 7-bit i 2 c-bus address to which the sbi is to respond. the als bit must be cleared for the sbi to recognize the incoming slave address. 14.5.5 configuring the sbi as a master or a slave setting the sbi0cr2.mst bit configures the sbi as a master, and clearing it configures the sbi as a slave. this bit is cleared by hardware when a stop condition has been detected and when arbitration for the i 2 c bus has been lost. internal scl level (master a) internal scl level (master b) scl bus line counter reset wait state start counting high period abc
TMP1941AF 2003-03-27 TMP1941AF-201 14.5.6 configuring the sbi as a transmitter or a receiver the sbi0cr2.trx bit is set or cleared by hardware to configure the sbi as a transmitter or a receiver. as a slave, the sbi is put in either slave-receiver or slave-transmitter mode, depending on the value of the data direction ( w / r ) bit transmitted by the master. when the sbi is addressed as a slave, the trx bit reflects the value of the w / r bit. the trx bit is set or cleared on the following occasions: ? when transferring data using addressing format ? when the received slave address matches the value in i2c0cr ? when a general-call address is received; i.e., the eight bits following the start condition are all zeros. as a master, the sbi is put in either master-transmitter or a master-receiver mode upon reception of an acknowledge from an addressed slave. the trx bit changes to the opposite value of the w / r bit sent by the sbi. if the sbi does not receive an acknowledge from a slave, the trx bit retains the previous value. the trx bit is cleared by hardware when a stop condition has been detected and when arbitration for the i 2 c bus has been lost. 14.5.7 generating start and stop conditions when the sbi0sr.bb bit is cleared, the bus is free. at this time, writing 1s to the mst, trx, bb and pin bits in the sbi0cr2 causes the sbi to generate a start condition on the bus and shift out 8- bit i 2 c-bus data. before generating a start condition, the ack bit must be set to 1. figure 14.9 generating a start condition and a slave address when the sbi0sr.bb bit is set, the bus is busy. when sbi0sr.bb=1, writing 1s to the mst, trx and pin bits and a 0 to the bb bit causes the sbi to start a sequence for generating a stop condition on the bus to abort the transfer. the mst, trx, bb and pin bits should not be altered until a stop condition appears on the bus. figure 14.10 generating a stop condition the bb bit can be read to determine if the i 2 c bus is in use. the bb bit is set when a start condition is detected and cleared when a stop condition is detected. scl line start condition a6 slave address and direction bit acknowledge signal 1 sda line 23456789 a5 a4 a3 a2 a1 a0 r/w stop condition scl line sda line
TMP1941AF 2003-03-27 TMP1941AF-202 14.5.8 asserting and deasserting interrupt requests when an sbi interrupt (ints2) is generated, the pending interrupt not (pin) bit in the sbi0cr2 is cleared to 0. while the pin bit is 0, the sbi pulls the scl line low. after transmission or reception of one data word on the i 2 c bus, the pin bit is automatically cleared. in transmitter mode, the pin bit is subsequently set to 1 each time the sbi0dbr is written. in receiver mode, the pin bit is set to 1 each time the sbi0dbr is read. it takes a period of t low for the scl line to be released after the pin bit is set. in address recognition mode (als=0), the pin bit is cleared when the sbi is addressed as a slave and the received slave address matches the value in the i2c0cr or is all 0s (i.e., a general call). a write of 1 by software sets the pin bit, but a write of 0 has no effect on this bit. 14.5.9 sbi operating modes the sbim[1:0] field in the sbi0cr2 is used to select an operating mode of the sbi. to configure the sbi for i 2 c bus mode, set the sbim[1:0] field to 10. a switch to port mode should only be attempted when the bus is free. 14.5.10 lost-arbitration detection monitor the i 2 c bus is a multi-master bus and has an arbitration procedure to ensure correct data transfers. a master may start a transfer only if the bus is free. a master that attempts to generate a start condition while the bus is busy loses bus arbitration, with no start condition occurring on the sda and scl lines. the i 2 c-bus arbitration takes place on the sda line. figure 14.11 shows the arbitration procedure for two masters. up until point a, the internal data levels of master a and master b are the same. at point a master b?s internal data level makes a low-to-high transition while master a?s internal data level remains at logic low. however, the sda bus line is held low because it is the wired-and of the two data outputs. when the scl bus clock goes high at point b, the addressed slave device reads the data transmitted by master a (i.e., winning master). master b loses arbitration and switches off its data output stage, releasing its sda line (high), so that it does not affect the data transfer initiated by the winning master. in case two competing masters have transmitted exactly the same first data word, the arbitration procedure continues with the second data word. figure 14.11 arbitration procedure of two masters master b loses arbitration and connects a high output level to the bus. scl bus line internal sda level (master a) internal sda level (master b) sda bus line ab
TMP1941AF 2003-03-27 TMP1941AF-203 a master compares its internal data level to the actual level on the sda line at the rising edge of the scl clock. the master loses arbitration if there is a difference between these two values. the losing master sets the al bit in the sbi0sr to 1, which causes the mst and trx bits in the same register to be cleared. that is, the losing master switches to slave-receiver mode. the al bit is subsequently cleared when data is written to or read from the sbi0dbr and when the sbi0cr2 is programmed with new parameters. figure 14.12 master b loses arbitration (d7a ? d7b, d6a ? d6b) 14.5.11 slave address match monitor when acting as a slave-receiver, the als bit in the i2c0cr determines whether the sbi recognizes the incoming slave address or not. in address recognition mode (i.e., als=0), the addressed-as-slave (aas) bit in the sbi0sr is set when an incoming address over the i 2 c bus matches the value in the i2c0cr or when the general-call address has been received. when als=1, the aas bit is set when the first data word has been received. the aas bit is cleared each time the sbi0dbr is read or written. 14.5.12 general-call detection monitor when acting as a slave receiver, the ad0 bit in the sbi0sr is set when a general-call address has been received. the general-call address is detected when the eight bits following a start condition are all zeros. the ad0 bit is cleared when a start or stop condition is detected on the bus. 14.5.13 last received bit monitor the lrb bit in the sbi0sr holds the value of the last bit received over the sda line at the rising edge of the scl clock. in acknowledge mode, reading this bit immediately after generation of the ints2 interrupt returns the value of the ack signal. al mst trx clock output stops here 1 internal sda level is held high because master b has lost arbitration. access to the sbi0dbr or sbi0cr2 internal scl level internal sda level internal sda level internal scl level master a master b 23456789 1234 d7a d6b d5a d4a d3a d2a d1a d0a d7a? d6a? d5a? d4a? 1234 d7b d6a
TMP1941AF 2003-03-27 TMP1941AF-204 14.5.14 software reset the sbi provides a software reset, which permits recovery from system lockups caused by external noise. a software reset is performed by a write of 10 followed by a write of 01 to the swrst[1:0] field in the sbi0cr2. after a software reset, all control and status register bits are initialized to their reset values. upon resetting the sbi, the swrst[1:0] field is automatically cleared to 00. note: a software reset causes the sbi operating mode to switch from i 2 c bus mode to port mode. this does not affect the port a function register, however. 14.5.15 serial bus interface data buffer register (sbi0dbr) the sbi0dbr is a data buffer interfacing to the i 2 c bus. all read and write operations to/from the i 2 c bus are done via this register. when the sbi is acting as a master, loading this register with a slave address and a data direction bit causes a start condition to be generated. 14.5.16 i 2 c bus address register (i2c0ar) when the sbi is configured as a slave, the sa[6:0] field in the i2c0ar must be loaded with the 7-bit i 2 c-bus address to which the sbi is to respond. if the als bit in the i2c0ar is cleared, the sbi recognizes a slave address transmitted by the master device, interpreting incoming frame structures as per addressing format. if the als bit is set, the sbi does not recognize a slave address and interprets all frame structures as per free data format. 14.5.17 baud rate register 1 (sbi0dbr1) before the i 2 c bus can be used, the p4en bit in the sbi0br1 must be set to enable the sbi internal baud rate generation logic. 14.5.18 baud rate register 0 (sbi0br0) the i2sbi0 bit in the sbi0br0 determines whether the sbi is shut down or not when the TMP1941AF is put in idle standby mode. this register must be programmed before executing an instruction for entering a standby mode.
TMP1941AF 2003-03-27 TMP1941AF-205 14.6 programming sequences in i 2 c bus mode 14.6.1 sbi initialization first, program the p4en bit in the sbi0br1, and the ack and sck[2:0] bits in the sbi0cr1. set the sbi0br1.p4en bit to 1 to enable the internal baud rate generation logic. write 0s to bits 7?5 and bit 3 in the sbi0cr1. next, program the i2c0ar. the sa[6:0] field in the i2c0ar defines the chip?s slave address, and the als bit (bit 0) selects an address recognition mode. (the als bit must be cleared when using the addressing format.) next, program the sbi0cr2 to initially configure the sbi in slave-receiver mode; i.e., clear the mst, trx and bb bits to 0, set the pin bit to 1 and set the sbim[1:0] field to 10. write 00 to the swrst[1:0] field. 76543210 sbi0br1 enable internal baud rate generator. sbi0cr1 disable generation of ack and select scl clock frequency. i2c0ar load a slave address and selects address recognition mode. sbi0cr2 configure the sbi in slave-receiver mode. note: x = don?t care 14.6.2 generating a start condition and a slave address (1) master mode in master mode, the following steps are required to generate a start condition and a slave address on the i 2 c-bus. first, ensure that the bus is free (i.e., sbi0cr2.bb = 0). next, set the ack bit in the sbi0cr1 to enable generation of acknowledge clock pulses. then, loads the sbi0dbr with a slave address and a data direction bit to be transmitted via the i 2 c bus. when bb=0, writing 1s to the mst, trx, bb and pin bits in the sbi0cr2 causes a start condition to be generated on the bus. following a start condition, the sbi generates scl clock pulses nine times: the sbi shifts out the contents of the sbi0dbr with the first eight scl clocks, and releases the sda line during the last (i.e., ninth) scl clock to receive an acknowledgement signal from the addressed slave. the ints2 interrupt request is generated on the falling edge of the ninth scl clock pulse, and the pin bit in the sbi0cr2 is cleared to 0. in master mode, the sbi holds the scl line low while the pin bit is 0. upon interrupt, the trx bit either remains set or is cleared according to the value of the transmitted direction bit, provided an acknowledgement signal has been returned from the slave. settings in main routine 76543210 reg. sbi0sr reg. reg. & 0x20 if reg. 0x00 ensure that the bus is free. then sbi0cr1 xxx10xxx select acknowledgement mode. sbi0dbr xxxxxxxx load the slave address and a data direction bit. sbi0cr2 11111000 generate a start condition. ints2 interrupt routine intclr 0x34 clear the interrupt request. interrupt processing end of interrupt
TMP1941AF 2003-03-27 TMP1941AF-206 (2) slave mode in slave mode, the following steps are required to receive a start condition and a slave address via the i 2 c bus. upon detection of a start condition, the sbi clocks in a 7-bit slave address and a data direction bit transmitted by the master during the first eight scl clock pulses. if the received slave address matches its own address in the i2c0ar or is equal to the general-call address (00h), the sbi pulls the sda line low during the last (i.e., ninth) scl clock for acknowledgement. the ints2 interrupt request is generated on the falling edge of the ninth scl clock pulse, and the pin bit in the sbi0cr2 is cleared to 0. in slave mode, the sbi holds the scl line low while the pin bit is 0. note: the user can only use a dma transfer: - when there is only one master and only one slave on the i 2 c bus; and - continuous transmission or reception is possible. figure 14.13 generation of a start condition and a slave address 14.6.3 transferring a data word each time a data word has been transmitted or received, the ints2 interrupt is generated. it is the responsibility of the ints2 interrupt service routine to test the mst bit in the sbi0cr to determine whether the sbi is in master or slave mode. (1) master mode (sbi0cr2.mst = 1) if the mst bit in the sbi0cr2 is set, then test the trx bit in the same register to determine whether the sbi is in master-transmitter or master-receiver mode. master-transmitter mode (sbi0cr2.trx = 1) test the lrb bit in the sbi0sr. if the lrb bit is set, that means the slave-receiver requires no further data to be sent from the master-transmitter. the master-transmitter must then generate a stop condition as described later to stop transmission. if the lrb bit is cleared, that means the slave-receiver requires further data. if the number of bits per transfer is 8, then write the transmit data into the sbi0dbr. when using other data length, program the bc[2:0] and ack bits in the sbi0cr1, and then write the transmit data into the sbi0dbr. when the sbi0dbr is loaded, the pin bit in the sbi0sr is set to 1, and the transmit data is shifted out from the sda pin, clocked by the scl clock. once the transfer is complete, the ints2 interrupt is generated, the pin bit is cleared, and the scl line is pulled low. to transmit further data, test the lrb bit again and repeat the above procedure. scl start condition a6 slave address + direction bit acknowledgment from slave 1 sda 23456789 a5 a4 a3 a2 a1 a0 w r/ pin bit ints2 interrupt request ack master to slave slave to master
TMP1941AF 2003-03-27 TMP1941AF-207 ints2 interrupt if mst = 0 then go to slave-mode processing if trx = 0 then go to receiver-mode processing if lrb = 0 then go to processing for generating a stop condition sbi0dbr xxxxxxxx set number of bits to be transmitted and specify whether ack is required. sbi0dbr load the transmit data. end of interrupt processing x = don?t care figure 14.14 sbi0cr1.bc[2:0] = 000 and sbi0cr1.ack = 1 (master-transmitter mode) master-receiver mode (sbi0cr2.trx = 0) if the number of bits per transfer is 8, read the sbi0dbr. when using other data length, program the bc[2:0] and ack bits in the sbi0cr1, and then read the sbi0dbr. the first read of the sbi0dbr is a dummy read because data has not yet been received. a dummy read returns an undefined value. upon this read, the scl line is released, the pin bit in the sbi0sr is set, and the scl clock is driven out to receive a data word into the sbi0dbr. the master-transmitter generates an acknowledgement signal (i.e., a low level) on the sda line following the last received bit. figure 14.15 sbi0cr1.bc[2:0] = 000 and sbi0cr1.ack = 1 (master-receiver mode) to prepare to terminate the data transfer, the master-receiver must clear the ack bit in the sbi0cr1 immediately before the read of the second to last data word. this causes an acknowledge clock pulse not to be generated on the last data word. when the transfer is complete, the ints2 interrupt is generated. after interrupt processing, the ints2 interrupt handler must set the bc[2:0] field in the sbi0cr1 to 001 and read the sbi0dbr, ints2 interrupt request scl pin write to sbi0dbr d7 acknowledgement signal from receiver 1 sda pin 23456789 d6 d5 d4 d3 d2 d1 pin bit ack master to slave slave to master d0 scl d7 acknowledgement signal to transmitter 1 sda 23456789 d6 d5 d4 d3 d2 d1 pin bit ints2 interrupt request ack master to slave slave to master d0 read of the received data. next d7
TMP1941AF 2003-03-27 TMP1941AF-208 so that a clock is generated on the scl line once. with the ack bit cleared, the master-receiver holds the sda line high, which signals the end of transfer to the slave-transmitter. then, the sbi generates the ints2 interrupt again, whereupon the ints2 interrupt service routine must generate a stop condition to stop communication via the i 2 c bus. figure 14.16 terminating data transmission in master-receiver mode example: when receiving n data words ints2 interrupt (after data transmission) 76543210 sbi0cr1 xxxx0xxx set the number of bits to be received and specify whether ack is required. reg. sbi0dbr dummy read end of interrupt ints2 interrupt (first to (n-2)th data reception) 76543210 reg. sbi0dbr read the first to (n-2)th data words. end of interrupt ints2 interrupt ((n-1)th data reception) 76543210 sbi0cr1 xxx00xxx disable generation of acknowledgement clock. reg. sbi0dbr read the (n-1)th data word. end of interrupt ints2 interrupt (nth data reception) 76543210 sbi0cr1 00100xxx generate a clock once. reg. sbi0dbr read the nth data word. end of interrupt ints2 interrupt (after completing data reception) 76543210 sbi0cr1 generate a clock once. reg. sbi0dbr read the nth data word. end of interrupt x = don?t care scl d7 negative acknowledge (high) to transmitter 1 sda 23456781 d6 d5 d4 d3 d2 d1 pin bit ints2 interrupt request master to slave slave to master d0 read out the received data after clearing the sbi0cr1.ack bit. 9 read out the received data after setting the sbi0cr1.bc[2:0] field to 001.
TMP1941AF 2003-03-27 TMP1941AF-209 (2) slave mode (sbi0cr2.mst = 0) if the mst bit in the sbi0cr2 is cleared, the sbi is in slave mode. in slave mode, the sbi generates the ints2 interrupt on four occasions: 1) when the sbi has received any slave address; 2) when the sbi has received a general-call address; 3) when the received slave address matches its own address in the i2c0ar; and 4) when a data transfer has been completed in response to a general-call. also, if the sbi, as a master, loses arbitration for the i 2 c bus, it switches to slave mode. if arbitration is lost during a data transfer, scl continues to be generated until the data word is complete; then the ints2 interrupt is generated. when the ints2 interrupt occurs, the pin bit in the sbi0sr is cleared, and the scl line is pulled low. when the sbi0dbr is read or written or when the pin bit is set back to 1, the scl line is released after a period of t low . processing to be done in slave mode varies, depending on whether or not the sbi has switched over to slave mode as a result of lost arbitration. test the al, trx, aas and ad0 bits in the sbi0sr to determine the processing required, as summarized in table 14.2. example: when the received slave address matches the sbi?s own address and the data direction ( w / r ) bit is 1 ints2 interrupt if trx = 0 then go to other processing if al = 1 then go to other processing if aas = 0 then go to other processing sbi0cr1 xxx10xxx set the number of bits to be transmitted. sbi0dbr xxxx0xxx load the transmit data. x = don?t care
TMP1941AF 2003-03-27 TMP1941AF-210 table 14.2 processing in slave mode trx al aas ad0 state processing 1 1 0 arbitration was lost while the slave address was being transmitted, and the sbi received a slave address with the direction bit set transmitted by another master. 1 0 in slave-receiver mode, the sbi received a slave address with the direction bit set transmitted by the master. set the sbi0cr1.bc[2:0] field to the number of bits in a data word and write the transmit data into the sbi0dbr. 1 0 0 0 in slave-transmitter mode, the sbi has completed a transmission of one data word. test the sbi0sr.lrb bit. if the lrb bit is set, that means the master-receiver does not require further data. set the sbi0cr2.pin bit to 1 and clear the trx bit to 0 to release the bus. if the lrb bit is cleared, that means the master-receiver requires further data. set the sbi0cr1.bc[2:0] field to the number of bits in the data word and write the transmit data to the sbi0dbr. 1 1/0 arbitration was lost while a slave address was being transmitted, and received either a slave address with the direction bit cleared or a general-call address transmitted by another master. 1 0 0 arbitration was lost while a slave address or a data word was being transmitted, and the transfer terminated. 11/0 in slave-receiver mode, the sbi received either a slave address with the direction bit cleared or a general-call address transmitted by the master. read the sbi0dbr (a dummy read) to set the sbi0cr2.pin bit to 1, or write a 1 to this bit. 0 0 0 1/0 in slave-receiver mode, the sbi has completed a reception of a data word. set the sbi0cr1.bc[2:0] field to the number of bits in the data word and read the received data from the sbi0dbr. 14.6.4 generating a stop condition when the sbi0sr.bb bit is set, setting the mst, trx and pin bits in the sbi0cr2 to 1 and clearing the bb bit in the same register causes the sbi to start a sequence for generating a stop condition on the i 2 c bus. do not alter the contents of these bits until the stop condition is present on the bus. if another device is holding down the scl bus line, the sbi waits until the scl line is released (high) again; when scl is high, the sbi drives the sda pin high to generate a stop condition. 76543210 sbi0cr2 generate a stop condition. figure 14.17 generating a stop condition scl pin sda pin pin bit bb bit (read) stop condition 1 mst 1 trx 0 bb 1 pin
TMP1941AF 2003-03-27 TMP1941AF-211 14.6.5 repeated start condition a data transfer is always terminated by a stop condition. however, if a master still wishes to communicate on the bus, it can generate a repeated start condition and address another slave or change the data direction without first generating a stop condition. the following describes the steps required to generate a repeated start condition. first, clear the mst, trx and bb bits in the sbi0cr2 and set the pin bit in the same register to release the bus. this causes the sda pin to be held high and the scl pin to be released. because no stop condition is generated on the bus, other devices think that the bus is busy. then, poll the sbi0sr.bb bit until it is cleared to ensure that the scl pin is released. next, poll the lrb bit until it is set to ensure that no other device is pulling the scl bus line low. once the bus is determined to be free this way, use the steps described in section 14.6.2 to generate a start condition. to satisfy the minimum setup time of the start condition, in standard-mode, at least 4.7- s wait period must be created by software after the bus becomes free. 76543210 sbi0cr2 release the bus. if sbi0sr 0 check that the scl pin is released. then if sbi0sr 1 check that no other device is pulling the scl line low. then 4.7- s wait sbi0cr1 xxx10xxx select acknowledge mode. sbi0dbr xxxxxxxx load a slave address and the direction bit. sbi0cr2 11111000 generate a start condition. x = don?t care figure 14.18 repeated start condition 0 mst 0 trx 0 bb 1 pin 1 mst 1 trx 1 bb 1 pin scl bus line scl pin sda pin lrb bit 4.7 s (min) start condition bb bit pin bit 9
TMP1941AF 2003-03-27 TMP1941AF-212 14.7 description of registers used in clock-synchronous 8-bit sio mode this section provides a summary of the registers which control clock-synchronous 8-bit sio operation and provides its status information for monitoring. serial bus interface control register 1 76543210 name sios sioinh siom1 siom0 ? sck2 sck1 sck0 read/write w ? wr/w reset value0000 ? 001 function start transfer 0: stop 1: start abort transfer 0: continue 1: abort transfer mode 00: transmit mode 01: reserved 10: transmit/receive mode 11: receive mode serial clock frequency / software reset monitor on writes: sck[2:0] = serial clock frequency 1.25 625 312.5 156.3 78.13 39.06 19.53 mhz khz khz khz khz khz khz 000 001 010 011 100 101 110 111 n = 3 n = 4 n = 5 n = 6 n = 7 n = 8 n = 9 ? external clock assumptions: system clock: fc (= 40 mhz) clock gear: fc/1 t0 = fperiph/4 (= 10 mhz) frequency = n 2 0 t (hz) note: clear the sios bit and set the sioinh bit before programming the transfer mode and serial clock frequency bits. serial bus interface data buffer register 76543210 name db7 db6 db5 db4 db3 db2 db1 db0 read/write r (receive)/ w (transmit) reset value undefined figure 14.19 sio mode registers (1) sbi0cr1 (0xffff_f240) sbi0dbr (0xffff_f241)
TMP1941AF 2003-03-27 TMP1941AF-213 serial bus interface control register 2 76543210 name ???? sbim1 sbim0 ?? read/write ???? w ?? reset value ???? 00 ?? function sbi operating mode 00: port mode 01: clock-synchronous 8-bit sio mode 10: i 2 c bus mode 11: reserved serial bus interface register 76543210 name ???? siof sef ?? read/write ???? r ?? reset value ???? 00 ?? serial transfer status shift operation status function 0: terminated 1: in progress serial bus interface baud rate register 0 76543210 name ? i2sbi0 ?????? read/write ? r/w ????? w reset value ? 0 ????? function idle 0: off 1: on must be written as 0. serial bus interface baud rate register 1 76543210 name p4en ??????? read/write r/w ??????? reset value 0 ??????? function internal clock 0: off 1: on must be written as 0. figure 14.20 sio mode registers (2) sbi0br0 (0xffff_f244) sbi0sr (0xffff_f243) sbi0br1 (0xffff_f245) sbi0cr2 (0xffff_f243)
TMP1941AF 2003-03-27 TMP1941AF-214 14.8 clock-synchronous 8-bit sio mode operation 14.8.1 serial clock (1) clock source the clock source for the sio mode can be selected from internal and external clocks through the programming of the sck[2:0] field in the sbi0cr1. ? internal clocks one of the seven internal clocks can be used as a serial clock, which is driven onto the sck pin. at the beginning of a transfer, the sck clock will start out at logic high. if software is slow and the reading of the received data or the writing of the transmit data can not keep up with the serial clock rate, the sbi automatically inserts a wait period, as shown below. during this period, the serial clock is temporarily stopped to suspend a shift operation. figure 14.21 automatic wait insertion ? external clock (sbi0cr1.sck[2:0] = 111) if the sck[2:0] field in the sbi0cr1 contains 111, the sbi uses an external clock supplied from the sck pin as a serial clock. for proper shift operations, the clock high width and the clock low width must satisfy the following relationship. figure 14.22 maximum external clock frequency sck output so output writes of the transmit data 3 17 2 8 12 678123 c 0 abc automatically inserted wait period a 0 a 1 a 2 a 5 a 6 a 7 b 0 b 5 b 6 b 7 c 1 c 2 b 1 b 4 t sckh t sckl , t sckh > 8/fsys sck pin t sckl
TMP1941AF 2003-03-27 TMP1941AF-215 (2) shift edge types in transmit mode, leading-edge shift is used. in receive mode, trailing-edge shift is used. ? leading-edge shift every bit of sio data is shifted by the leading edge of the serial clock (falling edge of sck). ? trailing-edge shift every bit of sio data is shifted by the trailing edge of the serial clock (rising edge of sck). figure 14.23 shift edge types bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 76543210 * 7654321 ** 765432 *** 76543 **** 7654 ***** 765 ****** 76 ****** 7 so pin sck pin shift register (a) leading-edge shift bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 6543210 * 543210 ** 0 ******* 10 ****** 210 ***** 3210 **** 43210 *** ******** 76543210 sck pin si pin shift register (b) trailing-edge shift
TMP1941AF 2003-03-27 TMP1941AF-216 14.8.2 sio transfer modes the sbi supports three sio transfer modes: receive mode, transmit mode and transmit/receive mode. the siom[1:0] field in the sbi0cr1 is used to select a transfer mode. (1) 8-bit transmit mode configure the sio interface in transmit mode and write the transmit data into the sbi0dbr. then setting the sios bit in the sbi0cr1 initiates a transmission. the contents of the sbi0dbr is moved to an internal shift register and then shifted out on the so pin, with the least-significant bit (lsb) first, synchronous to the serial clock. once the transmit data is transferred to the shift register, the sbi0dbr becomes empty, and the buffer-empty interrupt (ints2) is generated. in internal clock mode, the sio interface will be in wait state (sck will stop) until the ints2 interrupt service routine provides the next transmit data to the sbi0dbr. once the sbi0dbr is loaded, the sio interface will automatically get out of the wait state. in external clock mode, the ints2 interrupt service routine must provide the next transmit data to the sbi0dbr before the previous transmit data has been shifted out. therefore, the data rate is a function of the maximum latency between when the ints2 interrupt is generated and when the sbi0dbr is loaded by the interrupt service routine. at the beginning of a transmission, the value of the last bit of the previously transmitted byte appears on the so pin between when the sbi0sr.siof bit is set and when sck subsequently goes low. transmission can be terminated by the ints2 interrupt service routine clearing the sios bit to 0 or setting the sioinh bit to 1. if the sios bit is cleared, the remaining bits in the sbi0dbr continue to be shifted out before transmission ends. in this case, software can check the sbi0sr.siof bit to determine whether transmission has come to an end (0 = end-of-transmission). if the sioinh bit is set, the ongoing transmission is aborted immediately, and the siof bit is cleared at that point. in external clock mode, the sios bit must be cleared before the sio interface begins shifting out the next transmit data. otherwise, the sio will stop after sending out dummy data. 76543210 sbi0cr1 01000xxx select transmit mode. sbi0dbr xxxxxxxx write the transmit data. sbi0cr1 10000xxx start transmission. ints2 interrupt sbi0dbr xxxxxxxx write the next transmit data.
TMP1941AF 2003-03-27 TMP1941AF-217 figure 14.24 transmit mode example: mip16 code to terminate transmission by sios (external clock mode) addiu r3, r0, 0x04 stest1 : lb r2,(sbi0sr) ; if sbi0sr.sef = 1 then loop and r2, r3 bnez r2, stest1 addiu r3, r0, 0x20 stest2 : lb r2, (pa) ; if sck = 0 then loop and r2, r3 beqz r2, stest2 addiu r3, r0, 0x00000111 stb r3, (sbi0cr1) ; sios 0 sbi0dbr ints2 interrupt request sios bit siof bit sef bit sck output so pin b a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 * the sios bit is cleared. a writes of the transmit data (a) internal clock mode sbi0dbr ints2 interrupt request sios bit siof bit sef bit sck input so pin b a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 * the sios bit is cleared. a writes of the transmit data (b) external clock mode
TMP1941AF 2003-03-27 TMP1941AF-218 figure 14.25 retention time of the last transmitted bit (2) 8-bit receive mode configure the sio interface in receive mode. then setting the sios bit in the sbi0cr1 enables reception. the receive data is clocked into the internal shift register via the si pin, synchronous to the serial clock. once the shift register is fully loaded, the received byte is transferred to the sbi0dbr, and the buffer-full interrupt (ints2) is generated. the ints2 interrupt service routine must then pick up the received data from the sbi0dbr. in internal clock mode, the sio interface will be in wait state (sck will stop) until the ints2 interrupt service routine reads the data from the sbi0dbr. in external clock mode, shift operations continue, synchronous to the external clock. in this mode, the maximum data rate is a function of the maximum latency between when the ints2 interrupt is generated and when the sbi0dbr is read by the interrupt service routine. reception can be terminated by the ints2 interrupt service routine clearing the sios bit to 0 or setting the sioinh bit to 1. if the sios bit is cleared, reception continues until the shift register is fully loaded and transferred to the sbi0dbr. in this case, software can check the sbi0sr.siof bit to determine whether reception has come to an end (0 = end-of-reception). if the sioinh bit is set, the ongoing reception is aborted immediately, and the siof bit is cleared at that point. (the received data becomes invalid; there is no need to read it out.) note: the contents of the sbi0dbr is not preserved after changing the transfer mode. before changing the transfer mode, clear the sios bit to complete the ongoing reception and have the ints2 interrupt service routine pick up the last received data. 76543210 sbi0cr1 01110xxx select receive mode. sbi0cr1 10110000 start reception. ints2 interrupt reg. sbi0dbr read the received data. bit 7 sck pin siof bit so pin bit 6 t sodh = 3.5 / fsys /2 seconds (min.)
TMP1941AF 2003-03-27 TMP1941AF-219 figure 14.26 receive mode (internal clock mode) (3) 8-bit transmit/receive mode configure the sio interface in transmit/receive mode and write the transmit data into the sbi0dbr. then setting the sios bit in the sbi0cr1 initiates transmission and reception. the transmit data is shifted out through the so pin, with the least-significant bit (lsb) first, with the falling edge of the serial clock, while at the same time the receive data is shifted in through the si pin with the rising edge of the serial clock. once the shift register is fully loaded with eight bits of the received data, it is transferred to the sbi0dbr, and the ints2 interrupt is generated. the ints2 interrupt service routine must then pick up the received data from the sbi0dbr and writes the next transmit data into the sbi0dbr. because the sbi0dbr is shared between transmit and receive operations, the received data must be read before the next transmit data is written. in internal clock mode, the sio interface will be in wait state (sck will stop) after a read of the received data until a write of the transmit data. in external clock mode, shift operations continue, synchronous to the external clock. therefore, software must read the received data and write the transmit data before the next shift operation begins. in this mode, the maximum data rate is a function of the maximum latency between when the ints2 interrupt is generated and when the interrupt service routine reads the received data and writes the transmit data. at the beginning of a transmission, the value of the last bit of the previously transmitted byte appears on the so pin between when the sbi0sr.siof bit is set and when sck subsequently goes low. transmission/reception can be terminated by the ints2 interrupt service routine clearing the sios bit to 0 or setting the sioinh bit to 1. if the sios bit is cleared, reception continues until the shift register is fully loaded and transferred to the sbi0dbr. in this case, software can check the sbi0sr.siof bit to determine whether transmission/reception has come to an end (0 = end-of- reception/transmission). if the sioinh bit is set, the ongoing transmission/reception is aborted immediately, and the siof bit is cleared at that point. note: the contents of the sbi0dbr is not preserved after changing the transfer mode. before changing the transfer mode, clear the sios bit to complete the ongoing transmission/reception and have the ints2 interrupt service routine pick up the last received data. sbi0dbr iints2 interrupt request sios bit siof bit sef bit sck output si pin b the sios bit is cleared. a a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 read of the received data read of the received data
TMP1941AF 2003-03-27 TMP1941AF-220 figure 14.27 receive/transmit mode (internal clock mode) figure 14.28 retention time of the transmit data in receive/transmit mode 76543210 sbi0cr1 01100xxx select receive/transmit mode. sbi0dbr xxxxxxxx write the transmit data. sbi0cr1 10100xxx start reception/transmission. ints2 interrupt reg. sbi0dbr read the received data. sbi0dbr xxxxxxxx write the transmit data. sbi0dbr iints2 interrupt request sios bit siof bit sef bit sck output so pin si pin the sios bit is cleared. c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 (a) write of the transmit data (d) read of the received data a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 * d b c a (c) read of the received data (b) write of the transmit data bit 7 of the last byte transmitted sck pin siof bit so pin bit 6 t sodh = 4/fsys/2 seconds (min.)
TMP1941AF 2003-03-27 TMP1941AF-221 15. analog-to-digital converter (adc) the TMP1941AF has a 8-channel, multiplexed-input, 10-bit successive-approximation ananlog-to-digital converter (adc). figure 15.1 shows a block diagram of the adc. the eight analog input channels (an0?an7) can be used as general-purpose digital inputs (port 5) if not needed as analog channels. note: ensure that the adc has halted before executing an insturction to place the TMP1941AF in idle, sleep or stop mode to reduce power supply current. otherwise, the TMP1941AF might go into a standby mode while the internal analog comparator is still active. in slow mode, the adc must be disabled. figure 15.1 adc block diagram interrupt request (intad) an7 (p57) an6 (p56) an5 (p55) an4 (p54) an3/ adtrg (p53) an2 (p52) an1 (p51) an0 (p50) comparator vrefh vrefl internal data bus multiplexer sample-and- hold a/d mode control register 1 (admod1) adtrge adch[2:0] vrefon scan repeat interrupt busy end start + ? internal data bus internal data bus channel selection control circuit a/d mode control register 0 (admod0) eocf adbf itm0 repeat scan ads adtrg a/d conversion result registers (adreg04l?37l) (adreg04h?37h) d/a converter a/d converter control circuit
TMP1941AF 2003-03-27 TMP1941AF-222 15.1 register description the adc has two mode control registers (admod0 and admod1), four conversion result high/low register pairs (adreg04h/l, adreg15h/l, adreg26h/l, adreg37h/l) and a clock select register (adcclk). the conversion result registers contain the digital values of completed conversions. the clock select register selects an a/d conversion clock. figure 15.2 to figure 15.6 show the registers available in the adc. a/d mode control register 0 76543210 name eocf adbf ?? itm0 repeat scan ads read/write r r/w reset value 0 0 0 0 0 0 0 0 function end-of- conversion flag 0: before or during conversion 1: completed a/d conversion busy flag 0: idle 1: during conversion must be written as 0. must be written as 0. interrupt see below. continuous conversion mode 0: single 1: continuous channel scan mode 0: fixed- channel 1: channel scan a/d conversion start 0: don?t care 1: start this bit is always read as 0. interrupt in fixed-channel continuous conversion mode fixed-channel continuous conversion mode scan = 0, repeat = 1 0 generates intad interrupt when a single conversion has been completed. 1 generates intad interrupt when a sequence of four conversions has been completed. note: the eocf bit is cleared when read. figure 15.2 a/d mode control register 0 (admod0) admod0 (0xffff_f310)
TMP1941AF 2003-03-27 TMP1941AF-223 a/d mode control register 1 76543210 name vrefon i2ad ?? adtrge adch2 adch1 adch0 read/write r/w r/w ?? r/w reset value 0 0 ?? 0000 function vref control 0: off 1: on adc operation in idle mode 0: off 1: on external conversion trigger 0: disable 1: enable analog input channel select analog input channel select scan adch[2:0] 0 fixed-channel mode 1 channel scan mode 000 an0 an0 001 an1 an0 an1 010 an2 an0 an1 an2 011 (note) an3 an0 an1 an2 an3 100 an4 an4 101 an5 an4 an5 110 an6 an4 an5 an6 111 an7 an4 an5 an6 an7 a/d external conversion trigger ( adtrg input) 0 disable 1 enable note 1: set the vrefon bit to 1 before setting the ads bit in the admod0 to start a conversion. note 2: the an3 pin is shared with the adtrg pin. therefore, when the external conversion trigger input ( adtrg ) is enabled (i.e., when admod1.adtrge = 1), the adch[2:0] field must not be programmed to 011. figure 15.3 a/d mode control register (admod1) admod1 (0xffff_f311)
TMP1941AF 2003-03-27 TMP1941AF-224 a/d conversion result low register 0/4 76543210 name adr01 adr00 ????? adr0rf read/write r ????? r reset value undefined ????? 0 function lower 2 bits of an a/d conversion result conversion result store flag 1: stored a/d conversion result high register 0/4 76543210 name adr09 adr08 adr07 adr06 adr05 adr04 adr03 adr02 read/write r reset value undefined function upper 8 bits of an a/d conversion result a/d conversion result low register 1/5 76543210 name adr11 adr10 ????? adr1rf read/write r ????? r reset value undefined ????? 0 function lower 2 bits of an a/d conversion result conversion result store flag 1: stored a/d conversion result high register 1/5 76543210 name adr19 adr18 adr17 adr16 adr15 adr14 adr13 adr12 read/write r reset value undefined function upper 8 bits of an a/d conversion result 9876543210 channel x conversion result bits adregxh adregxl 76543210 76543210 note 1: bits 5?1 are always read as 1s. note 2: bit 0 (adrxrf), when set, indicates that the conversion result has been stored in the adregxh/l register pair. this bit is cleared when either the adregxh or the adregxl is read. figure 15.4 a/d convesion result high/low registers (1) adreg04h (0xffff_f301) adreg15h (0xffff_f303) adreg04l (0xffff_f300) adreg15l (0xffff_f302)
TMP1941AF 2003-03-27 TMP1941AF-225 a/d conversion result low register 2/6 76543210 name adr21 adr20 ????? adr2rf read/write r ????? r reset value undefined ????? 0 function lower 2 bits of an a/d conversion result conversion result store flag 1: stored a/d conversion result high register 2/6 76543210 name adr29 adr28 adr27 adr26 adr25 adr24 adr23 adr22 read/write r reset value undefined function upper 8 bits of an a/d conversion result a/d conversion result low register 3/7 76543210 name adr31 adr30 ????? adr3rf read/write r ????? r reset value undefined ????? 0 function lower 2 bits of an ad conversion result conversion result store flag 1: stored a/d conversion result high register 3/7 76543210 name adr39 adr38 adr37 adr36 adr35 adr34 adr33 adr32 read/write r reset value undefined function upper 8 bits of a/d conversion result 9876543210 channel x conversion result bits adregxh adregxl 76543210 76543210 note 1 bits 5?1 are always read as 1s. note 2 bit 0 (adrxrf), when set, indicates that the conversion result has been stored in the adregxh/l register pair. this bit is cleared when either the adregxh or the adregxl is read. figure 15.5 a/d conversion result high/low registers (2) adreg26h (0xffff_f305) adreg37h (0xffff_f307) adreg26l (0xffff_f304) adreg37l (0xffff_f306)
TMP1941AF 2003-03-27 TMP1941AF-226 a/d conversion clock select register 76543210 name ?????? adcck1 adcck0 read/write ?????? r/w r/w reset value ?????? 00 function a/d conversion clock (fadc) select 00: fsys/2 01: fsys/4 10: fsys/8 11: reserved note 1: the adc operates off the selected a/d conversion clock, which must be selected from table 15.3, conversion time , to assure conversion accuracy. note 2: programming the adcclk register should only be attempted when an a/d conversion is not in progress. figure 15.6 a/d conversion clock select register (adcclk) adcclk (0xffff_ee04)
TMP1941AF 2003-03-27 TMP1941AF-227 15.2 operation 15.2.1 analog reference voltages the vrefh and vrefl pins provide the reference voltages for the adc. these pins estabilish the full-scale range for the internal resistor string, which divides the range into 1024 steps. the digital result of the conversion is derived by comparing the sampled analog input voltage to the resistor string voltages. clearing the vrefon bit in the admod1 turns off the switch between vrefh and vrefl. once the vrefon bit is cleared, the internal reference voltage requires a recovery time of 3 s to stabilize after the vrefon bit is again set to 1. this recovery time is independent of the system clock frequency. the ads bit in the admod0 must then be set to initiate an conversion. 15.2.2 selecting an analog input channel (s) there are two basic conversion modes: fixed-channel mode and channel scan mode. the scan bit in the admod0 affects the conversion channel(s) that will be selected as follows. ? fixed-channel mode (admod0.scan = 0) when the scan bit in the admod0 is cleared, the adc runs conversions on a single input channel selected from an0?an7 via the adch[2:0] field in the admod1. ? channel scan mode (admod0.scan = 1) when the scan bit in the admod0 is set, the adc runs conversions on sequential channels in a specific group selected via the adch[2:0] field in the admod1. refer to table 15.1. after a reset, the admod0.scan bit defaults to 0, and the admod1.adch[2:0] field defaults to 000. thus, the an0 pin is selected as the conversion channel. the an0?an7 pins can be used as general-purpose input ports if not used as analog input channels. table 15.1 analog input channel selection admod1.adch[2:0] fixed-channel mode admod1.scan = 0 channel scan mode admod0.scan = 1 000 an0 an0 001 an1 an0 an1 010 an2 an0 an1 an2 011 an3 an0 an1 an2 an3 100 an4 an4 101 an5 an4 an5 110 an6 an4 an5 an6 111 an7 an4 an5 an6 an7 15.2.3 starting an a/d conversion the adc initiates a conversion or a sequence of conversions when the ads bit in the admod0 is set, or when a falling edge is applied to the adtrg pin if the adtrge bit in the admod1 is set. when a conversion starts, the busy flag (admod0.adbf) is set. writing a 1 to the ads bit causes the adc to abort any ongoing conversion and start sampling the selected channel to begin a new conversion. the conversion result store flag (adregxl.adrxrf) indicates whether the result register contains a valid digital result at that point. in external conversion trigger mode, a falling edge on the adtrg pin is ignored while a conversion is in progress.
TMP1941AF 2003-03-27 TMP1941AF-228 15.2.4 conversion modes and conversion-done interrupts the adc supports the following four conversion modes: ? fixed-channel single conversion mode ? channel scan single conversion mode ? fixed-channel continuous conversion mode ? channel scan continuous conversion mode the repeat and scan bits in the admod1 select the conversion mode. the adc generates the intad interrupt and sets the eocf bit in the admod0 at the end of the conversion process. ? fixed-channel single conversion mode this mode is selected by programming the repeat and scan bits in the admod0 to 00. in this mode, the adc performs a single conversion on a single selected channel. when a conversion is completed, the adc sets the admod0.eocf bit, clears the admod0.adbf bit and generates the intad interrupt. ? channel scan single conversion mode this mode is selected by programming the repeat and scan bits in the admod0 to 01. in this mode, the adc performs a single conversion on each of a selected group of channels. when a single conversion sequence is completed, the adc sets the admod0.eocf bit, clears the admod0.adbf bit and generates the intad interrupt. ? fixed-channel continuous conversion mode this mode is selected by programming the repeat and scan bits in the admod0 to 10. in this mode, the adc repeatedly converts a single selected channel. when a conversion process is completed, the adc sets the admod.eocf bit. the admod0.adbf bit remains set. the itm0 bit in the admod0 controls interrupt generation in this mode. if the itm0 bit is cleared, the adc generates an interrupt after each conversion. if the itm0 bit is set, the adc generates an interrupt after every four conversions. ? channel scan continuous conversion mode this mode is selected by programming the repeat and scan bits in the admod0 to 11. in this mode, the adc repeatedly converts the selected group of channels. when a single conversion sequence is completed, the adc sets the admod0.eocf bit and generates the intad interrupt. the admod0.adbf bit remains set. in continuous conversion modes, clearing the admod0.repeat bit stops the conversion sequence after the ongoing conversion process is completed. if the i2ad bit in the admod1 is cleared, putting the TMP1941AF in any standby mode (idle, sleep or stop) causes the adc to be immediately disabled, even if a conversion is in progress. once the TMP1941AF exits the standby mode, the adc restarts a conversion sequence when in a continuous conversion mode, but remains inactive when in a single conversion mode. table 15.2 summarizes interrupt request generation in each of the conversion modes.
TMP1941AF 2003-03-27 TMP1941AF-229 table 15.2 interrupt request generation in each ad conversion mode admod0 mode interrupt request generation itm0 repeat scan fixed-channel single conversion mode after a conversion x 0 0 channel scan single conversion mode after a scan conversion sequence x01 after each conversion 0 fixed-channel continuous conversion mode after every four conversions 1 10 channel scan continuous conversion mode after each scan conversion sequence x11 x = don?t care 15.2.5 conversion time the conversion process requires 86 conversion clocks per channel. for example, this results in a conversion time of 8.6 s with 10-mhz fadc. the a/d conversion clock can be selected from fsys/2, fsys/4 and fsys/8 through the programming of the adcck[1:0] field in the adcclk register. to assure conversion accuracy, conversion time must be no shorter than 8.6 s. table 15.3 conversion time conversion clock fsys fsys/2 fsys/4 fsys/8 40 mhz don?t use. 8.6 s 17.2 s 32 mhz don?t use. 10.75 s 21.5 s 20 mhz 8.6 s 17.2 s 34.4 s 16 mhz 10.75 s 21.5 s 43.0 s 10 mhz 17.2 s 34.4 s 68.8 s 8 mhz 21.5 s 43.0 s 86.0 s 15.2.6 storing and reading the a/d conversion result conversion results are loaded into conversion result high/low register pairs (adreg04h/l to adreg37h/l). these registers are read-only. in fixed-channel continuous conversion mode, conversion data goes into the adreg04h/l to the adreg37h/l sequentially. in other modes, channels an0 and an4 share the adreg04h/l; channels an1 and an5 share the adreg15h/l; channels an2 and an6 share the adreg26h/l; and channels an3 and an7 share the adreg37h/l. table 15.4 shows the relationships between the analog input channels and the a/d conversion result registers.
TMP1941AF 2003-03-27 TMP1941AF-230 table 15.4 relationships between analog input channels and a/d conversion result registers a/d conversion result register analog input channel (port 5) fixed-channel continuous conversion mode (for each sequence of four conversions) other modes an0 adreg04h/l an1 adreg15h/l an2 adreg26h/l an3 adreg37h/l an4 adreg04h/l an5 adreg15h/l an6 adreg26h/l an7 adreg04h/l adreg15h/l adreg26h/l adreg37h/l adreg37h/l bit 0 (adrxrf) in each adregxl register indicates whether the conversion result has been read. this bit is set when the conversion result is loaded into the adregxh/l pair, and cleared when either the adregxh or adregxl is read. reading the conversion result clears the end-of-conversion flag (admod0.eocf).
TMP1941AF 2003-03-27 TMP1941AF-231 15.3 programming examples ? converting the analog input voltage on the an3 pin to a digital value and storing the converted value in a memory location (0xffff_b800) using an a/d interrupt (intad) handler routine settings in the main routine 76543210 imcehh xx010100 enables intad and sets its priority level to 4. admod1 1xxx0011 selects an3 as the analog input channel. admod0 xx000001 starts conversion in fixed-channel single conversion mode. interrupt routine processing example r4 adreg37 loads the conversion result into general-purpose register r4 from adreg37l and adreg37h. r4 > > 6 shifts the contents of r4 six bits to the right, padding 0s to the vacated msb bits. (ffffb800h) r4 stores the contents of r4 to address 0xffff_b800. ? converting the analog input voltages on an0?an2 sequentially in channel scan continuous conversion mode imcehh xx010000 disables intad. admod1 1xxx0011 selects an0?an2 as analog input channels. admod0 xx000001 starts conversion in channel scan continuous conversion mode. x = don't care notes: the adc supports both polled and interrupt-driven operation. the cpu can perform polling operation to detect completion of a conversion. ? don?t poll the adrxrf bit in the adregxxl register. ? in single conversion modes, poll the adbf bit in the admod0. ? in any conversion modes, the eocf bit in the admod0 can be polled. after the eocf bit is set, one or two fadc clocks are required as shown below before the adregxh/l can be read. conversion mode time required before reading the adregxx fixed-channel single conversion mode 1 fadc clock fixed-channel continuous conversion mode 1 fadc clock channel scan single scan conversion mode 2 fadc clocks channel scan continuous conversion mode 2 fadc clocks fadc: a/d conversion clock selected by the adcclk register
TMP1941AF 2003-03-27 TMP1941AF-232 16. watchdog timer (wdt) the TMP1941AF contains a watchdog timer (wdt). the wdt is used to regain control of the system in the event of software or system lockups due to spurious noises, etc. when a watchdog timer time-out occurs, the wdt generates a nonmaskable interrupt to the cpu. also, the time-out event can be programmed for system reset generation, which is accomplished by routing the time-out signal to the internal reset pin. 16.1 implementation figure 16.1 shows a block diagram of the wdt. figure 16.1 wdt block diagram 2 21 2 19 2 17 2 15 internal reset wdmod. wdtp[1:0] wdmod.wdte reset q rs internal reset wdmod.rescr interrupt request (intwdt) fsys/2 selector internal data bus write of b1h write of 4eh reset pin reset control 22-stage binary counter watchdog timer control register (wdcr)
TMP1941AF 2003-03-27 TMP1941AF-233 the wdt contains a 22-stage binary counter clocked by the fsys/2 clock. this binary counter provides 2 15 , 2 17 , 2 19 or 2 21 as a counter overflow signal, as programmed into the wdtp[1:0] field in the wdmod. when a counter overflow occurs, the wdt generates a wdt interrupt, as shown below. figure 16.2 default operation also, the counter overflow can be programmed to cause a system reset as the time-out action. if so programmed, a counter overflow causes the wdt to assert the internal reset signal for a 22- to 29-state time. after a reset, the fsys clock is, by default, generated by dividing the high-speed oscillator clock (fc) by eight through the clock gear function; the wdt clock source (fsys/2) is derived from this fsys clock. note: the TMP1941AF continues sampling the plloff pin during a reset operation caused by the wdt. therefore, the plloff pin must be tied to either logic high or logic low. figure 16.3 reset operation 0 wdt interrupt wdt clear (via software) a write of a special clear-count code wdt counter n overflow overflow wdt counter n wdt interrupt 22?29 states (8.8?11.6 s @ fc = 40 mhz, fsys = 5 mhz, fsys/2 = 2.5 mhz) internal reset
TMP1941AF 2003-03-27 TMP1941AF-234 16.2 register description the wdt is controlled by two registers called wdmod and wdcr. 16.2.1 watchdog timer mode register (wdmod) ? time-out period (wdmod.wdtp[1:0]) this 2-bit field determines the duration of the wdt time-out interval. upon reset, the wdtp[1:0] field defaults to 00. figure 16.5 shows possible time-out periods. ? wdt enable (wdmod.wdte) upon reset, the wdte bit is set to 1, enabling the wdt. to disable the wdt, the clearing of the wdte bit must be followed by a write of a special key code (b1h) to the wdcr register. this prevents a ?lost? program from disabling the wdt operation. the wdt can be re-enabled only by setting the wdte bit. ? system reset (wdmod.rescr) this bit is used to program the wdt to generate a system reset on a time-out. upon reset, this bit is cleared; thus the time-out does not cause a system reset. 16.2.2 watchdog timer control register (wdcr) this register is used to disable the wdt and to clear the wdt binary counter. ? disabling the wdt the wdt can be disabled by clearing the wdmod.wdte to 0 and then writing the special disable code (b1h) to the wdcr register. wdmod 0 ??????? clears the wdte bit to 0. wdcr 10110001 writes the disable code (b1h) to the wdcr. ? enabling the wdt the wdt can be enabled only by setting the wdte bit in the wdmod to 1. ? clearing the wdt counter writing the special clear-count code (4eh) to the wdcr resets the binary counter to zero. the counting process begins again. wdcr 01001110 writes the clear-count code (4eh) to the wdcr. note: writing the disable code (b1h) to the wdcr causes the binary counter to be reset to zero.
TMP1941AF 2003-03-27 TMP1941AF-235 76543210 name wdte wdtp1 wdtp0 ?? i2wdt rescr ? read/write r/w r/w ?? r/w r/w reset value100 ?? 000 function wdt enable 1: enable time-out period 00: 2 16 /fsys 01: 2 18 / fsys 10: 2 20 / fsys 11: 2 22 / fsys idle 0: off 1: on 1: system reset must be written as 0. system reset 0 ? 1 internally routes the wdt time-out signal to the system reset time-out peiord (@ fc = 40 mhz, fs = 32.768 khz) watchdog timer time-out period wdmod.wdtp[1:0] system clock select syscr1.sysck clock gear value syscr1.gear[1:0] 00 01 10 11 1 (fs) xxx 2.0 s 8.0 s 32.0 s 128.0 s 00 (fc) 1.638 ms 6.554 ms 26.214 ms 104.858 ms 01 (fc/ 2 ) 3.277 ms 13.107 ms 52.429 ms 209.715 ms 10 (fc/ 4 ) 6.554 ms 26.214 ms 104.858 ms 419.430 ms 0 (fgear) 11 (fc/ 8 ) 13.107 ms 52.429 ms 209.715 ms 838.861 ms wdt enable 0 disable 1 enable figure 16.4 watchdog timer mode register (wdmod) 76543210 name ? read/write w reset value ? function b1h: wdt disable code 4eh : wdt clear-count code special code b1h wdt disable code 4eh wdt clear-count code other values don?t care figure 16.5 watchdog timer control register (wdcr) wdmod (0xffff_f090) wdcr (0xffff_f091)
TMP1941AF 2003-03-27 TMP1941AF-236 16.3 operation the watchdog timer is a kind of timer that generates an interrupt request if it times out. the wdt of the TMP1941AF allows the user to program the time-out period in the wdtp[1:0] field in the wdmod. while enabled, the software can reset the counter to zero at any time by writing a special clear-count code. if the software is unable to reset the counter before it reaches the time-out count, the wdt generates the intwdt interrupt. in response to the interrupt, the cpu jumps to a system recovery routine to regain control of the system. the wdt begins counting immediately after reset. when the TMP1941AF goes into sleep or stop mode, the wdt counter is reset to zero automatically and stops counting. the wdt continues counting while an off-chip peripheral has mastership of the bus (i.e., busak = 0). in idle mode, the i2wdt bit in the wdmod determines whether or not to disable the wdt. the i2wdt bit can be programmed before putting the TMP1941AF in idle mode. examples: ? clearing the wdt binary counter 76543210 wdcr 01001110 writes the clear-count code (4eh) to the wdcr. ? programming the time-out interval to 2 18 /fsys 76543210 wdmod ????? ? disabling the watchdog timer 76543210 wdmod 0 ??????? clears the wdte bit to 0. wdcr 10110001 writes the disable code (b1h) to the wdcr.
TMP1941AF 2003-03-27 TMP1941AF-237 17. real-time clock (rtc) the TMP1941AF contains a real-time clock (rtc). clocked by a 32.768-khz clock, the rtc provides a periodic interrupt at a programmed interval: 0.0625 seconds, 0.125 seconds, 0.25 seconds or 0.50 seconds. the rtc can continue operating in any standby modes in which the low-speed oscillator is active. the rtc interrupt (intrtc) can be used as a wake-up signal to exit a standby mode (except stop mode). the imcgb3 register located within the cg must be programmed to use the intrtc interrupt. 17.1 implemention figure 17.1 shows a block diagram of the rtc. figure 17.1 rtc block diagram the rtc control register (rtccr) provides control over the rtc. the organization of the rtccr is shown below. 76543210 name ? rtcrclr rtcsel1 rtcsel0 rtcrun read/write r/w r/w r/w r/w reset value 0 0 0 0 0 function must be written as 0. accumu- lator clear 0: clear rtcreg 1: don?t care 00: 2 14 /fs 01: 2 13 /fs 10: 2 12 /fs 11: 2 11 /fs 0: stop and clear the counter. 1: begin counting. interrupt interval (fs = 32.768 khz) 00 0.50 seconds 01 0.25 seconds 10 0.125 seconds 11 0.0625 seconds figure 17.2 rtc control register (rtccr) rtccr (0xffff_f0a0) 14-stage binary counter selector interrupt request (intrtc) rtccr.rtcsel rtccr.rtcrun 2 14 run/clear 2 13 2 12 2 11 fs (32.768 khz) 8-bit accumulator rtcreg
TMP1941AF 2003-03-27 TMP1941AF-238 the rtc provides an 8-bit read-only accumulator (rtcreg) that counts the number of intrtc interrupts that have occurred. the accumulator allows the user to keep track of time up to 127.5 seconds if the interrupt interval is programmed to 0.5 seconds. accumulator 76543210 name rui7 rui6 rui5 rui4 rui3 rui2 rui1 rui0 read/write r reset value00000000 function accumulate count value figure 17.3 rtc accumulator register (rtcreg) the rtcreg is incremented with a delay of one fs clock after the intrtc interrupt is generated. reads of the rtcreg must be performed in slow mode. the resetting of the rtcreg is inhibited for one fs clock cycle after the intrtc interrupt is generated. the rtcreg can be reset to zero by executing the accumulator-clear command twice in slow mode. example 1: clearing the accumulator 76543210 syscr1 xx1 ?? x ?? puts the TMP1941AF in slow mode. rtccr 0xxx0 ?? 1 rtccr 0xxx0 ?? 1 executes accumulator-clear command twice. syscr1 xx0 ?? x ?? puts the TMP1941AF back in normal mode. example 2: programming the rtc interrupt interval initialization 76543210 imcgb3 00110001 imcehl 00010xxx sets the interrupt level. eicrcg 00000111 clears the interrupt request via the cg block. intclr 00111010 clears the interrupt request via the intc block. rtccr 00001xx1 starts counting. intrtc interrupt 76543210 eicrcg 00000111 clears the interrupt request via the cg block. intclr 00111010 clears interrupt request via the intc block. interrupt processing end of interrupt x = don't care note: to disable interrupts, program the imcehl and then the imcgb3 in this order. rtcreg (0xffff_f0a4) fs clock intrtc interrupt don?t execute an instruction to reset the accumulator during this period. accumulate count value n n + 1
TMP1941AF 2003-03-27 TMP1941AF-239 18. electrical characteristics the letter x in equations presented in this chapter represents the cycle period of the fsys clock selected through the programming of the syscr1.sysck bit. the fsys clock may be derived from either the high- speed or low-speed crystal oscillator. the programming of the clock gear function also affects the fsys frequency. all relevant values in this chapter are calculated with the high-speed (fc) system clock (syscr1.sysck=0) and a clock gear factor of 1/fc (syscr1.gear[1:0]=00). 18.1 maximum ratings parameter symbol rating unit supply voltage v cc ? 0.5 to 4.0 v input voltage v in ? 0.5 to v cc + 0.5 v per pin i ol 5 low-level output current total i ol 80 per pin i oh ? 5 high-level output current total i oh ? 80 ma power dissipation (ta = 85c) pd 600 mw soldering temperature (10 s) t solder 260 c storage temperature t stg ? 65 to 150 c operating temperature t opr ? 40 to 85 c v cc = dv cc = av cc ; v ss = dv ss = av ss note: maximum ratings are limiting values of operating and environmental conditions which should not be exceeded under the worst possible conditions. the equipment manufacturer should design so that no maximum rating value is exceeded with respect to current, voltage, power dissipation, temperature, etc. exposure to conditions beyond those listed above may cause permanent damage to the device or affect device reliability, which could increase potential risks of personal injury due to ic blowup and/or burning.
TMP1941AF 2003-03-27 TMP1941AF-240 18.2 dc electrical characteristics (1/2) ta = ? 40 to 85c parameter symbol condition min typ (note 1) max unit fosc = 4 to 10 mhz fsys = 2 to 40 mhz fs = 30 to 34 khz 3.0 pllon fosc = 4 to 7 mhz fsys = 2 to 28 mhz fs = 30 to 34 khz 2.7 plloff (crystal) fosc = 16 to 20 mhz fsys = 1 to 20 mhz fs = 30 to34 khz 2.7 fosc = 16 to 20 mhz fsys = 1 to 20 mhz fs = 30 to 34 khz supply voltage av cc = v cc av ss = v ss = 0 v v cc plloff (external clock) fosc = 20 to 40 mhz fsys = 1.25 to 20 mhz fs = 30 to 34 khz (syscr1.dfosc = 0) (note 2) 2.7 3.6 v ad0 ? 15 v il 0.6 a16 ? 23, a0 ? 7, rd , wr , hwr , wait , busrq , busak , w / r , p37 ? pa7 (except p77) v il1 0.3v cc plloff , bw0, bw1, reset , nmi , p77 (int0) v il2 0.25v cc low-level input voltage x1 v il4 ? 0.3 0.2v cc ad0 ? 15 v ih 2.0 a16 ? 23, a0 ? 7, rd , wr , hwr , wait , busrq , busak , w / r , p37 ? pa7 (except p77) v ih1 0.7v cc plloff , bw0, bw1, reset , nmi , p77 (int0) v ih2 0.80v cc high-level input voltage x1 v ih4 v cc 2.7 v 0.8v cc v cc + 0.3 v low-level output voltage v ol i ol = 1.6 ma 0.45 high-level output voltage v oh i oh = ? 400 a v cc 2.7 v 2.4 v note 1: v cc = = = = 3.3 v, ta = 25c, unless otherwise noted. note 2: the dfosc bit in the syscr1 register must be cleared to 0.
TMP1941AF 2003-03-27 TMP1941AF-241 18.3 dc electrical characteristics (2/2) ta = ? 40 to 85c parameter symbol condition min typ (note 1) max unit input leakage current i li 0.0 v in v cc 0.02 5 output leakage current i lo 0.2 v in v cc ? 0.2 0.05 10 a power-down voltage (stop mode, ram backup) v stop v il2 = 0.2v cc , v ih2 = 0.8v cc 2.2 3.6 v pull-up resistor at reset rrst v cc = 3.3 v 0.3 v 100 450 k ? pin capacitance (except power/ground pins) c io fc = 1 mhz 10 pf schmitt hysteresis plloff , bw0, bw1, reset , nmi , int0 v th v cc 2.7 v 0.4 v programmable pull-up resistor pkh v cc = 3.3 v 0.3 v 100 450 k ? normal (note 2); gear = 1/1 75 85 idle (doze) 27 40 idle (halt) v cc = 3.3 v 0.3 v f sys = 40 mhz (f osc = 10 mhz, pllon) 22 36 ma normal (note 2); gear = 1/1 25 40 idle (doze) 13 20 idle (halt) v cc = 3.3 v 0.3 v f sys = 20 mhz (f osc = 20 mhz, plloff) 11 18 ma slow v cc = 3.3 v 0.3 v fs = 32.768 khz 70 220 a sllep v cc = 3.3 v 0.3 v fs = 32.768 khz 20 180 a stop i cc v cc = 2.7 to 3.6 v 5 150 a note 1: v cc = 3.3 v, ta = 25c, unless otherwise noted. note 2: measured with the operating cpu (scanning ports), 16-bit bus (ale = 1.5 cycles, 1 wait state), open output pins and input pins levels held at fixed logic values. iref excluded.
TMP1941AF 2003-03-27 TMP1941AF-242 18.4 ac electrical characteristics (1) v cc = 3.0 to 3.6 v, ta = 0 to 70 c, ale width = 0.5 clock cycle (recommended when t sys is 50 ns or longer) equation fsys = 20 mhz * no. parameter symbol min max min max unit 1 system clock period (x) t sys 31.25 33333 50 ns 2 a0?a15 valid to ale low t al 0.4x ? 12 8 ns 3 a0?a15 hold after ale low t la 0.4x ? 8 12 ns 4 ale pulse width high t ll 0.4x ? 6 14 ns 5 ale low to rd or wr asserted t lc 0.4x ? 8 12 ns 6 rd or wr negated to ale high t cl x ? 15 35 ns 7 a0?a15 valid to rd or wr asserted t acl x ? 20 30 ns 8 a0?a23 valid to rd or wr asserted t ach x ? 20 30 ns 9 a0?a23 hold after rd or wr negated t car x ? 15 35 ns 10 a0?a15 valid to d0?d15 data in t adl x (2 + w) ? 37 63 ns 11 a0?a23 valid to d0?d15 data in t adh x (2 + w) ? 37 63 ns 12 rd asserted to d0?d15 data in t rd x (1 + w) ? 22 28 ns 13 rd width low t rr x (1 + w) ? 10 40 ns 14 d0?d15 hold after rd negated t hr 00ns 15 rd negated to next a0?a15 output t rae x ? 15 35 ns 16 wr width low t ww x (1 + w) ? 10 40 ns 17 d0?d15 valid to wr negated t dw x (1 + w) ? 18 32 ns 18 d0?d15 hold after wr negated t wd x ? 15 35 ns 19 a0?a23 valid to wait input t awh 1.5x ? 30 45 ns 20 a0?a15 valid to wait input t awl 1.5x ? 30 45 ns 21 wait hold after rd or wr asserted t cw (0.5 + n ? 1) x + 2 (0.5 + n) x ? 17 27 58 ns * w = 0 w: number of wait-state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (1 + n) wait insertion ac measurement conditions: ? output levels: high = 2.4 v, low = 0.45 v, cl = 30 pf ? input levels: high = 2 v, low = 0.6 v
TMP1941AF 2003-03-27 TMP1941AF-243 (2) v cc = 3.0 to 3.6 v, ta = 0 to 70 c, ale width = 1.5 clock cycles equation fsys = 40 mhz * no. parameter symbol min max min max unit 1 system clock period (x) t sys 31.25 33333 ns 2 a0?a15 valid to ale low t al 1.4x ? 12 23 ns 3 a0?a15 hold after ale low t la 0.4x ? 8 2 ns 4 ale pulse width high t ll 1.4x ? 6 29 ns 5 ale low to rd or wr asserted t lc 0.4x ? 8 2 ns 6 rd or wr negated to ale high t cl x ? 15 10 ns 7 a0?a15 valid to rd or wr asserted t acl 2x ? 20 30 ns 8 a0?a23 valid to rd or wr asserted t ach 2x ? 20 30 ns 9 a0?a23 hold after rd or wr negated t ca x ? 15 10 ns 10 a0?a15 valid to d0?d15 data in t adl x (3 + w) ? 37 38 ns 11 a0?a23 valid to d0?d15 data in t adh x (3 + w) ? 37 38 ns 12 rd asserted to d0?d15 data in t rd x (1 + w) ? 22 3 ns 13 rd width low t rr x (1 + w) ? 10 15 ns 14 d0?d15 hold after rd negated t hr 00ns 15 rd negated to next a0?a15 output t rae x ? 15 10 ns 16 wr width low t ww x (1 + w) ? 10 15 ns 17 d0?d15 valid to wr negated t dw x (1 + w) ? 18 7 ns 18 d0?d15 hold after wr negated t wd x ? 15 10 ns 19 a0?a23 valid to wait input t awh 2.5x ? 30 32 ns 20 a0?a15 valid to wait input t awl 2.5x ? 30 32 ns 21 wait hold after rd or wr asserted t cw (0.5 + n ? 1) x + 2 (0.5 + n) x ? 17 15 20 ns * w = 0 w: number of wait-state cycles inserted (0 to 7 for programmed wait insertion) n: value of n for (1 + n) wait insertion ac measurement conditions: ? output levels: high = 2.4 v, low = 0.45 v, cl = 30 pf ? input levels: high = 2 v, low = 0.6 v
TMP1941AF 2003-03-27 TMP1941AF-244 note: the internal clk is not the system clock driven out from the scout pin. figure 18.1 read cycle timing (ale = 1.5, zero wait state) t rae t rr t car t hr t adh t adl t la d0?d15 t al t cl t ll ale internal clk ad0?ad15 rd cs0 ? 3 cs w / r s0 s1 s2 s3 s0 a0?a15 t acl t ach t lc t rd ad16?ad23 bus cycle = 4 clk cycles
TMP1941AF 2003-03-27 TMP1941AF-245 note: the internal clk is not the system clock driven out from the scout pin. figure 18.2 read cycle timing (ale = 1.5, 1 programmed wait state) t car t rr t hr t adh t adl t la d0?d15 t al t cl t ll ale internal clk ad0?ad15 rd cs0 ? 3 cs w / r s0 s1 s2 s3 s0 a0?a15 t acl t ach t lc t rd a16?a23 bus cycle = 5 clk cycles w1 t rae
TMP1941AF 2003-03-27 TMP1941AF-246 note1: if t awh and/or t awl cannot be satisified, a bus cycle must be initiated with the wait pin asserted. note2: the internal clk is not the system clock driven out from the scout pin. figure 18.3 read cycle timing (ale = 1.5, 2 externally generated wait states with n=1) internal clk t aw l/h ale ad0?ad15 rd cs0 ? 3 cs w / r ad16?ad23 bus cycle = 6 clk cycles wait d0?d15 s1 w s2 s3 s0 a0?a15 w t cw
TMP1941AF 2003-03-27 TMP1941AF-247 note: the internal clk is not the system clock driven out from the scout pin. figure 18.4 write cycle timing (ale = 1, zero wait state) t ww t car t dw t la d0?d15 t al t cl t ll ale internal clk ad0?ad15 wr , hwr cs0 ? 3 cs w / r a0?a15 t acl t ach t lc ad16?ad23 bus cycle = 4 clk cycles t wd
TMP1941AF 2003-03-27 TMP1941AF-248 18.5 adc electrical characteristics av cc = v cc , av ss = v ss parameter symbol condition min typ max unit analog reference voltage (+) vrefh v cc = 3.3 0.3 v v cc ? 0.2 v v cc v cc analog reference voltage (?) vrefl v cc = 3.3 0.3 v v ss v ss v ss + 0.2 v analog input voltage vain vrefl vrefh v admod1.vrefon = 1v cc = 3.3v 0.3 v 1.05 1.5 ma analog supply current admod1.vrefon = 0 iref (vrefl = vss) (vrefh = vcc) v cc = 2.7 to 3.6 v 0.02 5.0 a total error (not including quantization error) ? v cc = 3.3 v 0.3 v 1 3lsb note 1: 1 lsb = (vrefh ? vrefl) / 1024 (v) note 2: the a/d converter must be stopped when operating the TMP1941AF with the low-speed clock (fs). note 3: the supply current flowing through the avcc pin is included in the digital supply current parameter (icc).
TMP1941AF 2003-03-27 TMP1941AF-249 18.6 sio timing 18.6.1 i/o interface mode in the tables below, the letter x represents the fsys cycle period, which varies, depending on the programming of the clock gear function. (1) sclk input mode equation 20 mhz 40 mhz parameter symbol min max min max min max unit sclk period t scy 16x 800 400 ns txd data to sclk rise or fall * t oss (t scy /2) ? 5x ? 23 127 52 ns txd data hold after sclk rise or fall * t ohs (t scy /2) + 3x 550 275 ns rxd data valid to sclk rise or fall * t srd 2x + 8 108 58 ns rxd data hold after sclk rise or fall * t hsr 000ns * sclk rise or fall: measured relative to the programmed active edge of sclk. (2) sclk output mode equation 20 mhz 40 mhz parameter symbol min max min max min max unit sclk period (programmable) t scy 16x 800 400 ns txd data to sclk rise t oss (tscy/2) ? 15 385 185 ns txd data hold after sclk rise t ohs (tscy/2) ? 15 385 185 ns rxd data valid to sck rise t srd x + 23 73 48 ns rxd data hold after sck rise t hsr 000ns transmit data (txd) receive data (rxd) sclk sck output mode / active-high scl input mode 0 valid t oss t scy t ohs 1 2 3 t srd t hsr 0 1 2 3 valid valid valid sclk active-low sck input mode
TMP1941AF 2003-03-27 TMP1941AF-250 18.7 sbi timing 18.7.1 i 2 c mode in the table below, the letters x and t represent the fsys and t0 cycle periods, respectively. the letter n denotes the value of n programmed into the sck[2:0] (scl output frequency select) field in the sbi0cr1. equation standard mode fsys = 8 mhz, n = 4 fast mode fsys = 32 mhz, n = 4 parameter symbol min max min max min max unit scl clock frequency t sc 0 0 100 0 400 khz hold time for start condition t hd:sta 4.0 0.6 s input t low 4.7 1.3 s low period of the scl clock output 2 (n ? 1) t 4 (note 1) 1 (note 1) s input t high 4.0 0.6 s scl clock high width output (2 (n ? 1) + 4) t 6 1.5 s setup time for a repeated start condition t su;sta software- dependent 4.7 0.6 s data hold time t hd;dat 00 s data setup time t su;dat 250 100 ns setup time for stop condition t su;sto 4.0 0.6 s bus free time between stop and start conditions t buf software- dependent 4.7 1.3 s note 1: different from the philips i 2 c-bus specification. note 2: the ouptut data hold time is equal to 12x. note 3: the philips i 2 c-bus specification states that a device must internally provide a hold time of at least 300 ns for the sda signal to bridge the undefined region of the fall edge of scl. however, the TMP1941AF sbi does not satisfy this requirement. also, the output buffer for scl does not incorporate slope control of the falling edges; therefore, the equipment manufacturer should design so that the input data hold time shown in the table is satisfied, including tr/tf of the scl and sda lines. note 4: to operate the sbi in i 2 c fast mode, the fsys frequency must be no less than 20 mhz. to operate the sbi in i 2 c standard mode, the fsys frequency must be no less than 4 mhz. note 5: although the i 2 c bus specification from philips states that i/o pins of fast-mode devices must not obstruct the sda and scl lines if v dd is switched off, the TMP1941AF does not comply with this requirement. note 6: the sda hold time from the falling edge of scl varies with the fsys frequency, as shown at left. the fsys frequency must be determined, considering the devices connected on the i 2 c bus. if the devices on the i 2 c bus drive the sda line within a minimum delay of 100 ns from the falling edge of scl, the required hold time must be less than 100 ns; thus the fsys frequency must be 20 mhz or larger. sda scl t low t hd ; sta t scl t high t r t su ; dat t hd ; dat t su ; sta t su ; sto t buf s: start condition, sr: repeated start condition, p: stop condition t f ssrp required hold time 0 10 20 30 40 100 200 300 400 ns mhz fs y s
TMP1941AF 2003-03-27 TMP1941AF-251 18.7.2 clock-synchronous 8-bit sio mode in the tables below, the letters x and t represent the fsys and t0 cycle periods, respectively. the letter n denotes the value of n programmed into the sck[2:0] (scl output frequency select) field in the sbi0cr1. the electrical specifications below are for an sck signal with a 50% duty cycle. (1) sck input mode equation 40 mhz parameter symbol min max min max unit sck period tscy 16x 400 ns so data to sck rise toss (tscy/2) ? (6x + 30) 20 ns so data hold after sck rise tohs (tscy/2) + 4x 300 ns si data valid to sck rise tsrd 0 0 ns si data hold after sck rise thsr 4x + 10 110 ns (2) sck output mode equation 40 mhz parameter symbol min max min max unit sck period (programmable) t scy 2 n t 800 ns so data to sck rise t oss (t scy /2) ? 20 380 ns so data hold after sck rise t ohs (t scy /2) ? 20 380 ns si data valid to sck rise t srd 2x + 30 80 ns si data hold after sck rise t hsr 00ns transmit data (so) receive data (si) sck 0 valid t oss t scy t ohs 1 2 3 t srd t hsr 0 1 2 3 valid valid valid
TMP1941AF 2003-03-27 TMP1941AF-252 18.8 event counters (ta0in, ta2in, tb0in0, tb0in1, tb2in0) in the table below, the letter x represents the fsys cycle period. equation 40 mhz parameter symbol min max min max unit clock low pulse width t vckl 2x + 100 150 ns clock high pulse width t vckh 2x + 100 150 ns 18.9 timer capture (tb0in0, tb0in1, tb1in0, tb1in1, tb2in0, tb2in1) in the table below, the letter x represents the fsys cycle period. equation 40 mhz parameter symbol min max min max unit low pulse width t cpl 2x + 100 150 ns high pulse width t cph 2x + 100 150 ns 18.10 general interrupts in the table below, the letter x represents the fsys cycle period. equation 40 mhz parameter symbol min max min max unit low pulse width for int0?inta t intal x + 100 125 ns high pulse width for int0?inta t intah x + 100 125 ns 18.11 nmi and stop/sleep wake-up interrupts equation 40 mhz parameter symbol min max min max unit low pulse width for nmi and int0?int4 t intbl 100 100 ns high pulse width for int0?int4 t intbh 100 100 ns 18.12 scout pin in the table below, the letter t represents the cycle period of the scout output clock. equation 40 mhz parameter symbol min max min max unit clock low pulse width t sch 0.5t ? 57.5 ns clock high pulse width t scl 0.5t ? 57.5 ns t sch t scl scout
TMP1941AF 2003-03-27 TMP1941AF-253 18.13 bus request and bus acknowledge signals equation 40 mhz parameter symbol min max min max unit bus float to busak asserted t aba 0 80 0 80 ns bus float after busak negated t baa 0 80 0 80 ns note 1: if the current bus cycle has not terminated due to wait-state insertion, the TMP1941AF does not respond to busrq until the wait state ends. note 2: this broken lines indicate that output buffers are disabled, not that the signals are at indeterminate states. the pin holds the last logic value present at that pin before the bus is relinquished. this is dynamically accomplished through external load capacitances. the equipment manufacturer may maintain the bus at a predefined state by means of off-chip resistors, but he or she should design, considering the time (determined by the cr constant) it takes for a signal to reach a desired state. the on-chip, integrated programmable pullup/pulldown resistors remain active, depending on internal signal states. t aba (note 1) busrq ale a0?a23, rd , wr busak cs0 ? cs3 , w / r, hwr ad0?ad15 t baa (note 2) (note 2)
TMP1941AF 2003-03-27 TMP1941AF-254 19. i/o register summary the internal i/o registers configure and access the i/o ports, and control on-chip functions. these registers occupy 8-kbyte addresses from 0xffff_e000 thro ugh 0xffff_ffff. 1. i/o ports 2. watchdog timer (wdt) 3. real-time clock (rtc) 4. 8-bit timers (tmras) 5. 16-bit timer/event counters (tmrbs) 6. serial i/o (sio0 and sio1) 7. serial bus interface (sbi) 8. serial i/o (sio3 and sio4) 9. a/d converter (adc) 10. interrupt controller (intc) 11. dma controller (dmac) 12. chip select/wait controller 13. clock generator (cg) table organization mnemonic register name address 7 6 1 0 bit name read/write reset value function access r/w: read/write. the user can read and write the register bit. r: read only. w: write only. w*: the user can read and write the register bit, but a read always returns a value of 1.
TMP1941AF 2003-03-27 TMP1941AF-255 1. i/o ports address mnemonic address mnemonic address mnemonic address mnemonic 0xffff_f010 0xffff_f020 p4cr 0xffff_f030 p8 0xffff_f050 ode 11p4fc1p91 222p8cr2 333p8fc3 444p9cr4 55p55p9fc5 666pa6 7777 8p3 8 8pacr 8 9 9 9 pafc 9 ap3cr a a a bp3fc bp7 b b cccc dddd ep4 ep7cr e e ffp7fcff 2. wdt 3. rtc 4. 8-bit timers address mnemonic address mnemonic address mnemonic 0xffff_f090 wdmod 0xffff_f0a0 rtccr 0xffff_f100 ta01run 1wdcr 1 1 222ta0reg 333ta1reg 4 4 rtcreg 4 ta01mod 5 5 5 ta1ffcr 666 777 8 8 8 ta23run 999 aaata2reg bbbta3reg c c c ta23mod d d d ta3ffcr eee fff 5. 16-bit timer/event counters address mnemonic address mnemonic address mnemonic address mnemonic 0xffff_f180 tb0run 0xffff_f190 tb1run 0xffff_f1a0 tb2run 0xffff_f1b0 tb3run 1111 2tb0mod 2tb1mod 2tb2mod 2tb3mod 3 tb0ffcr 3 tb1ffcr 3 tb2ffcr 3 tb3ffcr 4444 5555 6666 7777 8tb0rg0l 8tb1rg0l 8tb2rg0l 8tb3rg0l 9tb0rg0h 9tb1rg0h 9tb2rg0h 9tb3rg0h atb0rg1l atb1rg1l atb2rg1l atb3rg1l btb0rg1h btb1rg1h btb2rg1h btb3rg1h ctb0cp0l ctb1cp0l ctb2cp0l ctb3cp0l dtb0cp0h dtb1cp0h dtb2cp0h dtb3cp0h etb0cp1l etb1cp1l etb2cp1l etb3cp1l ftb0cp1h ftb1cp1h ftb2cp1h ftb3cp1h figure 19.1 i/o register address map (1/5)
TMP1941AF 2003-03-27 TMP1941AF-256 6. sio0 and sio1 7. sbi 8. sio3 and sio4 9. adc address mnemonic address mnemonic address mnemonic address mnemonic 0xffff_f200 sc0buf 0xffff_f240 sbi0cr1 0xffff_f280 sc3buf 0xffff_f300 adreg04l 1sc0cr 1sbi0dbr 1sc3cr 1adreg04h 2 sc0mod0 2 i2c0ar 2 sc3mod0 2 adreg15l 3 br0cr 3 sbi0cr2/sr 3 br3cr 3 adreg15h 4 br0add 4 sbi0br0 4 br3add 4 adreg26l 5 sc0mod1 5 sbi0br1 5 sc3mod1 5 adreg26h 6666adreg37l 7777adreg37h 8 sc1buf 8 sc4buf 8 9 sc1cr 9 sc4cr 9 a sc1mod0 a sc4mod0 a b br1cr b br4cr b c br1add c br4add c d sc1mod1 d sc4mod1 d eee fff address mnemonic 0xffff_f310 admod0 1admod1 2 3 4 5 6 7 8 9 a b c d e f figure 19.1 i/o register address map (2/5)
TMP1941AF 2003-03-27 TMP1941AF-257 10. intc address mnemonic address mnemonic address mnemonic address mnemonic 0xffff_e000 imc0l 0xffff_e010 0xffff_e020 imc8l 0xffff_e030 imccl 1111 2 imc0h 2 2 imc8h 2 imcch 3333 4imc1l 4imc5l 4 4imcdl 5555 6 6 imc5h 6 6 imcdh 7777 8 8 8imcal 8imcel 9999 a imc2h a a imcah a imceh bbbb cimc3l cimc7l c cimcfl dddd eimc3h eimc7h e eimcfh fff address mnemonic address mnemonic address mnemonic address mnemonic 0xffff_e040 ivr 0xffff_e050 0xffff_e060 intclr 0xffff_e070 11 1 1 22 2 2 33 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 9 9 9 9 a a a a b b b b c c c c d d d d e e e e f f f f note: any attempt to access an address in the shaded areas causes a bus error to be signaled to the tx19 core processor. any attempt to access an address in the ranges 0xffff_e080 through 0xffff_e0ff and 0xffff_e10c through 0xffff_e1ff also causes a bus error. figure 19.1 i/o register address map (3/5)
TMP1941AF 2003-03-27 TMP1941AF-258 11. dmac address mnemonic address mnemonic address mnemonic address mnemonic 0xffff_e200 ccr0 0xffff_e210 bcr0 0xffff_e220 ccr1 0xffff_e230 bcr1 1111 2222 3333 4csr0 4 4csr1 4 5555 6666 7777 8 sar0 8 dtcr0 8 sar1 8 dtcr1 9999 aaaa bbbb cdar0 c cdar1 c dd dd ee ee ff ff address mnemonic address mnemonic address mnemonic address mnemonic 0xffff_e240 ccr2 0xffff_e250 bcr2 0xffff_e260 ccr3 0xffff_e270 bcr3 1111 2222 3333 4csr2 4 4csr3 4 5555 6666 7777 8 sar2 8 dtcr2 8 sar3 8 dtcr3 9999 aaaa bbbb cdar2 c cdar3 c dd dd ee ee ff ff address mnemonic address mnemonic address mnemonic address mnemonic 0xffff_e280 dcr 0xffff_e290 0xffff_e2a0 0xffff_e2b0 11 1 1 22 2 2 33 3 3 44 4 4 55 5 5 66 6 6 77 7 7 8 8 8 8 9 9 9 9 a a a a b b b b cdhr c c c dd d d ee e e ff f f note: any attempt to access an address in the shaded areas causes a bus error to be signaled to the tx19 core processor. any attempt to access an address in the range 0xffff_e2c0 through 0xffff_e2ff also causes a bus error. any attempt to access an address in the range 0xffff_e300 through 0xffff_e3ff is disallowed. figure 19.1 i/o register address map (4/5)
TMP1941AF 2003-03-27 TMP1941AF-259 12. cs/wait controller address mnemonic address mnemonic address mnemonic address mnemonic 0xffff_e400 bma0 0xffff_e410 0xffff_e480 b01cs 0xffff_e490 11 11 22 22 33 33 4bma1 4 4 b23cs 4 55 55 66 66 77 77 8bma2 8 8 bexcs 8 99 99 aa aa bb bb cbma3 c c c dd d d ee e e ff f f 13. cg address mnemonic address mnemonic address mnemonic 0xffff_ee00 syscr0 0xffff_ee10 imcga0 0xffff_ee20 eicrcg 1 syscr1 1imcga1 1 2 syscr2 2imcga2 2 3 syscr3 3imcga3 3 4 adcclk 4imcgb0 4 55 5 66 6 77imcgb3 7 8 8 8 9 9 9 a a a b b b c c c d d d e e e f f f note: any attempt to access an address in the shaded areas causes a bus error to be signaled to the tx19 core processor. any attempt to access an address in the following ranges also cause a bus error. 0xffff_e420 thru 0xffff_e47f 0xffff_e450 thru 0xffff_e4ff 0xffff_e700 thru 0xffff_edff 0xffff_ee30 thru 0xffff_eeff an attempt to access an address in the following ranges also cause a bus error. 0xffff_f040 thru 0xffff_f04f 0xffff_f060 thru 0xffff_f08f 0xffff_f0b0 thru 0xffff_f0ff 0xffff_f110 thru 0xffff_f17f 0xffff_f1c0 thru 0xffff_f1ff 0xffff_f210 thru 0xffff_f23f 0xffff_f248 thru 0xffff_f27f 0xffff_f290 thru 0xffff_f2ff 0xffff_f320 thru 0xffff_ffff figure 19.1 i/o register address map (5/5)
TMP1941AF 2003-03-27 TMP1941AF-260 19.1 i/o ports i/o port data registers mnemonic name address 7 6 5 4 3 2 1 0 p37 ??????? r/w r/w 111 p3 port 3 register ffff f018h input mode ??? p44 p43 p42 p41 p40 ??? r/w ??? 11111 p4 port 4 register ffff f01eh ??? input mode p57 p56 p55 p54 p53 p52 p51 p50 r p5 port 5 register ffff f025h input mode p77 p76 p75 p74 p73 p72 p71 p70 r/w 11111111 p7 port 7 register ffff f02bh input mode p87 p86 p85 p84 p83 p82 p81 p80 r/w 11111111 p8 port 8 register ffff f030h input mode p97 p96 p95 p94 p93 p92 p91 p90 r/w 11111111 p9 port 9 register ffff f031h output mode input mode pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 r/w 11111111 pa port a register ffff f036h input mode i/o port control and function registers (1 of 2) mnemonic name address 7 6 5 4 3 2 1 0 p37c p36c p35c p34c p33c p32c w 000000 p3cr port 3 control register ffff f01ah 0: in, 1: out ?? p44c p43c p42c p41c p40c w 00100 p4cr port 4 control register ffff f020h ??? 0: in, 1: out p44f p43f p42f p41f p40f w 00100 p4fc port 4 function register ffff f021h ??? 0: port 1: scout output 0: port 1: 3 cs output 0: port 1: 2 cs output 0: port 1: 1 cs output 0: port 1: 0 cs output p77c p76c p75c p74c p73c p72c p71c p70c w 00000000 p7cr port 7 control register ffff f02eh 0: in 1: out p77f p76f p75f p74f p73f p72f p71f p70f 00000000 p7fc port 7 function register ffff f02fh 0: port 1: wake-up int0 input 0: port 1: tb0out output 0: port 1: tb0in1 input 0: port 1: tb0in0 input 0: port 1: ta3out output / rxd4 input 0: port 1: ta2in input / txd4 output 0: port 1: ta1out output / rxd3 input 0: port 1: ta0in input / txd3 output note: p77f must be set to 1 when int0 is used to exit stop mode with syscr2.drve cleared.
TMP1941AF 2003-03-27 TMP1941AF-261 i/o port control and function registers (2 of 2) mnemonic name address 7 6 5 4 3 2 1 0 p87c p86c p85c p84c p83c p82c p81c p80c w 00000000 p8cr port 8 port 8 control register ffff f032h 0: in, 1: out ? p86f p85f p84f p83f p82f p81f p80f w 00000000 p8fc port 8 port 8 function register ffff f033h must be written as 0. 0: port 1: tb3out output 0: port 1: tb2out output 0: port 1: tb2in1 input 0: port 1: tb2in0 input 0: port 1: tb1out output 0: port 1: tb1in1 input 0: port 1: tb1in0 input p97c p96c p95c p94c p93c p92c p91c p90c w 00000000 p9cr port 9 port 9 control register ffff f034h 0: in, 1: out p95f p93f p92f p90f www 0000 p9fc port 9 port 9 function register ffff f035h ?? 0: port 1: sclk1 output or cts1 / sclk1 input ? 0: port 1: txd1 output 0: port 1: sclk0 output or cts0 / sclk0 input ? 0: port 1: txd0 output pa7c pa6c pa5c pa4c pa3c pa2c pa1c pa0c w 00000000 pacr port a port a control register ffff f038h 0: in, 1: out pa7f pa6f pa5f ? pa3f pa2f pa1f pa0f w 00000000 pafc port a port a function register ffff f039h 0: port 1: scl output 0: port 1: sda/so output 0: port 1: sck output must be written as 0. 0: port 1: wake-up int4 input 0: port 1: wake-up int3 input 0: port 1: wake-up int2 input 0: port 1: wake-up int1 input note: pa0f?pa3f must be set to 1 when int1?int4 are used to exit stop mode with syscr2.drve cleared. open-drain enable register mnemonic name address 7 6 5 4 3 2 1 0 ?? ode72 ode70 odea7 odea6 ode93 ode90 ?? r/w ?? 000000 ode open- drain enable register ffff f050h p72 0: push-pull 1: open- drain p70 0: push-pull 1: open- drain pa7 0: push-pull 1: open- drain pa6 0: push-pull 1: open- drain p93 0: push-pull 1: open- drain p90 0: push-pull 1: open- drain
TMP1941AF 2003-03-27 TMP1941AF-262 19.2 interrupt controller interrupt controller (1 of 12) mnemonicnameaddress76543210 ?? eim01 eim00 dm0 il02 il01 il00 ?? r/w ?? 000000 interrupt sensitivity 00: low level must be written as 00. dma trigger 0: disable 1: enable when dm0 = 0 interrupt number 0 (software set) 000: interrupt disabled. 001?111: priority level (1?7) when dm0 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 15 14 13 12 11 10 9 8 ?? eim11 eim10 dm1 il12 il11 il10 ?? r/w ?? 000000 imc0l interrupt mode control register 0l ffff e000h interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable when dm1 = 0 interrupt number 1 (int0 pin) 000: interrupt disabled. 001?111: priority level (1?7) when dm1 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 23 22 21 20 19 18 17 16 ?? eim21 eim20 dm2 il22 il21 il20 ?? r/w ?? 000000 interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable when dm2 = 0 interrupt number 2 (int1 pin) 000: interrupt disabled. 001?111: priority level (1?7) when dm2 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 31 30 29 28 27 26 25 24 ?? eim31 eim30 dm3 il32 il31 il30 ?? r/w ?? 000000 imc0h interrupt mode control register 0h ffff e002h interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable when dm3 = 0 interrupt number 3 (int2 pin) 000: interrupt disabled. 001?111: priority level (1?7) when dm3 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. note1: when using int0?int4 to exit stop and sleep modes, program their sensitivity in the imcga0 to imcga3 and imcgb0 located within the cg. in this case, the eimx[1:0] fields in the imc0l, imc0h and imc1l have no effect, but must always be set to ?high-level? (i.e., 01). note 2: interrupt sensitivity must be programmed before interrupt priority levels are programmed into the ilx[2:0] field.
TMP1941AF 2003-03-27 TMP1941AF-263 interrupt controller (2 of 12) mnemonic name address 7 6 5 4 3 2 1 0 ?? eim41 eim40 dm4 il42 il41 il40 ?? r/w ?? 000000 interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable when dm4 = 0 interrupt number 4 (int3 pin) 000: interrupt disabled. 001?111: priority level (1?7) when dm4 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 15 14 13 12 11 10 9 8 ?? eim51 eim50 dm5 il52 il51 il50 ?? r/w ?? 000000 imc1l interrupt mode control register 1l ffff e004h interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable when dm5 = 0 interrupt number 5 (int4 pin) 000: interrupt disabled. 001?111: priority level (1?7) when dm5 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 23 22 21 20 19 18 17 16 ?? eima1 eima0 dma ila2 ila1 ila0 ?? r/w ?? 000000 interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable when dma = 0 interrupt number 10 (int5 pin) 000: interrupt disabled. 001?111: priority level (1?7) when dma = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 31 30 29 28 27 26 25 24 ?? eimb1 eimb0 dmb ilb2 ilb1 ilb0 ?? r/w ?? 000000 imc2h interrupt mode control register 2h ffff e00ah interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable when dmb = 0 interrupt number 11 (int6 pin) 000: interrupt disabled. 001?111: priority level (1?7) when dmb = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use.
TMP1941AF 2003-03-27 TMP1941AF-264 interrupt controller (3 of 12) mnemonic name address 7 6 5 4 3 2 1 0 ?? eimc1 eimc0 dmc ilc2 ilc1 ilc0 ?? r/w ?? 000000 interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable when dmc = 0 interrupt number 12 (int7 pin) 000: interrupt disabled. 001?111: priority level (1?7) when dmc = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 15 14 13 12 11 10 9 8 ?? eimd1 eimd0 dmd ild2 ild1 ild0 ?? r/w ?? 000000 imc3l interrupt mode control register 3l ffff e00ch interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable when dmd = 0 interrupt number 13 (int8 pin) 000: interrupt disabled. 001?111: priority level (1?7) when dmd = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 23 22 21 20 19 18 17 16 ?? eime1 eime0 dme ile2 ile1 ile0 ?? r/w ?? 100000 interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable when dme = 0 interrupt number 14 (int9 pin) 000: interrupt disabled. 001?111: priority level (1?7) when dme = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 31 30 29 28 27 26 25 24 ?? eimf1 eimf0 dmf ilf2 ilf1 ilf0 ?? r/w ?? 000000 imc3h interrupt mode control register 3h ffff e00eh interrupt sensitivity 00: low level 01: high level 10: falling edge 11: rising edge dma trigger 0: disable 1: enable when dmf = 0 interrupt number 15 (inta pin) 000: interrupt disabled. 001?111: priority level (1?7) when dmf = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use.
TMP1941AF 2003-03-27 TMP1941AF-265 interrupt controller (4 of 12) mnemonic name address 7 6 5 4 3 2 1 0 ?? eim141 eim140 dm14 il142 il141 il140 ?? r/w ?? 000000 must be written as 11. dma trigger 0: disable 1: enable when dm14 = 0 interrupt number 20 (intta0) 000: interrupt disabled. 001?111: priority level (1?7) when dm14 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 15 14 13 12 11 10 9 8 ?? eim151 eim150 dm15 il152 il151 il150 ?? r/w ?? 000000 imc5l interrupt mode control register 5l ffff e014h must be written as 11. dma trigger 0: disable 1: enable when dm15 = 0 interrupt number 21 (intta1) 000: interrupt disabled. 001?111: priority level (1?7) when dm15 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 23 22 21 20 19 18 17 16 ?? eim161 eim160 dm16 il162 il161 il160 ?? r/w ?? 000000 must be written as 11. dma trigger 0: disable 1: enable when dm16 = 0 interrupt number 22 (intta2) 000: interrupt disabled. 001?111: priority level (1?7) when dm16 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 31 30 29 28 27 26 25 24 ?? eim171 eim170 dm17 il172 il171 il170 ?? r/w ?? 000000 imc5h interrupt mode control register 5h ffff e016h must be written as 11. dma trigger 0: disable 1: enable when dm17 = 0 interrupt number 23 (intta3) 000: interrupt disabled. 001?111: priority level (1?7) when dm17 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use.
TMP1941AF 2003-03-27 TMP1941AF-266 interrupt controller (5 of 12) mnemonic name address 7 6 5 4 3 2 1 0 ?? eim1c1 eim1c0 dm1c il1c2 il1c1 il1c0 ?? r/w ?? 000000 must be written as 11. dma trigger 0: disable 1: enable when dm1c = 0 interrupt number 28 (inttb00) 000: interrupt disabled. 001?111: priority level (1?7) when dm1c = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 15 14 13 12 11 10 9 8 ?? eim1d1 eim1d0 dm1d il1d2 il1d1 il1d0 ?? r/w ?? 000000 imc7l interrupt mode control register 7l ffff e01ch must be written as 11. dma trigger 0: disable 1: enable when dm1d = 0 interrupt number 29 (inttb01) 000: interrupt disabled. 001?111: priority level (1?7) when dm1d = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 23 22 21 20 19 18 17 16 ?? eim1e1 eim1e0 dm1e il1e2 il1e1 il1e0 ?? r/w ?? 000000 must be written as 11. dma trigger 0: disable 1: enable when dm1e = 0 interrupt number 30 (inttb10) 000: interrupt disabled. 001?111: priority level (1?7) when dm1e = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 31 30 29 28 27 26 25 24 ?? eim1f1 eim1f0 dm1f il1f2 il1f1 il1f0 ?? r/w ?? 000000 imc7h interrupt mode control register 7h ffff e01eh must be written as 11. dma trigger 0: disable 1: enable when dm1f = 0 interrupt number 31 (inttb11) 000: interrupt disabled. 001?111: priority level (1?7) when dm1f = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use.
TMP1941AF 2003-03-27 TMP1941AF-267 interrupt controller (6 of 12) mnemonic name address 7 6 5 4 3 2 1 0 ?? eim201 eim200 dm20 il202 il201 il200 ?? r/w ?? 000000 must be written as 11. dma trigger 0: disable 1: enable when dm20 = 0 interrupt number 32 (inttb20) 000: interrupt disabled. 001?111: priority level (1?7) when dm20 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 15 14 13 12 11 10 9 8 ?? eim211 eim210 dm21 il212 il211 il210 ?? r/w ?? 000000 imc8l interrupt mode control register 8l ffff e020h must be written as 11. dma trigger 0: disable 1: enable when dm21 = 0 interrupt number 33 (inttb21) 000: interrupt disabled. 001?111: priority level (1?7) when dm21 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 23 22 21 20 19 18 17 16 ?? eim221 eim220 dm22 il222 il221 il220 ?? r/w ?? 000000 must be written as 11. dma trigger 0: disable 1: enable when dm22 = 0 interrupt number 34 (inttb30) 000: interrupt disabled. 001?111: priority level (1?7) when dm22 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 31 30 29 28 27 26 25 24 ?? eim231 eim230 dm23 il232 il231 il230 ?? r/w ?? 000000 imc8h interrupt mode control register 8h ffff e022h must be written as 11. dma trigger 0: disable 1: enable when dm23 = 0 interrupt number 35 (inttb31) 000: interrupt disabled. 001?111: priority level (1?7) when dm23 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use.
TMP1941AF 2003-03-27 TMP1941AF-268 interrupt controller (7 of 12) mnemonic name address 7 6 5 4 3 2 1 0 ?? eim281 eim280 dm28 il282 il281 il280 ?? r/w ?? 000000 must be written as 11. dma trigger 0: disable 1: enable when dm28 = 0 interrupt number 40 (inttbof0) 000: interrupt disabled. 001?111: priority level (1?7) when dm28 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 15 14 13 12 11 10 9 8 ?? eim291 eim290 dm29 il292 il291 il290 ?? r/w ?? 000000 imcal interrupt mode control register al ffff e028h must be written as 11. dma trigger 0: disable 1: enable when dm29 = 0 interrupt number 41 (inttbof1) 000: interrupt disabled. 001?111: priority level (1?7) when dm29 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 23 22 21 20 19 18 17 16 ?? eim2a1 eim2a0 dm2a il2a2 il2a1 il2a0 ?? r/w ?? 000000 must be written as 11. dma trigger 0: disable 1: enable when dm2a = 0 interrupt number 42 (inttbof2) 000: interrupt disabled. 001?111: priority level (1?7) when dm2a = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 31 30 29 28 27 26 25 24 ?? eim2b1 eim2b0 dm2b il2b2 il2b1 il2b0 ?? r/w ?? 000000 imcah interrupt mode control register ah ffff e02ah must be written as 11. dma trigger 0: disable 1: enable when dm2b = 0 interrupt number 43 (inttbof3) 000: interrupt disabled. 001?111: priority level (1?7) when dm2b = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use.
TMP1941AF 2003-03-27 TMP1941AF-269 interrupt controller (8 of 12) mnemonic name address 7 6 5 4 3 2 1 0 ?? eim301 eim300 dm30 il302 il301 il300 ?? r/w ?? 000000 must be written as 11. dma trigger 0: disable 1: enable when dm30 = 0 interrupt number 48 (intrx0) 000: interrupt disabled. 001?111: priority level (1?7) when dm30 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 15 14 13 12 11 10 9 8 ?? eim311 eim310 dm31 il312 il311 il310 ?? r/w ?? 000000 imccl interrupt mode control register cl ffff e030h must be written as 11. dma trigger 0: disable 1: enable when dm31= 0 interrupt number 49 (inttx0) 000: interrupt disabled. 001?111: priority level (1?7) when dm31= 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 23 22 21 20 19 18 17 16 ?? eim321 eim320 dm32 il322 il321 il320 ?? r/w ?? 000000 must be written as 11. dma trigger 0: disable 1: enable when dm32 = 0 interrupt number 50 (intrx1) 000: interrupt disabled. 001?111: priority level (1?7) when dm32 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 31 30 29 28 27 26 25 24 ?? eim331 eim330 dm33 il332 il331 il330 ?? r/w ?? 000000 imcch interrupt mode control register ch ffff e032h must be written as 11. dma trigger 0: disable 1: enable when dm33 = 0 interrupt number 51 (inttx1) 000: interrupt disabled. 001?111: priority level (1?7) when dm33= 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use.
TMP1941AF 2003-03-27 TMP1941AF-270 interrupt controller (9 of 12) mnemonic name address 7 6 5 4 3 2 1 0 ?? eim341 eim340 dm34 il342 il341 il340 ?? r/w ?? 000000 must be written as 11. dma trigger 0: disable 1: enable when dm34 = 0 interrupt number 52 (ints2) 000: interrupt disabled. 001?111: priority level (1?7) when dm34 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 15 14 13 12 11 10 9 8 ?? ?? r/w ?? 000000 imcdl interrupt mode control register dl ffff e034h must be written as 00. must be written as 0. must be written as 000. 23 22 21 20 19 18 17 16 ?? eim361 eim360 dm36 il362 il361 il360 ?? r/w ?? 000000 must be written as 11. dma trigger 0: disable 1: enable when dm36 = 0 interrupt number 54 (intrx3) 000: interrupt disabled. 001?111: priority level (1?7) when dm36 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 31 30 29 28 27 26 25 24 ?? eim371 eim370 dm37 il372 il371 il370 ?? r/w ?? 000000 imcdh interrupt mode control register dh ffff e036h must be written as 11. dma trigger 0: disable 1: enable when dm37 = 0 interrupt number 55 (inttx3) 000: interrupt disabled. 001?111: priority level (1?7) when dm37 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use.
TMP1941AF 2003-03-27 TMP1941AF-271 interrupt controller (10 of 12) mnemonic name address 7 6 5 4 3 2 1 0 ?? eim381 eim380 dm38 il382 il381 il380 ?? r/w ?? 000000 must be written as 11. dma trigger 0: disable 1: enable when dm38 = 0 interrupt number 56 (intrx4) 000: interrupt disabled. 001?111: priority level (1?7) when dm38 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 15 14 13 12 11 10 9 8 ?? eim391 eim390 dm39 il392 il391 il390 ?? r/w ?? 000000 imcel interrupt mode control register el ffff e038h must be written as 11. dma trigger 0: disable 1: enable when dm39 = 0 interrupt number 57 (inttx4) 000: interrupt disabled. 001?111: priority level (1?7) when dm39 = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 23 22 21 20 19 18 17 16 ?? eim3a1 eim3a0 dm3a il3a2 il3a1 il3a0 ?? r/w ?? 000000 must be written as 01. dma trigger 0: disable 1: enable when dm3a = 0 interrupt number 58 (intrtc) 000: interrupt disabled. 001?111: priority level (1?7) when dm3a = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 31 30 29 28 27 26 25 24 ?? eim3b1 eim3b0 dm3b il3b2 il3b1 il3b0 ?? r/w ?? 000000 imceh interrupt mode control register eh ffff e03ah must be written as 11. dma trigger 0: disable 1: enable when dm3b = 0 interrupt number 59 (intad) 000: interrupt disabled. 001?111: priority level (1?7) when dm3b = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use.
TMP1941AF 2003-03-27 TMP1941AF-272 interrupt controller (11 of 12) mnemonic name address 7 6 5 4 3 2 1 0 ?? eim3c1 eim3c0 dm3c il3c2 il3c1 il3c0 ?? r/w ?? 000000 must be written as 10. dma trigger 0: disable 1: enable when dm3c = 0 interrupt number 60 (intdma0) 000: interrupt disabled. 001?111: priority level (1?7) when dm3c = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 15 14 13 12 11 10 9 8 ?? eim3d1 eim3d0 dm3d il3d2 il3d1 il3d0 ?? r/w ?? 000000 imcfl interrupt mode control register fl ffff e03ch must be written as 10. dma trigger 0: disable 1: enable when dm3d = 0 interrupt number 61 (intdma1) 000: interrupt disabled. 001?111: priority level (1?7) when dm3d = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 23 22 21 20 19 18 17 16 ?? eim3e1 eim3e0 dm3e il3e2 il3e1 il3e0 ?? r/w ?? 000000 must be written as 10. dma trigger 0: disable 1: enable when dm3e = 0 interrupt number 62 (intdma2) 000: interrupt disabled. 001?111: priority level (1?7) when dm3e = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use. 31 30 29 28 27 26 25 24 ?? eim3f1 eim3f0 dm3f il3f2 il3f1 il3f0 ?? r/w ?? 000000 imcfh interrupt mode control register fh ffff e03eh must be written as 10. dma trigger 0: disable 1: enable when dm3f = 0 interrupt number 63 (intdma3) 000: interrupt disabled. 001?111: priority level (1?7) when dm3f = 1 dmac channel select 000?011: ch. number (0?3) 100?111: don?t use.
TMP1941AF 2003-03-27 TMP1941AF-273 interrupt controller (12 of 12) mnemonic name address 7 6 5 4 3 2 1 0 ivrl ???? r 00000000 interrupt vector for the source of the current interrupt 15 14 13 12 11 10 9 8 ivrh ivrl r/w r 00000000 interrupt vector for the source of the current interrupt 23 22 21 20 19 18 15 16 ivrh r/w 00000000 31 30 29 28 27 26 25 24 ivrh r/w ivr interrupt vector register ffff e040h 00000000 76543210 ?? eiclr5 eiclr4 eiclr3 eiclr2 eiclr1 eiclr0 ?? w ???????? intclr interrupt request clear register ffff e060h ivrl[9:4] value for an interrupt to be cleared
TMP1941AF 2003-03-27 TMP1941AF-274 19.3 chip select/wait controller chip select/wait controller (1 of 4) mnemonicnameaddress76543210 ma0 r/w 11111111 bits 9?0 specify the address bits (a23?a14) to be masked. 0: the corresponding address bit is not masked. 1: the corresponding address bit is masked. 15 14 13 12 11 10 9 8 ma0 r/w 00000000 must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. address mask 0: not masked 1: masked 23 22 21 20 19 18 17 16 ba0 r/w 00000000 a23?a16 of the starting address for cs0 31 30 29 28 27 26 25 24 ba0 r/w 00000000 bma0 base/ mask address register ffff e400h a31?a24 of the starting address for cs0 76543210 ma1 r/w 11111111 bits 9?0 specify the address bits (a23?a14) to be masked. 0: the corresponding address bit is not masked. 1: the corresponding address bit is masked. 15 14 13 12 11 10 9 8 ma1 r/w 00000000 must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. address mask 0: not masked 1: masked 23 22 21 20 19 18 17 16 ba1 r/w 00000000 a23?a16 of the starting address for cs1 31 30 29 28 27 26 25 24 ba1 r/w 00000000 bma1 base/ mask address register ffff e404h a31?a24 of the starting address for cs1
TMP1941AF 2003-03-27 TMP1941AF-275 chip select/wait controller (2 of 4) mnemonic name address 7 6 5 4 3 2 1 0 ma2 r/w 11111111 bits 8?0 specify the address bits (a23?a15) to be masked 0: the corresponding address bit is not masked. 1: the corresponding address bit is masked. 15 14 13 12 11 10 9 8 ma2 r/w 00000000 must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. address mask 0: not masked 1: masked 23 22 21 20 19 18 17 16 ba2 r/w 00000000 a23?a16 of the starting address for cs2 31 30 29 28 27 26 25 24 ba2 r/w 00000000 bma2 base/ mask address register ffff e408h a31?a24 of the starting address for cs2 76543210 ma3 r/w 11111111 bits 8?0 specify the address bits (a23?a15) to be masked 0: the corresponding address bit is not masked. 1: the corresponding address bit is masked. 15 14 13 12 11 10 9 8 ma3 r/w 00000000 must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. address mask 0: not masked 1: masked 23 22 21 20 19 18 17 16 ba3 r/w 00000000 a23?a16 of the starting address for cs3 31 30 29 28 27 26 25 24 ba3 r/w 00000000 bma3 base/ mask address register ffff e40ch a31?a24 of the starting address for cs3
TMP1941AF 2003-03-27 TMP1941AF-276 chip select/wait controller (3 of 4) mnemonic name address 7 6 5 4 3 2 1 0 b0om ? b0bus b0w w ? w 00 ? 00101 chip select output waveform 00: rom/sram don?t use any other value. data bus width 0: 16-bit 1: 8-bit number of wait-state cycles 0000: no wait state, 0001: 1 wait state 0010: 2 wait states, 0011: 3 wait states 0100: 4 wait states, 0101: 5 wait states 0110: 6 wait states, 0111: 7 wait states 1111: (1 + n) wait states, as determined by the wait pin don?t use any other value. 15 14 13 12 11 10 9 8 ???? b0e ? b0rcv ???? w ? w ???? 0 ? 00 cs0 enable 0: disable 1: enable number of dummy cycles (read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: don?t use. 23 22 21 20 19 18 17 16 b1om ? b1bus b1w w ? w 00 ? 00101 chip select output waveform 00: rom/sram don?t use any other value. data bus width 0: 16-bit 1: 8-bit number of wait-state cycles 0000: no wait state, 0001: 1 wait state 0010: 2 wait states, 0011: 3 wait states 0100: 4 wait states, 0110: 5 wait states 0110: 6 wait states, 0111: 7 wait states 1111: (1 + n) wait states, as determined by the wait pin don?t use any other value. 31 30 29 28 27 26 25 24 ???? b1e ? b1rcv ???? w ? w ???? 0 ? 00 b01cs chip select/ wait control register ffff e480h cs1 enable 0: disable 1: enable number of dummy cycles (read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: don?t use.
TMP1941AF 2003-03-27 TMP1941AF-277 chip select/wait controller (4 of 4) mnemonic name address 7 6 5 4 3 2 1 0 b2om ? b2bus b2w w ? w 00 ? 00101 chip select output waveform 00: rom/sram don?t use any other value. data bus width 0: 16-bit 1: 8-bit number of wait-state cycles 0000: no wait state, 0001: 1 wait state 0010: 2 wait states, 0011: 3 wait states 0100: 4 wait states, 0101: 5 wait states 0110: 6 wait states, 0111: 7 wait states 1111: (1 + n) wait states, as determined by the wait pin don?t use any other value. 15 14 13 12 11 10 9 8 ???? b2e b2m b2rcv ???? ww w ???? 1000 cs2 enable 0: disable 1: enable cs2 space select 0: whole 4-gbyte space 1: cs space number of dummy cycles (read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: don?t use. 23 22 21 20 19 18 17 16 b3om ?? b3bus b3w w ?? w 00 ? 00101 chip select output waveform 00: rom/sram don?t use any other value. data bus width 0: 16-bit 1: 8-bit number of wait-state cycles 0000: no wait state, 0001: 1 wait state 0010: 2 wait states, 0011: 3 wait states 0100: 4 wait states, 0101: 5 wait states 0110: 6 wait states, 0111: 7 wait states 1111: (1 + n) wait states, as determined by the wait pin don?t use any other value. 31 30 29 28 27 26 25 24 ???? b3e ? b3rcv ???? w ? w ???? 0 ? 00 b23cs chip select/ wait control register ffff e484h cs3 enable 0: disable 1: enable number of dummy cycles (read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: don?t use. 76543210 bexom ? bexbus bexw w ? w 00 ? 00101 chip select output waveform 00: rom/sram don?t use any other value. data bus width 0: 16-bit 1: 8-bit sets the number of wait cycles 0000?0111: 0?7 wait states 1111: (1 + n) wait states, as determined by the wait pin don?t use any other value. 15 14 13 12 11 10 9 8 ?????? bexrcv ?????? w ?????? 00 bexcs chip select/ wait control register ffff e488h number of dummy cycles (read recovery time) 00: 2 dummy cycles 01: 1 dummy cycle 10: no dummy cycle 11: don?t use.
TMP1941AF 2003-03-27 TMP1941AF-278 19.4 clock generator (cg) clock generator (1 of 2) mnemonic name address 7 6 5 4 3 2 1 0 xen xten rxen rxten rsysck wuef prck1 prck0 r/w 10100000 syscr0 system clock control register 0 ffff ee00h high-speed oscillator 0: disable 1: enable low-speed oscillator 0: disable 1: enable high-speed oscillator after exiting stop mode 0: disable 1: enable low-speed oscillator after exiting stop mode 0: disable 1: enable clock select after exiting stop mode 0: high- speed 1: low- speed oscillator warm-up period (wup) timer on writes: 0: don?t- care 1: start wup on reads: 0: expired 1: not expired prescaler clock select 00: fperiph/4 01: fperiph/2 10: fperiph 11: reserved ?? sysck fpsel dfosc ? gear1 gear0 ?? r/w ? r/w ?? 000 ? 11 syscr1 system clock control register 1 ffff ee01h system clock (fsys) select 0: high- speed (fgear) 1: low- speed (fs) fperiph select 0: fgear 1: fc high-speed oscillator frequency divide factor 0: divide-by- 2 1: divide-by- 1 high-speed clock (fc) gear select 00: fc 01: fc/2 10: fc/4 11: fc/8 drvosch drvoscl wupt1 wupt0 stby1 stby0 ? drve r/w r/w r/w r/w r/w r/w ? r/w 001011 ? 0 syscr2 system clock control register 2 ffff ee02h high-speed oscillator drive capability 0: high 1: low low-speed oscillator drive capability 0: high 1: low oscillator warm-up time 00: reserved 01: 2 8 /input frequency 10: 2 14 /input frequency 11: 2 16 /input frequency standby mode select 00: reserved 01: stop mode 10: sleep mode 11: idle mode 1: pins are driven in stop mode. 0: pins are not driven in stop mode. ? scosel ? alesel ?? lupfg luptm ? r/w ? r/w ?? r/w ? 0 ? 1 ?? 00 syscr3 system clock control register 3 ffff ee03h scout output select 0: fs 1: fsys ale output width select 0: fsys 0.5 1: fsys 1.5 pll lock 0: locked 1: unlocked pll lock time select 0: 2 16 /input frequency 1: 2 12 /input frequency ?????? adcck1 adcck0 ?????? r/w r/w ?????? 00 adcclk adc conversion clock register ffff ee04h adc conversion clock (fadc) select 00: fsys/2 01: fsys/4 10: fsys/8 11: don?t use.
TMP1941AF 2003-03-27 TMP1941AF-279 clock generator (2 of 2) mnemonic name address 7 6 5 4 3 2 1 0 ?? emcg01 emcg00 ??? int0en ?? r/w ??? r/w ?? 10 ??? 0 imcga0 interrupt cg control register a0 ffff ee10h wake-up int0 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int0 enable 0: disable 1: enable ?? emcg11 emcg10 ??? int1en ?? r/w ??? r/w ?? 10 ??? 0 imcga1 interrupt cg control register a1 ffff ee11h wake-up int1 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int1 enable 0: disable 1: enable ?? emcg21 emcg20 ??? int2en ?? r/w ??? r/w ?? 10 ??? 0 imcga2 interrupt cg control register a2 ffff ee12h wake-up int2 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int2 enable 0: disable 1: enable ?? emcg31 emcg30 ???? ???????? ?? 10 ??? 0 imcga3 interrupt cg control register a3 ffff ee13h wake-up int3 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int3 enable 0: disable 1: enable ?? emcg41 emcg40 ???? ???????? ?? 10 ??? 0 imcgb0 interrupt cg control register b0 ffff ee14h wake-up int4 sensitivity 00: low level 01: high level 10: falling edge 11: rising edge int4 enable 0: disable 1: enable ???????? ???????? ?? 10 ??? 0 imcgb1 interrupt cg control register b1 ffff ee15h must be written as 10. must be written as 0. ???????? ???????? ?? 10 ??? 0 imcgb2 interrupt cg control register b2 ffff ee16h must be written as 10. must be written as 0. ?? emcg71 emcg72 ??? intrtcen ?? r/w ??? r/w ?? 10 ??? 0 imcgb3 interrupt cg control register b3 ffff ee17h must be written as 11. intrtc enable 0:disable 1: enable ????? icrcg2 icrcg1 icrcg0 ?? ? ?? w ? ????? 000 eicrcg interrupt request clear register ffff ee20h clear interrupt request (only when relevant interrupts are programmed to be used to exit stop/sleep mode.) 000: int0 100: int4 001: int1 101: reserved 010: int2 110: reserved 011: int3 111: intrtc
TMP1941AF 2003-03-27 TMP1941AF-280 19.5 dma controller (dmac) dma controller (1 of 16) mnemonic name address 7 6 5 4 3 2 1 0 sac0 dio dac1 dac0 trsiz1 trsiz0 dps1 dps0 r/w 00000000 source address count (bits 8 & 7) 00: incre- mented 01: decre- mented 1x: fixed destination (i/o) 0: memory 1: i/o destination address count 00: incremented 01: decremented 1x: fixed transfer size 0x: 32 bits 10: 16 bits 11: 8 bits device port size 0x: 32 bits 10: 16 bits 11: 8 bits 15 14 13 12 11 10 9 8 ? exr pose lev sreq relen sio sac1 r/w 00000000 must be written as 0. external request mode 1: external transfer request 0: internal transfer request must be written as 0. must be written as 1. snoop request 0: disabled 1: enabled bus release request enable 0: disabled 1: enabled source (i/o) 0: memory 1: i/o source address count (bits 8 & 7) 00: incre- mented 01: decre- mented 1x: fixed 23 22 21 20 19 18 17 16 nien abien ???? big ? r/w 11100010 normal completion interrupt enable 0: disabled 1: enabled abnormal termination interrupt enable 0: disabled 1: enabled must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. 31 30 29 28 27 26 25 24 str ??????? w ?????? w 00000000 ccr0 dma channel control register 0 ffff e200h 1: channel 0 start must be written as 0.
TMP1941AF 2003-03-27 TMP1941AF-281 dma controller (2 of 16) mnemonic name address 7 6 5 4 3 2 1 0 ????? ??? ????? r/w 00000 000 must be written as 0. must be written as 0. must be written as 0. 15 14 13 12 11 10 9 8 ????? ??? ????? ??? 00000 000 ????? ??? 23 22 21 20 19 18 17 16 nc abc ? bes bed conf ?? r/w r ?? 00000 000 1: normal completion status flag 1: abnormal termination status flag must be written as 0. 1: bus error (source) 1: bus error (destination) 1: configuration error 31 30 29 28 27 26 25 24 act ???? ??? r ???? ??? 00000 000 csr0 dma channel status register 0 ffff e204h 1: channel 0 active
TMP1941AF 2003-03-27 TMP1941AF-282 dma controller (3 of 16) mnemonicnameaddress76543210 saddr7 saddr6 saddr5 saddr4 saddr3 saddr2 saddr1 saddr0 r/w undefined 15 14 13 12 11 10 9 8 saddr15 saddr14 saddr13 saddr12 saddr11 saddr10 saddr9 saddr8 r/w undefined 23 22 21 20 19 18 17 16 saddr23 saddr22 saddr21 saddr20 saddr19 saddr18 saddr17 saddr16 r/w undefined 31 30 29 28 27 26 25 24 saddr31 saddr30 saddr29 saddr28 saddr27 saddr26 saddr25 saddr24 r/w sar0 dma source address register 0 ffff e208h undefined 76543210 daddr7 daddr6 daddr5 daddr4 daddr3 daddr2 daddr1 daddr0 r/w undefined 15 14 13 12 11 10 9 8 daddr15 daddr14 daddr13 daddr12 daddr11 daddr10 daddr9 daddr8 r/w undefined 23 22 21 20 19 18 17 16 daddr23 daddr22 daddr21 daddr20 daddr19 daddr18 daddr17 daddr16 r/w undefined 31 30 29 28 27 26 25 24 daddr31 daddr30 daddr29 daddr28 daddr27 daddr26 daddr25 daddr24 r/w dar0 dma destination address register 0 ffff e20ch undefined 76543210 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 r/w undefined 15 14 13 12 11 10 9 8 bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 r/w undefined 23 22 21 20 19 18 17 16 bc23 bc22 bc21 bc20 bc19 bc18 bc17 bc16 r/w undefined 31 30 29 28 27 26 25 24 ???????? ? bcr0 dma byte count register 0 ffff e210h 00000000
TMP1941AF 2003-03-27 TMP1941AF-283 dma controller (4 of 16) mnemonic name address 7 6 5 4 3 2 1 0 ?? dacm2 dacm1 dacm0 sacm2 sacm1 sacm0 ?? r/w 00000000 bit position at which destination addresses are counted 000: bit 0 001: bit 4 010: bit 8 011: bit 12 100: bit 16 101: reserved 110: reserved 111: reserved bit position at which source addresses are counted 000: bit 0 001: bit 4 010: bit 8 011: bit 12 100: bit 16 101: reserved 110: reserved 111: reserved 15 14 13 12 11 10 9 8 ???????? 00000000 23 22 21 20 19 18 17 16 ???????? 00000000 31 30 29 28 27 26 25 24 ???????? dtcr0 dma transfer control register 0 ffff e218h 00000000
TMP1941AF 2003-03-27 TMP1941AF-284 dma controller (5 of 16) mnemonic name address 7 6 5 4 3 2 1 0 sac0 dio dac1 dac0 trsiz1 trsiz0 dps1 dps0 r/w 00000000 source address count (bits 8 & 7) 00: incre- mented 01: decre- mented 1x: fixed destination (i/o) 0: memory 1: i/o destination address count 00: incremented 01: decremented 1x: fixed transfer size 0x: 32 bits 10: 16 bits 11: 8 bits device port size 0x: 32 bits 10: 16 bits 11: 8 bits 15 14 13 12 11 10 9 8 ? exr pose lev sreq relen sio sac1 r/w 00000000 must be written as 0. external request mode 1: external 0: internal must be written as 0. must be written as 1. snoop request 0: disabled 1: enabled bus release request enable 0: disabled 1: enabled source (i/o) 0: memory 1: i/o source address count (bits 8 & 7) 00: inc 01: dec 1x: fixed 23 22 21 20 19 18 17 16 nien abien ???? big ? r/w 11100010 normal completion interrupt enable 0: disabled 1: enabled abnormal termination interrupt enable 0: disabled 1: enabled must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. 31 30 29 28 27 26 25 24 str ??????? w ?????? w 00000000 ccr1 dma channel control register 1 ffff e220h 1: channel 1 start must be written as 0.
TMP1941AF 2003-03-27 TMP1941AF-285 dma controller (6 of 16) mnemonic name address 7 6 5 4 3 2 1 0 ????? ??? ????? r/w 00000 000 must be written as 0. must be written as 0. must be written as 0. 15 14 13 12 11 10 9 8 ????? ??? ????? ??? 00000 000 23 22 21 20 19 18 17 16 nc abc ? bes bed conf ?? r/w r ?? 00000 000 1: normal termination status flag 1: abnormal termination status flag must be written as 0. 1: bus error (source) 1: bus error (destination) 1: configuration error 31 30 29 28 27 26 25 24 act ???? ??? r ???? ??? 00000 000 csr1 dma channel status register 1 ffff e224h 1: channel 1 active
TMP1941AF 2003-03-27 TMP1941AF-286 dma controller (7 of 16) mnemonic name address 7 6 5 4 3 2 1 0 saddr7 saddr6 saddr5 saddr4 saddr3 saddr2 saddr1 saddr0 r/w undefined 15 14 13 12 11 10 9 8 saddr15 saddr14 saddr13 saddr12 saddr11 saddr10 saddr9 saddr8 r/w undefined 23 22 21 20 19 18 17 16 saddr23 saddr22 saddr21 saddr20 saddr19 saddr18 saddr17 saddr16 r/w undefined 31 30 29 28 27 26 25 24 saddr31 saddr30 saddr29 saddr28 saddr27 saddr26 saddr25 saddr24 r/w sar1 dma source address register 1 ffff e228h undefined 76543210 daddr7 daddr6 daddr5 daddr4 daddr3 daddr2 daddr1 daddr0 r/w undefined 15 14 13 12 11 10 9 8 daddr15 daddr14 daddr13 daddr12 daddr11 daddr10 daddr9 daddr8 r/w undefined 23 22 21 20 19 18 17 16 daddr23 daddr22 daddr21 daddr20 daddr19 daddr18 daddr17 daddr16 r/w undefined 31 30 29 28 27 26 25 24 daddr31 daddr30 daddr29 daddr28 daddr27 daddr26 daddr25 daddr24 r/w dar1 dma destination address register 1 ffff e22ch undefined 76543210 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 r/w undefined 15 14 13 12 11 10 9 8 bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 r/w undefined 23 22 21 20 19 18 17 16 bc23 bc22 bc21 bc20 bc19 bc18 bc17 bc16 r/w undefined 31 30 29 28 27 26 25 24 ???????? ? bcr1 dma byte count register 1 ffff e230h 00000000
TMP1941AF 2003-03-27 TMP1941AF-287 dma controller (8 of 16) mnemonic name address 7 6 5 4 3 2 1 0 ?? dacm2 dacm1 dacm0 sacm2 sacm1 sacm0 ?? r/w 00000000 bit position at which destination addresses are counted 000: bit 0 001: bit 4 010: bit 8 011: bit 12 100: bit 16 101: reserved 110: reserved 111: reserved bit position at which source addresses are counted 000: bit 0 001: bit 4 010: bit 8 011: bit 12 100: bit 16 101: reserved 110: reserved 111: reserved 15 14 13 12 11 10 9 8 ???????? ? 00000000 23 22 21 20 19 18 17 16 ???????? ? 00000000 31 30 29 28 27 26 25 24 ???????? ? dtcr1 dma transfer control register 1 ffff e238h 00000000
TMP1941AF 2003-03-27 TMP1941AF-288 dma controller (9 of 16) mnemonic name address 7 6 5 4 3 2 1 0 sac0 dio dac1 dac0 trsiz1 trsiz0 dps1 dps0 r/w 00000000 source address count (bits 8 & 7) 00: incre- mented 01: decre- mented 1x: fixed destination (i/o) 0: memory 1: i/o destination address count 00: incremented 01: decremented 1x: fixed transfer size 0x: 32 bits 10: 16 bits 11: 8 bits device port size 0x: 32 bits 10: 16 bits 11: 8 bits 15 14 13 12 11 10 9 8 ? exr pose lev sreq relen sio sac1 r/w 00000000 must be written as 0. external request mode 1: external transfer request 0: internal transfer request must be written as 0. must be written as 1. snoop request 0: disabled 1: enabled bus release request enable 0: disabled 1: enabled source (i/o) 0: memory 1: i/o source address count (bits 8 & 7) 00: incre- mented 01: decre- mented 1x: fixed 23 22 21 20 19 18 17 16 nien abien ???? big ? r/w 11100010 normal completion interrupt enable 0: disabled 1: enabled abnormal termination interrupt enable 0: disabled 1: enabled must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. 31 30 29 28 27 26 25 24 str ??????? w ?????? w 00000000 ccr2 dma channel control register 2 ffff e240h 1: channel 2 start must be written as 0.
TMP1941AF 2003-03-27 TMP1941AF-289 dma controller (10 of 16) mnemonic name address 7 6 5 4 3 2 1 0 ????? ??? ????? r/w 00000 000 must be written as 0. must be written as 0. must be written as 0. 15 14 13 12 11 10 9 8 ????? ??? ????? ??? 00000 000 23 22 21 20 19 18 17 16 nc abc ? bes bed conf ?? r/w r ?? 00000 000 1: normal completion status flag 1: abnormal termination status flag must be written as 0. 1: bus error (source) 1: bus error (destination) 1: configuration error 31 30 29 28 27 26 25 24 act ???? ??? r ???? ??? 00000 000 csr2 dma channel status register 2 ffff e244h 1: channel 2 active
TMP1941AF 2003-03-27 TMP1941AF-290 dma controller (11 of 16) mnemonic name address 7 6 5 4 3 2 1 0 saddr7 saddr6 saddr5 saddr4 saddr3 saddr2 saddr1 saddr0 r/w undefined 15 14 13 12 11 10 9 8 saddr15 saddr14 saddr13 saddr12 saddr11 saddr10 saddr9 saddr8 r/w undefined 23 22 21 20 19 18 17 16 saddr23 saddr22 saddr21 saddr20 saddr19 saddr18 saddr17 saddr16 r/w undefined 31 30 29 28 27 26 25 24 saddr31 saddr30 saddr29 saddr28 saddr27 saddr26 saddr25 saddr24 r/w sar2 dma source address register 2 ffff e248h undefined 76543210 daddr7 daddr6 daddr5 daddr4 daddr3 daddr2 daddr1 daddr0 r/w undefined 15 14 13 12 11 10 9 8 daddr15 daddr14 daddr13 daddr12 daddr11 daddr10 daddr9 daddr8 r/w undefined 23 22 21 20 19 18 17 16 daddr23 daddr22 daddr21 daddr20 daddr19 daddr18 daddr17 daddr16 r/w undefined 31 30 29 28 27 26 25 24 daddr31 daddr30 daddr29 daddr28 daddr27 daddr26 daddr25 daddr24 r/w dar2 dma destination address register 2 ffff e24ch undefined 76543210 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 r/w undefined 15 14 13 12 11 10 9 8 bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 r/w undefined 23 22 21 20 19 18 17 16 bc23 bc22 bc21 bc20 bc19 bc18 bc17 bc16 r/w undefined 31 30 29 28 27 26 25 24 ???????? ? bcr2 dma byte count register 2 ffff e250h 00000000
TMP1941AF 2003-03-27 TMP1941AF-291 dma controller (12 of 16) mnemonic name address 7 6 5 4 3 2 1 0 ?? dacm2 dacm1 dacm0 sacm2 sacm1 sacm0 ?? r/w 00000000 bit position at which destination addresses are counted 000: bit 0 001: bit 4 010: bit 8 011: bit 12 100: bit 16 101: reserved 110: reserved 111: reserved bit position at which source addresses are counted 000: bit 0 001: bit 4 010: bit 8 011: bit 12 100: bit 16 101: reserved 110: reserved 111: reserved 15 14 13 12 11 10 9 8 ???????? ? 00000000 23 22 21 20 19 18 17 16 ???????? ? 00000000 31 30 29 28 27 26 25 24 ???????? ? dtcr2 dma transfer control register 2 ffff e258h 00000000
TMP1941AF 2003-03-27 TMP1941AF-292 dma controller (13 of 16) mnemonic name address 7 6 5 4 3 2 1 0 sac0 dio dac1 dac0 trsiz1 trsiz0 dps1 dps0 r/w 00000000 source address count (bits 8 & 7) 00: incre- mented 01: decre- mented 1x: fixed destination (i/o) 0: memory 1: i/o destination address count 00: incremented 01: decremented 1x: fixed transfer size 0x: 32 bits 10: 16 bits 11: 8 bits device port size 0x: 32 bits 10: 16 bits 11: 8 bits 15 14 13 12 11 10 9 8 ? exr pose lev sreq relen sio sac1 r/w 00000000 must be written as 0. external request mode 1: external transfer request 0: internal transfer request must be written as 0. must be written as 1. snoop request 0: disabled 1: enabled bus release request enable 0: disabled 1: enabled source (i/o) 0: memory 1: i/o source address count (bits 8 & 7) 00: incre- mented 01: decre- mented 1x: fixed 23 22 21 20 19 18 17 16 nien abien ???? big ? r/w 11100010 normal completion interrupt enable 0: disabled 1: enabled abnormal termination interrupt enable 0: disabled 1: enabled must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. must be written as 0. 31 30 29 28 27 26 25 24 str ??????? w ?????? w 00000000 ccr3 dma channel control register 3 ffff e260h 1: channel 3 start must be written as 0.
TMP1941AF 2003-03-27 TMP1941AF-293 dma controller (14 of 16) mnemonic name address 7 6 5 4 3 2 1 0 ????? ??? ????? r/w 00000 000 must be written as 0. must be written as 0. must be written as 0. 15 14 13 12 11 10 9 8 ????? ??? ????? ??? 00000 000 23 22 21 20 19 18 17 16 nc abc ? bes bed conf ?? r/w r ?? 00000 000 1: normal termination status flag 1: abnormal termination status flag must be written as 0. 1: bus error (source) 1: bus error (destination) 1: configuration error 31 30 29 28 27 26 25 24 act ???? ??? r ???? ??? 00000 000 csr3 dma channel status register 3 ffff e264h 1: channel 3 active
TMP1941AF 2003-03-27 TMP1941AF-294 dma controller (15 of 16) mnemonic name address 7 6 5 4 3 2 1 0 saddr7 saddr6 saddr5 saddr4 saddr3 saddr2 saddr1 saddr0 r/w undefined 15 14 13 12 11 10 9 8 saddr15 saddr14 saddr13 saddr12 saddr11 saddr10 saddr9 saddr8 r/w undefined 23 22 21 20 19 18 17 16 saddr23 saddr22 saddr21 saddr20 saddr19 saddr18 saddr17 saddr16 r/w undefined 31 30 29 28 27 26 25 24 saddr31 saddr30 saddr29 saddr28 saddr27 saddr26 saddr25 saddr24 r/w sar3 dma source address register 3 ffff e268h undefined 76543210 daddr7 daddr6 daddr5 daddr4 daddr3 daddr2 daddr1 daddr0 r/w undefined 15 14 13 12 11 10 9 8 daddr15 daddr14 daddr13 daddr12 daddr11 daddr10 daddr9 daddr8 r/w undefined 23 22 21 20 19 18 17 16 daddr23 daddr22 daddr21 daddr20 daddr19 daddr18 daddr17 daddr16 r/w undefined 31 30 29 28 27 26 25 24 daddr31 daddr30 daddr29 daddr28 daddr27 daddr26 daddr25 daddr24 r/w dar3 dma destination address register 3 ffff e26ch undefined 76543210 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 r/w undefined 15 14 13 12 11 10 9 8 bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 r/w undefined 23 22 21 20 19 18 17 16 bc23 bc22 bc21 bc20 bc19 bc18 bc17 bc16 r/w undefined 31 30 29 28 27 26 25 24 ???????? ? bcr3 dma byte count register 3 ffff e270h 00000000
TMP1941AF 2003-03-27 TMP1941AF-295 dma controller (16 of 16) mnemonic name address 7 6 5 4 3 2 1 0 ?? dacm2 dacm1 dacm0 sacm2 sacm1 sacm0 ?? r/w 00000000 bit position at which destination addresses are counted 000: bit 0 001: bit 4 010: bit 8 011: bit 12 100: bit 16 101: reserved 110: reserved 111: reserved bit position at which source addresses are counted 000: bit 0 001: bit 4 010: bit 8 011: bit 12 100: bit 16 101: reserved 110: reserved 111: reserved 15 14 13 12 11 10 9 8 ???????? ? 00000000 23 22 21 20 19 18 17 16 ???????? ? 00000000 31 30 29 28 27 26 25 24 ???????? ? dtcr3 dma transfer control register 3 ffff e278h 00000000 76543210 ???????? ???????? 00000000 15 14 13 12 11 10 9 8 ???????? ???????? 00000000 23 22 21 20 19 18 17 16 ???????? ???????? 00000000 31 30 29 28 27 26 25 24 rst ??????? w ??????? 00000000 dcr dma control register ffff e280h 1: dmac software reset 76543210 dot7 dot6 dot5 dot4 dot3 dot2 dot1 dot0 r/w undefined 15 14 13 12 11 10 9 8 dot15 dot14 dot13 dot12 dot11 dot10 dot9 dot8 r/w undefined 23 22 21 20 19 18 17 16 dot23 dot22 dot21 dot20 dot19 dot18 dot17 dot16 r/w undefined 31 30 29 28 27 26 25 24 dot31 dot30 dot29 dot28 dot27 dot26 dot25 dot24 r/w dhr dma data holding register ffff e28ch undefined
TMP1941AF 2003-03-27 TMP1941AF-296 19.6 8-bit timers (tmras) mnemonic name address 7 6 5 4 3 2 1 0 ta0rde ??? i2ta01 ta01prun ta1run ta0run r/w ??? r/w 0 ??? 0000 ta01run tmra01 run register ffff f100h double buffering 0: disable 1: enable idle 0: off 1: on prescalar run/stop control 0: stop 1: run run/stop control 0: stop & clear 1: run ta2rde ??? i2ta23 ta23prun ta3run ta2run r/w ??? r/w 0 ??? 0000 ta23run tmra23 run register ffff f108h double buffering 0: disable 1: enable idle 0: off 1: on prescalar run/stop control 0: stop 1: run run/stop control 0: stop & clear 1: run ta01m1 ta01m0 pwm01 pwm00 ta1clk1 ta1clk0 ta0clk1 ta0clk0 r/w 00000000 ta01mod tmra01 mode register ffff f104h operating mode 00: 8-bit interval timer 01: 16-bit interval timer 10: 8-bit ppg 11: 8-bit pwm pwm period 00: reserved 01: 2 6 -1 10: 2 7 -1 11: 2 8 -1 tmra1 clock source 00: ta0trg 01: t1 10: t16 11: t256 tmra0 clock source 00: ta0in input 01: t1 10: t4 11: t16 ta23m1 ta23m0 pwm21 pwm20 ta3clk1 ta3clk0 ta2clk1 ta2clk0 r/w 00000000 ta23mod tmra23 mode register ffff f10ch operating mode 00: 8-bit interval timer 01: 16-bit interval timer 10: 8-bit ppg 11: 8-bit pwm pwm period 00: reserved 01: 2 6 -1 10: 2 7 -1 11: 2 8 -1 tmra3 clock source 00: ta2trg 01: t1 10: t16 11: t256 tmra2 clock source 00: ta2in input pin 01: t1 10: t4 11: t16 ???? taff1c1 taff1c0 taff1ie taff1is ???? r/w ???? 1100 ta1ffcr tmra01 timer flip- flop control register ffff f105h 00: toggles ta1ff. (software toggle) 01: sets ta1ff to 1. 10: clears ta1ff to 0. 11: don?t-care this field is always read as 11. ta1ff toggle enable 0: disable 1: enable ta1ff toggle trigger 0: tmra0 1: tmra1 ???? taff3c1 taff3c0 taff3ie taff3is ???? r/w ???? 1100 ta3ffcr tmra23 timer flip- flop control register ffff f10dh 00: toggles ta3ff (software toggle). 01: sets ta3ff to 1 10: clears ta3ff to 0 11: don?t care this field is always read as 11. ta3ff toggle enable 0: disable 1: enable ta3ff trigger 0: tmra2 1: tmra3
TMP1941AF 2003-03-27 TMP1941AF-297 19.7 16-bit timer/event counters (tmrbs) 16-bit timer control (1 of 2) mnemonic name address 7 6 5 4 3 2 1 0 tb0rde ??? i2tb0 tb0prun ? tb0run r/w ?? r/w ? r/w 00 ?? 00 ? 0 tb0run tmrb0 run register ffff f180h double buffering 0: disable 1: enable must be written as 0. idle 0: off 1: on prescalar run/stop control 0: stop 1: run run/stop control 0: stop & clear 1: run tb1rde ??? i2tb1 tb1prun ? tb1run r/w ?? r/w ? r/w 00 ?? 00 ? 0 tb1run tmrb1 run register ffff f190h double buffering 0: disable 1: enable must be written as 0. idle 0: off 1: on prescalar run/stop control 0: stop 1: run run/stop control 0: stop & clear 1: run tb2rde ??? i2tb2 tb2prun ? tb2run r/w ?? r/w ? r/w 00 ?? 00 ? 0 tb2run tmrb2 run register ffff f1a0h double buffering 0: disable 1: enable must be written as 0. idle 0: off 1: on prescalar run/stop control 0: stop 1: run run/stop control 0: stop & clear 1: run tb3rde ??? i2tb3 tb3prun ? tb3run r/w ?? r/w ? r/w 00 ?? 00 ? 0 tb3run tmrb3 run register ffff f1b0h double buffering 0: disable 1: enable must be written as 0. idle 0: off 1: on prescalar run/stop control 0: stop 1: run run/stop control 0: stop & clear 1: run ?? tb0cp0 tb0cpm1 tb0cpm0 tb0cle tb0clk1 tb0clk0 r/w w * r/w 00100000 tb0mod tmrb0 mode register ffff f182h must be written as 00. software capture 0: capture 1: don?t care capture triggers 00: disabled 01: tb0in0 tb0in1 10: tb0in0 tb0in0 11: ta1out ta1out uc0 clear control 0: disable 1: enable tmrb0 clock source 00: tb0in0 input 01: t1 10: t4 11: t16 ?? tb1cp0 tb1cpm1 tb1cpm0 tb1cle tb1clk1 tb1clk0 r/w w * r/w 00100000 tb1mod tmrb1 mode register ffff f192h must be written as 00. software capture 0: capture 1: don?t care capture triggers 00: disabled 01: tb1in0 tb1in1 10: tb1in0 tb1in0 11: ta1out ta1out uc1 clear control 0: disable 1: enable tmrb1 clock source 00: tb1in0 input 01: t1 10: t4 11: t16 ?? tb2cp0 tb2cpm1 tb2cpm0 tb2cle tb2clk1 tb2clk0 r/w w * r/w 00100000 tb2mod tmrb2 mode register ffff f1a2h must be written as 00. software capture 0: capture 1: don?t care capture triggers 00: disabled 01: tb2in0 tb2in1 10: tb2in0 tb2in0 11: ta1out ta1out uc2 clear control 0: disable 1: enable tmrb2 clock source 00: tb2in0 input 01: t1 10: t4 11: t16 ?? tb3cp0 tb3cpm1 tb3cpm0 tb3cle tb3clk1 tb3clk0 r/w w * r/w 00100000 tb3mod tmrb3 mode register ffff f1b2h must be written as 00. software capture 0: capture 1: don?t care capture triggers 00: disabled 01: disabled 10: disabled 11: ta1out ta1out uc3 clear control 0: disable 1: enable tmrb3 clock source 00: tb3in0 input 01: t1 10: t4 11: t16
TMP1941AF 2003-03-27 TMP1941AF-298 16-bit timer control (2 of 2) mnemonic name address 7 6 5 4 3 2 1 0 ?? tb0c1t1 tb0c0t1 tb0e1t1 tb0e0t1 tb0ff0c1 tb0ff0c0 w * r/w w * 11000011 tb0ff0 toggle-trigger 0: trigger disabled 1: trigger enabled tb0ffcr tmrb0 timer flip- flop control register ffff f183h must be written as 11. * this field is always read as 11. uc0 tb0cp1 uc0 tb0cp0 uc0 = tb0rg1 uc0 = tb0rg0 tb0ff0 control 00: toggle 01: set 10: clear 11: don?t care * this field is always read as 11. ?? tb1c1t1 tb1c0t1 tb1e1t1 tb1e0t1 tb1ff0c1 tb1ff0c0 w * r/w w * 11000011 tb1ff0 toggle-trigger 0: trigger disabled 1: trigger enabled tb1ffcr tmrb1 timer flip- flop control register ffff f193h must be written as 11. * this field is always read as 11. uc1 tb1cp1 uc1 tb1cp0 uc1 = tb1rg1 uc1 = tb1rg0 tb1ff0 control 00: toggle 01: set 10: clear 11: don?t care * this field is always read as 11. ?? tb2c1t1 tb2c0t1 tb2e1t1 tb2e0t1 tb2ff0c1 tb2ff0c0 w * r/w w * 11000011 tb2ff0 toggle-trigger 0: trigger disabled 1: trigger enabled tb2ffcr tmrb2 timer flip- flop control register ffff f1a3h must be written as 11. * this field is always read as 11. uc2 tb2cp1 uc2 tb2cp0 uc2 = tb2rg1 uc2 = tb2rg0 tb2ff0 control 00: toggle 01: set 10: clear 11: don?t care * this field is always read as 11. ?? tb3c1t1 tb3c0t1 tb3e1t1 tb3e0t1 tb3ff0c1 tb3ff0c0 w * r/w w * 11000011 tb3ff0 toggle-trigger 0: trigger disabled 1: trigger enabled tb3ffcr tmrb3 timer flip- flop control register ffff f1b3h must be written as 11. * this field is always read as 11. uc3 tb3cp1 uc3 tb3cp0 uc3 = tb3rg1 uc3 = tb3rg0 tb3ff0 control 00: toggle 01: set 10: clear 11: don?t care * this field is always read as 11.
TMP1941AF 2003-03-27 TMP1941AF-299 19.8 serial i/o (sio) sio0 mnemonic name address 7 6 5 4 3 2 1 0 rb8 even pe oerr perr ferr sclks ioc r r/w r (cleared when read) r/w 00000000 1: error has occurred. sc0cr serial channel 0 control register ffff f201h bit 8 of a received character parity type 0: odd 1: even parity 0: disabled 1: enabled overrun parity framing 0:sclk0 1:sclk0 0: baud rate generator 1: sclk0 input tb8 ctse rxe wu sm1 sm0 sc1 sc0 r/w 00000000 sc0mod0 serial channel 0 mode register 0 ffff f202h bit 8 of a transmitted character handshake control 0: disables cts operation 1: enables cts operation receive control 0: disables receiver 1: enables receiver wake-up function 0: disabled 1: enabled serial transfer mode 00: i/o interface mode 01: 7-bit uart mode 10: 8-bit uart mode 11: 9-bit uart mode serial clock (for uart) 00: ta0trg (timer) 01: baud rate generator 10: internal fsys/2 clock 11: external clock (sclk0 input) ? br0adde br0ck1 br0ck0 br0s3 br0s2 br0s1 br0s0 r/w 00000000 br0cr baud rate generator 0 control register ffff f203h must be written as 0. n + (16?k)/16 function 0: disabled 1: enabled 00: t0 01: t2 10: t8 11: t32 clock divisor value n ???? br0k3 br0k2 br0k1 br0k0 ???? r/w ???? 0000 br0add baud rate generator 0 control register ffff f204h value of k in n+(16?k)/16 i2s0 fdpx0 ?????? r/w r/w ?????? 00 ?????? sc0mod1 serial channel 0 mode register 1 ffff f205h idle 0: off 1: on synchro- nous 0: half- duplex 1: full- duplex
TMP1941AF 2003-03-27 TMP1941AF-300 sio1 mnemonic name address 7 6 5 4 3 2 1 0 rb8 even pe oerr perr ferr sclks ioc r r/w r (cleared when read) r/w 00000000 1: error has occurred. sc1cr serial channel 1 control register ffff f209h bit 8 of a received character parity type 0: odd 1: even parity 0: disabled 1: enabled overrun parity framing 0: sclk1 1: sclk1 0: baud rate generator 1: sclk1 input tb8 ctse rxe wu sm1 sm0 sc1 sc0 r/w 00000000 sc1mod0 serial channel 1 mode register 0 ffff f20ah bit 8 of a transmitted character handshake control 0: disables cts operation 1: enables cts operation receive control 0: disables receiver 1: enables receiver wake-up function 0: disabled 1: enabled serial transfer mode 00: i/o interface mode 01: 7-bit uart mode 10: 8-bit uart mode 11: 9-bit uart mode serial clock (for uart) 00: ta0trg (timer) 01: baud rate generator 10: internal fsys/2 clock 11: external clock (sclk1 input) ? br1adde br1ck1 br1ck0 br1s3 br1s2 br1s1 br1s0 r/w 00000000 br1cr baud rate generator 1 control register ffff f20bh must be written as 0. n + (16?k)/16 function 0: disabled 1: enabled 00: t0 01: t2 10: t8 11: t32 clock divisor value n ???? brk1k3 brk1k2 brk1k1 brk1k0 ???? r/w ???? 0000 br1add baud rate generator 1 control register ffff f20ch value of k in n+(16?k)/16 i2s0 fdpx0 ?????? r/w ?????? 00 ?????? sc1mod1 serial channel 1 mode register 1 ffff f20dh idle 0: off 1: on synchro- nous 0: half- duplex 1: full- duplex
TMP1941AF 2003-03-27 TMP1941AF-301 sio3 mnemonic name address 7 6 5 4 3 2 1 0 rb8 even pe oerr perr ferr ?? r r/w r (cleared when read) r/w 00000000 1: error has occurred. sc3cr serial channel 3 control register ffff f281h bit 8 of a received character parity type 0: odd 1: even parity 0: disabled 1: enabled overrun parity framing must be written as 00. tb8 ctse rxe wu sm1 sm0 sc1 sc0 r/w 00000000 sc3mod0 serial channel 3 mode register 0 ffff f282h bit 8 of a transmitted character must be written as 0. receive control 0: disables receiver 1: enables receiver wake-up function 0: disabled 1: enabled serial transfer mode 00: reserved 01: 7-bit uart mode 10: 8-bit uart mode 11: 9-bit uart mode serial clock (for uart) 00: ta0trg (timer) 01: baud rate generator 10: internal fsys/2 clock 11: don?t care ? br3adde br3ck1 br3ck0 br3s3 br3s2 br3s1 br3s0 r/w 00000000 br3cr baud rate generator 3 control register ffff f283h must be written as 0. n + (16?k)/16 function 0: disabled 1: enabled 00: t0 01: t2 10: t8 11: t32 clock divisor value n ???? br3k3 br3k2 br3k1 br3k0 ???? r/w ???? 0000 br3add baud rate generator 3 control register ffff f284h ???? value of k in n+(16?k)/16 i2s0 ??????? r/w ??????? 0 ??????? sc3mod1 serial channel 3 mode register 1 ffff f285h idle 0: off 1: on sio4 mnemonic name address 7 6 5 4 3 2 1 0 rb8 even pe oerr perr ferr ?? r r/w r (cleared when read) r/w 00000000 1: error has occurred. sc4cr serial channel 4 control register ffff f289h bit 8 of a received character parity type 0: odd 1: even parity 0: disabled 1: enabled overrun parity framing must be written as 00. tb8 ctse rxe wu sm1 sm0 sc1 sc0 r/w 00000000 sc4mod0 serial channel 4 mode register 0 ffff f28ah bit 8 of a transmitted character must be written as 0. receive control 0: disables receiver 1: enables receiver wake-up function 0: disabled 1: enabled serial transfer mode 00: reserved 01: 7-bit uart mode 10: 8-bit uart mode 11: 9-bit uart mode serial clock (for uart) 00: ta0trg (timer) 01: baud rate generator 10: internal fsys/2 clock 11: don?t care ? br4adde br4ck1 br4ck0 br4s3 br4s2 br4s1 br4s0 r/w 00000000 br4cr baud rate generator 4 control register ffff f28bh must be written as 0. n + (16?k)/16 function 0: disabled 1: enabled 00: t0 01: t2 10: t8 11: t32 clock divisor value n ???? br4k3 br4k2 br4k1 br4k0 ???? r/w ???? 0000 br4add baud rate generator 4 control register ffff f28ch value of k in n+(16?k)/16 i2s0 ??????? r/w ??????? 0 ??????? sc4mod1 serial channel 4 mode register 1 ffff f28dh idle 0: off 1: on
TMP1941AF 2003-03-27 TMP1941AF-302 19.9 serial bus interface (sbi) mnemonic name address 7 6 5 4 3 2 1 0/ bc2 bc1 bc0 ack ? sck2 sck1 sck0 swrmon wr/w ? wwr/w 0000 ? 001 ffff f240h (i 2 c bus mode) number of bits per transfer (when ack = 0) 000: 8, 001: 1, 010: 2 011: 3, 100: 4, 101: 5 110: 6, 111: 7 ack clock pulse 0: no ack 1: ack internal scl output clock frequency (on writes) / software reset monitor 000: 4, 001: 5, 010: 6 011: 7, 100: 8, 101: 9 110: 10, 111: reserved sios sioinh siom1 siom0 ? sck2 sck1 sck0 w ? wr/w 0000 ? 001 sbi0cr1 serial bus interface control register 1 ffff f240h (sio mode) start transfer 0: stop 1: start abort transfer 0: continue 1: abort transfer mode 00: transmit mode 01: reserved 10: transmit/receive mode 11: receive mode serial clock frequency (on writes) / software reset monitor 000: 3, 001: 4, 010: 5 011: 6, 100: 7, 101: 8 110: 9, 111: external clock db7 db6 db5 db4 db3 db2 db1 db0 r (receive) / w (transmit) sbi0dbr sbi data buffer register ffff f241h undefined sa6 sa5 sa4 sa3 sa2 sa1 sa0 als w 00000000 i2c0ar i 2 c bus address register ffff f242h when the sbi is addressed as a slave, this field specifies a 7-bit i 2 c-bus address to which the sbi responds. address recognition 0: recognize 1: does not recognize mst trx bb pin sbim1 sbim0 swrst1 swrst0 w 00010000 master/ slave transmit/ receive start/ stop generation intsbi interrupt clear operating mode 00: port mode 01: sio mode 10: i 2 c bus mode 11: reserved software reset a write of 10 followed by a write of 01 mst trx bb pin al aas ad0 lrb r 00010000 ffff f243h (i 2 c bus mode) master/ slave transmit/ receive i 2 c bus status ints2 interrupt status arbitration lost 0: ? 1: detected addressed as slave 0: ? 1: detected address 0 (general call) 0: ? 1: detected last received bit 0: 0 1: 1 ???? siof sef ?? ???? r ?? ???? 00 ?? sbi0cr2 on writes sbi0sr on reads serial bus interface control 2 /status register ffff f243h (sio mode) serial transfer status 0: terminated 1: in progress shift operation status 0: terminated 1: in progress ? i 2 sbi0 ?????? ? r/w ????? w ? 0 ????? 0 sbi0br0 serial bus interface control register 0 ffff f244h idle 0: off 1: on must be written as 0. p4en ??????? r/w ??????? 0 ??????? sbi0br1 serial bus interface control register 1 ffff f245h internal clock 0: off 1: on
TMP1941AF 2003-03-27 TMP1941AF-303 19.10 a/d converter (adc) mnemonic name address 7 6 5 4 3 2 1 0 eocf adbf ?? itm0 repeat scan ads rr/w 00000000 admod0 a/d mode control register 0 ffff f310h end-of- conversion flag 0: before conversion or conversion in progress 1: conversion completed a/d conversion busy flag 0: idle 1: conversion in progress must be written as 0. must be written as 0. interrupt timing in fixed- channel continuous conversion mode 1: continuous conversion 1: channel scan conversion 1: a/d conversion start vrefon i2ad ?? adtrge adch2 adch1 adch0 r/w ?? r/w 00 ?? 0000 analog input channel select scan=0 scan=1 000 an0 an0 001 an1 an0 an1 010 an2 an0 an1 an2 011 an3 an0 an1 an2 an3 100 an4 an4 101 an5 an4 an5 110 an6 an4 an5 an6 111 an7 an6 an7 admod1 a/d mode control register 1 ffff f311h vref control 0: off 1: on idle 0: off 1: on external conversion trigger 0: disable 1: enable adr01 adr00 ????? adr0rf r ????? r adreg04l a/d conversion result reg 0/4 low ffff f300h undefined ????? 0 adr09 adr08 adr07 adr06 adr05 adr04 adr03 adr02 r adreg04h a/d conversion result reg 0/4 high ffff f301h undefined adr11 adr10 ????? adr1rf r ????? r adreg15l a/d conversion result reg 1/5 low ffff f302h undefined ????? 0 adr19 adr18 adr17 adr16 adr15 adr14 adr13 adr12 r adreg15h a/d conversion result reg 1/5 high ffff f303h undefined adr21 adr20 ????? adr2rf r ????? r adreg26l a/d conversion result reg 2/6 low ffff f304h undefined ????? 0 adr29 adr28 adr27 adr26 adr25 adr24 adr23 adr22 r adreg26h a/d conversion result reg 2/6 high ffff f305h undefined adr31 adr30 ????? adr3rf r ????? r adreg37l ad result reg 3/7 low ffff f306h undefined ????? 0 adr39 adr38 adr37 adr36 adr35 adr34 adr33 adr32 r adreg37h a/d conversion result reg 3/7 high ffff f307h undefined ?????? adcck1 adcck0 ?????? r/w ?????? 00 adcclk a/d conversion clock select register ffff ee04h a/d conversion clock 00: fsys/2 01: fsys/4 10: fsys/8 11: reserved
TMP1941AF 2003-03-27 TMP1941AF-304 19.11 watchdog timer (wdt) mnemonic name address 7 6 5 4 3 2 1 0 wdte wdtp1 wdtp0 ?? i2wdt rescr ? r/w r/w ?? r/w 100 ?? 000 wdmod wdt mode register ffff f090h 1: wdt enable 00: 2 16 /fsys 01: 2 18 / fsys 10: 2 20 / fsys 11: 2 22 / fsys idle 0: off 1: on 1: system reset must be written as 0. ? w ? wdcr wdt control register ffff f091h b1h: wdt disable code; 4eh: wdt clear-count code 19.12 real-time clock (rtc) mnemonic name address 7 6 5 4 3 2 1 0 ???? rtcrclr rtcsel1 rtcsel0 rtcrun r/w ??? r/w r/w r/w 0 ??? 0000 rtccr rtc control register ffff f0a0h must be written as 0. 0: clears accumulator. 00: 2 14 /fs 01: 2 13 /fs 10: 2 12 /fs 11: 2 11 /fs 0: stop and clear the counter. 1: begin counting. rui7 rui6 rui5 rui4 rui3 rui2 rui1 rui0 r rtcreg rtc accumu- lator register ffff f0a4h 0000 0 000
TMP1941AF 2003-03-27 TMP1941AF-305 20. i/o port equivalent-circuit diagrams ? how to read circuit diagrams the circuit diagrams in this chapter are drawn using the same gate symbols as for the 74hcxx series standard cmos logic ics. the signal named stop has a unique function. this signal goes active-high if the cpu sets the halt bit when the stby[1:0] field in the syscr2 register is programmed to 01 (i.e., stop mode) and the drive enable (drve) bit in the same register is cleared. if the drve bit is set, the stop signal remains inactive (at logic 0). ? the input protection circuit has a resistor in the range of several tens to several hundreds of ohms. ad0?ad7, ad8?ad15, a8?a15, p44, p71, p73?p76, p80?p87, p91?p92, p94?p95, pa0?pa5 a16?a23, a0?a7, rd , wr hwr , wait , busrq , busak , w / r , p37, p40?43 vcc output data p-ch input/output input data output enable stop input enable n-ch output vcc output data stop n-ch input/output input enable vcc output data output enable stop input data vcc programmable pullup resistor p-ch
TMP1941AF 2003-03-27 TMP1941AF-306 port 5 (an0?an7) p77 (int0) p70, p72, p90, p93, pa6?pa7 p96 (xt1), p97 (xt2) analog input channel select input input data analog input input enable input/output input enable vcc output data output enable stop input data open-drain output enable p-ch n-ch p96(xt1) p97(xt2) in p ut enable clock output data stop input data in p ut enable low-frequency oscillator enable input data output data output enable output enable oscillator circuit input/output schmitt-trigger vcc output data output enable stop input data
TMP1941AF 2003-03-27 TMP1941AF-307 nmi , am0?am1, plloff ale reset x1, x2 vrefh, vrefl input nmi plloff schmitt-trigger internal ale p-ch n-ch output enable vcc output input wdtout reset reset enable schmitt-trigger vcc x2 high-frequency oscillator enable oscillator circuit clock x1 vrefh vrefon vrefl p-ch ladder resistors
TMP1941AF 2003-03-27 TMP1941AF-308 21. notations, precautions and restrictions 21.1 notations and terms (1) i/o register fields are often referred to as . for the interest of brevity. for example, ta01run.ta0run means the ta0run bit in the ta01run register. (2) fc, fs, fsys, state fosc: clock supplied from the x1 and x2 pins fpll: clock generated by the on-chip pll fc: clock selected by the plloff pin fs: clock supplied from the xt1 and xt2 pins fgear: clock selected by the syscr1.gear[1:0] bits fsys: clock selected by the syscr1.sysck bit the fsys cycle is referred to as a state. in addition, the clock selected by the syscr1.fpsel bit and the prescalar clock source selected by the syscr0.prck[1:0] bits are referred to as fperiph and t0 respectively. 21.2 precautions and restrictions (1) processor revision identifier the process revision identifier (prid) register in the tx19 core of the TMP1941AF contains 0x0000_2c90. (2) am0? am1 pins the bw0 and bw1 pins must be connected to the dvcc pin to ensure that their signal levels do not fluctuate during chip operation. (3) oscillator warm-up counter if an external crystal is utilized, an interrupt signal programmed to bring the TMP1941AF out of stop mode triggers the on-chip warm-up counter. the system clock is not supplied to the on-chip logic until the warm-up counter expires. (4) programmable pullup resistors when port pins are configured as input ports, the integrated pullup resistors can be enabled and disabled under software control. the pullup resistors are not programmable when port pins are configured as output ports. the relevant port registers must be programmed by using store instructions. (5) external bus mastership the pin states while the bus is granted to an external device are described in chapter 7, i/o ports . (6) watchdog timer (wdt) upon reset, the wdt is enabled. if the watchdog timer function is not required, it must be disabled after reset. when relevant pins are configured as bus arbitration signals, the i/o peripherals including the wdt can operate during external bus mastership. (7) a/d converter (adc) the ladder resistor network between the vrefh and vrefl pins can be disconnected under software control. this helps to reduce power dissipation, for example, in stop mode. (8) undefined bits in i/o registers undefined i/o register bits are read as undefined states. therefore, software must be coded without relying on the states of any undefined bits.
TMP1941AF 2003-03-27 TMP1941AF-309 (9) usage restrictions overflow exception #1 problem: when an overflow exception is taken, the epc register might contain an incorrect return address, pointing to the instruction immediately following the one that caused an overflow. the restart location in the epc register should be the address of the arithmetic instruction that caused the exception, rather than the following instruction. in the above example, the processor writes address n to the epc register upon detection of an overflow. however, executing the next instruction generates an interrupt at the same time, causing the processor to rewrite the epc register with address n+4 in the next cycle. ? problem-causing situation: a) software uses the add, addi or sub instruction in the 32-bit isa. b) the add, addi or sub instruction causes an overflow. c) another exception is requested simultaneously with the overflow. this problem occurs when all of these conditions are true. workarounds: ? before returning from the overflow exception handler, determine whether the instruction pointed to by the epc register caused an overflow. ? make sure that two arithmetic instructions will not appear consecutively. ? disable interrupts prior to arithmetic instructions. you should always use one of these workarounds to avoid this problem. note: toshiba?s compiler uses no instructions that could cause an overflow. therefore, since condition c) above never becomes true, this problem does not occur. n arithmetic instruction (e.g., add) n + 4 next instruction f instruction pipeline epc register d e m w f d e m w n n + 4 detects an overflow and writes to epc. detects an interrupt. writes to epc.
TMP1941AF 2003-03-27 TMP1941AF-310 overflow exception #2 problem: if an overflow exception caused a jump to the exception handler and the first instruction in that exception handler caused another exception, the epc register should point to the address of the first instruction in the exception handler. however, the epc register might contain the address that caused the overflow exception. ? problem-causing situation: when, with the instruction pipeline full, an overflow exception was taken at the following sequence of instructions and then the first instruction in the overflow exception handler causes another exception add, addi or sub <= # instruction that causes an overflow jump or branch instruction <= # instruction with a delay slot delay slot note: toshiba?s compiler uses no instructions that could cause an overflow. therefore, this problem does not occur. workaround: don?t place a jump or branch instruction immediately following an instruction that could cause an overflow (add, addi or sub).
TMP1941AF 2003-03-27 TMP1941AF-311 when using multiple dmac channels (external bus interface unit) problem: switching between dma channels might cause an external chip select (cs) signal to be incorrectly driven active for one cycle. rd, wr, ale and other external bus control signals are not driven active. in cases where the dmac continually assumes bus mastership, switching from one channel to another causes channel 3 to be selected for one cycle as shown above. if the destination address for channel 3 references an external address space and a chip select is programmed for that address space, the external bus interface unit drives the chip select signal off chip even though no bus cycle has been started. ? problem-causing situation: a) the system hardware uses two or more dmac channels. b) the system hardware uses one or more external cs channels. c) while a dma request for one channel is being serviced, a next dma request has been received on another channel and left pending. or, two or more channels have received dma requests simultaneously. d) the destination address for channel 3 points to an external address space. (upon reset, the content of the destination address register is undefined. therefore, even when channel 3 is not used, its destination address register might be pointing to an external address space.) this problem occurs when all of these conditions are true. workaround: the system hardware must be designed not to operate with cs alone. dmac bus mastership e.g., dmac ch. 1 internal select signal e.g., dmac ch. 2 internal select signal cs from external bus i/f unit dmac ch. 3 internal select signal
TMP1941AF 2003-03-27 TMP1941AF-312 lwl and lwr instructions problem: the lwl or lwr instruction might provide incorrect results. ? problem-causing situation #1: a. the destination of a load instruction (lb, lbu, lh, lhu, lw, lwl or lwr) is identical to that of the lwl or lwr instruction. b. the instruction pipeline is full. (the load instruction and the lwl or lwr instruction will be executed consecutively.) c. the dmac is programmed for data cache snooping. once the load instruction is executed, the dmac initiates a dma transaction. after it has been serviced, the lwlor lwr instruction is executed. this problem occurs when all of these conditions are true. ? problem-causing situation #2: a. the destination of a load instruction (lb, lbu, lh, lhu, lw, lwl or lwr) is identical to that of the lwl or lwr instruction. b. the doze or halt bit in the config register is set to 1 immediately before the load instruction. c. the instruction pipeline is full. (the load instruction and the lwl or lwr instruction will be executed consecutively.) d. after the load instruction is executed, the processor is put in the stop, sleep or idle mode. e. after an interrupt signaling brings the processor out of the stop, sleep or idle mode, the lwl or lwr instruction is executed. note: this applies to the case in which an interrupt signaling does not generate an interrupt upon exit from stop, sleep or idle mode. in other words, either the iec bit in the status register is cleared (interrupts disabled), or if the iec bit is set, the priority level of the incoming interrupt signaling is lower than the mask level programmed in the cmask field in the status register. (exit from stop, sleep or idle mode can be accomplished even with such settings.) this problem occurs when all of these conditions are true. workarounds: to use the lwl or lwr instruction, 1) place a nop between a load instruction and the lwl or lwr instruction, or 2) disable the data cache snooping of the dmac before the lwl or lwr instruction is executed. also, don?t put the processor in stop, sleep or idle mode before the lwl or lwr instruction is executed.
TMP1941AF 2003-03-27 TMP1941AF-313 overflow exception when a dsu probe is used problem: it looks as if an overflow exception caused a jump to the reset and nonmaskable exception vector address (0xbfc0_0000). ? problem-causing situation: when an overflow exception occurs, with the processor connected to a dsu probe note: toshiba?s compiler uses no instructions that could cause an overflow. therefore, this problem does not occur. workaround: don?t place a jump or branch instruction immediately following an instruction that could cause an overflow (add, addi or sub). idle (doze) mode problem: a deadlock might occur when returning to normal operating mode from idle (doze) mode. ? problem-causing situation: when the dmac initiates a dma transaction with snooping enabled after the doze bit in the config register is set and before the cpu clock stops. workaround: if snooping is enabled, stop the dmac before putting the processor in idle (doze) mode.
TMP1941AF 2003-03-27 TMP1941AF-314

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