 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| commercial temperature range IDTCV152 programmable flexpc clock for p4 processor 1 may 2005 IDTCV152 commercial temperature range programmable flexpc clock for p4 processor xtal osc amp sm bus controller control logic cpu clk output buffers stop logic xtal_in xtal_out sdata sclk v tt_pwrgd #/pd fsa.b.c i ref cpu[4:0] ref[1:0] pll1 ssc n programmable src clk output buffer stop logic 48mhz output buffer i ref src[4:1] 48mhz pll2 ssc n programmable pll3 pci[3:0], pcif[2:0] the idt logo is a registered trademark of integrated device technology, inc. ? 2005 integrated device technology, inc. dsc 6537/5 features: ? one high precision pll for cpu, ssc, and n programming ? one high precision pll for src/pci, ssc, and n programming ? one high precision pll for 48mhz ? band-gap circuit for differential outputs ? support spread spectrum modulation, down spread 0.5% and others ? support smbus block read/write, index read/write ? selectable output strength for ref, 48mhz, pci ? allows for cpu frequency to change to a higher frequency for maximum system computing power ? available in ssop and tssop packages functional block diagram description: IDTCV152 is a 56 pin clock device, compliant with intel ck410b specification.the cpu output buffer is designed to support up to 400mhz processor. this chip has three plls inside for cpu, src/pci, and 48mhz io clocks. this device also implements band-gap referenced i ref to reduce the impact of v dd variation on differential outputs, which can provide more robust system performance. each cpu and src/pci has its own spread spectrum selection, which allows for isolated changes instead of affecting other clock groups. outputs: ? 5*0.7v current ?mode differential cpu clk pair ? 4*0.7v current ?mode differential src clk pair ? 7*pci, 3 free running, 33.3mhz ? 1*48mhz ? 2*ref key specification: ? cpu clk cycle to cycle jitter < 85ps ? src clk cycle to cycle jitter < 100ps ? pci clk cycle to cycle jitter < 250ps
commercial temperature range 2 IDTCV152 programmable flexpc clock for p4 processor pin configuration ssop/ tssop top view 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 fsc/test_sel ref0 v ss _ref xtal_in xtal_out v dd _ref v ss _cpu cpu0 cpu0# v dd _cpu cpu1 cpu1# v ssa v dda cpu4# cpu4 sda scl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 v dd _pci v ss _pci pci0 pci1 pci2 v ss _pci v dd _pci pcif1 v dd_ 48mhz 48mhz v ss_ 48mhz pcif2 src1# src1 v dd _src src2 src2# src3# v dd _ src src4 src4# src3 iref pci3 pcif0 nc v tt _p wrgd #/ p wrdwn v ss _src v dd _src ref1 fsb/test_mode fsa v dd _cpu cpu2 cpu2# cpu3 cpu3# v dd _cpu cpu and src spread spectrum magnitude control smc[2:0] % 000 - 0.25 001 - 0.5 010 - 0.75 011 - 1 100 0.125 101 0.25 110 0.375 111 0.5 frequency selection table fsc, b, a cpu src pci usb ref 101 100 100 33.3 48 14.318 001 133 100 33.3 48 14.318 011 166 100 33.3 48 14.318 010 200 100 33.3 48 14.318 000 266 100 33.3 48 14.318 100 333 100 33.3 48 14.318 110 400 100 33.3 48 14.318 111 reserve 100 33.3 48 14.318 symbol description min max unit v dda 3.3v core supply voltage 4.6 v v dd 3.3v logic input supply voltage gnd - 0.5 4.6 v t stg storage temperature ?65 +150 c t ambient ambient operating temperature 0 +70 c t case case temperature +115 c esd prot input esd protection 2000 v human body model absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. commercial temperature range IDTCV152 programmable flexpc clock for p4 processor 3 pin description pin name type pin # description xtal_in i 52 14.318 xtal input xtal_out o 51 14.318 xtal output ref[1:0] o 54, 55 14.318 mhz pci[3:0] o 3, 4, 5, 6 33.33mhz pci clk pcif[2:0] o 9, 10, 11 33.33mhz pci free running clk usb48 o 13 48mhz cpu[4:0], cpu#[4:0] o 31,32, 36, 37, 39, cpu differential clk 40, 42, 43, 45, 46 src[4:1], src#[4:1] o 18, 19, 21-24, 26, 27 src differential clk fsb/test_mode i 49 frequency select. when in test mode, 0 = clk hi-z, 1 = clk ref/n fsc/test_sel i 56 frequency select. select test mode if pulled to 2v and above when v tt _p wrgnd # assertion. fsa i 48 frequency select, sampled on v tt _p wrgnd # assertion iref i 33 reference current for differential outputs v tt _p wrgnd #/pd i 17 3.3v lvttl input, a level-sensitive strobe used to latch the fsa, fsb, fsc/test_sel inputs. after v tt _p wrgnd # assertion, becomes a real-time input for asserting power down (active high). sda i/o 30 smbus data scl i 29 smbus clock commercial temperature range 4 IDTCV152 programmable flexpc clock for p4 processor se signal strength selection str[1:0] strength 00 0.6x 01 0.8x 10 1 x 11 1.2x index block write protocol bit # of bits from description 1 1 master start 2-9 8 master d2h 10 1 slave ack (acknowledge) 11-18 8 master register offset byte (starting byte) 19 1 slave ack (acknowledge) 20-27 8 master byte count, n (0 is not valid) 28 1 slave ack (acknowledge) 29-36 8 master first data byte (offset data byte) 37 1 slave ack (acknowledge) 38-45 8 master 2nd data byte 46 1 slave ack (acknowledge) : master nth data byte slave acknowledge master stop index byte write setting bit[11:18] = starting address, bit[20:27] = 01h. resolution cpu (mhz) resolution n = 100 0.666667 150 133 0.666667 200 166 1.333333 125 200 1.333333 150 266 1.333333 200 333 2.666667 125 400 2.666667 150 index block read protocol master can stop reading any time by issuing the stop bit without waiting until nth byte (byte count bit30-37). bit # of bits from description 1 1 master start 2-9 8 master d2h 10 1 slave ack (acknowledge) 11-18 8 master register offset byte (starting byte) 19 1 slave ack (acknowledge) 20 1 master repeated start 21-28 8 master d3h 29 1 slave ack (acknowledge) 30-37 8 slave byte count, n (block read back of n bytes), power on is 8 38 1 master ack (acknowledge) 39-46 8 slave first data byte (offset data byte) 47 1 master ack (acknowledge) 48-55 8 slave 2nd data byte ack (acknowledge) : master ack (acknowledge) slave nth data byte not acknowledge master stop index byte read setting bit[11:18] = starting address. after reading back the first data byte, master issues stop bit. commercial temperature range IDTCV152 programmable flexpc clock for p4 processor 5 byte 2 bit output(s) affected description/function 0 1 type power on 0 usb_48 output enable disable enable rw 1 1 pcif0 output enable disable enable rw 1 2 pcif1 output enable disable enable rw 1 3 pcif2 output enable disable enable rw 1 4 pci0 output enable disable enable rw 1 5 pci1 output enable disable enable rw 1 6 pci2 output enable disable enable rw 1 7 pci3 output enable disable enable rw 1 byte 0 bit output(s) affected description/function 0 1 type power on 0 cpu[t/c]4 output enable tristate enable rw 1 1 srct1, srcc1 output enable tristate enable rw 1 2 srct2, srcc2 output enable tristate enable rw 1 3 srct3, srcc3 output enable tristate enable rw 1 4 srct4, srcc4 output enable tristate enable rw 1 5 reserved 1 6 reserved 1 7 reserved 1 byte 1 bit output(s) affected description/function 0 1 type power on 0 spread spectrum enable spread spectrum mode enable spr ead off spread on rw 0 1 cput0, cpuc0 output enable tristate enable rw 1 2 cput1, cpuc1 output enable tristate enable rw 1 3 reserved 1 4 cput2, cpuc2 output enable tristate enable rw 1 5 cput3, cpuc3 output enable tristate enable rw 1 6 ref0 output enable tristate enable rw 1 7 ref1 output enable tristate enable rw 1 byte 3 bit output(s) affected description / function 0 1 type power on 0 cpuclk4 allow controlled by free running stoppable rw 0 src_stop/cpu_stop# assertion 1 srct1, srcc1 rw 0 2 srct2, srcc2 rw 0 3 srct3, srcc3 allow controlled by free running, not stopped with rw 0 4 srct4, srcc4 pci_stop# assertion affected by pci_stop# pci_stop# rw 0 5 pcif0 rw 0 6 pcif1 rw 0 7 pcif2 rw 0 commercial temperature range 6 IDTCV152 programmable flexpc clock for p4 processor byte 4 bit output(s) affected description / function 0 1 type power on 0 cpuclk0 stop en rw 1 1 cpuclk1 stop en free-running control, free-running stoppable rw 1 2 cpuclk2 stop en default: not affected by cpu_stop rw 1 3 cpuclk3 stop en rw 1 4 cput0, cpuc0 cpu0 pwrdwn drive mode rw 0 5 cput1, cpuc1 cpu1 pwrdwn drive mode driven in power down tristate in rw 0 6 cput2, cpuc2 cpu2 pwrdwn drive mode power down rw 0 7 cput3, cpuc3 cpu3 pwrdwn drive mode rw 0 byte 5 bit output(s) affected description / function 0 1 type power on 0 cpuclk0 rw 0 1 cpuclk1 rw 0 2 cpuclk2 stop drive - drive mode in stop driven tri-state rw 0 3 cpuclk3 rw 0 4 cpuclk4 rw 0 5 src src pwrdwn drive mode driven in power down tristate in power down rw 0 6 src pci_stop drive mode driven in pci_stop tristate in power down rw 0 7 cpuclk4 cpu1 pwrdwn drive mode driven in power down tristate in power down rw 0 byte 6 bit output(s) affected description / function 0 1 type power on 0 fsa latched value on power up r fsa 1 fsb latched value on power up r fsb 2 fsc latched value on power up r fsc stop all pci/f & src 3 software pci_stop except pcif[2:0] and src no stop rw 1 function clocks set to free running 4 refstr1 ref dr ive strength , work with rw 1 byte12 bit2, see strength table 5 cpu cpu_stop control stop non-free running run rw 1 cpu clocks 6 test mode entry control normal operation test mode, controlled rw 0 by byte 6 bit 7 7 only valid when byte6 bit6 hi-z ref/n mode rw 0 is high commercial temperature range IDTCV152 programmable flexpc clock for p4 processor 7 byte 7 bit output(s) affected description / function 0 1 type power on 0 vendor id r 1 1 vendor id r 0 2 vendor id r 1 3 vendor id r 0 4 revision id r 0 5 revision id r 0 6 revision id r 0 7 revision id r 0 byte 8 (block read byte count) bit output(s) affected description / function 0 1 type power on 0 0 1 1 2 1 3 1 4 0 5 0 6 0 7 0 byte 9 bit output(s) affected description / function 0 1 type power on 0 src smc0 ssc control rw 1 1 src smc1 (see smc table) rw 0 2 src smc2 rw 0 3 reserved rw 0 4 cpu smc0 ssc control rw 1 5 cpu smc1 (see smc table) rw 0 6 cpu smc2 rw 0 7 reserved rw 0 byte 10 bit output(s) affected description / function 0 1 type power on 0 cpu_n0, lsb cpu clk = n* resolution rw 0 1 cpu_n1 rw 1 2 cpu_n2 rw 1 3 cpu_n3 rw 0 4 cpu_n4 rw 1 5 cpu_n5 rw 0 6 cpu_n6 rw 0 7 cpu_n7, msb rw 1 commercial temperature range 8 IDTCV152 programmable flexpc clock for p4 processor byte 13 bit output(s) affected description / function 0 1 type power on 0 test_scl on chip test mode enable normal sclk=1, clk outputs=1 rw 0 sclk=0, clk outputs=0 1 n programming enable disable enable rw 0 2 reserved rw 0 3 reserved rw 0 4 usb pll power down normal power down rw 0 5 src pll power down normal power down rw 0 6 cpu pll power down normal power down rw 0 7 reserved rw 0 byte 62 device id + rev bit[7:4] = 2h bit[3:0] = 0h byte 63 = device id bit[7:4] = 1h bit[3:0] = 5h byte 11 bit output(s) affected description / function 0 1 type power on 0 src_n0, lsb cpu clk = n* resolution rw 0 1 src_n1 rw 1 2 src_n2 rw 1 3 src_n3 rw 0 4 src_n4 rw 1 5 src_n5 rw 0 6 src_n6 rw 0 7 src_n7, msb rw 1 byte 12 bit output(s) affected description / function 0 1 type power on 0 48mhzstr0 rw 1 1 48mhstr1 usb48mhz strength selection rw 1 2 refstr0 work with byte 6 bit 4 refstr1 rw 1 ( see strength table) 3 reserved rw 0 4 pcistrc0 rw 0 5 pcistrc1 pci strength selection rw 1 6 pcifstr0 rw 0 7 pcifstr1 pcif strength selection rw 1 commercial temperature range IDTCV152 programmable flexpc clock for p4 processor 9 symbol parameter test conditions min. typ. max. unit v ih input high voltage 3.3v 5% 2 ? v dd + 0.3 v v il input low voltage 3.3v 5% v ss - 0.3 ? 0.8 v v ih _fs low voltage, high threshold for fsa.b.c test_mode 0.7 ? v dd + 0.3 v v il _fs low voltage, low threshold for fsa.b.c test_mode v ss - 0.3 ? 0.35 v i il input leakagecurrent 0< v in < v dd , no internal pull-up or pull-down ?5 ? +5 ma i dd3.3op operating supply current full active, c l = full load ? ? 400 ma i dd3.3pd powerdown current all differential pairs driven ? ? 70 ma all differential pairs tri-stated ? ? 12 f i input frequency (1) v dd = 3.3v ? 14.31818 ? mhz l pin pin inductance (2) ?? 7 nh c in logic inputs ? ? 5 c out input capacitance (2) output pin capacitance ? ? 6 pf c inx xtal_in and xtal_out pins ? ? 5 t stab clock stabilization (2,3) from v dd power-up or de-assertion of pd to first clock ? ? 1.8 ms modulation frequency (2) triangular modulation 30 ? 33 khz t drive _pd (2) cpu output enable after pd de-assertion ? ? 300 us t fall _pd (2) fall time of pd ? ? 5 ns t rise _pd (2) rise time of pd ? ? 5 ns electrical characteristics - input / supply / common output parameters following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5% notes: 1. input frequency should be measured at the ref output pin and tuned to ideal 14.31818mhz to meet ppm frequency accuracy on pll outputs. 2. this parameter is guaranteed by design, but not 100% production tested. 3. see timing diagrams for timing requirements. commercial temperature range 10 IDTCV152 programmable flexpc clock for p4 processor symbol parameter test conditions min. typ. max. unit z o current source output impedance (2) v o = v x 3000 ? ? v oh3 output high voltage i oh = -1ma 2.4 ? ? v v ol3 output low voltage i ol = 1ma ? ? 0.4 v v high voltage high (2) statistical measurement on single-ended signal using 660 ? 1150 mv v low voltage low (2) oscilloscope math function ?300 ? 150 v ovs max voltage (2) measurement on single-ended signal using absolute value ? ? 1150 mv v uds min voltage (2) ?300 ? ? v cross(abs) crossing voltage (abs) (2) 250 ? 550 mv d - v cross crossing voltage (var) (2) variation of crossing over all edges ? ? 140 mv ppm static error (2,3) see t period min. - max. values ? ? 0 ppm 400mhz nominal / -0.5% spread 2.4993 ? 2.5133 333.33mhz nominal / -0.5% spread 2.9991 ? 3.016 266.66mhz nominal / -0.5% spread 3.7489 ? 3.77 t period average period (3) 200mhz nominal / -0.5% spread 4.9985 ? 5.0266 ns 166.66mhz nominal / -0.5% spread 5.9982 ? 6.032 133.33mhz nominal / -0.5% spread 7.4978 ? 7.54 100mhz nominal / -0.5% spread 9.997 ? 10.0533 96mhz nominal 10.4135 ? 10.4198 400mhz nominal / -0.5% spread 2.4143 ? ? 333.33mhz nominal / -0.5% spread 2.9141 ? ? 266.66mhz nominal / -0.5% spread 3.6639 ? ? 200mhz nominal / -0.5% spread 4.9135 ? ? t absmin absolute min period (2,3) 166.66mhz nominal / -0.5% spread 5.9132 ? ? ns 133.33mhz nominal / -0.5% spread 7.4128 ? ? 100mhz nominal / -0.5% spread 9.912 ? ? 96mhz nominal 10.1635 ? ? t r rise time (2) v ol = 0.175v, v oh = 0.525v 175 ? 700 ps t f fall time (2) v ol = 0.175v, v oh = 0.525v 175 ? 700 ps d-t r rise time variation (2) ? ? 125 ps d-t f fall time variation (2) ? ? 125 ps d t3 duty cycle (2) measurement from differential waveform 45 ? 55 % electrical characteristics - cpu and src 0.7 current mode differential pair (1) following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 2pf notes: 1. src clock outputs run only at 100mhz. 2. this parameter is guaranteed by design, but not 100% production tested. 3. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz. commercial temperature range IDTCV152 programmable flexpc clock for p4 processor 11 symbol parameter test conditions min. typ. max. unit ppm static error (1,2) see tperiod min. - max. values ? ? 0 ppm t period clock period (2) 33.33mhz output nominal 29.991 ? 30.009 ns 33.33mhz output spread 29.991 ? 30.1598 v oh output high voltage i oh = -1ma 2.4 ? ? v v ol output low voltage i ol = 1ma ? ? 0.55 v i oh output high current v oh at min. = 1v -33 ? ? ma v oh at max. = 3.135v ? ? -33 i ol output low current v ol at min. = 1.95v 30 ? ? ma v ol at max. = 0.4v ? ? 38 edge rate (1) rising edge rate 1 ? 4 v/ns edge rate (1) falling edge rate 1 ? 4 v/ns t r1 rise time (1) v ol = 0.8v, v oh = 2v 0.3 ? 1.2 ns t f1 fall time (1) v ol = 0.8v, v oh = 2v 0.3 ? 1.2 ns d t1 duty cycle (1) v t = 1.5v 45 ? 55 % t sk1 skew (1) v t = 1.5v ? ? 500 ps t jcyc - cyc jitter, cycle to cycle (1) v t = 1.5v ? ? 500 ps electrical characteristics - pciclk / pciclk_f following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 30pf notes: 1. this parameter is guaranteed by design, but not 100% production tested. 2. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz. electrical characteristics - cpu and src 0.7 current mode differential pair, continued (1) following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 2pf symbol parameter test conditions min. typ. max. unit t sk 3 skew, cpu (2) v t = 50% ? ? 100 ps skew, src (2) ? ? 250 t jcyc - cyc jitter, cycle to cycle, cpu (2) measurement from differential waveform ? ? 85 ps jitter, cycle to cycle, src (2) ? ? 125 notes: 1. src clock outputs run only at 100mhz. 2. this parameter is guaranteed by design, but not 100% production tested. commercial temperature range 12 IDTCV152 programmable flexpc clock for p4 processor symbol parameter test conditions min. typ. max. unit ppm static error (1,2) see tperiod min. - max. values ? ? 0 ppm t period clock period (2) 48mhz output nominal 20.8257 ? 20.834 ns v oh output high voltage i oh = -1ma 2.4 ? ? v v ol output low voltage i ol = 1ma ? ? 0.55 v i oh output high current v oh at min. = 1v -29 ? ? ma v oh at max. = 3.135v ? ? -23 i ol output low current v ol at min. = 1.95v 29 ? ? ma v ol at max. = 0.4v ? ? 27 edge rate (1) rising edge rate 1 ? 2 v/ns edge rate (1) falling edge rate 1 ? 2 v/ns t r1 rise time (1) v ol = 0.8v, v oh = 2v 0.5 ? 1.2 ns t f1 fall time (1) v ol = 0.8v, v oh = 2v 0.5 ? 1.2 ns d t1 duty cycle (1) v t = 1.5v 45 ? 55 % t jcyc - cyc jitter, cycle to cycle ? ? 350 ps electrical characteristics, 48mhz, usb following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 20pf notes: 1. this parameter is guaranteed by design, but not 100% production tested. 2. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz. symbol parameter test conditions min. typ. max. unit ppm long accuracy (1) see tperiod min. - max. values ? ? 0 ppm t period clock period 14.318mhz output nominal 69.827 ? 69.855 ns v oh output high voltage (1) i oh = -1ma 2.4 ? ? v v ol output low voltage (1) i ol = 1ma ? ? 0.4 v i oh output high current v oh at min. = 1v -33 ? ? ma v oh at max. = 3.135v ? ? -33 i ol output low current v ol at min. = 1.95v 30 ? ? ma v ol at max. = 0.4v ? ? 38 edge rate (1) rising edge rate 1 ? 4 v/ns edge rate (1) falling edge rate 1 ? 4 v/ns t r 1 rise time (1) v ol = 0.8v, v oh = 2v 0.3 ? 1.2 ns t f 1 fall time (1) v ol = 0.8v, v oh = 2v 0.3 ? 1.2 ns d t1 duty cycle (1) v t = 1.5v 45 ? 55 % t jcyc - cyc jitter, cycle to cycle (1) v t = 1.5v ? ? 1000 ps electrical characteristics - ref-14.318mhz following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 20pf note: 1. this parameter is guaranteed by design, but not 100% production tested. commercial temperature range IDTCV152 programmable flexpc clock for p4 processor 13 pd assertion pd cpu 133mhz cpu# 133mhz src 100mhz src# 100mhz usb 48mhz pci 33mhz ref 14.31818 pci stop functionality if pcif (2:0) and src clocks are set to be free-running through smbus programming, they will ignore the pci_stop register bit. pci_stop cpu cpu# src src# pcif/pci usb dot96 dot96# ref (byte 6 bit 3) 1 normal normal normal normal 33mhz 48mhz normal normal 14.318mhz 0 normal normal i ref * 6 or float low low 48mhz normal normal 14.318mhz pd, power down pd is an asynchronous active high input used to shut off all clocks cleanly prior to clock power. when pd is asserted high all clocks will be driven low before turning off the vco. in pd de-assertion all clocks will start without glitches. pd cpu cpu# src src# pcif/pci usb ref 0 normal normal normal normal 33mhz 48mhz 14.318mhz 1i ref * 2 or float float i ref * 2 or float float low low low commercial temperature range 14 IDTCV152 programmable flexpc clock for p4 processor pd de-assertion the time from the de-assertion of pd or until power supply ramps to get stable clocks will be less than 1.8ms. if the drive mod e control bit for pd tristate is programmed to ?1? the stopped differential pair must first be driven high to a minimum of 200mv in less than 300s of pd deasse rtion. pd cpu 133mhz cpu# 133mhz src 100mhz src# 100mhz usb 48mhz pci 33mhz ref 14.31818 t stable <1.8ms t drive_pd <300 s, <200mv commercial temperature range IDTCV152 programmable flexpc clock for p4 processor 15 ordering information xxx xx package pa pag pv pvg thin small shrink outline package tssop - green small shrink outline package ssop - green programmable flexpc clock for p4 processor 152 device type x grade blank idtcv commercial temperature range (0c to +70c) corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 logichelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com |
Price & Availability of IDTCV152
 |
||||||||||||||||
|
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |
