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ssc050-01 two-wire serial backplane controller data sheet revision 4.0 november 10, 2004 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maxim-ic.com. maxim integrated products
-i contents ssc050-01 data sheet revision 4.0 november 10, 2004 revision history chapter 1 introduction............. ................. ................ ................. ................ ........ 1-1 feature summary ..............................................................................................................1 -2 typical applications .......................................................................................................... .1-3 fc-al drive enclosure configuration .......................................................................1-3 general purpose i/o configuration ...........................................................................1-3 chapter 2 functional description.. ........................................................... ........ 2-1 two-wire serial interface ...................................................................................................2- 1 control registers ............................................................................................................. ..2-2 i/o logic ............................................................................................................................2-3 clock generator ............................................................................................................... .2-3 power-on reset ................................................................................................................ 2-3 chapter 3 pin description ... ...................................................................... ........ 3-1 functional signal grouping ...............................................................................................3-1 pinout diagram ..................................................................................................................3-2 pin description list ............................................................................................................3-3 chapter 4 control registers ........ ................ ............................................. ........ 4-1 register map .....................................................................................................................4-1 address map .....................................................................................................................4-4 control register definition ................................................................................................4-6 00h: general purpose i/o port 0 data (gpd0) .........................................................4-6 01h: general purpose i/o port 1 data (gpd1) .........................................................4-7 02h: general purpose i/o port 2 data (gpd2) .........................................................4-7 03h: general purpose i/o port 3 data (gpd3) .........................................................4-8 04h: general purpose i/o port 4 data (gpd4) .........................................................4-8 10h: i/o port 0 data direction (ddp0) ......................................................................4-9 11h: i/o port 1 data direction (ddp1) ......................................................................4-9 12h: i/o port 2 data direction (ddp2) ....................................................................4-10 13h: i/o port 3 data direction (ddp3) ....................................................................4-10 14h: i/o port 4 data direction (ddp4) ....................................................................4-11 20h: port bypass control 0 (pbc0) .......................................................................4-12 21h: port bypass control 1 (pbc1) .......................................................................4-13 22h: port bypass control 2 (pbc2) .......................................................................4-14 23h: port bypass control 3 (pbc3) .......................................................................4-15 24h: port bypass control 4 (pbc4) .......................................................................4-16 25h: port bypass control 5 (pbc5) .......................................................................4-17 contents
-ii contents ssc050-01 data sheet revision 4.0 november 10, 2004 26h: port bypass control 6 (pbc6) .......................................................................4-18 27h: port bypass control 7 (pbc7) .......................................................................4-19 30h: fan speed control 0 register (fsc0) ............................................................4-20 31h: fan speed count overflow 0 (fsco0, r/w) .................................................4-22 32h: fan speed current count 0 (fscc0) ............................................................4-23 34h: fan speed control 1 (fsc1) ..........................................................................4-24 35h: fan speed count overflow 1 (fsco1) ..........................................................4-26 36h: fan speed current count 1 (fscc1) ............................................................4-27 38h: fan speed control 2 (fsc2) ..........................................................................4-28 39h: fan speed count overflow 2 (fsco2) ..........................................................4-30 3ah: fan speed current count 2 (fscc2) ...........................................................4-31 3ch: fan speed control 3 (fsc3) .........................................................................4-32 3dh: fan speed count overflow 3 (fsco3) .........................................................4-34 3eh: fan speed current count 3 (fscc3) ...........................................................4-35 80h-87h: bit control port 0 registers (bcp00-bcp07) .........................................4-36 90h-97h: bit control port 1 registers (bcp10-bcp17) .........................................4-38 98h-9bh: pulse width modulation control registers (pwmc0-pwmc3) .............4-40 a0h-a7h: bit control port 2 registers (bcp20-bcp27) ........................................4-42 b0h-b7h: bit control port 3 registers (bcp30-bcp37) ........................................4-44 c0h-c7h: bit control port 4 registers (bcp40-bcp47) ........................................4-46 f8h: backplane controller interrupt status (bcis) ................................................4-48 fch: backplane controller test (bct) ...................................................................4-49 fdh: backplane controller option (bco) ..............................................................4-50 ffh: backplane controller version (ver) ..............................................................4-51 chapter 5 electrical char acteristics............... .......................................... ........ 5-1 maximum ratings ..............................................................................................................5 -1 dc characteristics ............................................................................................................ 5-1 ac characteristics ............................................................................................................ .5-5 external clock timing ...............................................................................................5-5 two-wire serial interface operation ..........................................................................5-7 oscillator requirements ............................................................................................5-7 external reset circuit ...............................................................................................5-9 optional external tach filter ...................................................................................5-10 chapter 6 mechanical drawing ..... ............... ............................................. ........ 6-1 chapter 7 ordering information.... ............... ............................................. ........ 7-1
ssc050-01 data sheet revision 4.0 november 10, 2004 r evision h istory revision date section change 1.01 11/4/03 all initial revision 1.0 11/10/04 updated 4.0 11/10/04 data manual migrated to data sheet status
1-1 introduction ssc050-01 data sheet revision 4.0 november 10, 2004 chapter 1 introduction the ssc050-01 is a i/o-intensive peripheral device whic h is intended to be a po rtion of a cost effective fc-al, scsi, sas or sata enclosure management solution. the device contains an address programmable two wire serial interface, a block of co ntrol and status registers, i/o port control logic, specialized port bypass control logic and a clock generation block. along with an external crystal, the device can be configured to support up to 40 bits of general purpose i/o or 16 bits of general purpose i/ o, 16 bits of port bypass control (8 pairs supporting 8 drives), 4 fan speed monitoring inputs and 4 pulse width modulated outputs. the ssc050-01 is capable of supporting various comb inations of individual pbc/cru/sdu functions as well as integrated solutions. the control register portion of the device allows the user to individually program each i/o pin as an input, output or open source/drain output. additional control features include selectable flash rates for direct led drive, input edge detection for interrupt generation, fan speed monitoring and pulse width modulated outputs. the addressing capability of the ssc050-01 includes three pins, which are used fo r device addressing, as well as one pin, which can be used to select two device type identifiers. sixteen devices can be us ed in a single two-wire serial interface system.
1-2 introduction ssc050-01 feature summary data sheet revision 4.0 november 10, 2004 f eature s ummary figure 1-1. chip block diagram interrupt priority and control i/o ports p1.0 - p1.7 power on reset osci osco sda scl a2-a0 asel int# p2.0 - p2.7 p0.0 - p0.7 p3.0 - p3.7 p4.0 - p4.7 port bypass control fan speed sensors and pwm control i/o control and led flashing two-wire serial slave interface clock generator and dividers
1-3 introduction ssc050-01 typical applications data sheet revision 4.0 november 10, 2004 t ypical a pplications fc-al drive enclosure configuration general purpose i/o configuration figure 1-2. single loo p, single controller with four drives drive bay 1 drive bay 2 drive bay 3 drive bay 4 vsc7147 maxim backplane controller (ssc050-01) local i/o (x26) maxim embedded controller (vsc120) temperature sensor (lm75) flash (512k x 16) two-wire serial interface pbc_en1 pbc_en2 pbc_en3 pbc_en4 power supplies leds (x16) pbc_en fans (x4) cu or optics x24c16 eeprom tach in pwm out
1-4 introduction ssc050-01 typical applications data sheet revision 4.0 november 10, 2004 figure 1-3. four backplane controllers, 160 bidirectional i/o lines maxim backplane controller (ssc050-01) microcontroller with two wire serial i/f two wire serial i/f maxim backplane controller (ssc050-01) interrupt(optional) maxim backplane controller (scc050-01) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) maxim backplane controller (scc050-01) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8)
2-1 functional description ssc050-01 two-wire serial interface data sheet revision 4.0 november 10, 2004 chapter 2 f unctional d escription the ssc050-01 is composed of five major functional blocks; a slave mode two-wire serial interface, a block of control registers, general purpose i/o and specialized port bypass control logic, a clock generator and power-on reset control logic. the ssc050-01 fully supports a generic two-wire serial interface and is compatible with other industry standa rd devices which also support this interface at both 100k and 400k bits per second. t wo - wire s erial i nterface the device supports a single slave mode two-wire serial interface. al l inter-chip communication to a microcontroller takes place over this bus. the interf ace supports a three-bit address bus, which allows the user to select one of eight poss ible addresses. the address bus is compared to bits three through one of the slave address byte, which is the first byte tr ansmitted to the device afte r a start condition. the ssc050-01 supports two pin selectable four-bit device type identifier values, 1000b and 1100b. the address bits and the device identifi er allow the use of up to 16 devices on a single two-wire serial interface. the serial interface contro l logic includes the slave state m achine, address comparison logic, serial to parallel and parallel to se rial conversion, register read/write control and filtering for the clock and data line. a read or write transaction is determined by the least significant bit (r/w) of the first byte transferred. write accesses require a three-byte tran sfer. the first byte is the slave address with the r/w bit low, the second byte contains the register address and the third byte is the wr ite data. read accesses require a four-byte transfer since data transf er direction can not change after re ceipt of the slave address byte. the first byte is the slave address with the r/w bit low, the second byte contains the register address, the third byte is a repeated slave address with the r/w bi t high and the fourth byte is the read data. if the transaction is a write, the data will be latched into the appropriate register during the acknowledge of the third byte. all transactions to or from the devi ce complete during the acknowledge of the third byte allowing the user to immediately initiate another transfer to the device. sequential read or write transactions are allowed and are exte nsions of the above protocol with additional data bytes added to the end of the transaction. all sequential transactions will cause the internal a ddress to increment by one regardless of the register address.
2-2 functional description ssc050-01 control registers data sheet revision 4.0 november 10, 2004 c ontrol r egisters the ssc050-01 contains five groups of control registers. each group supports a specific function within the device as follows; the first group is the port data registers, the second is the data direction registers, the third contains special bit cont rol features, the fourth supports the port bypass control function and the fifth supports fan speed monitoring. currently the device contains 78 registers to support all required functions. in normal i/o opera tion, each eight-bit gr oup of i/o pins are controlled by a pa ir of registers, port data and data direction. the use of these pairs of registers allows each i/o line to be individually configured as an input with internal pull-up, output or open drain output with internal pull-up. the bit control features are enabled through a separate register for each i/o pin. the bit control registers allow the user to independently configure each i/o pin to enable one of the special control features as well as control port data and data di rection (which are shadowed copies of the standard control bits found in the port data and data direction registers). each i/o pin which has been configured as an input can also be configured to a ssert the open drain interrupt pin when a rising edge, a falling edge or either edge is detected on the i/o pin. an interrupt status regist er provides the user with a binary indication of which i/o pin is the source of the current interrupt. each i/o pin which is configured as an output can automa tically generate one of seven selectable flashing rates, which are normally driven in an open drain mode. by providing all i/o control capability in a single register, the user can control the operation of the i/o on a pin-by-pin basis. the port bypass registers control the operation of a selected group of i/o line s which can be dedicated to support various combinations of individual pbc/ cru/sdu functions as well as integrated solutions. enabling port bypass control causes the normal or bit control register settings to be overridden and any further changes to the affected re gisters will have no effect. each port bypass control register will automatically configure the i/o lines to support a force bypass output and a signal detected input. the fan speed registers control th e operation of four programmable inputs which can be used to monitor signals from fans equipped with tachometer outputs. enabling fan speed control causes the normal or bit control register settings to be overrid den and any further changes to the affected registers will have no effect. each group of three registers provides the capability to enable the function, establish a user defined rpm overflow value which indicates a failure and determine the current rpm value of the fan. the digital filters on the fan speed inputs can optionally be enabled to increase the normal 100 to 200 nanosecond filter to 400 to 500 nanoseconds. the pulse width modulation control registers enable internal logic to provide duty cycles of 0% to 100% in 3% increments at default frequencies of 26khz, 52khz and 104khz. optionally, the pwm outputs can be programmed for three additional freque ncy ranges of 5.2khz, 10.4khz and 20.8khz or 1.04khz, 2.08khz and 4.16khz or 208hz, 416hz and 833hz. these outputs can vary the speed of up to four fans through the use of external drivers and power mosfets or pulse width to voltage converters. they can also be used to support ot her pulse width modulated requirements within the system.
2-3 functional description ssc050-01 i/o logic data sheet revision 4.0 november 10, 2004 i/o l ogic each general purpose i/o pin is controlled by a set of registers in the control register block. the i/o supports a high current drive output buffer, which can be configured as a totem pole or open drain driver. the input section of the i/o supports ttl signaling an d includes an internal weak pull-up device. this allows unused i/o pins to be left unconnected without high current drain issues. the port bypass control i/o pins which are shared with port 3 and port 4 are generated using th e same buffer logic as the other ports. when enabled in port bypass control mode, internal logic overrides the existing configuration, with each i/o pin dedicated to the specific port bypass fu nction. all i/o lines default as inputs with the weak internal pul l-up enabled. c lock g enerator clock generation for the device is composed of an in ternal oscillator, divider circuits and a distribution network. the primary clock frequenc y of 10.0mhz is used for filtering incoming serial interface signals and interrupt sources as well as clocking the slave state machine. divided cloc ks provide the source for led flash rate generators. logic within the ss c050-01 synchronizes the divided clocks between devices attached to the same two-wire serial bus with no more than 200 nanoseconds of skew. multiple devices can then be used to drive different led' s at the same frequency, providing a synchronized visible indication. the oscillator pr ovides a stable clock source for the device and requires the use of an off chip crystal and related passive components or external clock source. there are no programmable options related to clock generation except the selection of the seven fixed led flashing rates. the ssc050-01 can operate at frequencies other than 10.0mhz and continue to meet both the standard mode (100khz) and fast mode ( 400khz) serial interface timings. freque ncies from 8.0mhz to 12.5mhz are allowable as long as they meet the ac timing requirements listed in section 5.3.1 of this manual. operation of the led flashing circuits, fan speed counters and pulse width modulated outputs will be affected by a change in base operating frequency. th e user must scale the expected operating parameters by the change in frequency from a nominal 10.0mhz. as and example, operating the ssc050-01 at 8.0mhz will cause the led flashing circuits, fan speed counters and pulse width modulated outputs to operate 25% slower than normal. p ower -o n r eset power-on reset is accomplished by the use of logic in ternal to the device. no external components are required. after power-on, the serial interface state mach ine will always return an idle state waiting for a start condition to appear on the scl and sda pi ns. a proper power-on reset sequence will clear the serial interface state machine, the clock generators, the control registers, the i/o control logic and the port bypass control logic. the divided clocks used fo r led flash rate generation will also be in a known state. an external reset circuit utilizing the test1 and asel pins can be developed as an option to the internal power-on reset logic. regardless of the eff ectiveness of either power-on reset sequence, it is highly recommended that the control registers and i/o control logic be cleared through the soft reset register bit. this can be accomplished by wr iting a 80h to the bct re gister (fch) followed immediately by a stop condition. this bit is self resetting and will not require further attention.
3-1 pin description ssc050-01 functional signal grouping data sheet revision 4.0 november 10, 2004 chapter 3 pin description the ssc050-01 is packaged in a 64-pin pqfp. all pins have been placed to opt imize their connection to external components. power and ground distribution has also been optimized for core and high current i/ o connections. all serial interface pins as well as the interrupt output are 5 volt tolerant. vdd and vdd2 should be connected to a 3.3 volt supply with no more than 10% tolerances. f unctional s ignal g rouping figure 3-1. functional signal grouping p1.7-p1.0 p0.7-p0.0 p3.7-p3.0 p2.7-p2.0 int# a2-a0 scl asel sda test0 test1 test2 i/o ports clock serial interface p4.7-p4.0 functional test interrupt osci osco
3-2 pin description ssc050-01 pinout diagram data sheet revision 4.0 november 10, 2004 p inout d iagram figure 3-2. pinout diagram 51 33 vdd 52 32 1v d d 64 20 19 ssc050-01 p0.0 vdd2 test2 test1 test0 vss vss2 a0 a2 a1 osco p4.6 vdd vss sda p4.7 int# osci scl asel p4.4 p4.5 p4.3 p4.1 p4.2 p4.0 p3.6 p3.7 p3.5 p3.3 p3.4 vss2 p0.2 p0.1 p0.3 p0.5 p0.4 p0.6 p0.7 p1.0 p1.2 p1.1 p1.3 vdd2 p1.4 vss p1.5 p1.7 p1.6 p2.0 p2.2 p2.1 p2.3 p2.5 p2.4 p2.6 p3.0 p2.7 p3.1 vdd p3.2 vss 10 50 30 40 60
3-3 pin description ssc050-01 pin description list data sheet revision 4.0 november 10, 2004 p in d escription l ist the following pin descriptions are grouped by function. table 3-1: serial interface pin names pin no. type pin description a2-a0 9-7 inputs address select bus this pin group provides the value, which will be compared to bits 3 through 1 of the serial slave address. these pins should be strapped to vdd or vss to provide the appropriate binary value. asel 12 input device type address select this pin provides the ability to select between two-device type address values in the serial slave address. when tied to vss, the device type address is 1000b and when tied to vdd, the device type address is 1100b. scl 13 input two-wire serial interface clock this pin is used by the device to latch the data present on the sda pin. this pin in conjunction with the sda pin also deter- mines start and stop conditions on the serial bus. sda 14 bidirectional two-wire serial interface data this pin is used to transfer all serial data into and out of the device. this pin in conjunction wi th the scl pin also determines start and stop conditions on the serial bus. table 3-2: clock pin names pin no. type pin description osci 11 input oscillator input this pin is connected to one si de of an external 10.0mhz crystal to produce the clock required for serial signal filtering, state machine clocking and flash rate generation. an alternate exter- nal 3.3 volt 10.0mhz clock sour ce can be connected to this pin. osco 10 output oscillator output this pin is connected to the ot her side of an external 10.0mhz crystal. when an alternate external clock source is used, this pin should be left unconnected. table 3-3: interrupt pin names pin no. type pin description int# 15 open-drain output interrupt this open-drain output can be used to signal the microcontroller that an event has occurred on an i/o pin which is configured as an input or that a special function event has occurred. this pin can be wire ored with other open drain outputs to provide a sin- gle interrupt input source.
3-4 pin description ssc050-01 pin description list data sheet revision 4.0 november 10, 2004 table 3-4: i/o ports pin names pin no. type pin description p0.7-p0.0 57-64 bidirectional i/o port 0 port 0 is a dedicated eight-bit bi directional i/o port. the user can select between an input, totem pole output or open-drain output. additional capability to detect input edge changes and select various output flashing rates is also available. p1.7-p1.0 46-49, 53-56 bidirectional i/o port 1 port 1 is a dedicated eight-bit bi directional i/o port. the user can select between an input, totem pole output or open-drain output. additional capability to detect input edge changes and select various output flashing rates is also available. p2.7-p2.0 (tach inputs and pwm out- puts) 38-45 bidirectional i/o port 2 port 2 is an eight-bit bidirectional i/o port. the user can select between an input, totem pole output or open-drain output. addi- tional capability to detect input edge changes and select various output flashing rates is also avai lable. through control register setup, p2.7-p2.4 can be dedicated to monitoring fans equipped with tachometer outputs. through control register setup, p2.3- p2.0 can be dedicated to contro lling fan speed utilizing pulse width modulated outputs. p3.7-p3.0 (bypass i/o) 27-31, 35-37 bidirectional i/o port 3 port 3 is a shared eight bit bi directional i/o port which can be used as a general purpose i/o port or as port bypass control. the user can select between an input, totem pole output or open-drain output. additional capability to detect input edge changes and select various output flashing rates is also availa- ble. through control register setup, four two-bit portions of this port can be dedicated to the control of a combination of pbc/ cru/sdu functions. any combination of port bypass control functions can be enabled with the remaining i/o pins used for general purpose functions. p4.7-p4.0 (bypass i/o) 16, 17, 21-26 bidirectional i/o port 4 port 4 is a shared eight bit bi directional i/o port which can be used as a general purpose i/o port or as port bypass control. the user can select between an input, totem pole output or open-drain output. additional capability to detect input edge changes and select various output flashing rates is also availa- ble. through control register setup, four two-bit portions of this port can be dedicated to the control of a combination of pbc/ cru/sdu functions. any combination of port bypass control functions can be enabled with the remaining i/o pins used for general purpose functions. table 3-5: test pin names pin no. type pin description test2- test0 6-4 input functional test these inputs allow the device to be placed in specific test modes for device level testing. these inputs should be con- nected to vss for normal operation.
3-5 pin description ssc050-01 pin description list data sheet revision 4.0 november 10, 2004 table 3-6: supply pin names pin no. type pin description vdd 1, 19, 34, 51 power i/o power these pins are the power sources for the i/o drivers of all non- analog output and bidirectional pins. vss 3, 18, 33, 50 ground i/o ground these pins are the ground connecti ons for the i/o drivers of all non-analog output and bidirectional pins. vdd2 20, 52 power digital core power these pins are the power sources for the digital core logic and receivers of all non-analog input and bidirectional pins. vss2 2, 32 ground digital core ground these pins are the ground connecti ons for the digital core logic and receivers of all non-analog i nput and bidirectional pins.
4-1 control registers ssc050-01 register map data sheet revision 4.0 november 10, 2004 chapter 4 c ontrol r egisters this section contains descriptions for the device-spec ific control registers. a ll register locations are fixed within the device and are mapped for easy access as well as future enhancements. the control register section is sepa rated into three sub-sections; a regi ster map, an address map and the bit level description of all registers. the register ma p lists all registers by operating address. the address map shows the relative layout of all control regist ers. all registers can be accessed at any time and no register function will interfere with the operation of the serial in terface. however, changing register bits will have an immediate effect on the respective i/o lines. r egister m ap table 4-1: register map data memory address read/write label description 00h r/w gpd0 general purpose i/o port 0 data register 01h r/w gpd1 general purpose i/o port 1 data register 02h r/w gpd2 general purpose i/o port 2 data register 03h r/w gpd3 general purpose i/o port 3 data register 04h r/w gpd4 general purpose i/o port 4 data register 10h r/w ddp0 i/o port 0 data direction register 11h r/w ddp1 i/o port 1 data direction register 12h r/w ddp2 i/o port 2 data direction register 13h r/w ddp3 i/o port 3 data direction register 14h r/w ddp4 i/o port 4 data direction register 20h r/w pbc0 port bypass control 0 register 21h r/w pbc1 port bypass control 1 register 22h r/w pbc2 port bypass control 2 register 23h r/w pbc3 port bypass control 3 register
4-2 control registers ssc050-01 register map data sheet revision 4.0 november 10, 2004 24h r/w pbc4 port bypass control 4 register 25h r/w pbc5 port bypass control 5 register 26h r/w pbc6 port bypass control 6 register 27h r/w pbc7 port bypass control 7 register 30h r/w fsc0 fan speed control 0 register 31h r/w fsco0 fan speed count overflow 0 register 32h r fscc0 fan speed current count 0 register 34h r/w fsc1 fan speed control 1 register 35h r/w fsco1 fan speed count overflow 1 register 36h r fscc1 fan speed current count 1 register 38h r/w fsc2 fan speed control 2 register 39h r/w fsco2 fan speed count overflow 2 register 3ah r fscc2 fan speed current count 2 register 3ch r/w fsc3 fan speed control 3 register 3dh r/w fsco3 fan speed count overflow 3 register 3eh r fscc3 fan speed current count 3 register 80h r/w bcp00 bit control port 0 - bit 0 register 81h r/w bcp01 bit control port 0 - bit 1 register 82h r/w bcp02 bit control port 0 - bit 2 register 83h r/w bcp03 bit control port 0 - bit 3 register 84h r/w bcp04 bit control port 0 - bit 4 register 85h r/w bcp05 bit control port 0 - bit 5 register 86h r/w bcp06 bit control port 0 - bit 6 register 87h r/w bcp07 bit control port 0 - bit 7 register 90h r/w bcp10 bit control port 1 - bit 0 register 91h r/w bcp11 bit control port 1 - bit 1 register 92h r/w bcp12 bit control port 1 - bit 2 register 93h r/w bcp13 bit control port 1 - bit 3 register 94h r/w bcp14 bit control port 1 - bit 4 register 95h r/w bcp15 bit control port 1 - bit 5 register 96h r/w bcp16 bit control port 1 - bit 6 register 97h r/w bcp17 bit control port 1 - bit 7 register table 4-1: register map (continued) data memory address read/write label description
4-3 control registers ssc050-01 register map data sheet revision 4.0 november 10, 2004 98h r/w pwmc0 pulse width modulation control 0 register 99h r/w pwmc1 pulse width modulation control 1 register 9ah r/w pwmc2 pulse width modulation control 2 register 9bh r/w pwmc3 pulse width modulation control 3 register a0h r/w bcp20 bit control port 2 - bit 0 register a1h r/w bcp21 bit control port 2 - bit 1 register a2h r/w bcp22 bit control port 2 - bit 2 register a3h r/w bcp23 bit control port 2 - bit 3 register a4h r/w bcp24 bit control port 2 - bit 4 register a5h r/w bcp25 bit control port 2 - bit 5 register a6h r/w bcp26 bit control port 2 - bit 6 register a7h r/w bcp27 bit control port 2 - bit 7 register b0h r/w bcp30 bit control port 3 - bit 0 register b1h r/w bcp31 bit control port 3 - bit 1 register b2h r/w bcp32 bit control port 3 - bit 2 register b3h r/w bcp33 bit control port 3 - bit 3 register b4h r/w bcp34 bit control port 3 - bit 4 register b5h r/w bcp35 bit control port 3 - bit 5 register b6h r/w bcp36 bit control port 3 - bit 6 register b7h r/w bcp37 bit control port 3 - bit 7 register c0h r/w bcp40 bit control port 4 - bit 0 register c1h r/w bcp41 bit control port 4 - bit 1 register c2h r/w bcp42 bit control port 4 - bit 2 register c3h r/w bcp43 bit control port 4 - bit 3 register c4h r/w bcp44 bit control port 4 - bit 4 register c5h r/w bcp45 bit control port 4 - bit 5 register c6h r/w bcp46 bit control port 4 - bit 6 register c7h r/w bcp47 bit control port 4 - bit 7 register f8h r/w bcis backplane controller interrupt status register fch r/w bct backplane controller test register fdh r/w bco backplane controller option register ffh r ver backplane controller version register table 4-1: register map (continued) data memory address read/write label description
4-4 control registers ssc050-01 address map data sheet revision 4.0 november 10, 2004 a ddress m ap table 4-2: address map 11b 10b 01b 00b address gpd3 gpd2 gpd1 gpd0 00h reserved reserved reserved gpd4 04h reserved reserved reserved reserved 08h reserved reserved reserved reserved 0ch ddp3ddp2ddp1ddp0 10h reserved reserved reserved ddp4 14h reserved reserved reserved reserved 18h reserved reserved reserved reserved 1ch pbc3 pbc2 pbc1 pbc0 20h pbc7 pbc6 pbc5 pbc4 24h reserved reserved reserved reserved 28h reserved reserved reserved reserved 2ch reserved fscc0 fsco0 fsc0 30h reserved fscc1 fsco1 fsc1 34h reserved fscc2 fsco2 fsc2 38h reserved fscc3 fsco3 fsc3 3ch reserved reserved reserved reserved 40h-7ch bcp03 bcp02 bcp01 bcp00 80h bcp07 bcp06 bcp05 bcp04 84h reserved reserved reserved reserved 88h reserved reserved reserved reserved 8ch bcp13 bcp12 bcp11 bcp10 90h bcp17 bcp16 bcp15 bcp14 94h pwmc3 pwmc2 pwmc1 pwmc0 98h reserved reserved reserved reserved 9ch bcp23 bcp22 bcp21 bcp20 a0h bcp27 bcp26 bcp25 bcp24 a4h reserved reserved reserved reserved a8h reserved reserved reserved reserved ach bcp33 bcp32 bcp31 bcp30 b0h
4-5 control registers ssc050-01 address map data sheet revision 4.0 november 10, 2004 bcp37 bcp36 bcp35 bcp34 b4h reserved reserved reserved reserved b8h reserved reserved reserved reserved bch bcp43 bcp42 bcp41 bcp40 c0h bcp47 bcp46 bcp45 bcp44 c4h reserved reserved reserved reserved c8h-f4h reserved reserved reserved bcis f8h ver reserved bco bct fch table 4-2: address map (continued) 11b 10b 01b 00b address
4-6 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 c ontrol r egister d efinition the register definition provides a bit-level descriptio n of all register bits including power-on and default values. the terms "set" and "assert" refer to bits which are programmed to a binary one. the terms "reset", "de-assert" and "clear" refe r to bits which are programmed to a binary zero. reserved bits are represented by "res" and will always return an unknown value and should be masked. any bits which are reserved should never be set to a binary one. these bits may be defined in future versions of the device. 00h: general purpose i/o port 0 data (gpd0) register name: gpd0 address: 00h reset value: xxxx_xxxxb description general purpose i/o port 0 data 76543210 general purpose data bit(s) bit label access description 7:0 gpd0.7-0 r/w when the i/o pin has been enabled as an out put, writing these bits determines the data value which will be present on the co rresponding i/o pin. if the i/o pin has been enabled as an input, reading t hese register bits will represent the current voltage applied to the pin. at no time will the bits directly represent the value latched into the data register. if a pin is enabled as an in put and there is no signal applied, weak internal pull-up resistors will hold the pin at a binary one. after a reset or power-on, the register bits will be set to a binary one, but the value returned from a register read will be the level applied to the pi n since by default each pin is an input. figure 4-1. i/o port block diagram filter d dq qi / o p o r t ck ck gpd read data dd write data dd read data gpd write data i/o port block diagram
4-7 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 01h: general purpose i/o port 1 data (gpd1) 02h: general purpose i/o port 2 data (gpd2) register name: gpd1 address: 01h reset value: xxxx_xxxxb description general purpose i/o port 1 data 76543210 general purpose data bit(s) bit label access description 7:0 gpd0.7-0 r/w when the i/o pin has been enabled as an output, writing these bits determines the data value which will be present on the co rresponding i/o pin. if the i/o pin has been enabled as an input, reading these register bits will represent the current voltage applied to the pin. at no time will the bits directly represent the value latched into the data register. if a pin is enabled as an input and there is no signal applied, weak internal pull-up resistors will hold the pin at a binary one. after a reset or power-on, the register bits will be set to a binary one, but the value returned from a register read will be the level applied to the pi n since by default each pin is an input. register name: gpd2 address: 02h reset value: xxxx_xxxxb description general purpose i/o port 2 data 76543210 general purpose data bit(s) bit label access description 7:0 gpd0.7-0 r/w when the i/o pin has been enabled as an output, writing these bits determines the data value which will be present on the co rresponding i/o pin. if the i/o pin has been enabled as an input, reading these register bits will represent the current voltage applied to the pin. at no time will the bits directly represent the value latched into the data register. if a pin is enabled as an input and there is no signal applied, weak internal pull-up resistors will hold the pin at a binary one. after a reset or power-on, the register bits will be set to a binary one, but the value returned from a register read will be the level applied to the pi n since by default each pin is an input.
4-8 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 03h: general purpose i/o port 3 data (gpd3) 04h: general purpose i/o port 4 data (gpd4) register name: gpd3 address: 03h reset value: xxxx_xxxxb description general purpose i/o port 3 data 76543210 general purpose data bit(s) bit label access description 7:0 gpd0.7-0 r/w when the i/o pin has been enabled as an out put, writing these bits determines the data value which will be present on the co rresponding i/o pin. if the i/o pin has been enabled as an input, reading t hese register bits will represent the current voltage applied to the pin. at no time will the bits directly represent the value latched into the data register. if a pin is enabled as an in put and there is no signal applied, weak internal pull-up resistors will hold the pin at a binary one. after a reset or power-on, the register bits will be set to a binary one, but the value returned from a register read will be the level applied to the pi n since by default each pin is an input. register name: gpd4 address: 04h reset value: xxxx_xxxxb description general purpose i/o port 4 data 76543210 general purpose data bit(s) bit label access description 7:0 gpd0.7-0 r/w when the i/o pin has been enabled as an out put, writing these bits determines the data value which will be present on the co rresponding i/o pin. if the i/o pin has been enabled as an input, reading t hese register bits will represent the current voltage applied to the pin. at no time will the bits directly represent the value latched into the data register. if a pin is enabled as an in put and there is no signal applied, weak internal pull-up resistors will hold the pin at a binary one. after a reset or power-on, the register bits will be set to a binary one, but the value returned from a register read will be the level applied to the pi n since by default each pin is an input.
4-9 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 10h: i/o port 0 data direction (ddp0) 11h: i/o port 1 data direction (ddp1) register name: ddp0 address: 10h reset value: 1111_1111b description i/o port 0 data direction 76543210 data direction bit(s) bit label access description 7:0 ddp0.7-0 r/w data direction these bits determine the direction of the data flow through the i/o pin. to enable the respective i/o pin as an in put, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individ- ually configured as a true bi directional function. addi tionally, an open-drain or open- source function can be developed by resett ing or setting the appropriate data bit and using the data direction bit as the programmed data value. after a reset or power-on, these bits will be set to a binary one, enabling the i/o as an input with weak pull-up. register name: ddp1 address: 11h reset value: 1111_1111b description i/o port 1 data direction 76543210 data direction bit(s) bit label access description 7:0 ddp0.7-0 r/w data direction these bits determine the direction of the data flow through the i/o pin. to enable the respective i/o pin as an in put, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individ- ually configured as a true bi directional function. addi tionally, an open-drain or open- source function can be developed by resett ing or setting the appropriate data bit and using the data direction bit as the programmed data value. after a reset or power-on, these bits will be set to a binary one, enabling the i/o as an input with weak pull-up.
4-10 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 12h: i/o port 2 data direction (ddp2) 13h: i/o port 3 data direction (ddp3) register name: ddp2 address: 12h reset value: 1111_1111b description i/o port 2 data direction 76543210 data direction bit(s) bit label access description 7:0 ddp0.7-0 r/w data direction these bits determine the direction of the data flow through the i/o pin. to enable the respective i/o pin as an i nput, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individ- ually configured as a true bidirectional function. ad ditionally, an open-drain or open- source function can be developed by resetting or setting the appropriate data bit and using the data direction bit as the programmed data value. after a reset or power-on, these bits will be set to a binary one, enabling the i/o as an input with weak pull-up. register name: ddp3 address: 13h reset value: 1111_1111b description i/o port 3 data direction 76543210 data direction bit(s) bit label access description 7:0 ddp0.7-0 r/w data direction these bits determine the direction of the data flow through the i/o pin. to enable the respective i/o pin as an i nput, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individ- ually configured as a true bidirectional function. ad ditionally, an open-drain or open- source function can be developed by resetting or setting the appropriate data bit and using the data direction bit as the programmed data value. after a reset or power-on, these bits will be set to a binary one, enabling the i/o as an input with weak pull-up.
4-11 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 14h: i/o port 4 data direction (ddp4) register name: ddp4 address: 14h reset value: 1111_1111b description i/o port 4 data direction 76543210 data direction bit(s) bit label access description 7:0 ddp0.7-0 r/w data direction these bits determine the direction of the data flow through the i/o pin. to enable the respective i/o pin as an in put, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individ- ually configured as a true bi directional function. addi tionally, an open-drain or open- source function can be developed by resett ing or setting the appropriate data bit and using the data direction bit as the programmed data value. after a reset or power-on, these bits will be set to a binary one, enabling the i/o as an input with weak pull-up.
4-12 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 20h: port bypass control 0 (pbc0) register name: pbc0 address: 20h reset value: 00xx_xx1xb description port bypass control 0 76543210 port bypass control ena- ble signal detected interrupt ena- ble force bypass signal detected bit(s) bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p3.1 and p3.0 are au tomatically configured to provide a force bypass output pin and a signal detected input pin. any other configuration which may have previously been enabled through ot her control registers will be overrid- den. when this bit is reset, the remaining bi ts in this register have no effect on the operation of p3.1 and p3.0. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input will be enabled to generate an interrupt if a transi- tion occurs on the pin. if a transition o ccurs, the int# pin will assert and a binary value equal to the address of this register will appear in the bcis register. when this bit is reset, transitions on the signal detect ed input will not generate an interrupt con- dition. 1 fb r/w force bypass this bit controls the p3.1 i/o pin which is configured as a totem pole output by set- ting the pbcen bit. when this bit is set, the force bypass input of a pbc/cru/sdu function is not enabled and the port bypass circ uit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass circuit is in bypass m ode. this register bit is au tomatically cleared when the synchronized and filtered p3.0 input is low which results in a maximum latency of 400 nanoseconds from detection of the lo ss of a high speed signal to the deasser- tion of the p3.1 output. note: since all i/o pins on the devi ce power-on as inputs with weak internal pull-ups, it is possible to define the default state of the force bypass function through the use of an external pull-down resistor. the default state of the i/o can be determined by reading this register since the read valu e of the register bits are always avail- able through an input synchronizer and filter. once the default state is deter- mined, a write to the fb bit of this re gister with the default values as well as setting the pbcen bit ensures that the port bypass control functions have been enabled correctly. additional writes to th is register can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit become s a read-only indication of the p3.0 i/o pin which has been connected to the signal detected output of a pbc/cru/sdu function. if this bit is set, a high speed signal has been detected by the signal detect unit. if this bit is reset, a high speed signal has not been detected by the signal detect unit.
4-13 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 21h: port bypass control 1 (pbc1) register name: pbc1 address: 21h reset value: 00xx_xx1xb description port bypass control 1 76543210 port bypass control ena- ble signal detected interrupt ena- ble force bypass signal detected bit(s) bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p3.3 and p3.2 are aut omatically configured to provide a force bypass output pin and a signal detected input pin. configurations for these i/o pins which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, t he remaining bits in this register have no effect on the operation of p3.3 and p3.2. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input will be enabled to generate an interrupt if a transi- tion occurs on the pin. if a transition occu rs, the int# pin will assert and a binary value equal to the address of this register will appear in the bcis register. when this bit is reset, transitions on the signal dete cted input will not generate an interrupt con- dition. 1 fb r/w force bypass this bit controls the p3.3 i/o pin, which is configured as a totem pole output by set- ting the pbcen bit. when this bit is set, the force bypass input of a pbc/cru/sdu function is not enabled and the port bypass circ uit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass circuit is in bypass mode. this register bit is automatically cleared when the synchronized and filtered p3.2 input is low which results in a maximum latency of 400 nanosceonds from detection of the loss of a high speed signal to the de-asser- tion of the p3.1 output. note: since all i/o pins on the device power-on as inputs with weak internal pull-ups, it is possible to define the default state of the force bypass func tion through the use of an external pull-down resistor. the default state of the i/o can be determined by reading this register since the read va lue of the register bits are always avail- able through an input sync hronizer and filter. once the default state is deter- mined, a write to the fb bit of this re gister with the default values as well as setting the pbcen bit ensures that the port bypass control functions have been enabled correctly. additional writes to this register can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit becomes a read-only indication of the p3.2 i/o pin which has been connected to the signal detected output of a pbc/cru/sdu function. if this bit is set, a high speed signal has been detected by the signal detect unit. if this bit is reset, a high speed signal has not been detected by the signal detect unit.
4-14 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 22h: port bypass control 2 (pbc2) register name: pbc2 address: 22h reset value: 00xx_xx1xb description port bypass control 2 76543210 port bypass control ena- ble signal detected interrupt ena- ble force bypass signal detected bit(s) bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p3.5 and p3.4 are au tomatically configured to provide a force bypass output pin and a signal detected input pin. configurations for these i/o pins which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, t he remaining bits in this register have no effect on the operation of p3.5 and p3.4. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input will be enabled to generate an interrupt if a transi- tion occurs on the pin. if a transition o ccurs, the int# pin will assert and a binary value equal to the address of this register will appear in the bcis register. when this bit is reset, transitions on the signal detect ed input will not generate an interrupt con- dition. 1 fb r/w force bypass this bit controls the p3.5 i/o pin, which is configured as a totem pole output by set- ting the pbcen bit. when this bit is set, the force bypass input of a pbc/cru/sdu function is not enabled and the port bypass circ uit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass circuit is in bypass m ode. this register bit is au tomatically cleared when the synchronized and filtered p3.4 input is low which results in a maximum latency of 400 nanosceonds from detection of the loss of a high speed signal to the de-asser- tion of the p3.1 output. note: since all i/o pins on the devi ce power-on as inputs with weak internal pull-ups, it is possible to define the default state of the force bypass function through the use of an external pull-down resistor. the default state of the i/o can be determined by reading this register since the read valu e of the register bits are always avail- able through an input synchronizer and filter. once the default state is deter- mined, a write to the fb bit of this re gister with the default values as well as setting the pbcen bit ensures that the port bypass control functions have been enabled correctly. additional writes to th is register can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit become s a read-only indication of the p3.4 i/o pin which has been connected to the signal detected output of a pbc/cru/sdu function. if this bit is set, a high speed signal has been detected by the signal detect unit. if this bit is reset, a high speed signal has not been detected by the signal detect unit.
4-15 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 23h: port bypass control 3 (pbc3) register name: pbc3 address: 23h reset value: 00xx_xx1xb description port bypass control 3 76543210 port bypass control ena- ble signal detected interrupt ena- ble force bypass signal detected bit(s) bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p3.7 and p3.6 are aut omatically configured to provide a force bypass output pin and a signal detected input pin. configurations for these i/o pins which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, t he remaining bits in this register have no effect on the operation of p3.7 and p3.6. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input will be enabled to generate an interrupt if a transi- tion occurs on the pin. if a transition occu rs, the int# pin will assert and a binary value equal to the address of this register will appear in the bcis register. when this bit is reset, transitions on the signal dete cted input will not generate an interrupt con- dition. 1 fb r/w force bypass this bit controls the p3.7 i/o pin, which is configured as a totem pole output by set- ting the pbcen bit. when this bit is set, the force bypass input of a pbc/cru/sdu function is not enabled and the port bypass circ uit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass circuit is in bypass mode. this register bit is automatically cleared when the synchronized and filtered p3.6 input is low which results in a maximum latency of 400 nanosceonds from detection of the loss of a high speed signal to the de-asser- tion of the p3.1 output. note: since all i/o pins on the device power-on as inputs with weak internal pull-ups, it is possible to define the default state of the force bypass func tion through the use of an external pull-down resistor. the default state of the i/o can be determined by reading this register since the read va lue of the register bits are always avail- able through an input sync hronizer and filter. once the default state is deter- mined, a write to the fb bit of this re gister with the default values as well as setting the pbcen bit ensures that the port bypass control functions have been enabled correctly. additional writes to this register can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit becomes a read-only indication of the p3.4 i/o pin which has been connected to the signal detected output of a pbc/cru/sdu function. if this bit is set, a high speed signal has been detected by the signal detect unit. if this bit is reset, a high speed signal has not been detected by the signal detect unit.
4-16 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 24h: port bypass control 4 (pbc4) register name: pbc4 address: 24h reset value: 00xx_xx1xb description port bypass control 4 76543210 port bypass control ena- ble signal detected interrupt ena- ble force bypass signal detected bit(s) bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p4.1 and p4.0 are au tomatically configured to provide a force bypass output pin and a signal detected input pin. configurations for these i/o pins which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, t he remaining bits in this register have no effect on the operation of p4.1 and p4.0. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input will be enabled to generate an interrupt if a transi- tion occurs on the pin. if a transition o ccurs, the int# pin will assert and a binary value equal to the address of this register will appear in the bcis register. when this bit is reset, transitions on the signal detect ed input will not generate an interrupt con- dition. 1 fb r/w force bypass this bit controls the p4.1 i/o pin, which is configured as a totem pole output by set- ting the pbcen bit. when this bit is set, the force bypass input of a pbc/cru/sdu function is not enabled and the port bypass circ uit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass circuit is in bypass m ode. this register bit is au tomatically cleared when the synchronized and filtered p4.0 input is low which results in a maximum latency of 400 nanosceonds from detection of the loss of a high speed signal to the de-asser- tion of the p3.1 output. note: since all i/o pins on the devi ce power-on as inputs with weak internal pull-ups, it is possible to define the default state of the force bypass function through the use of an external pull-down resistor. the default state of the i/o can be determined by reading this register since the read valu e of the register bits are always avail- able through an input synchronizer and filter. once the default state is deter- mined, a write to the fb bit of this re gister with the default values as well as setting the pbcen bit ensures that the port bypass control functions have been enabled correctly. additional writes to th is register can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit become s a read-only indication of the p3.4 i/o pin which has been connected to the signal detected output of a pbc/cru/sdu function. if this bit is set, a high speed signal has been detected by the signal detect unit. if this bit is reset, a high speed signal has not been detected by the signal detect unit.
4-17 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 25h: port bypass control 5 (pbc5) register name: pbc5 address: 25h reset value: 00xx_xx1xb description port bypass control 5 76543210 port bypass control ena- ble signal detected interrupt ena- ble force bypass signal detected bit(s) bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p4.3 and p4.2 are aut omatically configured to provide a force bypass output pin and a signal detected input pin. configurations for these i/o pins which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, t he remaining bits in this register have no effect on the operation of p4.3 and p4.2. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input will be enabled to generate an interrupt if a transi- tion occurs on the pin. if a transition occu rs, the int# pin will assert and a binary value equal to the address of this register will appear in the bcis register. when this bit is reset, transitions on the signal dete cted input will not generate an interrupt con- dition. 1 fb r/w force bypass this bit controls the p4.3 i/o pin, which is configured as a totem pole output by set- ting the pbcen bit. when this bit is set, the force bypass input of a pbc/cru/sdu function is not enabled and the port bypass circ uit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass circuit is in bypass mode. this register bit is automatically cleared when the synchronized and filtered p4.2 input is low which results in a maximum latency of 400 nanosceonds from detection of the loss of a high speed signal to the de-asser- tion of the p3.1 output. note: since all i/o pins on the device power-on as inputs with weak internal pull-ups, it is possible to define the default state of the force bypass func tion through the use of an external pull-down resistor. the default state of the i/o can be determined by reading this register since the read va lue of the register bits are always avail- able through an input sync hronizer and filter. once the default state is deter- mined, a write to the fb bit of this re gister with the default values as well as setting the pbcen bit ensures that the port bypass control functions have been enabled correctly. additional writes to this register can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit becomes a read-only indication of the p3.4 i/o pin which has been connected to the signal detected output of a pbc/cru/sdu function. if this bit is set, a high speed signal has been detected by the signal detect unit. if this bit is reset, a high speed signal has not been detected by the signal detect unit.
4-18 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 26h: port bypass control 6 (pbc6) register name: pbc6 address: 26h reset value: 00xx_xx1xb description port bypass control 6 76543210 port bypass control ena- ble signal detected interrupt ena- ble force bypass signal detected bit(s) bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p4.5 and p4.4 are au tomatically configured to provide a force bypass output pin and a signal detected input pin. configurations for these i/o pins which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, t he remaining bits in this register have no effect on the operation of p4.5 and p4.4. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input will be enabled to generate an interrupt if a transi- tion occurs on the pin. if a transition o ccurs, the int# pin will assert and a binary value equal to the address of this register will appear in the bcis register. when this bit is reset, transitions on the signal detect ed input will not generate an interrupt con- dition. 1 fb r/w force bypass this bit controls the p4.5 i/o pin, which is configured as a totem pole output by set- ting the pbcen bit. when this bit is set, the force bypass input of a pbc/cru/sdu function is not enabled and the port bypass circ uit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass circuit is in bypass m ode. this register bit is au tomatically cleared when the synchronized and filtered p4.4 input is low which results in a maximum latency of 400 nanosceonds from detection of the loss of a high speed signal to the de-asser- tion of the p3.1 output. note: since all i/o pins on the devi ce power-on as inputs with weak internal pull-ups, it is possible to define the default state of the force bypass function through the use of an external pull-down resistor. the default state of the i/o can be determined by reading this register since the read valu e of the register bits are always avail- able through an input synchronizer and filter. once the default state is deter- mined, a write to the fb bit of this re gister with the default values as well as setting the pbcen bit ensures that the port bypass control functions have been enabled correctly. additional writes to th is register can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit become s a read-only indication of the p3.4 i/o pin which has been connected to the signal detected output of a pbc/cru/sdu function. if this bit is set, a high speed signal has been detected by the signal detect unit. if this bit is reset, a high speed signal has not been detected by the signal detect unit.
4-19 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 27h: port bypass control 7 (pbc7) register name: pbc7 address: 27h reset value: 00xx_xx1xb description port bypass control 7 76543210 port bypass control ena- ble signal detected interrupt ena- ble force bypass signal detected bit(s) bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p4.7 and p4.6 are aut omatically configured to provide a force bypass output pin and a signal detected input pin. configurations for these i/o pins which may have previously been enabled through other control registers will be overridden except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, t he remaining bits in this register have no effect on the operation of p4.7 and p4.6. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input will be enabled to generate an interrupt if a transi- tion occurs on the pin. if a transition occu rs, the int# pin will assert and a binary value equal to the address of this register will appear in the bcis register. when this bit is reset, transitions on the signal dete cted input will not generate an interrupt con- dition. 1 fb r/w force bypass this bit controls the p4.7 i/o pin, which is configured as a totem pole output by set- ting the pbcen bit. when this bit is set, the force bypass input of a pbc/cru/sdu function is not enabled and the port bypass circ uit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass circuit is in bypass mode. this register bit is automatically cleared when the synchronized and filtered p4.6 input is low which results in a maximum latency of 400 nanosceonds from detection of the loss of a high speed signal to the de-asser- tion of the p3.1 output. note: since all i/o pins on the device power-on as inputs with weak internal pull-ups, it is possible to define the default state of the force bypass func tion through the use of an external pull-down resistor. the default state of the i/o can be determined by reading this register since the read va lue of the register bits are always avail- able through an input sync hronizer and filter. once the default state is deter- mined, a write to the fb bit of this re gister with the default values as well as setting the pbcen bit ensures that the port bypass control functions have been enabled correctly. additional writes to this register can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit becomes a read-only indication of the p3.4 i/o pin which has been connected to the signal detected output of a pbc/cru/sdu function. if this bit is set, a high speed signal has been detected by the signal detect unit. if this bit is reset, a high speed signal has not been detected by the signal detect unit.
4-20 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 30h: fan speed control 0 register (fsc0) register name: fsc0 address: 30h reset value: 00xx_xx00b description fan speed control 0. this register affects pin p2.4. 76543210 fan speed control ena- ble fan speed interrupt ena- ble fan divisor 1 fan divisor 0 bit(s) bit label access description 7 fscen r/w fan speed control enable when this bit is set, p2.4 is automaticall y configured to provide a fan speed monitor- ing input. configurations for this i/o pi n which may have previously been enabled through other control registers will be overridden except for the bypass select func- tion (bits 6 and 5 of the appropriate bit control registers). if the appropriate bypass bits have been set, the odd numbered fan speed input pins (p2.1, p2.3, p2.5, or p2.7) will be configured as outputs. when this bit is reset, the remaining bits in this register have no effect on the operation of p2.4. when enabled as a fan speed monitoring input, pulses from the fan tachometer out- put gate an internal 20khz clock into an ei ght-bit counter. a divisor value stored in bits one and zero of this register allow t he user to select one of four nominal rpm values based on fan tachometer outputs which pulse twice per revolution. the fscc0 register provides the user with an accurate binary fan speed count value which can be used to determine the current rpm value of the fan. incoming pulses are filtered and conditioned to accommodate the slow rise and fall times typical of fan tachometer outputs. the maximum input signal is limited to a range of vss to vdd. if this input is supplied from a fan tachometer output which exceeds this range, external components will be required to lim it the signal to an acceptable range. 6 fsien r/w fan speed interrupt enable when this bit is set, the p2.4 input will be enabled to generate an interrupt if the eight bit counter value is greater than or equal to the count overflow value loaded into the fsco0 register. if the condition oc curs, the int# pin will assert and a binary value equal to the address of this register will appear in the bcis register. when this bit is reset, the fan speed monitoring logi c will not generate an interrupt condition. 1:0 fd1-0 r/w fan divisor these two bits determine the divisor value used to determine the correct range of rpm values supplied to the eight-bit fan speed counter. table 4-3 describes the available divisor values. the decimal count value can be calc ulated using the following equation: decimal-count-value = (1,200,000)/(rpm x divisor) any nominal rpm value can be used in the above equation along with the appropri- ate divisor as long as the maximum non-fa ilure count value does not exceed the lim- its of an eight-bit counter. typical applications may consider 60% to 70% of normal rpm a fan failure which would result in a decimal count value of 250(fah) and 214(d6h) respectively at the above stated rpm values.
4-21 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 table 4-3: fan divisor fd1 fd0 divisor nominal rpm decimal count value 0 0 1 8000 150(96h) 0 1 2 4000 150(96h) 1 0 4 2000 150(96h) 1 1 8 1000 150(96h)
4-22 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 31h: fan speed count overflow 0 (fsco0, r/w) register name: fsco0 address: 31h reset value: 0000_0000b description fan speed count overflow 0. this register affects pin p2.4 76543210 fan speed count overflow bit(s) bit label access description 7 fsco7-0 r/w fan speed count overflow these eight bits are compared to the eight-bit fan speed counter. if the counter exceeds this value, an interrupt will be generated. this register should be loaded prior to setting the fan speed control enable (fscen) bit in the fsc0 register to avoid generating unintentional interrupts. the overflow count value can be deter- mined using the following equation where ff % is equal to the percentage of nominal rpm which constitutes a fan failure: decimal-overflow-count-value = (1 ,200,000)/(rpm x divisor x ff%) based on the above equation, a divisor of 8 and a detected fan failure at 70% of nominal rpm, the fan speed monitoring l ogic is capable of supporting a low end nominal rpm of 850. high end rpm values are basically unlimited but counter reso- lution will be diminished above 8000 rpm.
4-23 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 32h: fan speed curre nt count 0 (fscc0) register name: fscc0 address: 32h reset value: 0000_0000b description fan speed current count 0. this register affects pin p p2.4. 76543210 fan speed current count bit(s) bit label access description 7 fsco7-0 r these eight bits, when enabled by setting the fscen bit in the fsc0 register pro- vide the user with an accurate binary fan speed count value which can be used to determine the current rpm value of the fan. a minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. the following equation can be used to determine the current rpm value of the fan: rpm = (1,200,000)/(decimal-count-value x divisor) when the result of a read of this register is 00h, an accurate fan speed count value has not been generated indicating that the fan has not completed a minimum of one revolution. when the result of a read of this register is ffh, the fan is rotating very slowly or there are no tachometer pulse s present. when operating in a polled mode with the fsien bit reset in the fsc0 regist er, this register will automatically update with an accurate fan speed count once per revolution of the fan. when operating in an interrupt mode with the fsien bit set in th e fsc0 register, this register will auto- matically update with an accurate fan speed count once per revolution of the fan until an interrupt is generated. once the interrupt is generated, the value will remain sta- ble until the interrupt is cleared. when the inte rrupt is cleared, this register will also be cleared indicating that a valid rpm value is in the process of being generated.
4-24 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 34h: fan speed control 1 (fsc1) register name: fsc1 address: 34h reset value: 00xx_xx00b description fan speed control 1. this register affects pin p2.5 76543210 fan speed control ena- ble fan speed interrupt ena- ble fan divisor 1 fan divisor 0 bit(s) bit label access description 7 fscen r/w fan speed control enable when this bit is set, p2.5 is automaticall y configured to provide a fan speed monitor- ing input. configurations for this i/o pin which may have previously been enabled through other control registers will be ov erridden except for the bypass select func- tion (bits 6 and 5 of the appropriate bit control registers). if the appropriate bypass bits have been set, the odd numbered fan speed input pins (p1.1, p1.3, p1.5, p1.7, p2.1, p2.3, p2.5 or p2.7) will be configured as outputs . when this bit is reset, the remaining bits in this register have no effect on the operation of p2.5. when enabled as a fan speed monitoring input, pulses from the fan tachometer out- put gate an internal 20khz clock into an ei ght-bit counter. a divisor value stored in bits one and zero of this register allow t he user to select one of four nominal rpm values based on fan tachometer outputs which pulse twice per revolution. the fscc1 register provides the user with an accurate binary fan speed count value which can be used to determine the current rpm value of the fan. incoming pulses are filtered and conditioned to accommodate the slow rise and fall times typical of fan tachometer outputs. the maximum input signal is limited to a range of vss to vdd. if this input is supplied from a fan tachometer output which exceeds this range, external components will be required to lim it the signal to an acceptable range. 6 fsien r/w fan speed interrupt enable when this bit is set, the p2.5 input will be enabled to generate an interrupt if the eight bit counter value is greater than or equal to the count overflow value loaded into the fsco1 register. if the condition oc curs, the int# pin will assert and a binary value equal to the address of this register will appear in the bcis register. when this bit is reset, the fan speed monitoring logi c will not generate an interrupt condition. 1:0 fd1-0 r/w fan divisor these two bits determine the divisor value used to determine the correct range of rpm values supplied to the eight-bit fan speed counter. table 4-4 describes the available divisor values: the decimal count value can be calc ulated using the following equation: decimal-count-value = (1,200,000)/(rpm x divisor) any nominal rpm value can be used in the above equation along with the appropri- ate divisor as long as the maximum non-fa ilure count value does not exceed the lim- its of an eight-bit counter. typical applications may consider 60% to 70% of normal rpm a fan failure which would result in a decimal count value of 250 (fah) and 214 (d6h) respectively at the above stated rpm values.
4-25 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 table 4-4: fan divisor fd1 fd0 divisor nominal rpm decimal count value 0 0 1 8000 150(96h) 0 1 2 4000 150(96h) 1 0 4 2000 150(96h) 1 1 8 1000 150(96h)
4-26 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 35h: fan speed count overflow 1 (fsco1) register name: fsco1 address: 35h reset value: 0000_0000b description fan speed count overflow 1. this register affects pin p2.5 76543210 fan speed count overflow bit(s) bit label access description 7 fsco7-0 r/w fan speed count overflow these eight bits are compared to the eight-bit fan speed counter. if the counter exceeds this value, an interrupt will be generated. this register should be loaded prior to setting the fan speed control enable (fscen) bit in the fsc1 register to avoid generating unintentional interrupts. the overflow count value can be deter- mined using the following equation where ff % is equal to the percentage of nominal rpm which constitutes a fan failure: decimal-overflow-count-value = (1 ,200,000)/(rpm x divisor x ff%) based on the above equation, a divisor of 8 and a detected fan failure at 70% of nominal rpm, the fan speed monitoring l ogic is capable of supporting a low end nominal rpm of 850. high end rpm values are basically unlimited but counter reso- lution will be diminished above 8000 rpm.
4-27 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 36h: fan speed curre nt count 1 (fscc1) register name: fscc1 address: 36h reset value: 0000_0000b description fan speed current count 1. this register affects pin p2.5. 76543210 fan speed current count bit(s) bit label access description 7 fsco7-0 r these eight bits, when enabled by setting the fscen bit in the fsc1 register pro- vide the user with an accurate binary fan speed count value which can be used to determine the current rpm value of the fan. a minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. the following equation can be used to determine the current rpm value of the fan: rpm = (1,200,000)/(decimal-count-value x divisor) when the result of a read of this register is 00h, an accurate fan speed count value has not been generated indicating that the fan has not completed a minimum of one revolution. when the result of a read of this register is ffh, the fan is rotating very slowly or there are no tachometer pulse s present. when operating in a polled mode with the fsien bit reset in the fsc1 regist er, this register will automatically update with an accurate fan speed count once per revolution of the fan. when operating in an interrupt mode with the fsien bit set in th e fsc1 register, this register will auto- matically update with an accurate fan s peed count once per revolution of the fan until an interrupt is generated. once the inte rrupt is generated, the value will remain stable until the interrupt is cleared. when t he interrupt is cleared, this register will also be cleared indicating that a valid rpm value is in the process of being gener- ated.
4-28 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 38h: fan speed control 2 (fsc2) register name: fsc2 address: 38h reset value: 00xx_xx00b description fan speed control 2. this register affects pin p2.6 76543210 fan speed control ena- ble fan speed interrupt ena- ble fan divisor 1 fan divisor 0 bit(s) bit label access description 7 fscen r/w fan speed control enable when this bit is set, p2.6 is automaticall y configured to provide a fan speed monitor- ing input. configurations for this i/o pin which may have previously been enabled through other control registers will be ov erridden except for the bypass select func- tion (bits 6 and 5 of the appropriate bit control registers). if the appropriate bypass bits have been set, the odd numbered fan speed input pins (p1.1, p1.3, p1.5, p1.7, p2.1, p2.3, p2.5 or p2.7) will be configured as outputs . when this bit is reset, the remaining bits in this register have no effect on the operation of p2.6. when enabled as a fan speed monitoring input, pulses from the fan tachometer out- put gate an internal 20khz clock into an ei ght-bit counter. a divisor value stored in bits one and zero of this register allow t he user to select one of four nominal rpm values based on fan tachometer outputs which pulse twice per revolution. the fscc2 register provides the user with an accurate binary fan speed count value which can be used to determine the current rpm value of the fan. incoming pulses are filtered and conditioned to accommodate the slow rise and fall times typical of fan tachometer outputs. the maximum input signal is limited to a range of vss to vdd. if this input is supplied from a fan tachometer output which exceeds this range, external components will be required to lim it the signal to an acceptable range. 6 fsien r/w fan speed interrupt enable when this bit is set, the p2.6 input will be enabled to generate an interrupt if the eight bit counter value is greater than or equal to the count overflow value loaded into the fsco0 register. if the condition oc curs, the int# pin will assert and a binary value equal to the address of this register will appear in the bcis register. when this bit is reset, the fan speed monitoring logi c will not generate an interrupt condition. 1:0 fd1-0 r/w fan divisor these two bits determine the divisor value used to determine the correct range of rpm values supplied to the eight-bit fan speed counter. table 4-5 describes the available divisor values: the decimal count value can be calc ulated using the following equation: decimal-count-value = (1,200,000)/(rpm x divisor) any nominal rpm value can be used in the above equation along with the appropri- ate divisor as long as the maximum non-fa ilure count value does not exceed the lim- its of an eight-bit counter. typical applications may consider 60% to 70% of normal rpm a fan failure which would result in a decimal count value of 250 (fah) and 214 (d6h) respectively at the above stated rpm values.
4-29 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 table 4-5: fan divisor fd1 fd0 divisor nominal rpm decimal count value 0 0 1 8000 150(96h) 0 1 2 4000 150(96h) 1 0 4 2000 150(96h) 1 1 8 1000 150(96h)
4-30 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 39h: fan speed count overflow 2 (fsco2) register name: fsco2 address: 39h reset value: 0000_0000b description fan speed count overflow 2. this register affects pin p2.6. 76543210 fan speed count overflow bit(s) bit label access description 7 fsco7-0 r/w fan speed count overflow these eight bits are compared to the eight-bit fan speed counter. if the counter exceeds this value, an interrupt will be generated. this register should be loaded prior to setting the fan speed control enable (fscen) bit in the fsc2 register to avoid generating unintentional interrupts. the overflow count value can be deter- mined using the following equation where ff % is equal to the percentage of nominal rpm which constitutes a fan failure: decimal-overflow-count-value = (1 ,200,000)/(rpm x divisor x ff%) based on the above equation, a divisor of 8 and a detected fan failure at 70% of nominal rpm, the fan speed monitoring l ogic is capable of supporting a low end nominal rpm of 850. high end rpm values are basically unlimited but counter reso- lution will be diminished above 8000 rpm.
4-31 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 3ah: fan speed current count 2 (fscc2) register name: fscc2 address: 3ah reset value: 0000_0000b description fan speed current count 2. this register affects pin p2.6. 76543210 fan speed current count bit(s) bit label access description 7 fsco7-0 r/w these eight bits, when enabled by setting the fscen bit in the fsc2 register pro- vide the user with an accurate binary fan speed count value which can be used to determine the current rpm value of the fan. a minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. the following equation can be used to determine the current rpm value of the fan: rpm = (1,200,000)/(decimal-count-value x divisor) when the result of a read of this register is 00h, an accurate fan speed count value has not been generated indicating that the fan has not completed a minimum of one revolution. when the result of a read of this register is ffh, the fan is rotating very slowly or there are no tachometer pulse s present. when operating in a polled mode with the fsien bit reset in the fsc2 regist er, this register will automatically update with an accurate fan speed count once per revolution of the fan. when operating in an interrupt mode with the fsien bit set in th e fsc2 register, this register will auto- matically update with an accurate fan s peed count once per revolution of the fan until an interrupt is generated. once the inte rrupt is generated, the value will remain stable until the interrupt is cleared. when t he interrupt is cleared, this register will also be cleared indicating that a valid rpm value is in the process of being gener- ated.
4-32 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 3ch: fan speed control 3 (fsc3) register name: fsc3 address: 3ch reset value: 00xx_xx00b description fan speed control 3. this register affects pin p2.7. 76543210 fan speed control ena- ble fan speed interrupt ena- ble fan divisor 1 fan divisor 0 bit(s) bit label access description 7 fscen r/w fan speed control enable when this bit is set, p2.7 is automaticall y configured to provide a fan speed monitor- ing input. configurations for this i/o pin which may have previously been enabled through other control registers will be ov erridden except for the bypass select func- tion (bits 6 and 5 of the appropriate bit control registers). if the appropriate bypass bits have been set, the odd numbered fan speed input pins (p1.1, p1.3, p1.5, p1.7, p2.1, p2.3, p2.5 or p2.7) will be configured as outputs . when this bit is reset, the remaining bits in this register have no effect on the operation of p2.7. when enabled as a fan speed monitoring input, pulses from the fan tachometer out- put gate an internal 20khz clock into an ei ght-bit counter. a divisor value stored in bits one and zero of this register allow t he user to select one of four nominal rpm values based on fan tachometer outputs which pulse twice per revolution. the fscc3 register provides the user with an accurate binary fan speed count value which can be used to determine the current rpm value of the fan. incoming pulses are filtered and conditioned to accommodate the slow rise and fall times typical of fan tachometer outputs. the maximum input signal is limited to a range of vss to vdd. if this input is supplied from a fan tachometer output which exceeds this range, external components will be required to lim it the signal to an acceptable range. 6 fsien r/w fan speed interrupt enable when this bit is set, the p2.7 input will be enabled to generate an interrupt if the eight bit counter value is greater than or equal to the count overflow value loaded into the fsco0 register. if the condition oc curs, the int# pin will assert and a binary value equal to the address of this register will appear in the bcis register. when this bit is reset, the fan speed monitoring logi c will not generate an interrupt condition. 1:0 fd1-0 r/w fan divisor these two bits determine the divisor value used to determine the correct range of rpm values supplied to the eight-bit fan speed counter. table 4-6 describes the available divisor values: the decimal count value can be calc ulated using the following equation: decimal-count-value = (1,200,000)/(rpm x divisor) any nominal rpm value can be used in the above equation along with the appropri- ate divisor as long as the maximum non-fa ilure count value does not exceed the lim- its of an eight-bit counter. typical applications may consider 60% to 70% of normal rpm a fan failure which would result in a decimal count value of 250 (fah) and 214 (d6h) respectively at the above stated rpm values.
4-33 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 table 4-6: fan divisor fd1 fd0 divisor nominal rpm decimal count value 0 0 1 8000 150(96h) 0 1 2 4000 150(96h) 1 0 4 2000 150(96h) 1 1 8 1000 150(96h)
4-34 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 3dh: fan speed count overflow 3 (fsco3) register name: fsco3 address: 3dh reset value: 0000_0000b description fan speed count overflow 3. this register affects pin p2.7. 76543210 fan speed count overflow bit(s) bit label access description 7 fsco7-0 r/w fan speed count overflow these eight bits are compared to the eight-bit fan speed counter. if the counter exceeds this value, an interrupt will be generated. this register should be loaded prior to setting the fan speed control enable (fscen) bit in the fsc1 register to avoid generating unintentional interrupts. the overflow count value can be deter- mined using the following equation where ff % is equal to the percentage of nominal rpm which constitutes a fan failure: decimal-overflow-count-value = (1 ,200,000)/(rpm x divisor x ff%) based on the above equation, a divisor of 8 and a detected fan failure at 70% of nominal rpm, the fan speed monitoring l ogic is capable of supporting a low end nominal rpm of 850. high end rpm values are basically unlimited but counter reso- lution will be diminished above 8000 rpm.
4-35 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 3eh: fan speed curre nt count 3 (fscc3) register name: fscc3 address: 3eh reset value: 0000_0000b description fan speed current count 3. this register affects pin p2.7. 76543210 fan speed current count bit(s) bit label access description 7 fsco7-0 r/w these eight bits, when enabled by setting the fscen bit in the fsc3 register pro- vide the user with an accurate binary fan speed count value which can be used to determine the current rpm value of the fan. a minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. the following equation can be used to determine the current rpm value of the fan: rpm = (1,200,000)/(decimal-count-value x divisor) when the result of a read of this register is 00h, an accurate fan speed count value has not been generated indicating that the fan has not completed a minimum of one revolution. when the result of a read of this register is ffh, the fan is rotating very slowly or there are no tachometer pulse s present. when operating in a polled mode with the fsien bit reset in the fsc3 regist er, this register will automatically update with an accurate fan speed count once per revolution of the fan. when operating in an interrupt mode with the fsien bit set in th e fsc3 register, this register will auto- matically update with an accurate fan s peed count once per revolution of the fan until an interrupt is generated. once the inte rrupt is generated, the value will remain stable until the interrupt is cleared. when t he interrupt is cleared, this register will also be cleared indicating that a valid rpm value is in the process of being gener- ated.
4-36 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 80h-87h: bit control port 0 registers (bcp00-bcp07) register name: bcp00-bcp07 address: 80h - 87h reset value: 0000_001xb description bit control port 0 registers these eight registers provi de individual bit control for the port 0 i/o pins. all register bits are identical from a control and status perspective with the only difference being the indi vidual i/o pin controlled. the data direction (bit 1) and general purpose data (b it 0) bits are effectively the same bits found in the ddp0 and gpd0 registers, with parallel read and write paths. 76543210 function select data direction general pur- pose data bit(s) bit label access description 4:2 fs2-0 r/w function select these three bits, along with the dd and gpd bits, determine the function of each i/ o pin. when configured as an output, these bits determine the rate at which the high current drive i/o will toggle, providing a simple mechanism for flashing led's. the five bits allow the user to select one of seven flash rates as well as drive the led both on and off. it is assumed that the led is connected to vdd through an external current limiting resistor. table 4-7 describes the possible combinations which can be used to drive an led. when configured as an input, these bits det ermine the type of i/o pin edge transition which will generate an interrupt condition. tr ansition detectors within the device will filter the changes observed at the i/o pi n and determine if a valid transition has occurred. if a valid transition occurs, the int# pin will assert and a binary value equal to the address of this register will appear in the bcis register. table 4-8 describes the available input edge combinations. note: when configuring an i/o pin from an outpu t to an input with in terrupt enabled, it is suggested that the data direction ch ange and interrupt enabling be accom- plished with separate regi ster write operations. this guarantees that any i/o transition which occurs as a result of the data direction change which may rely on the weak internal pull- up will not generate an unexpected interrupt. 1 dd r/w data direction this bit determines the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appr opriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually config- ured as a true bidirectional function. a dditionally, an open-drain or open-source function can be developed by resetting or setting the appropriate data bit and using the data direction bit as the programmed data value. after a reset or power-on, this bit will be set to a binary one, enabling th e i/o pin as an input with weak pull-up. 0 gpd r/w general purpose data when the i/o pin has been enabled as an output, writing this bit determines the data value which will be present on the corresponding i/o pin. if the i/o pin has been ena- bled as an input, reading this register bit will represent the current voltage applied to the pin. at no time will this bit directly represent the value latched into the data regis- ter. if the pin is enabled as an input and ther e is no signal applied, a weak internal pull-up resistor will hold the pin at a binary one. after a reset or power-on, this regis- ter bit will be set to a binary one, but the va lue returned from a register read will be the level applied to the pin since by default each pin is an input.
4-37 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 table 4-7: led combinations fs2 fs1 fs0 dd gpd i/o state led state 0 0 0 0 0 output low led turned on 0 0 0 0 1 output high led turned off 0 0 0 1 x pulled-up input led turned off - default state 0 0 1 0 x output toggling led flashing at 0.25hz 0 1 0 0 x output toggling led flashing at 0.33hz 0 1 1 0 x output toggling led flashing at 0.50hz 1 0 0 0 x output toggling led flashing at 1.00hz 1 0 1 0 x output toggling led flashing at 2.00hz 1 1 0 0 x output toggling led flashing at 3.08hz 1 1 1 0 x output toggling led flashing at 4.00hz note: the i/o is driven in an open drain mode when configured as a toggling output. table 4-8: input edge combinations fs2 fs1 fs0 dd gpd interrupt condition 0001xno interrupt generated - default state x 0 1 1 x interrupt generated on a rising edge x 1 0 1 x interrupt generated on a falling edge x 1 1 1 x interrupt generated on either edge 1001xno interrupt generated
4-38 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 90h-97h: bit control port 1 registers (bcp10-bcp17) register name: bcp10-bcp17 address: 90h-97h reset value: 0000_001xb description bit control port 1 registers these eight registers provi de individual bit control for the port 0 i/o pins. all register bits are identical from a control and status perspective with the only difference being the individual i/o pin controlled and the presence of the bypass function. the data di rection (bit 1) and general purpose data (bit 0) bits are effectively the same bits found in the ddp0 and gpd0 registers, with parallel read and write paths. these eight registers function the same as the ei ght bit control port 0 registers, described above, except that they relate to the port 1 i/o pins. 76543210 function select data direction general pur- pose data bit(s) bit label access description 4:2 fs2-0 r/w function select these three bits, along with the dd and gpd bits, determine the function of each i/ o pin. when configured as an output, these bits determine the rate at which the high current drive i/o will toggle, providing a simple mechanism for flashing led's. the five bits allow the user to select one of seven flash rates as well as drive the led both on and off. it is assumed that the led is connected to vdd through an external current limiting resistor. table 4-7 describes the possible combinations which can be used to drive an led. when configured as an input, these bits det ermine the type of i/o pin edge transition which will generate an interrupt condition. tr ansition detectors within the device will filter the changes observed at the i/o pi n and determine if a valid transition has occurred. if a valid transition occurs, the int# pin will assert and a binary value equal to the address of this register will appear in the bcis register. table 4-8 describes the available input edge combinations. note: when configuring an i/o pin from an outpu t to an input with in terrupt enabled, it is suggested that the data direction ch ange and interrupt enabling be accom- plished with separate regi ster write operations. this guarantees that any i/o transition which occurs as a result of the data direction change which may rely on the weak internal pull- up will not generate an unexpected interrupt. 1 dd r/w data direction this bit determines the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appr opriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually config- ured as a true bidirectional function. a dditionally, an open-drain or open-source function can be developed by resetting or setting the appropriate data bit and using the data direction bit as the programmed data value. after a reset or power-on, this bit will be set to a binary one, enabling th e i/o pin as an input with weak pull-up.
4-39 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 0 gpd r/w general purpose data when the i/o pin has been enabled as an output, writing this bit determines the data value which will be present on the corre sponding i/o pin. if the i/o pin has been ena- bled as an input, reading this register bit will represent the current voltage applied to the pin. at no time will this bit directly r epresent the value latched into the data regis- ter. if the pin is enabled as an input and t here is no signal applied, a weak internal pull-up resistor will hold the pin at a binary one. afte r a reset or power-on, this regis- ter bit will be set to a binary one, but the value returned from a register read will be the level applied to the pin since by default each pin is an input. bit(s) bit label access description
4-40 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 98h-9bh: pulse width modulation control registers (pwmc0-pwmc3) register name: pwmc0-pwmc3 address: 98h-9bh reset value: x000_0000b description pulse width modulation control these four registers provide a pulse width modulated output which can optionally be made available on the p2.0 through p2.3 i/o pins. configurations for these i/o pins which may have previously been enabled through other control registers will be overridden if either or both of the pwbf bits are set. the pwbf bits have higher priority control over the p2.0 through p2.3 i/o pins than any other mode of operation. the pulse width modulated outputs are based on a 32 step counter and provide values from a 3.125% to a 100% duty cycle in 3.125% increments. 76543210 pulse width base frequency pulse width percentage bit(s) bit label access description 6:5 pwbf1-0 r/w pulse width base frequency these two bits determine the base operati ng frequency of the pulse width modu- lated output. these frequencies are based on the input clock rate of 10.0mhz. three additional base frequency ranges are availa ble and are selected through bits 5 and 4 of the backplane controller option regist er located at address fdh. the following table describes the default base frequencies: 4:0 pwp4-0 r/w pulse width percentage these five bits determine the percentage of high time that the output pulse will con- tain. there are 32 steps that can be adjusted in 3.125% increments. table 4-9 describes the available percentages: table 4-9: pulse width percentages pwp4 pwp3 pwp2 pwp1 pwp0 pulse width percentage 0 0 0 0 0 3.125% on/high time 0 0 0 0 1 6.25% on/high time 0 0 0 1 0 9.375% on/high time pwbf1 pwbf0 pulse width base frequency 0 0 normal operation - control is provided through gpd1/ddp1 or bcp1 0 1 26khz base frequency 1 0 52khz base frequency 1 1 104khz base frequency
4-41 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 0 0 0 1 1 12.5% on/high time 0 0 1 0 0 15.625% on/high time 0 0 1 0 1 18.75% on/high time 0 0 1 1 0 21.875% on/high time 0 0 1 1 1 25.0% on/high time 0 1 0 0 0 28.125% on/high time 0 1 0 0 1 31.25% on/high time 0 1 0 1 0 34.375% on/high time 0 1 0 1 1 37.5% on/high time 0 1 1 0 0 40.625% on/high time 0 1 1 0 1 43.75% on/high time 0 1 1 1 0 46.875% on/high time 0 1 1 1 1 50.0% on/high time 1 0 0 0 0 53.125% on/high time 1 0 0 0 1 56.25% on/high time 1 0 0 1 0 59.375% on/high time 1 0 0 1 1 62.5% on/high time 1 0 1 0 0 65.625% on/high time 1 0 1 0 1 68.75% on/high time 1 0 1 1 0 71.875% on/high time 1 0 1 1 1 75.0% on/high time 1 1 0 0 0 78.125% on/high time 1 1 0 0 1 81.25% on/high time 1 1 0 1 0 84.375% on/high time 1 1 0 1 1 87.5% on/high time 1 1 1 0 0 90.625% on/high time 1 1 1 0 1 93.75% on/high time 1 1 1 1 0 96.875% on/high time 1 1 1 1 1 100% on/high time table 4-9: pulse width percentages pwp4 pwp3 pwp2 pwp1 pwp0 pulse width percentage
4-42 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 a0h-a7h: bit control port 2 registers (bcp20-bcp27) register name: bcp20-bcp27 address: a0h-a7h reset value: 0000_001xb description bit control port 2 registers these eight registers provi de individual bit control for the port 0 i/o pins. all register bits are identical from a control and status perspective with the only difference being the individual i/o pin controlled and the presence of the bypass function. the data di rection (bit 1) and general purpose data (bit 0) bits are effectively the same bits found in the ddp0 and gpd0 registers, with parallel read and write paths. these eight registers function the same as the ei ght bit control port 0 registers, described above, except that they relate to the port 2 i/o pins. 76543210 function select data direction general pur- pose data bit(s) bit label access description 4:2 fs2-0 r/w function select these three bits, along with the dd and gpd bits, determine the function of each i/ o pin. when configured as an output, these bits determine the rate at which the high current drive i/o will toggle, providing a simple mechanism for flashing led's. the five bits allow the user to select one of seven flash rates as well as drive the led both on and off. it is assumed that the led is connected to vdd through an external current limiting resistor. table 4-7 describes the possible combinations which can be used to drive an led. when configured as an input, these bits det ermine the type of i/o pin edge transition which will generate an interrupt condition. tr ansition detectors within the device will filter the changes observed at the i/o pi n and determine if a valid transition has occurred. if a valid transition occurs, the int# pin will assert and a binary value equal to the address of this register will appear in the bcis register. table 4-8 describes the available input edge combinations. note: when configuring an i/o pin from an outpu t to an input with in terrupt enabled, it is suggested that the data direction ch ange and interrupt enabling be accom- plished with separate regi ster write operations. this guarantees that any i/o transition which occurs as a result of the data direction change which may rely on the weak internal pull- up will not generate an unexpected interrupt. 1 dd r/w data direction this bit determines the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appr opriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually config- ured as a true bidirectional function. a dditionally, an open-drain or open-source function can be developed by resetting or setting the appropriate data bit and using the data direction bit as the programmed data value. after a reset or power-on, this bit will be set to a binary one, enabling th e i/o pin as an input with weak pull-up.
4-43 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 0 gpd r/w general purpose data when the i/o pin has been enabled as an output, writing this bit determines the data value which will be present on the corre sponding i/o pin. if the i/o pin has been ena- bled as an input, reading this register bit will represent the current voltage applied to the pin. at no time will this bit directly r epresent the value latched into the data regis- ter. if the pin is enabled as an input and t here is no signal applied, a weak internal pull-up resistor will hold the pin at a binary one. afte r a reset or power-on, this regis- ter bit will be set to a binary one, but the value returned from a register read will be the level applied to the pin since by default each pin is an input. bit(s) bit label access description
4-44 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 b0h-b7h: bit control port 3 registers (bcp30-bcp37) register name: bcp30-bcp37 address: b0h-b7h reset value: 0000_001xb description bit control port 3 registers these eight registers provi de individual bit control for the port 0 i/o pins. all register bits are identical from a control and status perspective with the only difference being the individual i/o pin controlled and the presence of the bypass function. the data di rection (bit 1) and general purpose data (bit 0) bits are effectively the same bits found in the ddp0 and gpd0 registers, with parallel read and write paths. these eight registers function the same as the ei ght bit control port 0 registers, described above, except that they relate to the port 3 i/o pins. in addition, the control of the individual i/o pins assigned to these registers can be overridden by the pbc0, pbc1, pbc2 and pbc3 registers when port bypass control is required. 76543210 function select data direction general pur- pose data bit(s) bit label access description 4:2 fs2-0 r/w function select these three bits, along with the dd and gpd bits, determine the function of each i/ o pin. when configured as an output, these bits determine the rate at which the high current drive i/o will toggle, providing a simple mechanism for flashing led's. the five bits allow the user to select one of seven flash rates as well as drive the led both on and off. it is assumed that the led is connected to vdd through an external current limiting resistor. table 4-7 describes the possible combinations which can be used to drive an led. when configured as an input, these bits det ermine the type of i/o pin edge transition which will generate an interrupt condition. tr ansition detectors within the device will filter the changes observed at the i/o pi n and determine if a valid transition has occurred. if a valid transition occurs, the int# pin will assert and a binary value equal to the address of this register will appear in the bcis register. table 4-8 describes the available input edge combinations. note: when configuring an i/o pin from an outpu t to an input with in terrupt enabled, it is suggested that the data direction ch ange and interrupt enabling be accom- plished with separate regi ster write operations. this guarantees that any i/o transition which occurs as a result of the data direction change which may rely on the weak internal pull- up will not generate an unexpected interrupt. 1 dd r/w data direction this bit determines the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appr opriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually config- ured as a true bidirectional function. a dditionally, an open-drain or open-source function can be developed by resetting or setting the appropriate data bit and using the data direction bit as the programmed data value. after a reset or power-on, this bit will be set to a binary one, enabling th e i/o pin as an input with weak pull-up.
4-45 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 0 gpd r/w general purpose data when the i/o pin has been enabled as an output, writing this bit determines the data value which will be present on the corre sponding i/o pin. if the i/o pin has been ena- bled as an input, reading this register bit will represent the current voltage applied to the pin. at no time will this bit directly r epresent the value latched into the data regis- ter. if the pin is enabled as an input and t here is no signal applied, a weak internal pull-up resistor will hold the pin at a binary one. afte r a reset or power-on, this regis- ter bit will be set to a binary one, but the value returned from a register read will be the level applied to the pin since by default each pin is an input. bit(s) bit label access description
4-46 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 c0h-c7h: bit control port 4 registers (bcp40-bcp47) register name: bcp40-bcp47 address: c0h-c7h reset value: 0000_001xb description bit control port 11 registers these eight registers provi de individual bit control for the port 0 i/o pins. all register bits are identical from a control and status perspective with the only difference being the individual i/o pin controlled and the presence of the bypass function. the data di rection (bit 1) and general purpose data (bit 0) bits are effectively the same bits found in the ddp0 and gpd0 registers, with parallel read and write paths. these eight registers function the same as the ei ght bit control port 0 registers, described above, except that they relate to the port 4 i/o pins. in addition, the control of the individual i/o pins assigned to these registers can be overridden by the pbc4, pbc5, pbc6 and pbc7 registers when port bypass control is required. 76543210 function select data direction general pur- pose data bit(s) bit label access description 4:2 fs2-0 r/w function select these three bits, along with the dd and gpd bits, determine the function of each i/ o pin. when configured as an output, these bits determine the rate at which the high current drive i/o will toggle, providing a simple mechanism for flashing led's. the five bits allow the user to select one of seven flash rates as well as drive the led both on and off. it is assumed that the led is connected to vdd through an external current limiting resistor. table 4-7 describes the possible combinations which can be used to drive an led. when configured as an input, these bits det ermine the type of i/o pin edge transition which will generate an interrupt condition. tr ansition detectors within the device will filter the changes observed at the i/o pi n and determine if a valid transition has occurred. if a valid transition occurs, the int# pin will assert and a binary value equal to the address of this register will appear in the bcis register. table 4-8 describes the available input edge combinations. note: when configuring an i/o pin from an outpu t to an input with in terrupt enabled, it is suggested that the data direction ch ange and interrupt enabling be accom- plished with separate regi ster write operations. this guarantees that any i/o transition which occurs as a result of the data direction change which may rely on the weak internal pull- up will not generate an unexpected interrupt. 1 dd r/w data direction this bit determines the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appr opriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually config- ured as a true bidirectional function. a dditionally, an open-drain or open-source function can be developed by resetting or setting the appropriate data bit and using the data direction bit as the programmed data value. after a reset or power-on, this bit will be set to a binary one, enabling th e i/o pin as an input with weak pull-up.
4-47 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 0 gpd r/w general purpose data when the i/o pin has been enabled as an output, writing this bit determines the data value which will be present on the corre sponding i/o pin. if the i/o pin has been ena- bled as an input, reading this register bit will represent the current voltage applied to the pin. at no time will this bit directly r epresent the value latched into the data regis- ter. if the pin is enabled as an input and t here is no signal applied, a weak internal pull-up resistor will hold the pin at a binary one. afte r a reset or power-on, this regis- ter bit will be set to a binary one, but the value returned from a register read will be the level applied to the pin since by default each pin is an input. bit(s) bit label access description
4-48 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 f8h: backplane controlle r interrupt status (bcis) register name: bcis address: f8h reset value: 0000_0000b description backplane controller interrupt status register 76543210 interrupt active bit(s) bit label access description 7:0 ia7-0 r interrupt active these eight bits determine the currently active interrupt source which has been ena- bled through the port bypass control register s, the fan speed control registers or the bit control registers. the address of the port bypass control registers, the address of the bit control registers or the address of the fan speed control regis- ters will be generated as an indicator of the currently active inte rrupt source. if multi- ple interrupt sources are active, the va lue generated will be prioritized from the lowest binary value to the highest binary value. to clear the current interrupt and deassert the int# pin, a value of ffh must be written to this register. if a higher binary value/lower priority interrupt source is still active, the new value will be gener- ated and the int# pin will re-assert.
4-49 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 fch: backplane controller test (bct) register name: bct address: fch reset value: 0xxx_x000b description backplane controller interrupt status register 76543210 soft reset fan speed bypass flash rate bypass serial inter- face filter bypass bit(s) bit label access description 7 srst r/w soft reset setting this bit resets the device at the end of the current serial transfer. all i/o's, control registers, clock dividers and the slav e state machine are reset by this bit. this bit is self resetting and writes of a zero to this bit will have no effect on the cur- rent state of the device. 2 fsb r/w fan speed bypass setting this bit causes the main clock divider for the fan speed monitors to be bypassed. bypassing the main clock divide r causes the fan speed counters to oper- ate 500 times faster than normal. when reset or after power-on, the normal clock divider will be activated. this bit should not be set during normal operation. 1 frb r/w flash rate bypass setting this bit causes the main clock divi der for the flash rate generators to be bypassed. bypassing the main clock divide r causes the expected flash rates to be 125,000 times faster than normal. when reset or after power-on, the normal clock divider will be activated. this bit should not be set during normal operation. 0 sifb r/w serial interface filter bypass setting this bit causes the digital filters on the scl and sda pins to be bypassed. bypassing the filters allows the serial transfer speed to be increased for test pur- poses. when reset or after power-on, normal filtering will be activated. this bit should not be set during normal operation.
4-50 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 fdh: backplane cont roller option (bco) register name: bco address: fdh reset value: x000_xxxxb description backplane controller interrupt status register 76543210 ta c h f i l t e r extend pulse width modulation divider select bit(s) bit label access description 6 tfe r/w tach filter extend setting this bit causes the input filters on p1.0 through p2.7 to be extended from a two stage voting circuit to a five stage vo ting circuit. additional noise immunity of approximately 300 nanoseconds will be achiev ed. this bit enables the filter exten- sion logic on all tach inputs and is independent of the tach control logic. the extended filters on p1.0 through p2.7 can be used in other applications with noisy signaling that require an enhanced input filter. after a reset or power-on, this register bit will be cleared to a zero, enab ling normal input filter operation. 5:4 pds1-0 r/w pulse width modulation divider select these two bits determine the divider that is used for the pulse width modulation cir- cuits. the base frequency range of all pulse width modulation circ uits are controlled by these bits. each pulse width modulati on circuit can be programmed to select one of the three available frequencies within the range. after a reset or power-on, these register bits will be cleared to a zero. the following table describes the available fre- quency ranges: table 4-10: pulse width modulation frequencies pds1 pds0 pulse width modulation frequency range 0 0 26khz, 52khz or 104khz (divide by 3) 0 1 5.2khz, 10.4khz or 20.8khz (divide by 15) 1 0 1.04khz, 2.08khz or 4. 16khz (divide by 75) 1 1 208hz, 416hz, 833hz (divide by 375)
4-51 control registers ssc050-01 control register definition data sheet revision 4.0 november 10, 2004 ffh: backplane controller version (ver) register name: ver address: ffh reset value: 0001_0001b description backplane controller version register 76543210 version bit(s) bit label access description 7:0 ver7-0 r/w version these bits define the current version of the backplane controller. if revisions are required, these bits will change to reflect the latest version of the device. in general, changes to bits 3 through 0 will reflect a minor revision and changes to bits 7 through 4 will reflect a major revision or different device type. firmware should check this register to determine the curr ent capabilities of the device. note: the ssc050-01 and ssc050 curr ently utilize the same bina ry value in the version register. however, the device type can be determined by performing the following register write and read before configurin g the device for normal operation. write a 15h to the pulse width modulation control register at location 98h. read this register and check the result, if the regi ster reads back 15h, the device is a ssc050-01, if the register reads back 00h, the device is a ssc050.
5-1 electrical characteristics ssc050-01 maximum ratings data sheet revision 4.0 november 10, 2004 chapter 5 electrical characteristics m aximum r atings dc c haracteristics table 5-1: absolute maximum ratings parameter symbol limits unit dc supply voltage vdd -0.3 to +3.9 v lvttl input voltage vin -1.0 to vdd+0.3 v 5 volt compatible input voltage vin -1.0 to +6.5 v dc input current iin 10 ua storage temperature range tstg -40 to +125 c latchup current ilp 150 ma table 5-2: operating conditions parameter symbol min max unit supply voltage vdd 3.00 3.60 v supply current idd 50 ma operating ambient temperature range ta -40 +85 c
5-2 electrical characteristics ssc050-01 dc characteristics data sheet revision 4.0 november 10, 2004 table 5-3: general purpose i/o ports, p4, p3, p2, p1, p0 parameter symbol condition min max unit output high voltage voh ioh=12ma 2.4 vdd v output low voltage vol iol=12ma vss 0.4 v input high voltage vih 2.0 5.5 v input low voltage vil vss-0.5 0.8 v schmitt threshold - positive vt+ 2.0 v schmitt threshold - negative vt- 0.8 v schmitt hysteresis vh 0.4 v input current with pull-up iin vin=vss -25 -125 ua three state output leakage (device test mode) ioz -10 +10 ua table 5-4: two-wire serial interface, sda parameter symbol condition min max unit output low voltage vol iol=4ma vss 0.4 v input high voltage vih 2.0 5.5 v input low voltage vil vss-0.5 0.8 v schmitt threshold - positive vt+ 2.0 v schmitt threshold - negative vt- 0.8 v schmitt hysteresis vh 0.4 v input current iin vin=vdd/vss -10 +10 ua three state output leakage ioz -10 +10 ua
5-3 electrical characteristics ssc050-01 dc characteristics data sheet revision 4.0 november 10, 2004 table 5-5: two-wire serial interface, scl parameter symbol condition min max unit input high voltage vih 2.0 5.5 v input low voltage vil vss-0.5 0.8 v schmitt threshold - positive vt+ 2.0 v schmitt threshold - negative vt- 0.8 v schmitt hysteresis vh 0.4 v input current iin vin=vdd/vss -10 +10 ua table 5-6: address inputs, a2, a1, a0, asel parameter symbol condition min max unit input high voltage vih 2.0 5.5 v input low voltage vil vss-0.5 0.8 v schmitt threshold - positive vt+ 2.0 v schmitt threshold - negative vt- 0.8 v schmitt hysteresis vh 0.4 v input current iin vin=vdd/vss -10 +10 ua table 5-7: interrupt output, int# parameter symbol condition min max unit output low voltage vol iol=4ma vss 0.4 v table 5-8: test inputs: test0, test1, test2 parameter symbol condition min max unit input high voltage vih 2.0 5.5 v input low voltage vil vss-0.5 0.8 v schmitt threshold - positive vt+ 2.0 v schmitt threshold - negative vt- 0.8 v schmitt hysteresis vh 0.4 v input current iin vin=vdd/vss -10 +10 ua
5-4 electrical characteristics ssc050-01 dc characteristics data sheet revision 4.0 november 10, 2004 table 5-9: oscillator/clock input, osci parameter symbol condition min max unit input high voltage vih vdd/2 vdd+0.3 v input low voltage vil vss-0.5 vdd/2 v switching threshold vt vdd/2 v input current iin vin=vdd/vss -10 +10 ua table 5-10: oscillator output, osco parameter symbol condition min max unit output high voltage voh ioh=4ma vdd-0.3 vdd v output low voltage vol iol=4ma vss vss+0.3 v
5-5 electrical characteristics ssc050-01 ac characteristics data sheet revision 4.0 november 10, 2004 ac c haracteristics external clock timing table 5-11: low frequency operation parameter symbol condition min max unit nominal frequency f 9.5 10.5 mhz frequency range f 8.0 12.5 mhz clock cycle time t1 80 125 ns clock low time t2 32 75 ns clock high time t3 32 75 ns clock slew rate t4 1 v/ns figure 5-1. clock cycle timing clock t2 t1 t4 clock cycle timing t3
5-6 electrical characteristics ssc050-01 ac characteristics data sheet revision 4.0 november 10, 2004 table 5-12: two-wire serial interface timing parameter symbol standard mode fast mode unit min max min max scl clock frequency fscl 0 100 0 400 khz bus free time tbuf 4.7 1.3 us hold time - start condition thd:sta 4.0 0.6 us scl low time tlow 4.7 1.3 us scl high time thigh 4.0 0.6 us setup time - start condition tsu:sta 4.7 0.6 us hold time - data thd:dat 0 0 0.9 us setup time - data tsu:dat 250 100 ns setup time - stop condition tsu:sto 4.0 0.6 us figure 5-2. scl s t o p sda two wire serial interface timing s t a r t tlow thigh thd:sta thd:dat tsu:dat tsu:sta tbuf tsu:sto
5-7 electrical characteristics ssc050-01 ac characteristics data sheet revision 4.0 november 10, 2004 two-wire serial interface operation the following diagrams illustrate the two-wire serial interface read and write capabilities of the ssc050-01. all operations ca n be performed in any order. oscillator requirements the ssc050-01 can use an external 3.3 volt 8.0mhz to 12.5mhz clock source connected to the osci pin with cksel2 tied to vss. an external 3.3 volt 32.0mhz to 50.0mhz clock source can be connected to the osci pin with cksel2 tied to vd d and cksel1 tied to vss. an external 3.3 volt 48.0mhz to 75.0mhz clock source can be connected to the osci pin with cksel2 tied to vdd and cksel1 tied to vdd. alternatively, an 8.0mhz to 12.5mhz crystal and several passive components figure 5-3. two-wire serial interface operation slave address a s e l s t a r t s a c k a c k a c k s t o p p a c k a c k multi-byte write data n word address (n) data n+x data n+1 slave address a s e l s t a r t s a c k a c k a c k s t o p p byte write data word address slave address a s e l s t a r t s a c k a c k a c k s t o p p a c k multi-byte read data n slave address data n+x data n+1 word address (n) a c k s a s e l s t a r t slave address a s e l s t a r t s a c k a c k s t o p p byte read data n slave address word address (n) a c k s a s e l s t a r t
5-8 electrical characteristics ssc050-01 ac characteristics data sheet revision 4.0 november 10, 2004 may be used. the following diagrams illustrate the two options available when using a crystal. the passive components shown will function properly for all crystal frequencies. option 1 requires fewer external components due to the high input capacita nce of the osci pin and results in a stable configuration. option 2 represen ts a classic approach with a higher level of stability. figure 5-4. oscillator options ssc050-01 30 pf osci osco vss 10mhz 390 ohm ssc050-01 30 pf osci osco vss 10mhz 390 ohm 10m ohm 30 pf vss option 1 option 2
5-9 electrical characteristics ssc050-01 ac characteristics data sheet revision 4.0 november 10, 2004 external reset circuit the ssc050-01 supports an internal power-on reset circuit that eliminates the need for an external reset source. however, the device does support a mechan ism that allows the use of an external reset for those applications where a system reset is availa ble and required. the following diagrams show the external connections required. the external reset s ource must be active high and does not need to be synchronous to the clock source of the ssc050-01. test0 and test2 must remain at a low level during the reset sequence. the minimum external reset pulse width is 50 nanoseconds. two-wire serial transactions to the ssc050-01 must not commence until a minimum of 500 nanoseconds after the deassertion of the external reset pulse. option 1 s hould be used when asel is normally held low (the device type identifier value is 1000b). option 2 shou ld be used when asel is normally held high (the device type identifier value is 1100b). figure 5-5. external reset circuit options ssc050-01 asel test1 option 1 active high system reset ssc050-01 asel test1 option 2 active high system reset vdd
5-10 electrical characteristics ssc050-01 ac characteristics data sheet revision 4.0 november 10, 2004 optional external tach filter the fan tach inputs of the ssc050-01 utilize schmi tt trigger input buffers and are also internally digitally filtered. however, excessive external noise on a tach input can result in inaccurate fan speed current count values. the use of an external low pass filter along with the use of the extended tach filter mode (tach filter extend, bit 6 of register fdh) of the ssc050-01 will eliminate in accurate current count values. the following circui t provides excellent noise rejec tion at all possible rpm ranges supported by the ssc050-01. figure 5-6. optional external tach filter ssc050-01 0.1 uf p2.4-p2.7 vss 330 ohm 3.3k ohm vdd fan tach output
6-1 mechanical drawing ssc050-01 data sheet revision 4.0 november 10, 2004 chapter 6 m echanical d rawing figure 6-1. mechanical drawing 2.80 0.20 0.18 0.80 1.95 0.40 1.00 15 432 64 12.00 14.00 17.90 23.90 20.00 18.00 3.40 max note: all dimensions are nominal unless otherwise specified
7-1 ordering information ssc050-01 data sheet revision 4.0 november 10, 2004 chapter 7 o rdering i nformation the ssc050-01 device is available in two package type s. l2a050-01 is a 64-pin plastic quad flat pack (pqfp). the device is also available in a lead(pb)-free p ackage, VSC050XKM-01. lead(pb)-free products from maxim co mply with the temperatures and profiles defined in the joint ipc and jedec standard ipc/jedec j-std-020. for more information, see the ipc and jedec standard. ssc050-01 two-wire serial backplane controller part number description l2a050-01 64-pin pqfp VSC050XKM-01 lead(pb)-free 64-pin pqfp

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