this document is intended as a spice modeling guideline and does not constitute a commercial product data sheet. designers sho uld refer to the appropriate data sheet of the same number for guaranteed specification limits. 1 www.visha y .com vishay siliconix spice device model SIA911ADJ document number: 64500 s-82729-rev. a, 17-nov-08 dual p-channel 20-v (d-s) mosfet characteristics ? p-channel vertical dmos ? macro model (subcircuit model) ? level 3 mos ? apply for both linear and switching application ? accurate over the - 55 c to 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics description the attached spice model descri bes the typical electrical characteristics of the p-channel vertical dmos. the subcircuit model is extracted and optimized over the - 55 c to 125 c temperature ranges under the pulsed 0 v to 5 v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capac itance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched c gd model. all model parameter values are optimized to provide a best fit to the me asured electrical data and are not intended as an exact physical in terpretation of the device. subcircuit model schematic
2 vishay siliconix spice device model SIA911ADJ www.visha y .com document number: 64500 s-82729-rev. a, 17-nov-08 specifications (t j = 25 c unless otherwise noted) parameter symbol test condition simulated data measured data unit static gate threshold voltage v gs(th) v ds = v gs , i d = - 250 a 0.83 v v gs = - 4.5 v, i d = - 2.8 a 0.097 0.096 drain-source on-state resistance a r ds(on) v gs = - 2.5 v, i d = - 2.3 a 0.126 0.126 forward transconductance a g fs v ds = - 10 v, i d = - 2.8 a 7 7 s diode forward voltage v sd i s = - 1 a - 0.79 - 0.80 v dynamic b input capacitance c iss 332 345 output capacitance c oss 75 65 reverse transfer capacitance c rss v ds = - 10 v, v gs = 0 v, f = 1 mhz 61 50 pf v ds = - 10 v, v gs = - 8 v, i d = - 3.5 a 7 8.4 total gate charge q g 4.2 4.9 gate-source charge q gs 0.75 0.75 gate-drain charge q gd v ds = - 10 v, v gs = - 4.5 v, i d = - 3.5 a 1.2 1.2 nc notes a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not subj ect to production testing.
3 vishay siliconix spice device model SIA911ADJ www.visha y .com document number: 64500 s-82729-rev. a, 17-nov-08 comparison of model with measured data (t j = 25 c unless otherwise noted)
4 vishay siliconix spice device model SIA911ADJ www.visha y .com document number: 64500 s-82729-rev. a, 17-nov-08 comparison of model with measured data (t j = 25 c unless otherwise noted)
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