ddr termination regulator tj2995 oct. 2009 - rev. 1.1 1/9 htc sop8 / sop8-pp pkg ordering information device (marking) package TJ2995D sop8 features z low output voltage offset z works with +5v, +3.3v, and 2.5v rails z source and sink current z low external component count z no external resistors required z linear topology z available in sop8, sop8-pp package z low cost and easy to use application z ddr-i and ddr-ii te rmin atio n voltage z sstl-2 and sstl-3 te rmin ation TJ2995Dp sop8-pp descripsion the tj2995 linear regulator is designed to meet the jedec sstl-2 and sstl-3 specifications for termination of ddr-sdram. the device contains a high-speed operational amplifier to provide excellent response to load transient. this device can deliver 1.5a continuous current and transient peaks up to 3a in the application as required for ddr-sdram termi nation. with an independent v sense pin, the tj2995 can provide superior load regulation. the tj2995 provides a v ref output as the reference for t he chipset and ddr dimms. the tj2995 can easily provide the accurate v tt and v ref voltages without external resistors that pcb areas can be reduced. the quiescent current is low to meet the low power consumption applications. absolute maximum ratings characteristic symbol min. max. unit supply voltage to gnd pv in av in v ddq -0.3 -0.3 -0.3 6.0 6.0 6.0 v lead temperature (soldering, 10 sec) t sol 260 storage temperature range t stg -65 150 operating junction temperature range t jopr -40 125 recommended operation range characteristic symbol min. max. unit av in to gnd av in 2.3 5.5 v pv in to gnd pv in 0 av in v ordering information package order no. description package marking supplied as sop8 TJ2995D ddr termination regulator tj2995 reel sop8-pp TJ2995Dp ddr termination regulator tj2995 reel
ddr termination regulator tj2995 oct. 2009 - rev. 1.1 2/9 htc pin configuration nc gnd vsense vref vtt pvin avin vddq 1 2 3 4 8 7 6 5 nc gnd vsense vref vtt pvin avin vddq 1 2 3 4 8 7 6 5 exposed thermal pad sop8 sop8-pp pin description pin no. pin name pin function 1 nc no internal connection 2 gnd ground 3 vsense feedback pin for regulating v tt 4 vref buffered internal reference voltage of v ddq /2 5 vddq input for internal reference equal to v ddq /2 6 avin analog input pin 7 pvin power input pin 8 vtt output voltage for connection to termination resistors exposed thermal pad exposed thermal connec tion. connect to ground. (sop8-pp only) typical application
ddr termination regulator tj2995 oct. 2009 - rev. 1.1 3/9 htc electrical characteristics (1) specifications with standard typeface are for t j = 25. unless otherwise specified, avin = pvin = 2.5v, vddq = 2.5v. (1), (4) parameter symbol test condit ion min. typ. max. unit v ref voltage v ref v ddq = 2.3v v ddq = 2.5v v ddq = 2.7v 1.11 1.21 1.31 1.15 1.25 1.35 1.19 1.29 1.39 v v tt output voltage v tt i out = 0 a v ddq = 2.3v v ddq = 2.5v v ddq = 2.7v i out = 1.5 a v ddq = 2.3v v ddq = 2.5v v ddq = 2.7v 1.11 1.21 1.31 1.11 1.21 1.31 1.15 1.25 1.35 1.15 1.25 1.35 1.19 1.29 1.39 1.19 1.29 1.39 v v tt output voltage offset (2) v osvtt i out = 0 a i out = +1.5 a i out = -1.5 a -40 -40 -40 0 0 0 40 40 40 mv quiescent current (3) i q i out = 0a - 250 2000 ua v ddq input impedance z vddq - 100 - k ? v sense input current i sense - 0.1 ua thermal shutdown (5) t sd - 165 - note 1. stresses listed as the absolute maximum ratings may c ause permanent damage to the device. these are for stress ratings. functional operating of the device at these or any other conditions beyond th ose indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rati ng conditions for extended periods may rema in possibly to affect device reliability. note 2: v tt offset is the voltage measurement defined as v tt subtracted from v ref . note 3: quiescent current defined as the current flow into avin. note 4: limits are 100% production tested at 25c. limits over the operating temperature range are guaranteed through correlati on. note 5. the maximum allowable power dissipation is a function of the maximum junction temperature, t j(max), the junction to ambient thermal resistance, ja , and the ambient temperature, t a . exceeding the maximum allowable power dissipation will cause excessive die temperature and the regulator will go into thermal shutdown.
ddr termination regulator tj2995 oct. 2009 - rev. 1.1 4/9 htc typical operating characteristics avin = 2.0v/div, vddq/pvin = 1.0v/div, vref = 500mv/div, vtt = 500mv/div, time = 10ms/div avin = 2.0v/div, vddq/pvin = 1.0v /div, vref = 500mv/div, vtt = 500mv/div, time = 10ms/div start up shut down avin = 2.0v/div, vddq/pvin = 2.0v/div, vtt = 100mv/div, iout = 1a/div, time = 10ms/div avin = 2.0v/div, vddq/pvin = 2.0v/div , vtt = 100mv/div, iout = 1a/div, time = 10ms/div load (0a 1a) load (1a 0a) av in vs. quiescent current v ddq = 2.5v
ddr termination regulator tj2995 oct. 2009 - rev. 1.1 5/9 htc description the tj2995 is a linear bus termination regulator designed to meet the jedec requirements of sstl-2 and sstl-3. the tj2995 is capable of sink ing and sourcing current at the output v tt , regulating the voltage to equal v ddq / 2. a buffered reference voltage that also tracks v ddq / 2 is generated on the v ref pin for providing a global reference to the ddr-sdram and northbridge chipset. v tt is designed to track the v ref voltage with a tight tolerance over the entir e current range while preventing shoot through on the output stage. series stub termination logic (sstl) was created to improve signal integrity of the data transmission across the memory bus. this termination scheme is es sential to prevent data error from signal reflections while transmitting at high frequencies encountered with ddr ram. the most common form of termination is class ii single parallel termination. this involves using one rs series resistor from the chipset to the memory and one rt termination resistor. this implementation can be seen below in figure 1. figure 1. sstl-termination scheme pin description av in and pv in av in and pv in are the input supply pins for the tj2995. av in is used to supply all the internal control circuitry for the two op-amps and the output stage of v ref . pv in is used exclusively to provide the rail voltage for the output stage on the power op erational amplifier used to create v tt . for sstl-2 applications av in and pv in pins should be connected directly and tied to the 2.5v rail for optimal performance. this eliminates the need for bypassing the two supply pins separately. v ddq v ddq is the input used to create the internal reference voltage for regulating v tt . the reference voltage is generated from a resistor divider of two internal 50 ? resistors. this guarantees that v tt will track v ddq / 2 precisely. the optimal implementation of v ddq is as a remote sense. this can be achieved by connecting v ddq directly to the 2.5v rail at the dimm instead of av in and pv in . this ensures that the reference voltage tracks the ddr memory rails precisely without a large voltage drop from the power lines. for sstl-2 applications v ddq will be a 2.5v signal, which will create a 1.25v termination voltage at v tt (see electrical characteristics table for exact values of v tt over temperature).
ddr termination regulator tj2995 oct. 2009 - rev. 1.1 6/9 htc v sense the purpose of the sense pin is to provide impr oved remote load regulation. in most motherboard applications the termination resistors will connect to v tt in a long plane. if the output voltage was regulated only at the output of the tj29 95, then the long trace will cause a significant ir drop, resulting in a termination voltage lower at one end of the bus than the other. the v sense pin can be used to improve this performance, by conn ecting it to the middle of the bus. this will provide a better distribution across the entire termination bus. if remote load regulation is not used, then the v sense pin must still be connected to v tt . v ref v ref provides the buffered output of the internal reference voltage v ddq / 2. this output should be used to provide the reference voltage for the northbridge chipset and memory. since these inputs are typically an extremely high impedance, there should be little current drawn from v ref . for improved performance, an output bypass capacitor can be used, located close to the pin, to help with noise. a ceramic capacitor in the range of 0.1 f to 0.01 f is recommended. this output remains active during the shutdown state and thermal shutdown events for the suspend to ram functionality. v tt v tt is the regulated output that is used to terminat e the bus resistors. it is capable of sinking and sourcing current while regulating the output precisely to v ddq / 2. the tj2995 is designed to handle peak transient currents of up to 3a with a fast tran sient response. if a transient is expected to last above the maximum continuous current rating for a signi ficant amount of time then the output capacitor should be sized large enough to prevent an excessive voltage drop. despite the fact that the tj2995 is designed to handle large transient output currents it is not capable of handling these for long durations, under all conditions. the reason for this is the stan dard packages are not able to thermally dissipate the heat as a result of the internal power loss. if lar ge currents are required for longer durations, then care should be taken to ensure that the maximum junction temperature is not exceeded. proper thermal derating should always be used (please refer to the thermal dissipation section). thermal dissipation since the tj2995 is a linear regulator any current flow from v tt will result in internal power dissipation generating heat. to prevent damaging the part from exceeding the maximum allowable junction temperature, care should be taken to derate th e part dependent on the maximum expected ambient temperature and power dissipation. the maximu m allowable internal temperature rise, t rmax can be calculated given the maximum ambient temperature, t amax of the application and the maximum allowable junction temperature, t jmax . t rmax = t jmax ? t amax from this equation, the maximum allowable power dissipation , p dmax of the part can be calculated: p dmax = t rmax / ja
ddr termination regulator tj2995 oct. 2009 - rev. 1.1 7/9 htc the maximum allowable value for junction-to-ambient thermal resistance, ja , can be calculated using the formula: ja = t rmax / p d = (t jmax ? t amax ) / p d the ja of the tj2995 will be dependent on several variables: the package used; the thickness of copper; the number of vias and the airflow. for instance, the ja of the sop8 is 165c/w with the package mounted to a standard 8x4 2-layer board with 1oz. copper, no airflow, and 0.5w dissipation at room temperature. this value can be reduced to 152c/w by changing to a 3x4 board with 2 oz. copper that is the jedec standard. additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an internal ground plane. using larger traces and more copper on the top side of the board can also help. with careful layout it is possible to reduce the ja further than the nominal values. additional improvements in lowering the ja can also be achieved with a constant airflow across the package. optimizing the ja and placing the tj 2995 in a section of a board exposed to lower ambient temperature allows the part to operate with higher power dissipation. the internal power dissipation can be calculated by summing the three main sources of loss: output current at v tt , either sinking or sourcing, and quiescent current at av in and v ddq . during the active state (when shutdown is not held low) the total internal power dissipation can be calculated from the following equations: p d = p avin + p vddq + p vtt where, p avin = i avin x v avin p vddq = v vddq x i vddq = v vddq2 x r vddq to calculate the maximum power dissipation at v tt both conditions at v tt need to be examined, sinking and sourcing current. although only one equation will add into the total, v tt cannot source and sink current simultaneously. p vtt = v vtt x i load (sinking) or p vtt = ( v pvin - v vtt ) x i load (sourcing) the power dissipation of the tj2995 can also be calculated during the shutdown state. during this condition the output v tt will tri-state, therefore that term in the power equation will disappear as it cannot sink or source any current (leakage is negligible). the only losses during shutdown will be the reduced quiescent current at av in and the constant impedance that is seen at the v ddq pin. p d = p avin + p vddq , where, p avin = i avin x v avin p vddq = v vddq x i vddq = v vddq2 x r vddq
ddr termination regulator tj2995 oct. 2009 - rev. 1.1 8/9 htc typical application information the typical application circuit used for sstl-2 te rmination schemes with ddr-sdram can be seen in figure 2. figure 2. sstl-2 implementation for sstl-3 and other applications, it may be desirabl e to change internal reference voltage scaling from the v ddq / 2. an external resistor in series with the v ddq pin can be used to lower the reference voltage. internally two 50 k ? resistors set the output v tt to be equal to v ddq / 2. the addition of a 11.1 k ? external resistor will change the internal refe rence voltage causing the two outputs to track v ddq * 0.45. an implementation of this circuit can be seen in figure 3. figure 3. sstl-3 implementation another application that is sometime s required is to increase the v tt output voltage from the scaling factor of v ddq * 0.5. this can be accomplished independently of v ref by using a resistor divider network between v tt , v sense and ground. an example of this circuit can be seen in figure 4. figure 4. increased vtt from the scaling factor
ddr termination regulator tj2995 oct. 2009 - rev. 1.1 9/9 htc pcb layout considerations 1. av in and pv in should be tied together for optimal performance. a local bypass capacitor should be placed as close as possible to the pv in pin. 2. gnd should be connected to a ground plane with multiple vias for improved thermal performance. 3. v sense should be connected to the v tt termination bus at the point w here regulation is required. for motherboard applications an ideal location w ould be at the center of the termination bus. 4. v ddq can be connected remotely to the v ddq rail input at either the dimm or the chipset. this provides the most accurate point for creating the reference voltage. 5. v ref should be bypassed with a 0.01 f or 0.1 f ceramic capacitor for improved performance. this capacitor should be located as close as possible to the v ref pin.
|
