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| w78le365/w78l365a data sheet 8-bit microcontroller publication release date: january 10, 2007 - 1 - revision a7 table of contents- 1. general des cription ......................................................................................................... 3 2. features ....................................................................................................................... .......... 3 3. pin configura tions ............................................................................................................ 4 4. pin descri ption................................................................................................................ ..... 5 5. functional des cription ................................................................................................... 6 5.1 ram ............................................................................................................................ .... 6 5.2 timers 0, 1 and 2 ............................................................................................................ 7 5.2.1 timer 2 out put ................................................................................................................. 7 5.3 clock .......................................................................................................................... ..... 7 5.3.1 crystal o scillato r ............................................................................................................. .7 5.3.2 external clo ck ................................................................................................................. .7 5.4 power m anagement ........................................................................................................ 8 5.4.1 idle mode...................................................................................................................... ....8 5.4.2 power-down mode ............................................................................................................8 5.4.3 reduce emi em ission ......................................................................................................8 5.5 reset.......................................................................................................................... ..... 9 5.5.1 w78l365a special function register s (sfrs) and re set val ues...................................9 5.6 port 4 ......................................................................................................................... ... 10 5.6.1 port options regist er ..................................................................................................... 10 5.6.2 int2 / int3 ..................................................................................................................10 5.6.3 port 4 base addr ess regist ers ......................................................................................13 5.7 pulse width modulated outputs (p wm)....................................................................... 14 5.8 watchdog ti mer ........................................................................................................... 17 5.9 in-system programmi ng (isp) mode............................................................................ 19 5.9.1 in-system programming contro l register (chpco n) ...................................................20 5.10 software re set ............................................................................................................. 21 5.11 h/w reboot mode (boot from l drom) ....................................................................... 21 6. securi ty ....................................................................................................................... ......... 24 6.1 lock bit ....................................................................................................................... .. 24 6.2 movc inhi bit................................................................................................................. 24 6.3 encryption ..................................................................................................................... 25 6.4 oscillator c ontrol .......................................................................................................... 25 7. electrical chara cteristi cs......................................................................................... 26
w78le365/w78l365a - 2 - 7.1 absolute maxi mum rati ngs .......................................................................................... 26 7.2 d.c. characte ristic s...................................................................................................... 26 7.3 a.c. characte ristic s ...................................................................................................... 28 8. timing w aveforms ............................................................................................................. 29 8.1 program fetc h cycle .................................................................................................... 29 8.2 data read cycle ........................................................................................................... 30 8.3 data write cycle........................................................................................................... 31 8.4 port access cycle......................................................................................................... 32 9. typical applicat ion circui t........................................................................................... 33 9.1 external program me mory and cr ystal ........................................................................ 33 9.2 expanded external data me mory and osc illator ......................................................... 34 10. package dime nsions ......................................................................................................... 35 10.1 40-pin dip ..................................................................................................................... 35 10.2 44-pin pl cc ................................................................................................................. 35 10.3 44-pin pq fp ................................................................................................................. 36 10.4 48-pin lq fp.................................................................................................................. 36 11. applicatio n no te ............................................................................................................... 37 11.1 in-system programming software ex amples ............................................................... 37 12. revision history ............................................................................................................... .42 w78le365/w78l365a publication release date: january 10, 2007 - 3 - revision a7 1. general description the w78l365a is an 8-bit microcontroller which has an in-system programmable flash eprom for firmware updating. the instruction set of the w 78l365a is fully compatible with the standard 8052. the w78l365a contains a 64k bytes of main rom and a 4k bytes of auxiliary rom which allows the contents of the 64kb main rom to be updated by t he loader program located at the 4kb auxiliary rom; 256+1k bytes of on-chip ram; four 8-bi t bi-directional and bit-addressable i/o ports; an additional 4-bit port p4; three 16-bit timer/counters; a serial port. these peripherals are supported by a eight sources two-level interrupt capability. to fa cilitate programming and verification, the rom inside the w78l365a allows the program memory to be programmed and read electronically. once the code is confirmed, the user can protect the code for security. the w78l365a microcontroller has two power r eduction modes, idle mode and power-down mode, both of which are software selectable. the idle m ode turns off the processor clock but allows for continued peripheral operation. the power-down mode stops the crystal oscillator for minimum power consumption. the external clo ck can be stopped at any time and in any state without affecting the processor. 2. features ? fully static design 8-bit cmos microcontroller ? 64k bytes of in-system programmable flas h eprom for application program (aprom) ? 4k bytes of auxiliary rom for loader program (ldrom) ? 256+1k bytes of on-chip ram. (including 1k bytes of aux-ram, software selectable) ? four 8-bit bi-directional ports ? one 4-bit multipurpose programmable port (i/o, interrupt, chip select function) ? three 16-bit timer/counters ? one full duplex serial port ? watchdog timer ? software reset ? p1.0 t2 programmable clock out ? eight-sources, two-level interrupt capability ? up to 20 mhz ? built-in power management ? code protection ? packaged in ? lead free (rohs) dip 40: w78l365a24dl ? lead free (rohs) plcc 44: w78l365a24pl ? lead free (rohs) qfp 44: w78l365a24fl ? lead free (rohs) lqfp 48: w78l365a24ll w78le365/w78l365a - 4 - 3. pin configurations 40-pin dip vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 39 40 34 35 36 37 38 30 31 32 33 26 27 28 29 21 22 23 24 25 p0.0, ad0 p0.1, ad1 p0.2, ad2 p0.3, ad3 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.5, a13 p2.6, a14 p2.7, a15 p2.0, a8 p2.1, a9 p2.2, a10 p2.3, a11 p2.4, a12 t2, p1.0 p1.2 p1.3 p1.4 p1.5 p1.6 rxd, p3.0 txd, p3.1 p1.7 rst int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 wr, p3.6 rd, p3.7 xtal1 xtal2 vss t2ex, p1.1 44-pin plcc 40 2 1 44 43 42 41 6543 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 10 9 8 7 14 13 12 11 16 15 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 a d 3 , p 0 . 3 t 2 , p 1 . 0 p 1 . 2 v d d a d 2 , p 0 . 2 a d 1 , p 0 . 1 a d 0 , p 0 . 0 t 2 e x , p 1 . 1 p 1 . 3 p 1 . 4 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 p4.1 p 4 . 0 int2, p4.3 / i n t 3 , p 4 . 2 44-pin pqfp 34 40 39 38 37 36 35 44 43 42 41 33 32 31 30 29 28 27 26 25 24 23 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 22 21 20 19 18 17 16 15 14 13 12 11 4 3 2 1 8 7 6 5 10 9 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r a d 3 , p 0 . 3 t 2 , p 1 . 0 p 1 . 2 v d d a d 2 , p 0 . 2 a d 1 , p 0 . 1 a d 0 , p 0 . 0 t 2 e x , p 1 . 1 p 1 . 3 p 1 . 4 p 4 . 0 / i n t 3 , p 4 . 2 p4.1 int2, p4.3 48-pin lqfp 2 1 4 3 6 5 8 7 10 9 11 32 33 30 31 28 29 26 27 25 p0.7 p2.7 p2.6 p2.5 p3.3 p3.4 p3.5 p3.1 p3.2 12 34 35 36 ea ale psen nc p1.7 p4.1 p4.3 p3.0 rst p1.6 p1.5 nc p0.4 p0.6 p0.5 w78le365/w78l365a publication release date: january 10, 2007 - 5 - revision a7 4. pin description symbol type descriptions e a i external access enable: this pin forces the processor to execute the external rom. the rom address and dat a will not be presented on the bus if the e a pin is high. psen o h program store enable: psen enables the external rom data in the port 0 address/data bus. when internal rom access is performed, no psen strobe signal outputs originate from this pin. ale o h address latch enable: ale is used to enable the address latch that separates the address from the data on po rt 0. ale runs at 1/6th of the oscillator frequency. rst i l reset: a high on this pin for two mach ine cycles while the oscillator is running resets the device. xtal1 i crystal 1: this is the crystal oscilla tor input. this pin may be driven by an external clock. xtal2 o crystal 2: this is the crystal osc illator output. it is the inversion of xtal1. v ss i ground: ground potential. v dd i power supply: supply voltage for operation. p0.0 ? p0.7 i/o d port 0: function is the same as that of standard 8052. p1.0 ? p1.7 i/o h port 1: function is the same as that of standard 8052. p2.0 ? p2.7 i/o h port 2: port 2 is a bi-directional i/o por t with internal pull-ups. this port also provides the upper address bits for accesses to external memory. the p2.6 and p2.7 also provide the alternate function reboot which is h/w reboot from ld flash. p3.0 ? p3.7 i/o h port 3: function is the same as that of the standard 8052. p4.0 ? p4.7 i/o h port 4: a bi-directional i/o. the p4.3 also provide the alternate function reboot which is h/w reboot from ld flash. * note: type i: input, o: output, i/o: bi-directional, h: pull-high, l: pull-low, d: open drain w78le365/w78l365a - 6 - 5. functional description the w78l365a architecture consists of a core cont roller surrounded by various registers, four general purpose i/o ports, one special purpos e programmable 4-bits i/o port, 256+1k bytes of ram, three timer/counters, a serial port. the processor suppor ts 111 different opcodes and references both a 64k program address space and a 64k data storage space. 5.1 ram the internal data ram in the w78l365a is 256+1k by tes. it is divided into two banks: 256 bytes of scratchpad ram and 1k bytes of aux-ram. thes e rams are addressed by different ways. ? ram 0h ? 7fh can be addressed directly and indirectly as the same as in 8051. address pointers are r0 and r1 of the selected register bank. ? ram 80h ? ffh can only be addressed indirectly as t he same as in 8051. address pointers are r0, r1 of the selected registers bank. ? aux-ram 0h ? 3ffh is addressed indirectly as the sa me way to access external data memory with the movx instruction. address pointer ar e r0 and r1 of the selected register bank and dptr register. an access to external data me mory locations higher than 3ffh will be performed with the movx instruction in the same way as in the 8051. the aux-ram is enable after a reset. setting the bit 4 in chpcon register will enable the access to aux-ram. when executing from internal program memory, an access to au x-ram will not affect the ports p0, p2, wr and rd . example: chpenr reg f6h chpcon reg bfh xramah reg a1h mov chpenr , #87h mov chpenr, #59h orl chpcon, #00010000b ; enable aux-ram mov chpenr, #00h mov xramah, #01h ; internal high address mov r0, #23h mov a, #55h movx @r0, a ; write 55h data to 0123h aux-ram address. mov xramah, #02h mov r1, #ffh ; read data from 02ffh aux-ram address. movx a, @r1 mov dptr, #0134h mov a, #78h movx @dptr,a ; write 78h data to 0134h aux-ram address. mov dptr, #7fffh movx a, @dprt ; read data from the external 7fffh address sram w78le365/w78l365a publication release date: january 10, 2007 - 7 - revision a7 5.2 timers 0, 1 and 2 timers 0, 1, and 2 each consist of two 8-bit data r egisters. these are called tl0 and th0 for timer 0, tl1 and th1 for timer 1, and tl2 and th2 for time r 2. the tcon and tmod registers provide control functions for timers 0, 1. the t2con regist er provides control functions for timer 2. rcap2h and rcap2l are used as reload/capture registers for timer 2. the operations of timer 0 and timer 1 are the same as in the w78c51. timer 2 is a 16-bi t timer/counter that is configured and controlled by the t2con register. like timers 0 and 1, timer 2 c an operate as either an external event counter or as an internal timer, depending on the setting of bi t c/t2 in t2con. timer 2 has three operating modes: capture, auto-reload, and baud rate generator . the clock speed at capture or auto-reload mode is the same as that of timers 0 and 1. 5.2.1 timer 2 output if set t2oe (t2mod.1) bit and clear c/t2 (t2con .1) bit at auto-reload mode, p1.0 will be toggled once overflow. timer 2 mode bit: 7 6 5 4 3 2 1 0 t2oe mnemonic: t2mod address: c9h t2oe: enable this bit to toggle p1.0 pin while timer2 has been overflowed. 5.3 clock the w78l365a is designed with either a crystal oscillato r or an external clock. internally, the clock is divided by two before it is used by default. this makes the w78l365a relatively insensitive to duty cycle variations in the clock. 5.3.1 crystal oscillator the w78l365a incorporates a built-in crystal oscillator. to make the oscillator work, a crystal must be connected across pins xtal1 and xtal2. in addition, a load capacitor must be connected from each pin to ground. 5.3.2 external clock an external clock should be connected to pin xtal1. pin xtal2 should be left unconnected. the xtal1 input is a cmos-type input, as required by the crystal oscillator. w78le365/w78l365a - 8 - 5.4 power management 5.4.1 idle mode setting the idl bit in the pcon register enters the id le mode. in the idle mode, the internal clock to the processor is stopped. the peripherals and the interrupt logic continue to be clocked. the processor will exit idle mode when either an interrupt or a reset occurs. 5.4.2 power-down mode when the pd bit in the pcon register is set, t he processor enters the power-down mode. in this mode all of the clocks are stopped, including the osc illator. to exit from power-down mode is by a hardware reset or external interrupts int0 to int1 when enabled and set to level triggered. 5.4.3 reduce emi emission the w78l365a allows user to diminish the gain of on- chip oscillator amplifier by using programmer to clear the b7 bit of security register. once b7 is set to 0, a half of gain will be decreased. care must be taken if user attempts to diminish the gain of osc illator amplifier, reducing a half of gain may affect the external crystal operating improperly at high frequency. the value of c1 and c2 may need some adjustment while running at lower gain. ale off function auxiliary register bit: 7 6 5 4 3 2 1 0 - - - - - - - aleoff mnemonic: auxr address: 8eh aleoff : set this bit to disable ale output. w78le365/w78l365a publication release date: january 10, 2007 - 9 - revision a7 5.5 reset the external reset signal is sampled at s5p2. to take effect, it must be held high for at least two machine cycles while the oscillator is running. an in ternal trigger circuit in the reset line is used to deglitch the reset line when the w78l365a is used with an external rc network. the reset logic also has a special glitch removal circuit that ignores g litches on the reset line. during reset, the ports are initialized to ffh, the stack pointer to 07h, pcon (w ith the exception of bit 4) to 00h, and all of the other sfr registers except sbu f to 00h. sbuf is not reset. 5.5.1 w78l365a special function regi sters (sfrs) and reset values f8 f0 +b 00000000 chpenr 00000000 e8 e0 +acc 00000000 d8 +p4 11111111 pwmp 00000000 pwm0 00000000 pwm1 00000000 pwmcon1 00000000 pwm2 00000000 pwm3 00000000 d0 +psw 00000000 c8 +t2con 00000000 t2mod 00000000 rcap2l 00000000 rcap2h 00000000 tl2 00000000 th2 00000000 pwmcon2 00000000 pwm4 00000000 c0 +xicon 00000000 p4cona 00000000 p4conb 00000000 sfral 00000000 sfrah 00000000 sfrfd 00000000 sfrcn 00000000 b8 +ip 00000000 chpcon 0xx00000 b0 +p3 00000000 p43al 00000000 p43ah 00000000 a8 +ie 00000000 p42al 00000000 p42ah 00000000 p4csin 00000000 a0 +p2 11111111 xramah 00000000 98 +scon 00000000 sbuf xxxxxxxx 90 +p1 11111111 p41al 00000000 p41ah 00000000 88 +tcon 00000000 tmod 00000000 tl0 00000000 tl1 00000000 th0 00000000 th1 00000000 auxr 00000000 wdtc 00000000 80 +p0 11111111 sp 00000111 dpl 00000000 dph 00000000 p40al 00000000 p40ah 00000000 por 00000000 pcon 00110000 notes: 1. the sfrs marked with a plus si gn(+) are both byte- and bit-addressable. 2. the text of sfr with bold type char acters are extension function registers. w78le365/w78l365a - 10 - 5.6 port 4 port 4, address d8h, is a 8-bit multipurpose programmable i/o port. each bit can be configured individually by software. the port 4 has four different operation modes. mode 0: p4.0 ? p4.3 is a bi-directional i/o port which is sa me as port 1. p4.2 and p4.3 also serve as external interrupt psen and int2 if enabled. mode 1: p4.0 ? p4.3 are read strobe signals that are synchronized with rd signal at specified addresses. these signals can be used as chip-s elect signals for external peripherals. mode 2: p4.0 ? p4.3 are write strobe signals that are synchronized with wr signal at specified addresses. these signals can be used as chip -select signals for external peripherals. mode 3: p4.0 ? p4.3 are read/write strobe signal s that are synchronized with rd or wr signal at specified addresses. these signals can be us ed as chip-select signals for external peripherals. when port 4 is configured with the feature of ch ip-select signals, the chip-select signal address range depends on the contents of the sfr p4xah, p4xa l, p4cona and p4conb. the registers p4xah and p4xal contain the 16-bit base address of p4.x. the registers p4cona and p4conb contain the control bits to configure the port 4 operation mode. the high nibble of port4(p4.4 to p4.7) can be select ed to serve to the direct led display drive outputs by setting the hdx bit is set, the corresponding pin p4.x can sink about 20 ma current for driving led display directly. 5.6.1 port options register bit: 7 6 5 4 3 2 1 0 - - - hd47 hd46 hd45 hd44 p0up mnemonic: por address: 86h hd47-44: enable pins p4.4 to p4.7 individually with high drive outputs. p0up: enable port 0 weak up. the pins of port 0 can be configured with either the open drain or standart port with internal pull-up. by the default, port 0 is an open drain bi-directional i/o port. when the p0up bit in the por register is set, the pins of port 0 will perform a bi-directional i/o port with internal pull-up that is structurally the same port2. 5.6.2 int2 / int3 two additional external interrupts, int2 and int3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80c52. the functions/status of these interrupts are determined/shown by the bits in the xicon (external interrupt control) register. the xicon register is bit-addressable but is not a standard register in the standard 80c52. its address is at 0c0h. to set/clear bits in the xicon register, one can use the "setb ( clr ) bit" instruction. for example, "setb 0c2h" sets the ex2 bit of xicon. w78le365/w78l365a publication release date: january 10, 2007 - 11 - revision a7 xicon - external interrupt control (c0h) px3 ex3 ie3 it3 px2 ex2 ie2 it2 px3: external interrupt 3 priority high if set ex3: external interrupt 3 enable if set ie3: if it3 = 1, ie3 is set/cleared automatically by hardware when interrupt is detected/serviced it3: external interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software px2: external interrupt 2 priority high if set ex2: external interrupt 2 enable if set ie2: if it2 = 1, ie2 is set/cleared automatically by hardware when interrupt is detected/serviced it2: external interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software eight-source interrupt information: interrupt source vector address polling sequence within priority level enable required settings interrupt type edge/level external interrupt 0 03h 0 (highest) ie.0 tcon.0 timer/counter 0 0bh 1 ie.1 - external interrupt 1 13h 2 ie.2 tcon.2 timer/counter 1 1bh 3 ie.3 - serial port 23h 4 ie.4 - timer/counter 2 2bh 5 ie.5 - external interrupt 2 33h 6 xicon.2 xicon.0 external interrupt 3 3bh 7 (lowest) xicon.6 xicon.3 p4conb (c3h) bit name function 7, 6 p43fun1 p43fun0 00: mode 0. p4.3 is a general purpose i/o port which is the same as port1. 01: mode 1. p4.3 is a read strobe signal for chip select purpose. the address range depends on the sfr p43ah, p43al, p43cmp1 and p43cmp0. 10: mode 2. p4.3 is a write strobe signal for chip select purpose. the address range depends on the sfr p43ah, p43al, p43cmp1 and p43cmp0. 11: mode 3. p4.3 is a read/write strobe signal for chip select purpose. the address range depends on the sfr p 43ah, p43al, p43cmp1, and p43cmp0. w78le365/w78l365a - 12 - p4conb (c3h), continued bit name function 5, 4 p43cmp1 p43cmp0 chip-select signals address comparison: 00: compare the full address (16 bits l ength) with the base address register p43ah, p43al. 01: compare the 15 high bits (a15 ? a1) of address bus with the base address register p43ah, p43al. 10: compare the 14 high bits (a15 ? a2) of address bus with the base address register p43ah, p43al. 11: compare the 8 high bits (a15 ? a 8) of address bus with the base address register p43ah, p43al. 3, 2 p42fun1 p42fun0 the p4.2 function control bits which are the similar definition as p43fun1, p43fun0. 1, 0 p42cmp1 p42cmp0 the p4.2 address comparator length contro l bits which are the similar definition as p43cmp1, p43cmp0. p4cona (c2h) bit name function 7, 6 p41fun1 p41fun0 the p4.1 function control bits which are the similar definition as p43fun1, p43fun0. 5, 4 p41cmp1 p41cmp0 the p4.1 address comparator length contro l bits which are the similar definition as p43cmp1, p43cmp0. 3, 2 p40fun1 p40fun0 the p4.0 function control bits which are the similar definition as p43fun1, p43fun0. 1, 0 p40cmp1 p40cmp0 the p4.0 address comparator length contro l bits which are the similar definition as p43cmp1, p43cmp0. p4csin (aeh) bit name function 7 p43csinv the active polarity of p4.3 when pin p4.3 is defined as read and/or write strobe signal. = 1: p4.3 is active high when pin p4.3 is defined as read and/or write strobe signal. = 0: p4.3 is active low when pin p4.3 is defined as read and/or write strobe signal. 6 p42csinv the similarity definition as p43sinv. 5 p41csinv the similarity definition as p43sinv. 4 p40csinv the similarity definition as p43sinv. 3 - reserve 2 - reserve 1 - 0 0 - 0 w78le365/w78l365a publication release date: january 10, 2007 - 13 - revision a7 5.6.3 port 4 base address registers p40ah, p40al: the base address register for comparator of p4.0 . p40ah contains the high- order byte of address, p40al contains the low-order byte of address. p41ah, p41al: the base address register for comparator of p4.1 . p41ah contains the high- order byte of address, p41al contains the low-order byte of address. p42ah, p42al: the base address register for comparator of p4.2 . p42ah contains the high- order byte of address, p42al contains the low-order byte of address. p43ah, p43al: the base address register for comparator of p4.3 . p43ah contains the high- order byte of address, p43al contains the low-order byte of address. p4 (d8h) bit name function 7 p47 i/o pin 6 p46 i/o pin. 5 p45 i/o pin. 4 p44 i/o pin. 3 p43 port 4 data bit which outputs to pin p4.3 at mode 0. 2 p42 port 4 data bit. which outputs to pin p4.2 at mode 0. 1 p41 port 4 data bit. which outputs to pin p4.1at mode 0. 0 p40 port 4 data bit which outputs to pin p4.0 at mode 0. here is an example to program the p4.0 as a write strobe signal at the i/o port address 1234h ? 1237h and positive polarity, and p4.1 ? p4.3 are used as general i/o ports. p4.4 ? p4.7 is only available for 48 pin package. mov p40ah, #12h mov p40al, #34h ; base i/o address 1234h for p4.0 mov p4cona, #00001010b ; p4.0 a write strobe signal and address line a0 and a1 are masked. mov p4conb, #00h ; p4.1 ? p4.3 as general i/o port which are the same as port1 mov p2econ, #10h ; write the p40sinv = 1 to inverse the p4.0 write strobe polarity ; default is negative. then any instruction movx @dptr, a (with dptr = 1234h ? 1237h) will generate the positive polarity write strobe signal at pin p4 .0. and the instruction mov p4, #xx will output the bit3 to bit1 of data #xx to pin p4.3 ? p4.1. w78le365/w78l365a - 14 - address bus bit length selectable comparator register p4xal p4xah equal p4.x mux 4->1 p4 register p4.x read write data i/o rd_cs wr_cs rd/wr_cs p4xcmp0 p4xcmp1 p4xfun0 p4xfun1 p4xcsinv p4.x input data bus register pin 5.7 pulse width modulated outputs (pwm) there are five pulse width modulated output c hannels to generate pulses of programmable length and interval. the repetition frequency is defined by an 8- bit prescaler pwmp, which supplies the clock for the counter. the prescaler and counter are common to both pwm channels. the 8-bit counter counts modular 255 (0 ? 254). the value of the 8-bit counter compar ed to the contents of five registers: pwm0, pwm1, pwm2, pwm3 and pwm4. provided the contents of either these registers is greater than the counter value, the corresponding pwm0, pwm1, pwm2, pwm3 or pwm4 output is set high. if the contents of these regi sters are equal to, or less than the counter value, the output will be low. the pulse-width-ratio is defined by the cont ents of the registers pwm0, pwm1, pwm2, pwm3 and pwm4. the pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments of 1/255. enpwm0, enpwm1, enpw m2, enpwm3 and enpwm4 bit will enable or disable pwm output. buffered pwm outputs may be used to drive dc moto rs. the rotation speed of the motor would be proportional to the contents of pw m0/1/2/3/4. the repetition frequency pwm f , at the pwm0/1/2/3/4 output is given by: 255 ) 1 ( 2 + = pwmp f f osc pwm prescaler division factor = pwm + 1 pwmn high/low ratio of (pwmn) - 255 pwmn) ( pwmn = w78le365/w78l365a publication release date: january 10, 2007 - 15 - revision a7 this gives a repetition frequency range of 123 hz to 31.4 khz ( osc f = 16 mhz). by loading the pwm registers with either 00h or ffh, the pwm channel s will output a constant high or low level, respectively. since the 8-bit counter counts modulo 255, it can never actually reach the value of the pwm registers when they are loaded with ffh. when a compare register (pwm0, pwm1, pwm2, pwm3, pwm4) is loaded with a new value, the associated output updated immediately. it does not hav e to wait until the end of the current counter period. there is weakly pulled high on pwm output. f 1/2 osc prescaler pwmp 8bit counter pwm0 comparator pwm1 comparator pwm1 pwm1oe pwm0oe pwm0 (p1.3) (p1.4) 8bit counter pwm2 comparator pwm3 comparator pwm3 pwm3oe pwm2oe pwm2 (p1.5) (p1.6) enpwm0/1/2/3/4 8bit counter pwm4 comparator pwm4 pwm4oe (p1.7) figure 1 pwm diagram please refer as below code. mov pwmcon1, #00110011b ; enable pwm3, 2, 1, 0 mov pwmcon2, #00000101b ; enable pwm4 mov pwmp, #40h ; fpwm = xt/(2*(1+pwmp)*255) jb p1.3, $ mov pwm0, #14h ; duty cycle high/low = pwm0/(255-pmw0) jb p1.4, $ mov pwm1, #18h w78le365/w78l365a - 16 - jb p1.5, $ mov pwm2, #20h jb p1.6, $ mov pwm3, #b0h jb p1.7, $ mov pwm4, #40h mov pwmcon1, #11111111b ; output enable pwm3, 2, 1, 0 pwm3 register bit: 7 6 5 4 3 2 1 0 mnemonic: pwm3 address: deh pwm2 register bit: 7 6 5 4 3 2 1 0 mnemonic: pwm2 address: ddh pwm control 1 register bit: 7 6 5 4 3 2 1 0 pwm3oe pwm2oe enpwm3 enpwm2 pwm1oe pwm0oe enpwm1 enwpm0 mnemonic: pwmcon1 address: dch pwm3oe: output enable for pwm3 pwm2oe: output enable for pwm2 enpwm3: enable pwm3 enpwm2: enable pwm2 pwm1oe: output enable for pwm1 pwm0oe: output enable for pwm0 enpwm1: enable pwm1 enpwm0: enable pwm0 pwm1 register bit: 7 6 5 4 3 2 1 0 mnemonic: pwm1 address: dbh w78le365/w78l365a publication release date: january 10, 2007 - 17 - revision a7 pwm0 register bit: 7 6 5 4 3 2 1 0 mnemonic: pwm0 address: dah pwmp register bit: 7 6 5 4 3 2 1 0 mnemonic: pwmp address: d9h pwm4 register bit: 7 6 5 4 3 2 1 0 mnemonic: pwm4 address: cfh pwm control 2 register bit: 7 6 5 4 3 2 1 0 - - - - - pwm4oe - enwpm4 mnemonic: pwmcon2 address: ceh pwm4oe: output enable for pwm4 enpwm: enable for pwm4 5.8 watchdog timer the watchdog timer is a free-running timer which c an be programmed by the user to serve as a system monitor, a time-base generator or an event timer. it is basically a set of dividers that divide the system clock. the divider output is selectable and determines the time -out interval. when the time-out occurs, a system reset can also be caused if it is enabled. the main use of the watchdog timer is as a system monitor. this is important in real-time control applications. in case of power glitches or electro- magnetic interference, the processor may begin to ex ecute errant code. if this is left unchecked the entire system may crash. the watchdog time-out sele ction will result in different time-out values depending on the clock speed. the watchdog timer will de disabled on reset. in general, software should restart the watchdog timer to put it into a known state. the contro l bits that support the watchdog timer are discussed below. watchdog timer control register bit: 7 6 5 4 3 2 1 0 enw clrw widl - - ps2 ps1 ps0 mnemonic: wdtc address: 8fh enw : enable watch-dog if set. clrw : clear watch-dog timer and prescaler if set. this flag will be cleared automatically widl : if this bit is set, watch-dog is enabled under idle mode. if cleared, watch-dog is disabled under idle mode. default is cleared. w78le365/w78l365a - 18 - ps2, ps1, ps0: watch-dog prescaler timer se lect. prescaler is selected when set ps2 ? 0 as follows: ps2 ps1 ps0 prescaler select 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 the time-out period is obtained using the following equation: 1 2 1000 12 14 osc prescaler ms before watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to wdtc.6 (clrw). after 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next instruction cycle. the watchdog timer is cleared on reset. osc 1/12 prescaler 14-bit timer clear clrw external reset internal reset widl idle enw watchdog timer block diagram typical watch-dog time-out period when osc = 20 mhz ps2 ps1 ps0 watchdog time-out period 0 0 0 19.66 ms 0 0 1 39.32 ms 0 1 0 78.64 ms 0 1 1 157.28 ms 1 0 0 314.57 ms 1 0 1 629.14 ms 1 1 0 1.25 s 1 1 1 2.50 s w78le365/w78l365a publication release date: january 10, 2007 - 19 - revision a7 5.9 in-system programming (isp) mode the w78l365a equips one 64k byte of main rom bank for application program (called aprom) and one 4k byte of auxiliary rom bank for loader program (called ldrom). in the normal operation, the microcontroller executes the code in the aprom. if the content of aprom needs to be modified, the w78l365a allows user to activate the in-sys tem programming (isp) mode by setting the chpcon register. the chpcon is read-only by default, software must write two specific values 87h, then 59h sequentially to the chpenr register to enable the chpcon write attribute. writing chpenr register with the values except 87h and 59h will close chpcon register write attribute. the w78l365a achieves all in-system progr amming operations including enter/exit isp mode, program, erase, read ... etc, during device in the idle mode. setting the bit chpcon.0 the device will enter in-system programming mode afte r a wake-up from idle mode. because device needs proper time to complete the isp operations before awaken from idle mode, software may use timer interrupt to control the duration for device wa ke-up from idle mode. to perform isp operation for revising contents of aprom, software located at apr om setting the chpcon register then enter idle mode, after awaken from idle mode the device execut es the corresponding interrupt service routine in ldrom. because the device will clear the program counter while switching from aprom to ldrom, the first execution of reti instruct ion in interrupt service routine will jump to 00h at ldrom area. the device offers a software reset for switching ba ck to aprom while the content of aprom has been updated completely. setting chpcon register bit 0, 1 and 7 to logic-1 will result a software reset to reset the cpu . the software reset serves as a external reset. this in-system programming feature makes the job easy and efficient in which the applic ation needs to update firmware frequently. in some applications, the in-system programming feature make it possible to easily update the system firmware without opening the chassis. sfrah, sfral: the objective address of on-chip rom in the in-system programming mode. sfrah contains the high-order byte of address, sfral contains the low-order byte of address. sfrfd: the programming data for on-chip rom in programming mode. sfrcn: the control byte of on-chip rom programming mode. sfrcn (c7) bit name function 7 - reserve. 6 wfwin on-chip rom bank select for in-system programming. = 0: 64k bytes rom bank is selected as destination for re-programming. = 1: 4k bytes rom bank is selected as destination for re-programming. 5 oen rom output enable. 4 cen rom chip enable. 3, 2, 1, 0 ctrl[3:0] the flash control signals w78le365/w78l365a - 20 - mode wfwin ctrl<3:0> oe n cen sfrah, sfral sfrfd erase 64kb aprom 0 0010 1 0 x x program 64kb aprom 0 0001 1 0 address in data in read 64kb aprom 0 0000 0 0 address in data out erase 4kb ldrom 1 0010 1 0 x x program 4kb ldrom 1 0001 1 0 address in data in read 4kb ldrom 1 0000 0 0 address in data out 5.9.1 in-system programming control register (chpcon) chpcon (bfh) bit name function 7 swreset when this bit is set to 1, and both fbootsl and fprogen are set to 1. it will enforce microcontroller reset to in itial condition just like power on reset. 6 - reserve. 5 ld/ap this bit is read only. 1: cpu is r unning ldrom program. 0: cpu is running aprom program. 4 enauxram 1: enable on-chip aux-ram. 0: disable the on-chip aux-ram 3 1 must be 1 2 - reserve. 1 fbootsl when this bit is set to 1, and both swreset and fprogen are set to 1. it will enforce microcontroller reset to in itial condition just like power on reset. 0 fprogen when this bit is set to 1, and both swreset and fbootsl are set to 1. it will enforce microcontroller reset to in itial condition just like power on reset. this register is protected by chpenr register. please write as below procedures while you would like to write chpcon register. mov chpenr, #87h mov chpenr, #59h anl chpcon, #efh ;disable aux-ram mov chpenr, #0h w78le365/w78l365a publication release date: january 10, 2007 - 21 - revision a7 5.10 software reset set chpcon = 0x83, timer and enter idle mode. cpu will reset and restart from apflash after time out. 5.11 h/w reboot mode (boot from ldrom) by default, the w78l365a boots from aprom program after a power on reset. on some occasions, user can force the w78l365a to boot from the ldrom program via following settings . the possible situation that you need to enter h/w reboot mode when the aprom program can not run properly and device can not jump back to ldrom to execut e in-system programming function. then you can use this h/w reboot mode to force the w 78l365a jumps to ldrom and executes in-system programming procedure. when you design your system , you may reserve the pins p2.6, p2.7 to switches or jumpers. for example in a cd-rom system, you can connect the p2.6 and p2.7 to play and eject buttons on the panel. when the aprom progr am fails to execute the normal application program. user can press both two buttons at t he same time and then turn on the power of the personal computer to force the w78l365a to ent er the h/w reboot mode. after power on of personal computer, you can release both buttons and finish the in-system programming procedure to update the aprom code. in application system design, user mu st take care of the p2, p3, ale, ea and psen pin value at reset to prevent from acci dentally activating the programming mode or h/w reboot mode. it is necessary to add 10k re sistor on these p2.6, p2.7 and p4.3 pins. h/w reboot mode p4.3 p2.7 p2.6 mode x l l reboot l x x reboot p2.7 p2.6 rst 30 ms hi-z the reset timing for entering f04kboot mode 10 ms hi-z w78le365/w78l365a - 22 - start the algorithm of in-system programming enter in-system programming mode ? (conditions depend on user's application) setting control registers mov chpenr,#87h mov chpenr,#59h mov chpcon,#03h setting timer (about 1.5 us) and enable timer interrupt start timer and enter idle mode. (cpu will be wakened from idle mode by timer interrupt, then enter in-system programming mode) execute the normal application program no yes end cpu will be wakened by interrupt and re-boot from 4kb ldrom to execute the loader program. go part 1:32kb aprom procedure of entering in-system programming mode w78le365/w78l365a publication release date: january 10, 2007 - 23 - revision a7 part 2: 4kb ldrom procedure of updating the 32kb aprom go timer interrupt service routine: stop timer & disable interrupt is f04kboot mode? (chpcon.7=1) reset the chpcon register: mov chpenr,#87h mov chpenr,#59h mov chpcon,#03h no yes setting timer and enable timer interrupt for wake-up . (15 ms for erasing operation) setting erase operation mode: mov sfrcn,#22h (erase 32kb aprom) start timer and enter idle mode. (erasing...) end of erase operation. cpu will be wakened by timer interrupt. pgm pgm setting timer and enable timer interrupt for wake-up . (50us for program operation) end of programming ? get the parameters of new code (address and data bytes) through i/o ports, uart or other interfaces. is currently in the f04kboot mode ? setting control registers for programming: mov sfrah,#address_h mov sfral,#address_l mov sfrfd,#data mov sfrcn,#21h software reset cpu and re-boot from the 32kb aprom. mov chpenr,#87h mov chpenr,#59h mov chpcon,#83h end executing new code from address 00h in the 32kb aprom. hardware reset to re-boot from new 32 kb aprom. (s/w reset is invalid in f04kboot mode) yes no yes no w78le365/w78l365a - 24 - 6. security during the on-chip rom programming mode, the rom can be programmed and verified repeatedly. until the code inside the rom is confirmed ok, t he code can be protected. the protection of rom and those operations on it are described below. the w78l365a has a security register that can be accessed in programming mode. those bits of the security registers can not be changed once they have been programmed from high to low. they can only be reset through erase-all operation. the secu rity register is locat ed at the 0ffffh of the ldrom space. b0 b1 b0: lock bit, logic 0: active b1: movc inhibit, logic 0: the movc instruction in external memory cannot access the code in internal memory. logic 1: no restriction. default 1 for all security bits. s p ecial settin g re g ister security bits 4kb on-chip rom program memory reserved security register ffffh 0000h 0fffh reserved b2 b2: encryption logic 0: the encryption logic enable logic 1: the encryption logic disable reserved bits must be kept in logic 1. b7 b07: osillator control logic 0: 1/2 gain logic 1: full gain ldrom reserved 32kb on-chip rom program memory aprom 7fffh 6.1 lock bit this bit is used to protect the customer's pr ogram code in the w78l365a. it may be set after the programmer finishes the programming and verifies sequenc e. once this bit is set to logic 0, both the rom data and security register can not be accessed again. 6.2 movc inhibit this bit is used to restrict the accessible region of the movc instruction. it can prevent the movc instruction in external program memory from reading the internal program code. when this bit is set to logic 0, a movc instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. a mo vc instruction in internal program memory space will always be able to access the rom data in both inte rnal and external memory. if this bit is logic 1, there are no restrictions on the movc instruction. w78le365/w78l365a publication release date: january 10, 2007 - 25 - revision a7 6.3 encryption this bit is used to enable/disable the encryption logi c for code protection. once encryption feature is enabled, the data presented on port 0 will be encoded via enc ryption logic. only whole chip erase will reset this bit. 6.4 oscillator control w78l365a/e516 allow user to diminish the gain of on-ch ip oscillator amplifier by using programmer to set the bit b7 of security register. once b7 is se t to 0, a half of gain will be decreased. care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may improperly affect the external crystal operati on at high frequency above 20 mhz. the value of r and c1, c2 may need some adjustment while running at lower gain. w78le365/w78l365a - 26 - 7. electrical characteristics 7.1 absolute maximum ratings parameter symbol min. max. unit dc power supply v dd ? v ss -0.3 +6.0 v input voltage v in v ss -0.3 v dd +0.3 v operating temperature t a 0 70 c storage temperature t st -55 +150 c note: exposure to conditions beyond those listed under absolute maxi mum ratings may adversely affect the life and reliability of the device. 7.2 d.c. characteristics (v ss = 0v, t a = 25 c, unless otherwise specified.) specification symbol parameter min. max. unit test conditions 2.4 5.5 v without isp v dd operating voltage 2.7 5.5 v with isp - 20 ma no load v dd = 5.5v i dd operating current 2.5 ma no load v dd = 2.4v - 6 ma v dd = 5.5v, fosc = 20 mhz i idle idle current 1 ma v dd = 2.4v, fosc = 12 mhz - 10 a v dd = 5.5v, fosc = 20 mhz i pwdn power down current - 10 a v dd = 2.4v, fosc = 12 mhz i in1 input current p1, p2, p3, p4 -50 +10 a v dd = 5.5v or 2.4v, v in = 0v or v dd -10 +150 a v dd = 5.5v, 0 w78le365/w78l365a - 28 - 7.3 a.c. characteristics the ac specifications are a function of the par ticular process used to manufacture the part, the ratings of the i/o buffers, the capacitive load, and the internal routing capacitance. most of the specifications can be expressed in term s of multiple input clock periods (t cp ), and actual parts will usually experience less than a 20 ns variation. clock input waveform t t xtal1 f ch cl op, t cp parameter symbol min. typ. max. unit notes operating speed f op 0 - 20 mhz 1 clock period tcp 41.7 - - ns 2 clock high t ch 20 - - ns 3 clock low t cl 20 - - ns 3 notes: 1. the clock may be stopped indefinitely in either state. 2. the t cp specification is used as a refe rence in other specifications. 3. there are no duty cycle requirements on the xtal1 input. w78le365/w78l365a publication release date: january 10, 2007 - 29 - revision a7 8. timing waveforms 8.1 program fetch cycle s1 xtal1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale port 2 a0-a7 a0-a7 data a0-a7 code t a0-a7 data code port 0 psen pdh, t pdz t pda t aah t aas t psw t apl t alw parameter symbol min. typ. max. unit notes address valid to ale low t aas 1 t cp - ? - - ns 4 address hold from ale low t aah 1 t cp - ? - - ns 1, 4 ale low to psen low t apl 1 t cp - ? - - ns 4 psen low to data valid t pda - - 2 t cp ns 2 data hold after psen high t pdh 0 - 1 t cp ns 3 data float after psen high t pdz 0 - 1 t cp ns ale pulse width t alw 2 t cp - ? 2 t cp - ns 4 psen pulse width t psw 3 t cp - ? 3 t cp - ns 4 notes: 1. p0.0 ? p0.7, p2.0 ? p2.7 remain stable throughout entire memory cycle. 2. memory access time is 3 t cp . 3. data have been latched internally prior to psen going high. 4. " ? " (due to buffer driving delay and wire loading) is 20 ns. w78le365/w78l365a - 30 - 8.2 data read cycle s2 s3 s5 s6 s1 s2 s3 s4 s5 s6 s1 s4 xtal1 ale psen data a8-a15 port 2 port 0 a0-a7 rd t ddh, t ddz t dda t drd t dar parameter symbol min. typ. max. unit notes ale low to rd low t dar 3 t cp - ? - 3 t cp+ ? ns 1, 2 rd low to data valid t dda - - 4 t cp ns 1 data hold from rd high t ddh 0 - 2 t cp ns data float from rd high t ddz 0 - 2 t cp ns rd pulse width t drd 6 t cp - ? 6 t cp - ns 2 notes: 1. data memory access time is 8 t cp . 2. " ? " (due to buffer driving delay and wire loading) is 20 ns. w78le365/w78l365a publication release date: january 10, 2007 - 31 - revision a7 8.3 data write cycle s2 s3 s5 s6 s1 s2 s3 s4 s1 s5 s6 s4 xtal1 ale psen a8-a15 data out port 2 port 0 a0-a7 wr t t daw dad t dwr t dwd parameter symbol min. typ. max. unit ale low to wr low t daw 3 t cp - ? - 3 t cp + ? ns data valid to wr low t dad 1 t cp - ? - - ns data hold from wr high t dwd 1 t cp - ? - - ns wr pulse width t dwr 6 t cp - ? 6 t cp - ns note: " ? " (due to buffer driving delay and wire loading) is 20 ns. w78le365/w78l365a - 32 - 8.4 port access cycle xtal1 ale s5 s6 s1 data out t t port input t sample pda pdh pds parameter symbol min. typ. max. unit port input setup to ale low t pds 1 tcp - - ns port input hold from ale low t pdh 0 - - ns port output to ale t pda 1 tcp - - ns note: ports are read during s5p2, and output data becomes available at the end of s6p2. the timing data are referenced to ale, since it provides a convenient reference. w78le365/w78l365a publication release date: january 10, 2007 - 33 - revision a7 9. typical application circuit 9.1 external program memory and crystal ad0 a0 a0 a0 10 a1 9 a2 8 a3 7 a4 6 a5 5 a6 4 a7 3 a8 25 a9 24 a10 21 a11 23 a12 2 a13 26 a14 27 a15 1 ce 20 oe 22 o0 11 o1 12 o2 13 o3 15 o4 16 o5 17 o6 18 o7 19 27512 ad0 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74ls373 ad0 ea 31 xtal1 19 xtal2 18 rst 9 int0 12 int1 13 t0 14 t1 15 p1.0 1 p1.1 2 p1.2 3 p1.3 4 p1.4 5 p1.5 6 p1.6 7 p1.7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 wr p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd 16 psen 29 ale 30 txd 11 rxd 10 w78le365/w78l365a 10 u 8.2 k v crystal c1 c2 r ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 ad1 ad2 ad3 ad4 ad5 ad6 ad7 gnd a1 a2 a3 a4 a5 a6 a7 a1 a2 a3 a4 a5 a6 a7 a8 a9 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a10 a11 a12 a13 a14 a15 gnd a9 a10 a11 a12 a13 a14 a15 dd figure a crystal c1 c2 r 6 mhz 47p 47p - 16 mhz 30p 30p - 20 mhz 15p 10p - above table shows the refe rence values for crystal applications. notes: 1. c1, c2, r components refer to figure a 2. crystal layout must get close to xta l1 and xtal2 pins on user's application board. w78le365/w78l365a - 34 - 9.2 expanded external data memory and oscillator 10 u 8.2 k oscillato r ea 31 xtal1 19 xtal2 18 rst 9 int0 12 int1 13 t0 14 t1 15 p1.0 1 p1.1 2 p1.2 3 p1.3 4 p1.4 5 p1.5 6 p1.6 7 p1.7 8 p0.0 39 p0.1 38 p0.2 37 p0.3 36 p0.4 35 p0.5 34 p0.6 33 p0.7 32 p2.0 21 p2.1 22 p2.2 23 p2.3 24 p2.4 25 p2.5 26 p2.6 27 p2.7 28 rd 17 wr 16 psen 29 ale 30 txd 11 rxd 10 w78le365/w78l365a ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a0 a1 a2 a3 a4 a5 a6 a7 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74ls373 a0 a1 a2 a3 a4 a5 a6 a7 10 9 8 7 6 5 4 3 a0 a1 a2 a3 a4 a5 a6 a7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 11 12 13 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 a8 a9 a10 a11 a12 a13 a14 25 24 21 23 26 1 20 2 a8 a9 a10 a11 a12 a13 a14 ce gnd a8 a9 a10 a11 a12 a13 a14 gnd 22 27 oe wr 20256 v dd v dd figure b w78le365/w78l365a publication release date: january 10, 2007 - 35 - revision a7 10. package dimensions 10.1 40-pin dip seating plane 1. dimension d max. & s include mold flash tie bar burrs. 2. dimension e1 does not include interlead fla s 3. dimension d & e1 include mold mismatch a are determined at the mold parting lin e 6. general appearance spec. should be base d final visual inspection spec. . 1.372 1.219 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in m 0.050 1.27 0.210 5.334 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.406 0.254 3.937 0.457 4.064 0.559 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.203 3.048 0.254 3.302 0.356 3.556 0.540 0.550 0.545 13.72 13.97 13.84 17.01 15.24 14.986 15.494 0.600 0.590 0.610 2.286 2.54 2.794 0.090 0.100 0.110 a b c d e a l s a a 1 2 e b 1 1 e e 1 a 2.055 2.070 52.20 52.58 015 0.090 2.286 0.650 0.630 16.00 16.51 protrusion/intrusion. 4. dimension b1 does not include damb a 5. controlling dimension: inches. 15 0 e a a a c e base plane 1 a 1 e l a s 1 e d 1 b b 40 21 20 1 2 10.2 44-pin plcc 44 40 39 29 28 18 17 7 61 l c 1 b 2 a h d d e b e h e y a a 1 seating plane d g g e symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h e l y a a 1 2 e b 1 h d g g d e notes: on final visual inspection spec. 4. general appearance spec. should be based 3. controlling dimension: inches protrusion/intrusion. 2. dimension b1 does not include dambar flash. 1. dimension d & e do not include interlead 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100 0.050 bsc 0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.508 3.683 0.66 0.406 0.203 16.46 14.99 17.27 2.296 3.81 0.711 0.457 0.254 16.59 15.49 17.53 2.54 1.27 4.699 3.937 0.813 0.559 0.356 16.71 16.00 17.78 2.794 0.10 bsc 16.71 16.59 16.46 0.658 0.653 0.648 16.00 15.49 14.99 0.630 0.610 0.590 17.78 17.53 17.27 0.700 0.690 0.680 w78le365/w78l365a - 36 - 10.3 44-pin pqfp seating plane 11 22 12 see detail f e b a y 1 a a l l 1 c e e h 1 d 44 h d 34 33 detail f 1. dimension d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeter 4. general appearance spec. should be based on final visual inspection spec. 0.254 0.101 0.010 0.004 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.006 0.152 --- 0.002 0.075 0.01 0.081 0.014 0.087 0.018 1.90 0.25 0.05 2.05 0.35 2.20 0.45 0.390 0.025 0.063 0.003 0 7 0.394 0.031 0.398 0.037 9.9 0.80 0.65 1.6 10.00 0.8 10.1 0.95 0.398 0.394 0.390 0.530 0.520 0.510 13.45 13.2 12.95 10.1 10.00 9.9 7 0 0.08 0.031 0.01 0.02 0.25 0.5 --- --- --- --- --- 2 0.025 0.036 0.635 0.952 0.530 0.520 0.510 13.45 13.2 12.95 0.051 0.075 1.295 1.905 10.4 48-pin lqfp 2 1 a h d d e b e h e y a a seating plane l l 1 see detail f detail f c 37 48 1 12 13 24 25 36 1. dimensions d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeters 4. general appearance spec. should be based on final visual inspection spec. notes: max. nom. min. dimension in mm symbol a b c d e h d h e l y 0 a a l 1 1 2 e 1.40 0.20 0.50 1.00 7.00 9.00 9.00 7.00 --- --- --- 1.60 0.15 1.45 1.35 0.05 0.17 0.27 --- 0.09 0.20 0.45 0.60 0.75 0.08 0 3.5 7 --- --- w78le365/w78l365a publication release date: january 10, 2007 - 37 - revision a7 11. application note 11.1 in-system programming software examples this application note illustrates the in-sys tem programmability of the winbond w78e365 rom microcontroller. in this example, microcontrolle r will boot from 64kb aprom bank and waiting for a key to enter in-system programming mode for re -programming the contents of 64kb aprom. while entering in-system programming mode, microcontrolle r executes the loader program in 4kb ldrom bank. the loader program erases the 64kb aprom then reads the new code data from external sram buffer (or through other interf aces) to update the 64kb aprom. example 1: ;******************************************************************************************************************* ;* example of 64k aprom program: program will scan the p1.0. if p1.0 = 0, enters in-system ;* programming mode for updating the content of apr om code else executes the current rom code. ;* xtal = 16 mhz ;******************************************************************************************************************* .chip 8052 .ramchk off .symbols chpcon equ bfh chpenr equ f6h sfral equ c4h sfrah equ c5h sfrfd equ c6h sfrcn equ c7h org 0h ljmp 100h ; jump to main program ; ************************************************************************ ;* timer0 service vector org = 000bh ;************************************************************************ org 00bh clr tr0 ; tr0 = 0, stop timer0 mov tl0, r6 mov th0, r7 reti ;************************************************************************ ;* 64k aprom main program ;************************************************************************ org 100h main_64k: mov a, p1 ; scan p1.0 anl a, #01h cjne a, #01h, program_64k ; if p1 .0 = 0, enter in-system programming mode jmp normal_mode program_64k: mov chpenr, #87h ; chpenr = 87h, chpcon register wrte enable mov chpenr, #59h ; chpenr = 59h, chpcon register write enable mov chpcon, #03h ; chpcon = 03h, enter in-system programming mode mov tcon, #00h ; tr = 0 timer0 stop w78le365/w78l365a - 38 - mov ip, #00h ; ip = 00h mov ie, #82h ; ti mer0 interrupt enable for wake-up from idle mode mov r6, #f0h ; tl0 = f0h mov r7, #ffh ; th0 = ffh mov tl0, r6 mov th0, r7 mov tmod, #01h ; tmod = 01h, set timer0 a 16-bit timer mov tcon, #10h ; tcon = 10h, tr0 = 1, go mov pcon, #01h ; enter idle mode for launching the in-system ; programming ;******************************************************************************** ;* normal mode 64kb aprom program: depending user's application ;******************************************************************************** normal_mode: . ; user's application program . . . example 2: ;****************************************************************************************************************************** example of 4 kb ldrom program: this loader program will erase the 64kb aprom first, then reads the new ;* code from external sram and program them into 32 kb aprom bank. xtal = 16 mhz ;***************************************************************************************************************************** .chip 8052 .ramchk off .symbols chpcon equ bfh chpenr equ f6h sfral equ c4h sfrah equ c5h sfrfd equ c6h sfrcn equ c7h org 000h ljmp 100h ; jump to main program ; ************************************************************************ ;* 1. timer0 service vector org = 0bh ;************************************************************************ org 000bh clr tr0 ; tr0 = 0, stop timer0 mov tl0, r6 mov th0, r7 reti ;************************************************************************ ;* 4kb ldrom main program ;************************************************************************ org 100h w78le365/w78l365a publication release date: january 10, 2007 - 39 - revision a7 main_4k: mov sp, #c0h mov chpenr, #87h ; chpenr = 87h, chpcon write enable. mov chpenr, #59h ; chpenr = 59h, chpcon write enable. mov chpcon, #03h ; chp con = 03h, enable in-system programming. mov chpenr, #00h ; disable chpcon write attribute mov tcon, #00h ; tcon = 00h, tr = 0 timer0 stop mov tmod, #01h ; tmod = 01h, set timer0 a 16bit timer mov ip, #00h ; ip = 00h mov ie, #82h ; ie = 82h, timer0 interrupt enabled mov r6, #f0h mov r7, #ffh mov tl0, r6 mov th0, r7 mov tcon, #10h ; tcon = 10h, tr0 = 1, go mov pcon, #01h ; enter idle mode update_64k: mov tcon, #00h ; tcon = 00h , tr = 0 tim0 stop mov ip, #00h ; ip = 00h mov ie, #82h ; ie = 82h, timer0 interrupt enabled mov tmod, #01h ; tmod = 01h, mode1 mov r6, #e0h ; set wake-up time for erase operation, about 15 ms. depending ; on user's system clock rate. mov r7, #b1h mov tl0, r6 mov th0, r7 erase_p_4k: mov sfrcn, #22h ; sfrcn(c7h) = 22h erase 64k mov tcon, #10h ; tcon = 10h, tr0 = 1, go mov pcon, #01h ; en ter idle mode (for erase operation) ;********************************************************************* ;* blank check ;********************************************************************* mov sfrcn, #0h ; read 64kb aprom mode mov sfrah, #0h ; start address = 0h mov sfral, #0h mov r6, #feh ; set timer for read operation, about 1.5 s. mov r7, #ffh mov tl0, r6 mov th0, r7 blank_check_loop: setb tr0 ; enable timer 0 mov pcon, #01h ; enter idle mode mov a, sfrfd ; read one byte cjne a, #ffh, blank_check_error inc sfral ; next address mov a, sfral jnz blank_check_loop inc sfrah mov a, sfrah w78le365/w78l365a - 40 - cjne a, #80h, blank_check_loop ; end address = 7fffh jmp program_64krom blank_check_error: mov p1, #f0h mov p3, #f0h jmp $ ;******************************************************************************* ;* re-programming 64kb aprom bank ;******************************************************************************* program_64krom: mov dptr, #0h ; the address of new rom code mov r2, #00h ; target low byte address mov r1, #00h ; target high byte address mov dptr, #0h ; external sram buffer address mov sfrah, r1 ; sfrah, target high address mov sfrcn, #21h ; sfrcn(c7h) = 21 (program 64k) mov r6, #beh ; set timer for programming, about 50 s. mov r7, #ffh mov tl0, r6 mov th0, r7 prog_d_64k: mov sfral, r2 ; sfral(c4h) = low byte address movx a, @dptr ; read data from external sram buffer. by according user? ; circuit, user must modify this instruction to fetch code mov sfrfd, a ; sfrfd(c6h) = data in mov tcon, #10h ; tcon = 10h, tr0 = 1, go mov pcon, #01h ; enter idle mode (prorgamming) inc dptr inc r2 cjne r2, #0h, prog_d_64k inc r1 mov sfrah, r1 cjne r1, #80h, prog_d_64k ;***************************************************************************** ; * verify 64kb aprom bank ;***************************************************************************** mov r4, #03h ; error counter mov r6, #feh ; set timer for read verify, about 1.5 s. mov r7, #ffh mov tl0, r6 mov th0, r7 mov dptr, #0h ; the start address of sample code mov r2, #0h ; target low byte address mov r1, #0h ; target high byte address mov sfrah, r1 ; sfrah, target high address mov sfrcn, #00h ; sfrcn = 00 (read rom code) read_verify_64k: mov sfral, r2 ; sfral(c4h) = low address mov tcon, #10h ; tcon = 10h, tr0 = 1,go mov pcon, #01h inc r2 w78le365/w78l365a publication release date: january 10, 2007 - 41 - revision a7 movx a, @dptr inc dptr cjne a, sfrfd, error_64k cjne r2, #0h, read_verify_64k inc r1 mov sfrah, r1 cjne r1, #80h, read_verify_64k ;****************************************************************************** ;* programming completly, software reset cpu ;****************************************************************************** mov chpenr, #87h ; chpenr = 87h mov chpenr, #59h ; chpenr = 59h mov chpcon, #83h ; chpcon = 83h, software reset. error_64k: djnz r4, update_64k ; if error occurs, repeat 3 times. . ; in-system programming fail, user's process to deal with it. . . . w78le365/w78l365a - 42 - 12. revision history version date page description a1 may 14, 2003 - initial issued a2 august, 2004 31 revise the title of 9.1 a3 april 19, 2005 41 add important notice a4 july 1, 2005 3 add lead free (rohs) parts a5 october 2, 2006 remove block diagram change operating frequency into 20mhz a6 december 4, 2006 3 remove all leaded package parts a7 january 10, 2007 3 4 36 add 48-pin lqfp part. add 48-pin lqfp package add 48-pin lqfp package dimension important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this datasheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c. |
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