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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. july 2006 rev 1 1/64 1 M69KB128AB 128 mbit (8mb x16) 1.8v supply, burst psram feature summary supply voltage ?v cc = 1.7 to 1.95v core supply voltage ?v ccq = 1.7 to v cc for i/o buffers user-selectable operating modes ? asynchronous modes: random read, and write, page read ? synchronous modes: nor-flash, full synchronous (burst read and write) asynchronous random read ? access times: 70ns asynchronous page read ? page size: 4, 8 or 16 words ? subsequent read within page: 20ns burst read ? fixed length (4, 8, 16 or 32 words) or continuous ? maximum clock frequency: 80 and 104mhz ? output delay: 7ns at 104mhz low power consumption ? active current: < 25ma ? standby current: 200a ? deep power-down current: 10a low power features ? partial array self refresh (pasr) ? deep power-down (dpd) mode operating temperature ? ?30c to +85c M69KB128AB is only available as part of a multi-chip package wafer www.st.com
contents M69KB128AB 2/64 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 address inputs (a0-a22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 data inputs/outputs (dq8-dq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 data inputs/outputs (dq0-dq7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 chip enable (e ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 output enable (g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 upper byte enable (ub ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 lower byte enable (lb ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.9 clock input (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.10 configuration register enable (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.11 latch enable (l ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.12 wait (wait) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.13 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.14 v ccq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.15 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.16 v ssq ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 deep power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 partial array self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 standard asynchronous operating modes . . . . . . . . . . . . . . . . . . . . . . 15 5.1 asynchronous read and write modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 asynchronous page read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 configuration registers asynchronous read and write . . . . . . . . . . . . . 16
M69KB128AB contents 3/64 6 synchronous operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 nor-flash synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 full synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 synchronous burst read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.1 variable latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.2 fixed latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.3 row boundary crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 synchronous burst read interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5 synchronous burst write interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.6 synchronous burst read and write suspend . . . . . . . . . . . . . . . . . . . . . 20 7 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 programming the registers by the cr controlled method . . . . . . . . . . . . 25 7.1.1 read configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1.2 program configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2 programming and reading the registers by the software method . . . . . 26 7.3 bus configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3.1 operating mode bit (bcr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3.2 latency type (bcr14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3.3 latency counter bits (bcr13-bcr11) . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3.4 wait polarity bit (bcr10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3.5 wait configuration bit (bcr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3.6 driver strength bits (bcr5-bcr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3.7 burst wrap bit (bcr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3.8 burst length bits (bcr2-bcr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.4 refresh configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.4.1 page mode operation bit (rcr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.4.2 deep power-down bit (rcr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.4.3 partial array refresh bits (rcr2-rcr0) . . . . . . . . . . . . . . . . . . . . . . . 33 7.5 device id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
contents M69KB128AB 4/64 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
M69KB128AB list of tables 5/64 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. page mode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3. standard asynchronous operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. operating frequency versus latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. asynchronous write operations (nor-flash synchronous mode) . . . . . . . . . . . . . . . . . . 21 table 6. synchronous read operations (nor-flash synchronous mode) . . . . . . . . . . . . . . . . . . . 21 table 7. full synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. register selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 9. bus configuration register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 10. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 11. refresh configuration register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 12. device id register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 13. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 14. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 15. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 16. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 17. asynchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 18. asynchronous page read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 19. asynchronous write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 20. clock related ac timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 21. synchronous burst read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 22. synchronous burst write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 23. power-up and deep power-down ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 24. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 25. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
list of figures M69KB128AB 6/64 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. latency configuration (varia ble latency mode, no refr esh collision) . . . . . . . . . . . . . . . . 23 figure 4. latency configuration (fixed latency mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 5. switching from asynchronous to synchronous write operation . . . . . . . . . . . . . . . . . . . . . 24 figure 6. refresh collision during sy nchronous read operation in vari able latency mode . . . . . . 24 figure 7. set configuration register (software method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 8. read configuration register (software method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9. wait configuration example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 10. wait polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 11. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 12. ac input transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 13. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 14. asynchronous random read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 15. latch enable controlled, asynchronous random read ac waveforms . . . . . . . . . . . . . . 41 figure 16. asynchronous page read ac waveforms (4 words) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 17. cr controlled configuration register read followed by read, asynchronous mode . . . . 42 figure 18. chip enable controlled, asynchronous write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . 44 figure 19. upper/lower byte enable controlled, asynchronous write ac waveforms . . . . . . . . . . . . 45 figure 20. write enable controlled, asynchronous write ac waveforms . . . . . . . . . . . . . . . . . . . . . . 46 figure 21. l controlled, asynchronous write ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 22. cr controlled configuration register program, asynchronous mode . . . . . . . . . . . . . . . . 48 figure 23. clock input ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 24. 4-word synchronous burst read ac waveforms (variable latency mode) . . . . . . . . . . . . 50 figure 25. synchronous burst read suspend and resume ac waveforms . . . . . . . . . . . . . . . . . . . . 51 figure 26. synchronous burst read showing end-of-row condition ac waveforms (no wrap) . . . . 52 figure 27. burst read interrupted by burst read or write ac waveforms . . . . . . . . . . . . . . . . . . . . . 53 figure 28. cr controlled configuration register read followed by read, synchronous mode . . . . . 54 figure 29. 4-word synchronous burst write ac waveforms (variable latency mode) . . . . . . . . . . . . 56 figure 30. synchronous burst write showing end-of-row condition ac waveforms (no wrap) . . . . 57 figure 31. synchronous burst write followed by read ac waveforms (4 words) . . . . . . . . . . . . . . . 58 figure 32. burst write interrupted by burst write or read ac waveforms . . . . . . . . . . . . . . . . . . . . . 59 figure 33. cr controlled configuration register program, synchronous mode. . . . . . . . . . . . . . . . . 60 figure 34. power-up ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 35. deep power-down entry and exit ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
M69KB128AB summary description 7/64 1 summary description the M69KB128AB is a 128 mbit (134,217,728 bit) psram, organized as 8,388,608 words by 16 bits. it uses a high-speed cmos dr am technology implemented using a one transistor-per-cell topology that achieves bigg er array sizes. it provides a high-density solution for low-power handheld applications. the M69KB128AB is supplied by a 1.7 to 1.95v supply voltage range. the psram interface supports various operating modes: asynchronous random read and write, asynchronous page read and synchronous mode that increases read/write speed. in asynchronous random read mode, the M69KB128AB is compatible with low power srams. in asynchronous page mode the devi ce has much shorter access times within the page that make it is compatible with the industry standard psrams. two types of synchronous modes are available: flash-nor: the device operates in sync hronous mode for read operations and asynchronous mode for write operations. full synchronous: the device supports sync hronous transfers for both read and write operations. the M69KB128AB features three configuration registers: two user-programmable registers used to define the device operation: the bus configuration register (bcr) and the refresh configuratio n register (rcr). a read-only device id register (didr) containing device identification. the bus configuration register (bcr) indicate s how the device interacts with the system memory bus. the refresh configuration register (rcr) is used to control how the memory array refresh is performed. at power-up, these registers are automatically loaded with default settings and can be updated any time during normal operation. psrams are based on the dram technology, but have a transparent internal self-refresh mechanism that requires no additional support from the system memory microcontroller. to minimize the value of the standby current during self-refresh operations, the M69KB128AB includes two system-accessible mechanisms configured via the refresh configuration register (rcr): the partial array self refresh (pasr) performs a limited refresh of the part of the psram array that contains essential data. the deep power-down (dpd) mode completely halts the refresh operation. it is used when no essential data is being held in the device.
summary description M69KB128AB 8/64 figure 1. logic diagram table 1. signal names a0-a22 address inputs dq0-dq15 data inputs/outputs e chip enable input cr configuration register enable input g output enable input w write enable input ub upper byte enable input lb lower byte enable input k clock input l latch enable input wait wait output v cc core supply voltage v ccq input/output buffers supply voltage v ss ground v ssq input/output buffers ground ai11295 23 a0-a22 w dq0-dq15 v cc M69KB128AB g 16 e ub lb v ss cr k l v ccq v ssq wait
M69KB128AB summary description 9/64 figure 2. block diagram 1. this functional bloc k diagram illustrates si mplified device operation. ai09965b a22-a0 i/o buffers 8,192k x 16 memory array k wait dq0-dq15 address decoder bus configuration register (bcr) control logic cr l ub lb w e g synchronous/ asynchronous logic cr w e row decoder column decoder
signal descriptions M69KB128AB 10/64 2 signal descriptions the signals are summarized in figure 1: logic diagram , and table 1: signal names . 2.1 address inputs (a0-a22) the address inputs select the cells in the memory array to access during read and write operations. 2.2 data inputs/outputs (dq8-dq15) the upper byte data inputs/outputs carry the data to or from the upper part of the selected address during a write or read operation, when upper byte enable (ub ) is driven low. when disabled, the data inputs/outputs are high impedance. 2.3 data inputs/outputs (dq0-dq7) the lower byte data inputs/outputs carry the data to or from the lower part of the selected address during a write or read operation, when lower byte enable (lb ) is driven low. when disabled, the data inputs/outputs are high impedance. 2.4 chip enable (e ) chip enable, e , activates the device when driven low (asserted). when deasserted (v ih ), the device is disabled and goes automatically in low-power standby mode or deep power- down mode, accordin g to the rcr settings. 2.5 output enable (g ) when held low, v il , the output enable, g , enables the bus read operations of the memory. 2.6 write enable (w ) write enable, w , controls the bus write operation of the memory. when asserted (v il ), the device is in write mode and write operations can be performed either to the configuration registers or to the memory array. 2.7 upper byte enable (ub ) the upper byte enable, ub , gates the data on the upper byte data inputs/outputs (dq8- dq15) to or from the upper part of the selected address during a write or read operation.
M69KB128AB signal descriptions 11/64 2.8 lower byte enable (lb ) the lower byte enable, lb , gates the data on the lower byte data inputs/outputs (dq0- dq7) to or from the lower part of the selected address during a write or read operation. if both lb and ub are disabled (high), the device will di sable the data bus from receiving or transmitting data. although the device will seem to be deselected, it remains in an active mode as long as e remains low. 2.9 clock input (k) the clock, k, is an input signal to synchronize the memory to the microcontroller or system bus frequency during synchronous burst read and write operations. the clock input signal increments the device internal address counter. the addresses are latched on the rising edge of the clock k, when l is low during synchronous bus operations. latency counts are defined from the first clock rising edge after l falling edge to the first data input latched or the first data output valid. the clock input is required during all synchronous operations and must be kept low during asynchronous operations. 2.10 configuration register enable (cr) when this signal is driven high, v ih , bus read or write operations access either the value of the refresh configuration register (rcr) or the bus configuration register (bcr) according to the value of a19. 2.11 latch enable (l ) in synchronous mode, addresses are latched on the rising edge of the clock k when the latch enable input, l is low. in asynchronous mode, addresses are latched on l rising edge. 2.12 wait (wait) the wait output signal provides data-valid feedback during synchronous burst read and write operations. the signal is gated by e . driving e high while wait is asserted may cause data corruption. once a read or write operation has been initiated, the wait signal goes active to indicate that the M69KB128AB device requires additional time before data can be transferred. the wait signal also is used for arbitration when a read or write operation is launched while an on-chip refresh is in progress (see figure 6: refresh collis ion during sy nchronous read operation in variable latency mode ). typically, the wait pin of the M69KB128AB can be connected to a shared wait signal used by the processor to coordinate transactions with multiple memories on the synchronous bus. see section 3: power-up for details on the wait signal operation.
power-up M69KB128AB 12/64 2.13 v cc supply voltage the v cc supply voltage is the core supply voltage. 2.14 v ccq supply voltage v ccq provides the power supply for the i/o pins. this allows all outputs to be powered independently from the core power supply, v cc . 2.15 v ss ground the v ss ground is the reference for all voltage measurements. 2.16 v ssq ground v ssq ground is the reference for the input/output circuitry driven by v ccq . v ssq must be connected to v ss . 3 power-up to guarantee correct operation, a specific power-up sequence must be followed to initialize the M69KB128AB. power must be applied simultaneously to v cc and v ccq . once v cc and v ccq have reached a stable level (see figure 35: deep power-down entry and exit ac waveforms and figure 34: power-up ac waveforms ), the device will require t vchel to complete its self-initializ ation process. during the initialization period, the e signal must remain high. once initialization has completed, the device is ready for normal operation. initialization will load the bus configuration re gister (bcr) and the refresh configuration register (rcr) with their default settings (see table 9: bus configuration register definition , and table 11: refresh configuration register definition ).
M69KB128AB low-power modes 13/64 4 low-power modes 4.1 standby when the device is in standby, the current consumption is reduced to the level necessary to perform the memory array refres h operation. the device will en ter standby when a read or write operation is completed, depending on the operating mode (asynchronous, nor-flash synchronous or full synchronous). for details on how to enter standby, refer to table 3: standard asynchronous operating modes , table 5: asynchronous write operations (nor-flash synchronous mode) and table 6: synchronous read operatio ns (nor-flash synchronous mode) . 4.2 deep power-down deep power-down (dpd) is used by the system memory microcontro ller to disable the psram device when its storage capabilities are not needed. all refresh operations are then disabled. for the device to enter deep power-down, bit 4 of the rcr must be set to ?0? and chip enable, e , must go high, v ih . when the deep power-down is enabled, the data stored in the device may be corrupted and bcr, rcr and didr content are saved. to exit deep power-down, the chip enable signal, e , must be held low, v il , for a minimum time of t ehel(dp) . bit 4 of the rcr will be automatically set to ?1?. once the deep power- down is exited, the device will be ava ilable for normal operations after t vchel (time to perform an initialization sequence) during this delay, the current consumption will be higher than the specified standby levels, but considerably lower than the active current. the content of the regist ers will be restored after deep power-down. for details on how to enter deep power-down, refer to table 3: standard asynchronous operating modes , table 5: asynchronous write operations (nor-flash synchronous mode) and table 6: synchronous read operations (nor-flash synchronous mode) .
low-power modes M69KB128AB 14/64 4.3 partial array self refresh the partial array self refresh (pasr) performs a limited refresh of part of the psram array. this mechanism enables the device to reduce the standby current by refreshing only the part of the memory array that contains essential data. different refresh options can be defined by setting the rcr0 to rcr2 bits of the rcr: full array one eighth of the array one half of the array one quarter of the array none of the array. these memory areas can be located either at the top or bottom of the memory array. the wait signal is used for arbitration when a read/write operation is launched while an on- chip refresh is in progress. if locations are addressed while they are undergoing refresh, the wait signal will be asserted for additional cl ock cycles, until the refresh has completed (see figure 6: refresh collision duri ng synchronous read operation in variable latency mode ). when the refresh operation is completed, the re ad or write operation will be allowed to continue normally.
M69KB128AB standard asynchronous operating modes 15/64 5 standard asynchronous operating modes the M69KB128AB supports asynchronous read and write modes (random read, page read, asynchronous write). the device is put in asynchronous mode by setting bit 15 (bcr15) of the bcr to ?1?. the page mode is controlled by the refres h configuration register (bit rcr7). during asynchronous operations, the wait signal should be ignored and the clock input signal k should be held low, v il . refer to table 3: standard asynchronous operating modes for a detailed description of asynchronous operating modes. 5.1 asynchronous read and write modes at power-up, the device defaults to asynchronous random read mode (bit bcr15 set to ?1?). this mode uses the industry standard control bus (e , g , w , lb , ub ). read operations are initiated by bringing e and g low, v il , while keeping w high, v ih . valid data will be gated through the output buffers after the specific access time t elqv has elapsed. write operations occur when e and w are low. during asynchronous random write operations, the g signal is ?don't care? and w will override g . the data to be written is latched on the rising edge of e , w , lb or ub (whichever occurs first). the write operation is terminated by de-asserting e , w , lb or ub. the l input can either be used to latch the address or kept low, v il, during the entire read/write operation. see figure 14 and figure 15 , and ta b l e 1 7 for details on asynchronous read ac waveforms and characteristics and figure 18 , figure 19 , figure 20 , and figure 19 for details of asynchronous write ac waveforms and characteristics. 5.2 asynchronous page read mode asynchronous page read mode is enabled by setting rcr7 to ?1?. the latch enable, l , and the chip enable e must be held low, v il during asynchronous page read operations. a page of data is internally read. a memory page may consist of 4, 8 or 16 words. during a 4-word page access, all the address bits except a0 to a1 should be fixed. during a 8-word and 16-word page access, all address bits are fixed except a0 to a2 and a0 to a3, respectively (see table 2: page mode characteristics ). the first read operation within the page has the normal access time (t avqv ), subsequent reads within the same page have much shorter access times (t avqv1 ). if the page changes then the normal, longer timings apply again. the page mode is not available for write operations. see figure 16 and ta b l e 1 7 for details of the asynchronous page read timing requirements.
standard asynchronous operating modes M69KB128AB 16/64 5.3 configuration registers as ynchronous read and write programming the registers (bcr and rcr) and reading the registers (bcr, rcr and didr) can be performed using the cr controlled method in standard asynchronous mode. table 2. page mode characteristics page size page read address page read start address page read direction 4 words a0-a1 don?t care don?t care 8 words a0-a2 don?t care don?t care 16 words a0-a3 don?t care don?t care table 3. standard asynchronous operating modes asynchronous modes (1) power l e w g ub lb wait cr a19 a18 a0-a17 a20-a22 dq0- dq7 dq8- dq15 word read active (i cc ) v il v il v ih v il v il v il low- z v il valid output valid output valid lower byte read v il v ih v il v il valid output valid high-z upper byte read v il v il v ih v il valid high-z output valid word write v il xv il v il v il valid input valid input valid lower byte write xv ih v il v il valid input valid invalid upper byte write xv il v ih v il valid invalid input valid read configuration register (cr controlled method) v ih v il v il v il v ih 00(rcr) 10(bcr) x1(didr) (2) x bcr/ rcr/didr content program configuration register (cr controlled) (3) v ih xxx 00(rcr) 10(bcr) (2) bcr/ rcr data high-z no operation active (i cc ) x xxxx v il xx x x deep power-down (4) deep power- down (i ccpd) v ih xxxx high- z x x x x high-z standby standby (i pasr ) v ih xxxx v il x x x high-z 1. the clock signal, k, must remain low in asynchronous operating mode. 2. a18 and a19 are used to select the bcr, rcr or didr registers. 3. bcr and rcr only. 4. bit 4 of the refresh configuration register must be set to ?0 ?, bit 4 (bcr4) of the bus configuration register must be set to ?0?, and e has to be maintained high, v ih , during deep power-down mode.
M69KB128AB synchronous operating modes 17/64 6 synchronous operating modes the synchronous modes allow high-speed read and write operations synchronized with the clock. refresh cycles are indicated to the host system by asserting the wait signal that, in turn, stalls the microcontroller. the M69KB128AB supports two types of synchronous modes: nor-flash :- this mode greatly simplifies the interfacing with traditional burst-mode flash memory microcontrollers. full synchronous : both read and write are performed in synchronous mode. all the options related to the synchronous modes can be configured through the bus configuration register, bcr. in particular, t he device is put in synchronous mode, either nor-flash or full synchronous, by setting bit bcr15 of the bus configuration register to ?0?. the device will automatically detect whether the nor-flash or the full synchronous mode is being used by monitoring the clock, k, and the latch enable, l , signals. if a rising edge of the clock k is detected while l is held low, v il (active), the device operates in full synchronous mode. 6.1 nor-flash synchronous mode in this mode, the device operates in synchronous mode for read operations, and in asynchronous mode for write operations. asynchronous write operations are performed at word level, with lb and ub low. the data is latched on e , w , lb , ub , whichever occurs first. rcr and bcr registers can be programmed in nor-flash asynchronous write mode, using the cr controlled method (see section 7.1: programming the regist ers by the cr controlled method ). a program configuration register operation can only be issued if the device is in idle state and no burst operations are in progress. nor-flash asynchronous write operations are described in table 5: asynchronous write operati ons (nor-flash synchronous mode) . synchronous read operations are also performed at word level. they are controlled by the state of e , l , g , w , lb and ub signals when a rising edge of the clock signal, k, occurs. the initial burst read access latches the burst start address. the number of words to be output is controlled by bits 0 to 2 of the bcr. the first data will be output after a nu mber of clock cycles, also called latency. nor-flash synchronous burst read operations are described in table 6: synchronous read operations (nor-flash synchronous mode) . when a burst write operation is initiated or when switching from nor-flash mode to full synchronous mode, the delay from e low to clock high, t elkh , should not exceed 20ns. however, when it is not possible to meet these specifications, special care must be taken to keep addresses stable after driving the write enable signal, w , low. write operations are considered as asynchronous operations until the device detects a valid clock edge and hence the address setup time of t avwl must be satisfied (see figure 5: switching from asynchronous to synchronous write operation ).
synchronous operating modes M69KB128AB 18/64 6.2 full synchronous mode in full synchronous mode, the device performs read and write operations synchronously. synchronous read and write operations are performed at word level. the initial burst read and write access latches the burst start address. the number of words to be output or input during synchronous read and write operations is controlled by bits 0 to 2 of the bcr. during burst read and write oper ations, the first data will be output after a number of clock cycles defined by the latency value. programming the registers (bcr and rcr) and reading the registers (bcr, rcr and didr) can be performed using the cr controlled method in full synchronous mode. full synchronous operations are described in table 7: full synchronous mode . 6.3 synchronous burst read and write during synchronous burst read or write operations, addresses are latched on the rising edge of the clock k when l is low and data are latched on the rising edge of k. the write enable, w , signal indicates whether the operation is going to be a read (w =v ih ) or a write (w =v il ). the wait output will be a sserted as soon as a synchronous burst operation is initiated and will be deasserted to indicate when data are to be transferred to (or fr om) the memory array. the burst length is the number of words to be output or input during a synchronous burst read or write operation. it can be configured as 4, 8, 16 or 32 words or continuous through bit bcr0 to bcr2 or the burst configuration register. the latency defines the number of clock cycles between the beginning of a burs t read operation and the first data output (counting from the first clock edge where l was detected low) or between the beginning of a burst write operation and the first data input. the latency can be set through bits bcr13 to bcr11 of the bus configuration register (see table 4: operating frequency versus latency ). the latency can also be configured to fixed or variable by programming bit bcr14. by default, the latency type is set to variable. synchronous read operations are performed in both fixed and variable latency mode while synchronous write operations are only performed with fixed latency. see figure 24 , note 1 , and figure 30 , note 31 , for details on synchronous read and write ac waveforms, respectively. 6.3.1 variable latency in variable latency mode, the latency programmed in the bcr is not guaranteed and is maintained only if there is no conflict with a refresh operation. the latency set in the bcr is applicable only for an initia l burst read access, when no refresh request is pending. for a given latency value, the variable latency mode allows higher operating frequencies than the fixed latency mode (see table 4: operating frequency versus latency and figure 3: latency configuration (variable latency mode, no refresh collision) ).
M69KB128AB synchronous operating modes 19/64 burst write operations are always performed at fixed latency, even if bcr14 is configured to variable latency (see section 6.3.2: fixed latency ). monitoring of the wait signal is recommended for reliable operation in this mode. see figure 24 . and figure 31 for details on synchronous burst read and write ac waveforms in variable latency mode. 6.3.2 fixed latency the latency programmed in the bcr is the re al latency. the number of clock cycles is calculated by taking into account the time necessary for a refresh operation and the time necessary for an initial burst access. this limits the operating frequency for a given latency value (see table 4: operating frequency versus latency and figure 4: latency configuration (fixed latency mode) ). it is recommended to use the fixed latency mode if the microcontroller cannot monitor the wait signal. 6.3.3 row boundary crossing row boundary crossings between adjacent rows may occur during burst read and write operations. row boundary crossings are not handled automatically by the psram. the microcontroller must stop the burst operation at the row boundary and restart it at the beginning of the next row. burst operations must be stopped by driving the chip enable signal, e , high, after the wait signal falling edge. e must transition: before the third clock cycle after the wait signal goes low if bcr[8] = 0 before the fourth clock cycle after wait signal goes low if bcr[8] = 1. refer to figure 26 and figure 30 for details on how to manage row boundary crossings during burst operations. 6.4 synchronous burst read interrupt ongoing burst read operations can be interrupted to start a new burst cycle by either of the following means: driving e high, v ih , and then low, v il on the next clock cycle (recommended). if necessary, refresh cycles will be added during the new burst operation to schedule any outstanding refresh. if variable latency mode is set, additional wait cycles will be added if a refresh operation is scheduled during the synchronous burst read interrupt. wait monitoring is mandatory for proper system operation. starting a new synchronous burst read operation without toggling e . an ongoing burst read operation can be interrupted only after the first valid data is output. when a new burst access starts, i/o signals immediately become high impedance.
synchronous operating modes M69KB128AB 20/64 6.5 synchronous burst write interrupt ongoing burst write operations can be interrupted to start a new burst cycle by either of the following means: driving e high, v ih , and then low, v il on the next clock cycle (recommended), starting a new synchronous burst write without toggling e . considering that burst writes are always performed in fixed latency mode, refresh is never scheduled. a maximum chip enable, e , low time (t eleh ) must be respected for proper device operation. an ongoing burst write can be interrupted only after the first data is input. when a new burst access starts, i/o signals immediately become high impedance. see figure 27: burst read interrupted by burst read or write ac waveforms and figure 32: burst write interrupted by burst write or read ac waveforms for details on burst read and burst write interrupt ac waveforms, respectively. 6.6 synchronous burst read and write suspend synchronous burst read and write operations can be suspended by halting the clock k holding it either high or low. the status of the i/o signa ls will depend on the status of output enable input, g . the device internal address counter is suspended and data outputs become high impedance t ghqz after the rising edge of the output enable signal, g . it is prohibited to suspend the first data output at the beginning of a synchronous burst read. see figure 25 for details on the synchronous burst read and write suspend mechanisms. during synchronous burst read and synchronous burst write suspend operations, the wait output will be asserted. bit bcr8 of th e bus configuration register is used to configure when the transition of the wait output signal between the asserted and the deasserted state occurs with respect to valid data available on the data bus. table 4. operating frequency versus latency latency mode configured latency (clock cycles) latency (clock cycles) max input clock frequency (mhz) normal if refresh collision 104 mhz 80 mhz variable latency bcr14 = 0 (default) 2 (3 clock cycles) 3 5 66 52 3 (4 clock cycles) (default) 47 104 80 fixed latency bcr14 = 1 2 (3 clock cycles) 3 33 33 3 (4 clock cycles) (default) 45252 4 (5 clock cycles) 5 66 66 5 (6 clock cycles) 6 75 75 6 (7 clock cycles) 7 104 80 all others - - -
M69KB128AB synchronous operating modes 21/64 table 5. asynchronous write operations (nor-flash synchronous mode) asynchronous operations power k l e w g ub , lb wait cr a19 a18 a0-a22 dq0-dq15 word write active (i cc ) v il v il v il v il xv il low- z v il valid input valid program configuration register (cr controlled) (1) v il v il v il v ih xv ih 00(rcr) 10(bcr) rcr/b cr data high-z no operation active (i cc )v ih xxx x v il xx standby standby (i pasr ) xv ih xx x high- z v il x high-z deep power-down deep power-down (i ccpd) xv ih x x x x x high-z 1. bcr and rcr only. table 6. synchronous read operations (nor-flash synchronous mode) synchronous operations (1) power k e l w g lb , ub wait cr a19 a18 a0- a22 (2) dq15- dq0 initial burst read active (i cc ) v il v il v ih xv il low-z v il valid valid valid output valid subsequent burst read v il v ih xxv il (3) v il x output valid read configuration register (cr controlled method) v il v il v ih v il v il v ih 00(rcr) 10(bcr) x1(didr) x rcr/bc r/didr content no operation active (i cc )v il v il xxx x v il xx standby standby (i pasr ) v il v ih xxx x high- z v il x high-z deep power-down deep power- down (i ccpd) v il v ih x x x x x x high-z 1. burst read interrupt, suspend and terminate ar e described in dedicated paragraph of the section 6: synchronous operating modes . 2. except a18 and a19. 3. the above table shows the device behavior if both lb and ub are asserted, v il . if either lb or ub is high, v ih , only one byte will be input or output, ac cording to the status of w .
synchronous operating modes M69KB128AB 22/64 table 7. full synchronous mode synchronous mode (1) power k e l w g lb , ub wait cr a19 a18 a0- a22 (2) dq15- dq0 initial burst read active (i cc ) v il v il v ih xv il low-z v il valid valid valid x subsequent burst read v il v ih xv il v il (3) v il xx output valid initial burst write v il v il v il v ih xv il valid valid valid input valid subsequent burst write v il v ih xv ih v il (2) xx x x input valid program configuration register (cr controlled) v il v il v il v ih xv ih 00(rcr) 10(bcr) rcr/b cr data x read configuration register (cr controlled method) v il v il v ih v il v il v ih 00(rcr) 10(bcr) x1(didr) x rcr/bc r/ didr content no operation active (i cc ) v il v il xxx x v il xx standby standby (i pa s r ) v il v ih xxx x high-z v il x high-z deep power-down deep power- down (i ccpd) v il v ih x x x x x x high-z 1. burst read interrupt, suspend, terminate and burst writ e interrupt, suspend and terminat e are described in dedicated paragraph of the section 6: synchronous operating modes . 2. except a18 and a19. 3. the above table shows the device behavior if both lb and ub are asserted, v il . if either lb or ub is high, v ih , only one byte will be input or output, ac cording to the status of w .
M69KB128AB synchronous operating modes 23/64 figure 3. latency configuration (variable latency mode, no refresh collision) figure 4. latency configuration (fixed latency mode) 1. see table 21: synchronous burst read ac characteristics for details on the synchronous r ead ac characteristics shown in the above waveforms. addr. dq0-dq15 k address valid q 1 hi z 012345 q 4 q 3 q 2 latency = 3 clock cycles ai11280 adv hi z q 1 q 3 q 2 q 5 q 4 67 latency = 4 clock cycles dq0-dq15 addr. dq0-dq15 out k address valid q 1 hi z n-1 cycle n cycle q 4 q 3 q 2 ai11281c adv q 5 e tkhqv2
synchronous operating modes M69KB128AB 24/64 figure 5. switching from asynchronous to synchronous write operation figure 6. refresh collision during synchronous read operation in variable latency mode 1. additional wait states are in serted to allow refresh completion. the latency is set to 3 clo ck cycles (bcr13-bcr11 = 010). the wait must be active low, v il , (bcr10 = 0) and asserted during delay (bcr8= 0). addr. k ai10203 e w l valid tavwl telkh a0-a22 wait dq0-dq15 k additional wait states inserted to allow refresh completion address valid ai11275b l e g w hi z hi z lb/ub q0 q1 q2 q3
M69KB128AB configuration registers 25/64 7 configuration registers the M69KB128AB features three registers: the bus configuration register (bcr) the refresh configuration register (rcr) the device id register (didr). bcr and rcr are user-programmable registers that define the device operating mode. they are automatically loaded with default settings during power-up, and selected by address bits a18 and a19 (see table 8: register selection ). didr is a read-only register that contains info rmation about the device identification. it is selected by setting address bit a18 to ?1? with a19 ? don?t care? (see table 8: register selection ). the configuration registers (only bcr and rcr) can be programmed and read using two methods: the cr controlled method (or hardware method) the software method. 7.1 programming the registers by the cr controlled method 7.1.1 read confi guration register the content of a register is read by issuing a read operation with configuration register enable signal, cr, high, v ih . address bits a18 and a19 select the register to be read (see table 8: register selection ). the value contained in the register is then available on data bits dq0 to dq15. the bcr, rcr and didr can be read either in normal asynchronous or synchronous mode. the cr pin has to be driven high prior to any access. see ta bl e 6 and ta bl e 7 for a detailed description of configuration register read by the cr controlled methods and figure 17 and figure 28 , cr controlled configuration register read waveforms in asynchronous and synchronous mode.
configuration registers M69KB128AB 26/64 7.1.2 program conf iguration register bcr and rcr registers can be programmed by issuing a bus write operation, in asynchronous or synchronous mode (nor-flash or full synchronous), with configuration register enable signal, cr, high, v ih . address bits a18 and a19 allow to select between bcr and rcr (see table 8: register selection ). in synchronous mode, the values placed on address lines a0 to a15 are latched on the rising edge of l , e , or w , whichever occurs first. in asynchronous mode, a register is programmed by toggling l signal. lb and ub are ?don?t care?. the cr pin has to be driven high prior to any access. refer to ta b l e 5 and ta bl e 7 for a detailed description of configuration register program by the cr controlled method and to figure 22 and figure 33 , showing cr controlled configuration register program waveforms in asynchronous and synchronous mode. 7.2 programming and reading th e registers by the software method all registers (bcr, rcr, didr) can be read by issuing a read configuration register sequence (see figure 8: read configuration register (software method) . bcr and rcr can be programmed by issuing a set configuration register sequence (see figure 7: set configuration register (software method) . the timings will be identical to those described in table 17: asynchronous read ac characteristics . the configuration register enable input, cr, is ?don?t care?. read configuration register and set configuration register sequences both require 4 read or write cycles. these cycles will be executed in asynchronous mode, whatever the device operating mode: 1. 2 bus read and one bus write cycles to a unique address location, 7fffffh, indicate that the next operation will read or write to a configuration regist er. the data written during the third cycle must be ?0000h? to access the rcr, ?0001h? to access the bcr and ?0002h? to access the didr during the next cycle. 2. the fourth cycle reads from or writes to the configuration register. the timings for programming and reading the registers by the software method are identical to the asynchronous write and read timings. table 8. register selection register read or write operation a18 a19 rcr read/write 0 0 bcr read/write 0 1 didr read-only 1 x
M69KB128AB configuration registers 27/64 figure 7. set configuration register (software method) 1. only the bus configuration register (bcr) and the refresh configuration regi ster (rcr) can be modified. 2. to program the bcr or the rcr on last bus write cycl e, dq0-dq15 must be set to ?0001h? and ?0000? respectively. 3. the highest order address location is not modified during this operation. 4. the control signal e must be toggled as shown in the above figure. figure 8. read configuration register (software method) 1. to read the bcr, rcr or didr on last bus read cycle, dq0- dq15 must be set to ?0001h?, ?0000? and ?0002? respectively. 2. the highest order address location is not modified during this operation. 3. the control signal e must be toggled as shown in the above figure. addr. 7fffffh e g w lb, ub ai12461 7fffffh 7fffffh 7fffffh dq0-dq15 (2) configuration register data t ehel2 t ehel2 t ehel2 invalid data invalid data 7fffffh addr. 7fffffh e g w lb, ub ai12462b 7fffffh 7fffffh 7fffffh dq0-dq15 (1) configuration register data tehel2 tehel2 tehel2 invalid data invalid data
configuration registers M69KB128AB 28/64 7.3 bus configuration register the bus configuration register (bcr) defines how the psram interacts with the system memory bus. all the device operating modes are configured through the bcr, except the page mode which is configured through the rcr. refer to ta b l e 9 for the description of the bus configuration register bits. 7.3.1 operating mode bit (bcr15) the operating mode bit allows the synchronous mode or the asynchronous mode (default setting) to be selected. selecting the synchr onous mode will allow the device to operate either in nor flash mode or in full synchronous burst mode. the device will automatically dete ct that the nor flash mode is being used by monitoring a rising edge of the clock signal, k, when l is low. if this should not be the case, the device operates in full synchronous mode. 7.3.2 latency type (bcr14) the latency type bit is used to configure the latency type. when the latency type bit is set to ?0?, the device operates in variable latency mode (only available for synchronous read mode). when it is ?1?, the fixed latency mode is selected and the latency is defined by the values of bits bcr13 to bcr11. refer to ta b l e 3 and ta bl e 4 for examples of fixed and variable latency configuration. 7.3.3 latency counter bits (bcr13-bcr11) the latency counter bits are used to set the number of clock cycles between the beginning of a read or write operation and the first data output or input. the latency counter bits can only assume the values shown in table 9: bus configuration register definition (see also figure 3 and figure 4 ). 7.3.4 wait polarity bit (bcr10) the wait polarity bit indicates whether the wait output signal is active high or low. as a consequence, it also determines whether the wait signal requires a pull-up or pull-down resistor to maintain the de-asserted state (see figure 10: wait polarity ). by default, the wait output signal is active high. 7.3.5 wait confi guration bit (bcr8) the system memory microcontroller uses the wait signal to control data transfer during synchronous burst read and write operations. the wait configuration bit is used to determine when the transition of the wait output signal between the asserted and the deasserted state occurs with respect to valid data available on the data bus. when the wait configur ation bit is set to ?0?, data is valid or invalid on the first clock rising edge immediately after the wait signal transition to the deasserted or asserted state. when the wait configuration bit is set to ?1? (default settings), the wait signal transition occurs one clock cycle prior to the data bus going valid or invalid. see figure 9: wait configuration example for an example of wait configuration.
M69KB128AB configuration registers 29/64 7.3.6 driver strengt h bits (bcr5-bcr4) the driver strength bits allow to set the output drive strength to adjust to different data bus loading. normal driver strength (full drive) and reduced driver strength (half drive and a quarter drive) are available. by default, outputs are configured at ?half drive? strength. 7.3.7 burst wrap bit (bcr3) burst read operations can be confined inside the 4, 8, 16 or 32 word boundary (wrap) or allowed to step across the boundary (no wrap). the burst wrap bit is used to select between ?wrap? and ?no wrap?. if the burst wrap bit is set to ?1? (no wrap), the device outputs data sequentially regardless of burst boundaries. when continuous burst operation is selected, the internal address switches to 000000h if the read address passes the last address. by default, burst wrap is disabled (see also table 10: burst type definition ). 7.3.8 burst length bits (bcr2-bcr0) the burst length bits set the number of words to be output or input during a synchronous burst read or write operation. they can be set for 4 words, 8 words, 16 words, 32 words or continuous burst (default settings), where all the words are output or input sequentially regardless of address boundaries (see also table 10: burst type definition ).
configuration registers M69KB128AB 30/64 table 9. bus configuration register definition address bits bus configuration register bits name value description a15 bcr15 operating mode bit 0 synchronous mode (nor flash or full synchronous mode) 1 asynchronous mode (default) a14 bcr14 latency type 0 variable latency (default) 1 fixed latency a13-a11 bcr13- bcr11 latency counter bits 010 3 clock cycles 011 4 clock cycles (default) 100 5 clock cycles 101 6 clock cycles 110 7 clock cycles other configurations reserved (1) a10 bcr10 wait polarity bit 0 wait active low 1 wait active high (default).see figure 10: wait polarity . a9 - - must be set to ?0? reserved (1) a8 bcr8 wait configuration bit 0 wait asserted during delay (see figure 9: wait configuration example ). 1 wait asserted one clock cycle before delay (default) a7-a6 - - must be set to ?0? reserved (1) a5-a4 bcr5-bcr4 driver strength bits 00 full drive 01 1/2 drive (default) 10 1/4 drive 11 reserved (1) a3 bcr3 burst wrap bit 0wrap 1 no wrap (default) a2-a0 bcr2-bcr0 burst length bit 001 4 words 010 8 words 011 16 words 100 32 words 111 continuous burst (default) other configurations reserved (1) 1. programming the bcr with reserved value will forc e the device to use the default register settings.
M69KB128AB configuration registers 31/64 table 10. burst type definition mode start add 4 words (sequential) bcr2- bcr0=001b 8 words (sequential) bcr2-bcr0=010b 16 words (sequential) bcr2-bcr0=011b 32 words (sequential) bcr2-bcr0=100b continuous burst bcr2-bcr0=111b wrap (bcr3=?0?) 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-...-1 4-15 0-1-2-3-...-30-31 0-1-2-3-..-511-. 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-...-14-15 -0 1-2-3-...-30-31-0 1-2-3-4-...-510-511- 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-...-1 5-0-1 2-3-4-...-31-0-1 2-3-4-5-6-...-511- 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-...-15-0-1-2 3-4-5-...-31-0-1-2 3-4-5-...-511- 4 4-5-6-7-0-1-2-3 4-5-...-15-0-1-2-3 4 -5-6-...-31-0-1-2-3 4-5-...-511- 5 5-6-7-0-1-2-3-4 5-6-7-...-15-0-1-...-4 5-6-7-..-31-0-1-..-4 5-6-7-...-511- 6 6-7-0-1-2-3-4-5 6-7-8-...-15-0-1-...-5 6-7-8-...-31-0-1-...-5 6-7-8-...-511- 7 7-0-1-2-3-4-5-6 7-8-9-...15-0-1-...- 6 7-8-9-...-31-0-1- ...-6 7-8-9-...-511- ... ... ... ... ... ... 14 14-15-0-1-2-...-13 14-15-...-31-0-...-13 14-...511- 15 15-0-1-2-...-14 15-0-1-...-31-0-...- 14 15-...511- ... ... ... ... ... ... 30 30-31-0-...-28-29 30-...-511- 31 31-0-1-...-29-30 31-...-511- no wrap (bcr3=?1?) 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-...-1 4-15 0-1-2-3-...-30-31 0-1-2-3-..-511-. 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-..-15- 16 1-2-3-4-...-32 1-2-3-4-...-512- 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-... -17 2-3-4-...-33 2 -3-4-5-...-513- 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-.. .-18 3-4-5-...-34 3-4-5-...-514- 4 4-5-6-7-8-9-10-11 4-5-6-...- 19 4-5-6-...-35 4-5-6-...-515- 5 5-6-7-8-9-10-11-12 5-6-7-... -20 5-6-7-...-3 6 5-6-7-...-516- 6 6-7-8-9-10-11-12-13 6-7-8-...- 21 6-7-8-...-37 6-7-8-...-517- 7 7-8-9-10-11-12-13-1 4 7-8-9-...-22 7-8-9-. ..-38 7-8-9-...-518- ... ... ... 14 14-15-...-29 14-15-16-...-46 14-...-525- 15 15-16-17-...-30 15-16-17-...-47 15-...-526- ... ... ... 30 30-31-0-...-28-62 30-...-541- 31 31-0-1-...-29-63 31-...-542-
configuration registers M69KB128AB 32/64 figure 9. wait configuration example figure 10. wait polarity 7.4 refresh configuration register the role of the refresh configuration register (rcr) is: to define how the self refresh of the psram array is performed, to select the deep power-down mode, to enable page read operations. refer to ta b l e 1 1 for the description of the refresh configuration register bits. 7.4.1 page mode operation bit (rcr7) the page mode operation bit determines whether the asynchronous page read mode is enabled. at power-up, the rcr7 bit is set to ?0 ?, and the asynchronous page read mode is disabled. ai06795c dq0-dq15 bcr8='0', bcr10='0' data valid during current cycle k wait data[0] data[1] hi-z data[0] hi-z dq0-dq15 bcr8='1', bcr10='0' data valid during next cycle ai09963b dq0-dq15 k bcr8='0' bcr10='0' data[0] data[1] hi-z dq0-dq15 data[0] data[1] hi-z wait wait bcr8='0' bcr10='1'
M69KB128AB configuration registers 33/64 7.4.2 deep power-down bit (rcr4) the deep power-down bit enables or disables all refresh-related operations. the deep power-down mode is enabled when the rcr4 bit is set to ?0?, and remains enabled until this bit is set to ?1?. at power-up, th e deep power-down mode is disabled. see the section 4.2: deep power-down for more details. 7.4.3 partial array re fresh bits ( rcr2-rcr0) the partial array refresh bits allow refresh operations to be restricted to a portion of the total psram array. the refresh options can be full array, one half, one quarter, one eighth or none of the array. these memory areas can be located either at the top or bottom of the memory array. by default, the full memory array is refreshed. table 11. refresh configuration register definition address bits refresh configuration register bits name value description a15-a8 - - must be set to ?0? reserved a7 rcr7 page mode operation bit 0 page read mode disabled (default) 1 page read mode enabled a6-a5 - - must be set to ?0? reserved a4 rcr4 deep power- down bit 0 deep power-down enabled 1 deep power-down disabled (default) a3 - - must be set to ?0? reserved a2-a0 rcr2-rcr0 partial array refresh bits 000 full array refresh (default) 001 refresh of the bottom half of the array 010 refresh of the bottom quarter of the array 011 refresh of the bott om eighth of the array 100 none of the array 101 refresh of the top half of the array 110 refresh of the top quarter of the array 111 refresh of the top eighth of the array
configuration registers M69KB128AB 34/64 7.5 device id register the device id register (didr) is a read-only register that contains the manufacturer code. it is preprogrammed by stmicroelectronics and cannot be modified by the user. refer to ta b l e 1 2 for the description of the bus configuration register bits. table 12. device id register definition address bits device id register bits name value description a15 didr15 row length 0 128 words 1 256 words a14-a11 didr14-didr11 design version 0000 a 0001 b 0010 c 0011 d 1111 p other configurations reserved a10-a8 didr10-didr8 device density 000 16 mbits 001 256 mbits 010 64 mbits 011 128 mbits 100 32 mbits other configurations reserved a7-a5 didr7-didr5 psram generation 001 1.0 010 1.5 011 2.0 other configurations reserved a4-a0 didr4-didr0 device id 00001 cypress 00010 infineon 00011 micron 00100 renesas 01111 stmicroelectronics other configurations reserved
M69KB128AB maximum rating 35/64 8 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device relia bility. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. refer also to the stmicroelectronics sure program and other relevant quality documents. table 13. absolute maximum ratings symbol parameter min. max. unit t a ambient operating temperature ?30 +85 c t stg storage temperature ?55 150 c v cc core supply voltage ?0.2 2.45 v v ccq input/output buffer supply voltage ?0.2 2.45 v v io input or output voltage ?0.2 2.45 v
dc and ac parameters M69KB128AB 36/64 9 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 14: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 11. ac measurement i/o waveform 1. logic states ?1? and ?0? correspond to ac test inputs driven at v ccq and v ss respectively. input timings begin at v ccq /2 and output timings end at v ccq /2. figure 12. ac input transitions table 14. operating and ac measurement conditions parameter (1) 1. all voltages are referenced to v ss . min max unit v cc supply voltage 1.7 1.95 v v ccq input/output buffer supply voltage 1.7 1.95 v load capacitance (c l )30pf output circuit protection resistance (r) 50 ? input pulse voltages (2) 2. v cc =v ccq 0v cc v input and output timing ref. voltages (2) v cc /2 v input rise time t r and fall time t f (2)(3) 3. referenced to v ss . 1v/ns ai09484c v ccq i/o timing reference voltage v ssq v ccq /2 90% 10% 90% 10% v cc typ v ss t r t f ai10122
M69KB128AB dc and ac parameters 37/64 figure 13. ac measurement load circuit table 15. capacitance symbol parameter test condition min. max. unit c in input capacitance t a = 25c, f = 1mhz, v in = 0v 26pf c io data input/output capacitance 3.5 6 pf ai11289 v ccq /2 out device under test c l r
dc and ac parameters M69KB128AB 38/64 table 16. dc characteristics symbol parameter refreshed array test conditions min. typ. max. unit v oh (1) output high voltage i oh = ?0.2ma 0.8v ccq v v ol (1) output low voltage i ol = 0.2ma 0.2v ccq v v ih (2) input high voltage v ccq ?0.4 v ccq + 0.2 v v il (3) input low voltage ?0.2 0.4 v i li input leakage current v in = 0 to v ccq 1a i lo output leakage current g = v ih or e = v ih 1a i cc1 (4) asynchronous read/write random at t rc min v in = 0v or v ccq , i out = 0ma, e = v il 70ns 25 ma i cc2 (4) asynchronous page read v in = 0v or v ccq i out = 0ma, e = v il 70ns 15 ma i cc3 (4) burst, initial read/write access v in = 0v or v ccq i out = 0ma, e = v il 104mhz 35 ma 80mhz 30 ma i cc4r (4) continuous burst read v in = 0v or v ccq i out = 0ma, e = v il 104mhz 30 ma 80mhz 25 ma i cc4w (4) continuous burst write v in = 0v or v ccq i out = 0ma, e = v il 104mhz 35 ma 80mhz 30 ma i pasr (4) partial array refresh standby current full array v in = 0v or v ccq e = v ccq 200 a 1/2 array 170 a 1/4 array 155 a 1/8 array 150 a none 140 a i sb (5) standby current v in = 0v or v ccq , e = v ccq 200 a i ccpd deep-power down current v in = 0v or v ccq , v cc , v ccq = 1.95v; t a = +85c 310a 1. bcr5-bcr4 = 01 (default settings). 2. input signals may overshoot to v ccq + 1.0v for periods of less than 2ns during transitions. 3. output signals may undershoot to v ss ? 1.0v for periods of less than 2ns during transitions. 4. this parameter is specified with all outputs disabled to avoid external loading effects. the user must add the current required to drive output capacitance expected for the actual system. 5. i sb maximum value is measured at +85c with par set to full array. in order to achieve low standby current, all inputs must be driven either to v ccq or v ssq . i sb might be slightly higher for up to 500ms after power-up, or when entering standby mode.
M69KB128AB dc and ac parameters 39/64 table 17. asynchronous read ac characteristics symbol alt. parameter (1) 70ns unit min max t avqv t aa address valid to output valid 70 ns t avlh t rhlh t avs address valid to l high configuration register high to l high 5ns t blqv t ba upper/lower byte enable low to output valid 70 ns t bhqz (2) t bhz upper/lower byte enable high to output hi-z 8 ns t blqx (3) t blz upper/lower byte enable low to output transition 10 ns t eltv t cew chip enable low to wait valid 1 7.5 ns t elqv t co chip enable low to output valid 70 ns t ellh t cvs chip enable low to l high 7 ns t ehel t cph chip enable high between subsequent asynchronous operations 5ns t ehqz (2) t hz output enable high to output hi-z chip enable high to output hi-z 8ns t elqx (3) t lz chip enable low to output transition 10 ns t glqv t oe output enable low to output valid 20 ns t ghqz (2) t ohz output enable low to output hi-z 8 ns t glqx (3) t olz output enable low to output transition 3 ns t avax t rc read cycle time 70 ns t lllh t vp latch enable low pulse width 5 ns t lhll t vph latch enable high pulse width 10 ns t llqv t aadv latch enable low to output valid 70 ns t lhax t lhrl t avh latch enable high to address transition latch enable high to configuration register low 2ns 1. these timings have been obtained in the measurement conditions described in table 14: operating and ac measurement conditions and figure 13: ac measurement load circuit . 2. the hi-z timings measure a 100mv transition from either v oh or v ol to v ccq /2. 3. the low-z timings measure a 100m v transition from the hi-z (v ccq /2) level to either v oh or v ol . table 18. asynchronous page read ac characteristics symbol alt. parameter (1) 70ns unit min max t avqv1 t apa page access time 20 ns t avav t pc page cycle time 20 ns t eleh t cem maximum chip enable pulse width 4 s t avqx t oh data hold from address change 5 ns 1. these timings have been obtained in the measurement conditions described in table 14: operating and ac measurement conditions and figure 13: ac measurement load circuit .
dc and ac parameters M69KB128AB 40/64 figure 14. asynchronous random read ac waveforms ai11276c addr. wait valid address tehqz tblqv hi-z hi-z tavax telqv tbhqz tghqz tglqv teltv valid output hi-z telqx tglqx e lb/ub g w dq0-dq15 tavqv hi-z tblqx l tehel
M69KB128AB dc and ac parameters 41/64 figure 15. latch enable controlled, asynchronous random read ac waveforms figure 16. asynchronous page read ac waveforms (4 words) 1. any address can be used as starting address. ai09474f addr. valid address tehqz tblqv telqv tbhqz tglqv valid output hi-z telqx tglqx l e lb/ub g dq0-dq15 tavqv hi-z tblqx tavlh tlhax tllqv tlllh tellh tehel tlhll tghqz ai09478e a2-a22 valid address tavax tglqv, tblqv tbhqz, tehqz, tghqz hi-z e g, lb,ub dq0-dq15 page address a0-a1 x y tavav dqn+a dqn+z dqn+y dqn+x l za tavav tavav teleh tavqv tavqv1 tavqx telqv tlhll
dc and ac parameters M69KB128AB 42/64 figure 17. cr controlled confi guration register read followed by read, asynchronous mode 1. a18-a19 must be set to ?00b? to select rcr, ?01b? to select the bcr and ?1xb? to select the didr. addr. (except a18-a19) address address a18-19 initiate configuration register access cr trhlh tlllh tlhll tehel telqv select configuration register l e g w ai09471c configuration register data valid dq0-dq15 lb/ub tlhrl data valid tavqv tllqv tehqz tglqx telqx
M69KB128AB dc and ac parameters 43/64 table 19. asynchronous write ac characteristics symbol alt. parameter (1) 70ns unit min max t avbl , t avel , t avwl , t llwl t as address set-up to beginning of write operation 0 ns t avlh , t rhlh t avs address valid to latch enable high configuration register high to latch enable high 5ns t avwh , t aveh , t avbh t aw address set-up to end of write operation 70 ns t avax t wc write cycle time 70 ns t blbh , t bleh t blwh t bw upper/lower byte enable low to end of write operation 70 ns t eltv t cew chip enable low to wait valid 1 7.5 ns t ehel t cph chip enable high between subsequent asynchronous operations 5ns t ellh t cvs chip enable low to l high 7 ns t elwh t eleh t elbh t cw chip enable low to end of write operation 70 ns t ehdx , t whdx , t bhdx t dh input hold from write 0 ns t elwh , t dvbh , t dveh t dvwh tdw input valid to write setup time 20 ns t ehtz , t bhtz (2) t hz chip enable high to wait hi-z lb /ub high to wait hi-z write enable high to wait hi-z 8ns t lhax , t lhrl t avh latch enable high to address transition or latch enable high to configuration register low 2ns t lllh t vp latch enable low pulse width 5 ns t lhll t vph latch enable high pulse width 10 ns t llwh t vs latch enable low to write enable high 70 ns t whqz t whz beginning of asynchronous write to data output hi-z 10 ns t wlbh , t wleh , t wlwh (3) t wp write pulse width 45 ns t whwl t wph write enable pulse width high 10 ns t whax , t ehax , t bhax t wr write recovery time 0 ns 1. these timings have been obtained in the measurement conditions described in table 14: operating and ac measurement conditions and figure 13: ac measurement load circuit . 2. the hi-z timings measure a 100mv transition from either v oh or v ol to v ccq /2. the low-z timings measure a 100mv transition from the hi-z (v ccq /2) level to either v oh or v ol . 3. w low time must be limited to t ehel .
dc and ac parameters M69KB128AB 44/64 figure 18. chip enable controlled, asynchronous write ac waveforms 1. data inputs are hi-z if e is high, v ih . dq0-dq15 valid address hi-z hi-z tavax teltv valid input taveh tehax teleh tdveh tbleh hi-z tehdx twleh twhwl ai11284b addr. g wait lb/ub w l e tavel, tavbl tehtz tehel
M69KB128AB dc and ac parameters 45/64 figure 19. upper/lower byte enable controlled, asynchronous write ac waveforms 1. data inputs are hi-z if e is high, v ih . dq0-dq15 in valid address hi-z hi-z tavax teltv valid input tavbh tbhax telbh tdvbh tblbh hi-z tbhdx twlbh twhwl ai11285b addr. g wait lb/ub w l e tbhtz dq0-dq15 out hi-z don't care telqx twlqz
dc and ac parameters M69KB128AB 46/64 figure 20. write enable controlled, asynchronous write ac waveforms 1. data inputs are hi-z if e is high, v ih . dq0-dq15 valid address hi-z hi-z tavax teltv valid input tavwh twhax telwh tdvwh tblwh hi-z twhdx twlwh twhwl ai11282b addr. g wait lb/ub w l e tavwl
M69KB128AB dc and ac parameters 47/64 figure 21. l controlled, asynchronous write ac waveforms 1. data inputs are hi-z if e is high, v ih . dq0-dq15 valid address hi-z hi-z tavlh teltv valid input tlhax tllwh telwh tdvwh tblwh hi-z tehdx twlwh twhwl ai11283c addr. g wait lb/ub w l e tlhll tlllh tavwh tllwl
dc and ac parameters M69KB128AB 48/64 figure 22. cr controlled configuration register program, asynchronous mode 1. only the content of the bus configuration register (b cr) and refresh configuration register (rcr) can be modified. 2. data inputs/outputs are not used. 3. the opcode is the value to be wr itten the configuration register. 4. w must go high after l goes high 5. cr is latched on the rising edge of l . there is no setup requirement of cr with respect to e . ai09467f addr. (except a18-a19) opcode (3) tlhll l e g w a18-a19 00(rcr), 01 (bcr) tlllh twlwh cr a0-a15 latched into register trhlh tlhrl lb, ub access to configuration register tlhax tavlh table 20. clock related ac timings symbol alt. parameter 104 mhz 80 mhz unit min. max. min. max. f clk f clk clock frequency 104 80 mhz t khkh t clk clock period 9.62 12.5 ns t r t f t khkl clock rise time clock fall time 1.6 1.8 ns t khkl t klkh t kp clock high to clock low clock low to clock high 34ns t khdz t khz clock high to output hi-z 3838ns t khdx t klz clock high to output transition 2525ns
M69KB128AB dc and ac parameters 49/64 table 21. synchronous burst read ac characteristics symbol alt. parameter (1) 104 mhz 80 mhz unit min. max. min. max. t avqv t aa address valid to output valid (fixed latency) 70 70 ns t llqv t aadv latch enable low to output valid (fixed latency) 70 70 ns t khqv1 t aba burst to read access time (variable latency) 35 46 ns t khqv2 t aclk clock high to output delay 7 9 ns t glqv t boe delay from output enable low to output valid in burst mode 20 20 ns t ehel (2) t cbph chip enable high between subsequent operations in full-synchronous or nor-flash mode. 56ns t eleh (2) t cem chip enable pulse width 4 4 s t eltv t lltv t cew chip enable low to wait valid latch enable low to wait valid 1 7.5 1 7.5 ns t elqv t co chip enable low to output valid 70 70 ns t elkh t csp chip enable low to clock high 3 4 ns t khax t khbh t khwl t kheh t khlh t khqx t hd hold time from active clock edge 2 2 ns t ehqz t ehtz (3) t hz chip enable high to output hi-z or wait hi-z 8 8 ns t khtx t khtv t khtl clock high to wait valid 7 9 ns t khqx1 t klz clock high to output transition 2 5 2 5 ns t khqx2 t koh output hold from clock high 2 2 ns t ghqz (3) t ohz output enable high to output hi-z 8 8 ns t glqx (4) t olz output enable low to output transition 3 3 ns t avkh t rhkh t qvkh t llkh t blkh t whkh t sp set-up time to active clock edge 3 3 ns 1. these timings have been obtained in the measurement conditions described in table 14: operating and ac measurement conditions and figure 13: ac measurement load circuit . 2. a refresh opportunity must be offered every t eleh . a refresh opportunity is possible either if e is high during the rising edge of k; or if e is high for longer than 15ns. 3. the hi-z timings measure a 100mv transition from either v oh or v ol to v ccq /2. 4. the low-z timings measure a 100m v transition from the hi-z (v ccq /2) level to either v oh or v ol .
dc and ac parameters M69KB128AB 50/64 figure 23. clock input ac waveform figure 24. 4-word synchronous burst read ac waveforms (variable latency mode) 1. the latency is set to 3 cloc k cycles (bcr13-bcr11 = 101). the wait signal is active low (bcr10=0), and is asserted during delay (bcr8=0). ai06981 tkhkh tf tr tkhkl tklkh addr. wait d0-d15 k tavkh tkhkh tkhax tkhqv1 valid address tkhqx2 tehqz tkheh tllkh tglqx tehel telkh twhkh tkhwl tblkh tghqz tkhkl read burst identified tkhtx hi-z hi-z hi-z tglqv ai11286d e g w lb/ub (w = high) teltv tkhqv2 l tkhlh valid output valid output valid output valid output teleh tkhbh tlhll
M69KB128AB dc and ac parameters 51/64 figure 25. synchronous burst read suspend and resume ac waveforms 1. the latency type (bcr14) can be set to fixed or variable during burst read su spend operations.the latency is set to 3 clock cycles (bcr13-bcr11 = 101). the wait signal is active low (bcr 10=0), and is asserted during delay (bcr8=0). 2. during burst read suspend operations, the clock signal must be stable (high or low). 3. g can be held low, v il , during burst suspend operations. if so, data output remain valid. don't care don't care addr. wait d0-d15 k tavkh tkhax tkhqx2 tehqz tllkh tglqx tehel telkh twhkh tkhwl tblkh tghqz tavlh tkhkl hi-z valid output hi-z hi-z ai11287d e g w lb/ub tkhqv1 l valid output valid address valid address tglqv tghqz valid output valid output valid output valid output tkhlh tglqv tkhtx don't care
dc and ac parameters M69KB128AB 52/64 figure 26. synchronous burst read showing e nd-of-row condition ac waveforms (no wrap) 1. the wait signal is active low (bcr10=0) , and is asserted during delay (bcr8=0). addr. dq0-dq15 k tkhtv tkhkh tklkh, tkhkl tf wait ai11574a e g lb/ub w don't care don't care tehtz l valid output valid output low low low high high-z end of row
M69KB128AB dc and ac parameters 53/64 figure 27. burst read interrupted by burst read or write ac waveforms 1. the latency type (bcr14) can be set to fixed or variab le.the latency is set to 3 clo ck cycles (bcr13-bcr11 = 101). wait is active low (bcr10=0), and is as serted during delay (bcr8=0). all burst op erations are given for variable latency and no refresh collision. 2. the burst read is interrupted during the fi rst allowable clock cycle, i.e. after th e first data is received by the microcontr oller. 3. e can remain low, v il , between burst operations, but it must not remain low for longer than t eleh . 4. if the latency is variable, wait is asserted t khtv after l is clocked low. if the latency is fixed, wait is asserted t lltv after l falling edge. hi-z addr. wait d0-d15 2nd read cycle k tavkh tkhkh tkhax valid address tkhqx2 tkheh tllkh telkh twhkh tkhwl tkhtv hi-z tglqv ai11292b e g 2nd read cycle w lb/ub 2nd read cycle tkhqv2 l tkhlh valid output teleh (3) valid address burst read interrupted by new burst read or write (2) tavkh tkhax tllkh tkhlh twhkh tkhwl hi-z note 4 tlltv hi-z tghqz tghqz valid output valid output valid output valid output d0-d15 2nd write cycle g 2nd write cycle lb/ub 2nd write cycle high valid input hi-z valid input valid input valid input tkhqv2 tkhqx2 tdvkh tkhdx tglqv
dc and ac parameters M69KB128AB 54/64 figure 28. cr controlled configuration register read followed by read, synchronous mode 1. a18-a19 must be set to ?00b? to select rcr, ?01b? to select bcr and ?1xb? to select the didr. address address data valid addr. (except a18-a19) k tavkh l e w cr a18-a19 g dq0-dq15 ub, lb wait cr valid tkhrl ai10132f trhkh tllkh tkhlh telkh tehel tehqz tghqz teltv tglqx tkhqv2 high high-z tkhqx2 tkhax tkhqv1 tblkh tglqv tllkh tblkh tglqv
M69KB128AB dc and ac parameters 55/64 table 22. synchronous burst write ac characteristics symbol alt. parameter (1) 1. these timings have been obtained in t he measurement conditi ons described in table 14: operating and ac measurement conditions and figure 13: ac measurement load circuit . 104mhz 80mhz unit min max min max t avwl t llwl (2) 2. t avwl and t llwl , are required if t elkh > 20ns. t as address set-up to beginning of write operation 00ns t avkh t dvkh t wlkh t llkh t blkh t whkh t whwl t sp set-up time to active clock edge 3 3 ns t ehel (3) 3. a refresh opportunity must be offered every t eleh . a refresh opportunity is possible either if e is high during the rising edge of k; or if e is high for longer than 15ns. t cbph chip enable high between subsequent operations in full-synchronous or nor- flash mode. 56ns t eleh (3) t cem maximum chip enable low pulse 4 4 s t eltv t lltv t cew chip enable low to wait valid 1 7.5 1 7.5 ns t elkh t csp chip enable low to clock high 3 4 ns t khax t khrl t khlh t khdx t kheh t khbh t khwh t hd hold time from active clock edge 3 3 ns t khll t kadv last clock rising edge to latch enable low 15 15 ns t ehdz t ehtz (4) 4. the hi-z timings measure a 100mv transition from either v oh or v ol to v ccq /2. t hz chip enable high to input hi-z or wait hi-z 88ns t khtv tkhtx t khtl clock high to wait valid or low 7 9 ns t lhax t avh latch enable high to address transition (fixed latency) 22ns
dc and ac parameters M69KB128AB 56/64 figure 29. 4-word synchronous burst write ac waveforms (variable latency mode) 1. the latency is set to 3 cloc k cycles (bcr13-bcr11 = 101). the wait sign al is active low (b cr10=0), and asserted during delay (bcr8=0). 2. the wait signal must remain assert ed for lc clock cycles (l c latency code), whatever the latency mode (fixed or variable). 3. t avll and t llwl , are required if t elkh > 20ns. addr. wait d0-d15 k tkhkh valid address tkhdx telkh twlkh tkhwh tavkh write burst identified tkhtx hi-z valid input hi-z hi-z ai11288b e g w (w = low) tkheh tehel tblkh lb/ub teltv tdvkh l valid input valid input valid input teleh tkhax tavwl tllwl tllkh tkhlh tkhll high tehtz note 2
M69KB128AB dc and ac parameters 57/64 figure 30. synchronous burst write showing e nd-of-row condition ac waveforms (no wrap) 1. the wait signal is active low (bcr10=0) , and is asserted during delay (bcr8=0). don't care addr. dq0-dq15 k tkhkh tklkh tf wait ai11575b e g lb/ub w don't care l tkhdx tdvkh valid input d[n] valid input d[n+1] end of row (a6-a0 = 7fh) high tkhtv tehtz high-z low
dc and ac parameters M69KB128AB 58/64 figure 31. synchronous burst write followed by read ac waveforms (4 words) 1. the latency type can set to fixed or variable mode. the latency is set to 3 cl ock cycles (bcr13-bcr11 = 101). the wait signal is active low (bcr10=0), and is asserted during delay (bcr8=0). 2. e can remain low between the burst read and burst write oper ation, but it must not be held low for longer than t eleh . addr. wait dq0- dq15 k tkhax ai11291b e g w l tkhkh d in0 d in1 d in2 d in3 ub, lb tklkh tkhkl tavkh tkhlh tllkh telkh twlkh tkhwh tdvkh tkhll tehel tghqz tglqx tkhqx2 d o0 d o1 d o2 d o3 tkhdx tkhax tavkh (2) tkheh telkh tkhlh tkheh tkhtx tkhtx twhkh tkhwl
M69KB128AB dc and ac parameters 59/64 figure 32. burst write interrupted by burst write or read ac waveforms 1. the latency type (bcr14) can be set to fixed or variab le.the latency is set to 3 clo ck cycles (bcr13-bcr11 = 101). wait is active low (bcr10=0), and is as serted during delay (bcr8=0). all burst op erations are given for variable latency and no refresh collision. 2. the burst write is interrupted during the first allowable cl ock cycle, i.e. after the first word written to the memory. 3. e , can remain low, v il , between burst operations, but it must not remain low for longer than t eleh . hi-z addr. wait d0-d15 2nd write cycle k tavkh tkhkh tkhax valid address tkhdx tkheh tllkh telkh twhkh tkhwh tkhtv hi-z ai11293b e g 2nd write cycle w lb/ub 2nd write cycle tdvkh l tkhlh valid input teleh (3) valid address burst write interrupted by new burst write or read (2) tavkh tkhax tllkh tkhlh twhkh tkhwl hi-z valid input d0-d15 2nd read cycle g 2nd read cycle lb/ub 2nd read cycle hi-z high valid input valid input valid input tkhdx tdvkh tglqv tghqz tglkh valid output valid output valid output valid output tkhqx tkhqv2 tkhbh
dc and ac parameters M69KB128AB 60/64 figure 33. cr controlled configuration register program, synchronous mode 1. only the configuration register (bcr) and the re fresh configuration register (rcr) can be modified. 2. data inputs/outputs are not used. 3. the opcode is the value to be written in the configuration register. 4. a19 gives the configuration register address. 5. cr initiates the configuration register access. addr. (3) k teleh hi-z ai10131d l e w cr (5) opcode a18-a19 (4) 00 (rcr) 01 (bcr) g ub, lb dq0-dq15 (2) wait tavkh tkhrl trhkh tllkh tkhlh tkhax twlkh tkhwh teltv
M69KB128AB dc and ac parameters 61/64 figure 34. power-up ac waveforms 1. power must be applied to v cc prior to or at the same time as v ccq . figure 35. deep power-down entry and exit ac waveforms table 23. power-up and deep power-down ac characteristics symbol alt. parameter min max unit t vchel t pu initialization delay after power-up or deep power-down exit 150 s t ehel(dp) t dpd deep power-down entry to deep power-down exit 10 s t eleh(dp) t dpdx chip enable low to deep power-down exit 10 s ai09465d v cc , v ccq tvchel 1.7v device ready for normal operation device initialization e ai11306 tehel(dp) device ready for normal operation e teleh (dp) deep power-down mode deep power-down entry (rcr4= 0) deep power-down exit tpu device initialization
part numbering M69KB128AB 62/64 10 part numbering the notation used for the device number is as shown in ta bl e 2 4 . not all combinations are necessarily available. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest stmicroelectronics sales office. table 24. ordering information scheme example: m69 k b 128 a b c w 8 device type m69 = psram mode k = bare die operating voltage b = v cc = 1.7 to 1.95v, burst, address/data bus standard x16 array organization 128 = 128 mbit (8mb x16) option 1 a = 1 chip enable option 2 b = b die maximum clock frequency c = 80mhz max clock frequency in burst read mode d = 104mhz max clock frequency in burst read mode package w = wafer form operating temperature 8 = ?30 to 85 c
M69KB128AB revision history 63/64 11 revision history table 25. document revision history date revision changes 07-jul-2006 1 initial release.
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