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| HT49C50 8-bit microcontroller 1 august 18, 1999 features operating voltage: 2.2v~5.2v 8 input lines 12 bidirectional i/o lines two external interrupt input two 8-bit programmable timer/event counter with pfd (programmable fre - quency divider) function lcd driver with 33 3or32 4 segments 4k 15 program memory rom 160 8 data memory ram real time clock (rtc) 8-bit prescaler for rtc watchdog timer buzzer output on-chip crystal and rc oscillator halt function and wake-up feature reduce power consumption 6-level subroutine nesting bit manipulation instruction 15-bit table read instruction up to 1 s instruction cycle with 4mhz system clock 63 powerful instructions all instructions in 1 or 2 machine cycles 80/100-pin qfp package general description the HT49C50 is an 8-bit high performance single chip microcontroller. its single cycle instruction and two-stage pipeline architecture make it suit - able for high speed applications. the device is suited for use in multiple lcd low power applica- tions among which are calculators, clock timers, games, scales, leisure products, other hand held lcd products, and battery system in particular.
block diagram HT49C50 2 august 18, 1999 ! " " # ! $ %& ' (& $") ' ! " * " * ' + %& "' $" ) * ,&& , -. /- + -/ + - + -/ & / 0 & 1 '" * ' &&,* & 1 ' $ pin assignment HT49C50 3 august 18, 1999 * * * * ' * $ * 2 * 3 * ) * 4 * 5 * * * * ' * $ * 2 * 3 * ) * 4 * 5 * * * * ' * $ , & , , * ' ' * ' * ' $ ,&& ' $ 2 3 ) 4 5 ' $ 2 3 ) 4 5 ' $ 3$ 3' 3 3 3 25 24 2) 23 22 2$ 2' 2 2 2 $5 $4 $) $3 $2 $$ $' $ $ 2 3 ) 4 5 ' ' ' '' '$ '2 '3 ') '4 '5 $ 32 33 3) 34 35 ) ) ) )' )$ )2 )3 )) )4 )5 4 ' (& $ 2 3 ) ' $ 2 3 ) ' , * ' * 5 * 3 * ) * 4 * 2 HT49C50 4 august 18, 1999 ' $ 2 3 ) 4 5 ' $ 2 3 ) 4 5 ' $ 2 3 ) 4 5 ' ' ' '' '$ '2 '3 ') '4 '5 $ $ $ $' $$ $2 $3 $)$4 $5 2 4 4 4' 4$ 42 43 4) 44 45 5 5 5 5' 5$ 52 53 5) 54 55 4 )5 )4 )) )3 )2 )$ )' ) ) ) 35 34 3) 33 32 3$ 3' 3 3 3 25 24 2) 23 22 2$ 2' 2 2 ' (& $ 2 3 ) ' $ 2 3 ) ' * $ * 2 * 3 * ) * 4 * 5 * ' * ' * ' ' , , , & , * * * * ' * $ * 2 * 3 * ) * 4 * 5 * * * * ' * $ * 2 * 3 * ) * 4 * 5 * * * * ' $ ' ,&& * pad assignment * the ic substrate should be connected to vss in the pcb layout artwork. HT49C50 5 august 18, 1999 ' $ 2 3 ) 4 5 ' $ 2 3 ) 4 5 ' $ 2 3 ) 4 5 ' ' ' '' '$ '2 '3 ') '4 '5 $ $ $ $' $$ $2 $3 $) $4 $5 2 2 2 2' 2$ 22 23 2) 24 25 3 3 3 3' 3$ 32 33 3) 34 6 7 8 ' (& $ 2 3 ) ' $ 2 3 ) ' , , & , , * ' ' * ' * ' * 5 * 4 * ) * 3 * 2 * $ * 5 * * * * ' * ' * $ * 2 * 3 * ) * 4 * ) * 4 * 5 * * * * * * ' * $ * 2 * 3 * $ ' ,&& * pin description pin name i/o mask option description pa0/bz pa1/bz pa2 pa3/pfd pa4~pa7 i/o wake-up pull-high or none cmos or nmos pa0~pa7 constitute an 8-bit bidirectional input/output port with schmitt trigger input capability. each bit on port can be configured as a wake-up input by mask option. pa0~pa3 can be configured as a cmos output or nmos input/output with or without pull-high resistor by mask option. pa4~pa7 are al - ways pull-high nmos input/output. of the eight bits, pa0~pa1 can be set as i/o pins or buzzer outputs by mask op - tion. pa3 can be set as an i/o pin or as a pfd output also by mask option. pb0/int0 pb1/int1 pb2/tmr0 pb3/tmr1 pb4~pb7 i pb0~pb7 constitute an 8-bit schmitt trigger input port. each bit on port are pull-high resistor. of the eight bits, pb0 and pb1 can be set as input pins or as external interrupt control pins (int0 ) and (int1 ) respectively, by software application. pb2 and pb3 can be set as an input pin or as a timer/event counter input pin tmr0 and tmr1 also by software application. pc0~pc3 i/o pull-high or none cmos or nmos pc0~pc3 constitute a 4-bit bidirectional input/output port with a schmitt trigger input capability. on the port, such can be configured as cmos output or nmos input/output with or without pull-high resistor by mask option. vss i negative power supply, gnd vlcd i lcd power supply v1,v2,c1,c2 i voltage pump seg32/com3 com2~com0 o 1/3 or 1/4 duty seg32 can be set as a segment or as a common output driver for lcd panel by mask option. com2~com0 are outputs for lcd panel plate. seg31~seg0 o lcd driver outputs for lcd panel segments osc4 osc3 o i real time clock oscillators vdd positive power supply osc2 osc1 o i crystal or rc osc1 and osc2 are connected to an rc network or a crystal (by mask option) for the internal system clock. in the case of rc operation, osc2 is the output terminal for 1/4 system clock. res i schmitt trigger reset input, active low HT49C50 6 august 18, 1999 absolute maximum ratings supply voltage........................v ss 0.3v to 5.5v storage temperature................. 50 cto125 c input voltage .................v ss 0.3v to v dd +0.3v operating temperature .............. 25 cto70 c note: these are stress ratings only. stresses exceeding the range specified under absolute maxi - mum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged expo - sure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 2.2 5.2 v i dd1 operating current (crystal osc) 3v no load, f sys =4mhz 12ma 5v 2.5 5 ma i dd2 operating current (rc osc) 3v no load, f sys =2mhz 0.75 1.5 ma 5v 1.5 3 ma i stb1 standby current (rtc enable, lcd on) 3v no load, system halt 5 a 5v 10 a i stb2 standby current (rtc disable, lcd off) 3v no load, system halt 1 a 5v 2 a v il i/o port input low voltage 3v 0 0.9 v 5v 0 1.5 v v ih i/o port input high voltage 3v 2.1 3v 5v 3.5 5v v il1 input low voltage (res , int0 , int1 , tmr0, tmr1) 3v res =0.5v dd int0/1 =0.3v dd tmr0/1=0.3v dd 0 1.5/0.9 v 5v 0 2.5/1.5 v v ih1 input high voltage (res , int0 , int1 , tmr0, tmr1) 3v 0.8v dd 2.4 3v 5v 4.0 5v i ol i/o ports sink current 3v v dd =3v, v ol =0.3v 1.5 2.5 ma 5v v dd =5v, v ol =0.5v 46 ma HT49C50 7 august 18, 1999 symbol parameter test conditions min. typ. max. unit v dd conditions i oh i/o ports source current 3v v dd =3v, v oh =2.7v 1 1.5 ma 5v v dd =5v, v oh =4.5v 2 3 ma r ph pull-high resistance of i/o ports and int0 , int1 3v 40 60 80 k 5v 10 30 50 k a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc) 3v v dd =3v 455 4000 khz 5v v dd =5v 455 4000 khz f sys2 system clock (rc osc) 3v v dd =3v 400 2000 khz 5v v dd =5v 400 3000 khz f timer timer i/p frequency (tmr0/tmr1) 3v v dd =3v 0 4000 khz 5v v dd =5v 0 4000 khz t wdtosc watchdog oscillator 3v v dd =3v 45 90 180 s 5v v dd =5v 35 65 130 s t res external reset low pulse width 1 s t sst system start-up timer period power-up or wake-up from halt 1024 t sys t int interrupt pulse width 1 s note: t sys = 1/f sys HT49C50 8 august 18, 1999 HT49C50 9 august 18, 1999 functional description execution flow the system clock is derived from either a crys - tal or an rc oscillator. it is internally divided into four non-overlapping clocks. one instruc - tion cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. the pipelining scheme causes each instruction to effectively execute in a cycle. if an instruction changes the value of the program counter, two cycles are re - quired to complete the instruction. program counter pc the program counter (pc) is of 12 bits wide and controls the sequence in which the instructions stored in the program rom are executed. the contents of the pc can specify a maximum of 4096 addresses. after accessing a program memory word to fetch an instruction code, the value of the pc is incremented by one. the pc then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip execution, loading a pcl register, a sub- routine call, an initial reset, an internal inter- rupt, an external interrupt, or returning from a subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instruc - tions. once the condition is met, the next in - struction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruc - tion; otherwise proceed with the next instruc - tion. the lower byte of the pc (pcl) is a readable and writeable register (06h). moving data into the pcl performs a short jump. the destina - tion is within 256 locations. when a control transfer takes place, an addi - tional dummy cycle is required. program memory rom the program memory (rom) is used to store the program instructions which are to be exe - cuted. it also contains data, table, and inter - rupt entries, and is organized into 4096 15 bits which are addressed by the pc and table pointer. certain locations in the rom are reserved for special usage: location 000h location 000h is reserved for program initial- ization. after chip reset, the program always begins execution at this location. ' $ ' $ ' $ ( / 6 8 * 9/- 6 :8 ( / 6 ; 8 * 9/- 6 8 ( / 6 ; 8 * 9/- 6 ;8 ; ; 1+ < /= 6 <18 execution flow HT49C50 10 august 18, 1999 location 004h location 004h is reserved for the external in - terrupt service program. if the int0 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004h. location 008h location 008h is reserved for the external in - terrupt service program also. if the int1 in - put pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 008h. location 00ch location 00ch is reserved for the timer/event counter 0 interrupt service program. if a timer interrupt results from a timer/event counter 0 overflow, and if the interrupt is en - abled and the stack is not full, the program begins execution at location 00ch. location 010h location 010h is reserved for the timer/event counter 1 interrupt service program. if a timer interrupt results from a timer/event counter 1 overflow, and if the interrupt is en - abled and the stack is not full, the program begins execution at location 010h. mode program counter *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0 000000000 00 external interrupt 0 0 000000001 00 external interrupt 1 0 000000010 00 timer/event counter 0 overflow 0 000000011 00 timer/event counter 1 overflow 0 000000100 00 time base interrupt 0 000000101 00 rtc interrupt 0 000000110 00 skip pc+2 loading pcl *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter notes: *11~*0: program counter bits #11~#0: instruction code bits s11~s0: stack register bits @7~@0: pcl bits > $> 4> & ?/ <@ . * 9 < -. +-a - ? / - -. +-a - 2a + $> =:-. a<623b 0+8 (((> c + ( 4> * 9 < -. +-a - > + - . - . =:-. a<623b 0+8 > ((> ? / - -. +-a - > program memory HT49C50 11 august 18, 1999 location 014h location 014h is reserved for the time base interrupt service program. if a time base in - terrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 014h. location 018h location 018h is reserved for the real time clock interrupt service program. if a real time clock interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 018h. table location any location in the rom can be used as a look-up table. the instructions tabrdc [m] (the current page, 1 page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to tblh (table higher-order byte register) (08h). only the destination of the lower-order byte in the ta - ble is well-defined; the other bits of the table word are all transferred to the lower portion of tblh, and the remaining 1 bit is read as 0 . the tblh is read only, and the table pointer (tblp) is a read/write register (07h), indicating the table location. before accessing the table, the location should be placed in tblp. all the table related instructions re- quire 2 cycles to complete the operation. these areas may function as a normal rom depending upon the user s requirements. stack register stack the stack register is a special part of the mem - ory used to save the contents of the pc. the stack is organized into 6 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. its activated level is indexed by a stack pointer (sp) and is neither readable nor writeable. at a commence - ment of a subroutine call or an interrupt ac - knowledgment, the contents of the pc is pushed onto the stack. at the end of the subrou - tine or interrupt routine, signaled by a return instruction (ret or reti), the contents of the pc is restored to its previous value from the stack. after chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag is re - corded but the acknowledgment is still inhib - ited. once the sp is decremented (by ret or reti), the interrupt is serviced. this feature prevents stack overflow, allowing the program - mer to use the structure easily. likewise, if the stack is full, and a call is subsequently exe - cuted, a stack overflow occurs and the first en - try is lost (only the most recent six return addresses are stored). data memory ram the data memory (ram) is designed with 192 8 bits, and is divided into two functional groups, namely special function registers and general purpose data memory, most of which are readable/writeable, although some are read only. instruction(s) table location *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location notes: *11~*0: table location bits @7~@0: table pointer bits p11~p8: current program counter bits HT49C50 12 august 18, 1999 of the two types of functional groups, the special function registers consist of an indirect address - ing register 0 (00h), a memory pointer register 0 (mp0;01h), an indirect addressing register 1 (02h), a memory pointer register 1 (mp1;03h), a bank pointer (bp;04h), an accumulator (acc;05h), a program counter lower-order byte register (pcl;06h), a table pointer (tblp;07h), a table higher-order byte register (tblh;08h), a real time clock control register (rtcc;09h), a status register (status;0ah), an interrupt control register 0 (intc0;0bh), a timer/event counter 0 (tmr0;0dh), a timer/event counter 0 control register (tmr0c;0eh), a timer/event counter 1 (tmr1;10h), a timer/event counter 1 control register (tmr1c;11h), i/o registers (pa;12h, pb;14h, pc;16h), and interrupt con - trol register 1 (intc1;1eh). on the other hand, the general purpose data memory, addressed from 60h to ffh, is used for data and control in - formation under instruction commands. the areas in the ram can directly handle arithmetic, logic, increment, decrement, and rotate operations. except some dedicated bits, each bit in the ram can be set and reset by set [m].i and clr [m].i . they are also indi - rectly accessible through the memory pointer register 0 (mp0;01h) or the memory pointer register 1 (mp1;03h). indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write operation of [00h] and [02h] ac- cesses the ram pointed to by mp0 (01h) and mp1(03h) respectively. reading location 00h or 02h indirectly returns the result 00h. while, writing it indirectly leads to no opera- tion. the function of data movement between two indi- rect addressing registers is not supported. the memory pointer registers, mp0 and mp1, are both 8-bit registers used to access the ram by combining corresponding indirect addressing reg- isters. mp0 can only be applied to data memory, while mp1 can be applied to data memory and lcd display memory. accumulator acc the accumulator (acc) is related to the alu operations. it is also mapped to location 05h of the ram and is capable of operating with im - mediate data. the data movement between two data memory locations must pass through the acc. < -. + & * # 63 1 +8 ./ < -. + & * # > > > '> $> 2> 3> )> 4> 5> > > > & > * > (> > > > '> $> 2> 3> )> 4> 5> > > > & > * > (> ((> c -+0d 0 + 3 > 0/ 00++ + 0/ 00++ + > ram mapping HT49C50 13 august 18, 1999 arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic operations and provides the following func - tions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz etc.) the alu not only saves the results of a data op - eration but also changes the status register. status register status the status register (0ah) is of 8 bits wide and contains, a carry flag (c), an auxiliary carry flag (ac), a zero flag (z), an overflow flag (ov), a power down flag (pd), and a watchdog time-out flag (to). it also records the status information and controls the operation sequence. except the to and pd flags, bits in the status register can be altered by instructions similar to other registers. data written into the status register does not alter the to or pd flags. oper - ations related to the status register, however, may yield different results from those intended. the to and pd flags can only be changed by a watchdog timer overflow, chip power-up, or clearing the watchdog timer and executing the halt instruction. the z, ov, ac, and c flags reflect the status of the latest operations. on entering the interrupt sequence or execut - ing the subroutine call, the status register will not be automatically pushed onto the stack. if the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precau - tions and save it properly. interrupts the HT49C50 provides two external inter - rupts, two internal timer/event counter inter - rupts, an internal time base interrupt, and an internal real time clock interrupt. the inter - rupt control register 0 (intc0;0bh) and inter - rupt control register 1 (intc1;1eh) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. labels bits function c0 c is set if the operation results in a carry during an addition operation or if a bor- row does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac 1 ac is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z2 z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. ov 3 ov is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pd 4 pd is cleared by either a system power-up or executing the clr wdt instruc - tion. pd is set by executing the halt instruction. to 5 to is cleared by a system power-up or executing the clr wdt or halt in - struction. to is set by a wdt time-out. 6 undefined, read as 0 7 undefined, read as 0 status register HT49C50 14 august 18, 1999 once an interrupt subroutine is serviced, other interrupts are all blocked (by clearing the emi bit). this scheme may prevent any further in - terrupt nesting. other interrupt requests may take place during this interval, but only the in - terrupt request flag will be recorded. if a cer - tain interrupt requires servicing within the service routine, the emi bit and the correspond - ing bit of the intc0 or of intc1 may be set in order to allow interrupt nesting. once the stack is full, the interrupt request will not be acknowl - edged, even if the related interrupt is enabled, until the sp is decremented. if immediate service is desired, the stack should be prevented from be - coming full. all these interrupts can support a wake-up function. as an interrupt is serviced, a control transfer occurs by pushing the contents of the pc onto the stack followed by a branch to a sub - register bit no. label function intc0 (0bh) 0 emi control the master (global) interrupt (1=enabled; 0=disabled) 1 eei0 control the external interrupt 0 (1=enabled; 0=disabled) 2 eei1 control the external interrupt 1 (1=enabled; 0=disabled) 3 et0i control the timer/event counter 0 interrupt (1=enabled; 0=disabled) 4 eif0 external interrupt 0 request flag (1=active; 0=inactive) 5 eif1 external interrupt 1 request flag (1=active; 0=inactive) 6 t0f internal timer/event counter 0 request flag (1=active; 0=inactive) 7 unused bit, read as 0 intc1 (1eh) 0 et1i control the timer/event counter 1 interrupt (1=enabled; 0=disabled) 1 etbi control the time base interrupt (1=enabled; 0:disabled) 2 erti control the real time clock interrupt (1=enabled; 0:disabled) 3 unused bit, read as 0 4 t1f internal timer/event counter 1 request flag (1=active; 0=inactive) 5 tbf time base request flag (1=active; 0=inactive) 6 rtf real time clock request flag (1=active; 0=inactive) 7 unused bit, read as 0 intc register HT49C50 15 august 18, 1999 routine at the specified location in the rom. only the contents of the pc is pushed onto the stack. if the contents of the register or of the status register (status) is altered by the in - terrupt service program which corrupts the de - sired control sequence, the contents should be saved in advance. external interrupts are triggered by a high to low transition of int0 or int1 , and the related interrupt request flag (eif0; bit 4 of intc0, eif1; bit 5 of intc0) is set as well. after the in - terrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04h or 08h occurs. the interrupt re - quest flag (eif0 or eif1) and emi bits are all cleared to disable other interrupts. the internal timer/event counter 0 interrupt is initialized by setting the timer/event counter 0 interrupt request flag (t0f; bit 6 of intc0), which is normally caused by a timer overflow. after the interrupt is enabled, and the stack is not full, and the t0f bit is set, a subroutine call to location 0ch occurs. the related interrupt request flag (t0f) is reset, and the emi bit is cleared to disable further interrupts. the timer/event counter 1 is operated in the same manner but its related interrupt request flag is t1f (bit 4 of intc1) and its subroutine call lo- cation is 10h. the time base interrupt is initialized by setting the time base interrupt request flag (tbf; bit 5 of intc1), that is caused by a regular time base signal. after the interrupt is enabled, and the stack is not full, and the tbf bit is set, a sub- routine call to location 14h occurs. the related interrupt request flag (tbf) is reset and the emi bit is cleared to disable further interrupts. the real time clock interrupt is initialized by setting the real time clock interrupt request flag (rtf; bit 6 of intc1), that is caused by a regular real time clock signal. after the inter - rupt is enabled, and the stack is not full, and the rtf bit is set, a subroutine call to location 18h occurs. the related interrupt request flag (rtf) is reset and the emi bit is cleared to dis - able further interrupts. during the execution of an interrupt subroutine, other interrupt acknowledgments are all held until the reti instruction is executed or the emi bit and the related interrupt control bit are set both to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti sets the emi bit and en - ables an interrupt service, but ret does not. interrupts occurring in the interval between the rising edges of two consecutive t2 pulses are serviced on the latter of the two t2 pulses if the corresponding interrupts are enabled. in the case of simultaneous requests, the priori - ties in the following table apply. these can be masked by resetting the emi bit. no. interrupt source priority vector a external interrupt 0 1 04h b external interrupt 1 2 08h c timer/event counter 0 overflow 3 0ch d timer/event counter 1 overflow 4 10h e time base interrupt 5 14h f real time clock interrupt 6 18h the timer/event counter 0 interrupt request flag (t0f), external interrupt 1 request flag (eif1), external interrupt 0 request flag (eif0), enable timer/event counter 0 interrupt bit (et0i), enable external interrupt 1 bit (eei1), enable external interrupt 0 bit (eei0), and enable master interrupt bit (emi) make up of the interrupt control register 0 (intc0) which is located at 0bh in the ram. the real time clock interrupt request flag (rtf), time base interrupt request flag (tbf), timer/event counter 1 interrupt request flag (t1f), enable real time clock interrupt bit (erti), and enable time base interrupt bit (etbi), enable timer/event counter 1 interrupt bit (et1i) on the other hand, constitute the interrupt con - trol register 1 (intc1) which is located at 1eh in the ram. emi, eei0, eei1, et0i, et1i, etbi, and erti are all used to control the en - able/disable status of interrupts. these bits prevent the requested i nterrupt from being ser - HT49C50 16 august 18, 1999 viced. once the interrupt request flags (rtf, tbf, t0f, t1f, eif1, eif0) are all set, they re - main in the intc1 or intc0 respectively until the interrupts are serviced or cleared by a soft - ware instruction. it is recommended that a program not use the call subroutine within the interrupt subroutine. it s because interrupts often occur in an unpredictable manner or require to be serviced immediately in some applications. at this time, if only one stack is left, and enabling the interrupt is not well con - trolled, operation of the call in the interrupt subroutine may damage the original control se - quence. oscillator configuration the HT49C50 provides two oscillator circuits for system clocks, i.e., rc oscillator and crystal oscillator, determined by mask option. no mat - ter what type of oscillator is selected, the signal is used for the system clock. the halt mode stops the system oscillator and ignores external signal to conserve power. of the two oscillators, if the rc oscillator is used, an external resistor between osc1 and vss is required, and the range of the resistance should be from 51k to 1m . the system clock, divided by 4, is available on osc2 with pull-high resistor, which can be used to syn- chronize external logic. the rc oscillator pro- vides the most cost effective solution. however, the frequency of the oscillation may vary with vdd, temperature, and the chip itself due to process variations. it is therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. on the other hand, if the crystal oscillator is se - lected, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator, and no other exter - nal components are required. a resonator may be connected between osc1 and osc2 to re - place the crystal and to get a frequency refer - ence, but two external capacitors in osc1 and osc2 are required. there is another oscillator circuit designed for the real time clock. in this case, only the 32.768khz crystal oscillator can be applied. the crystal should be connected between osc3 and osc4, and two external capacitors along with one external resistor are required for the oscillator circuit in order to get a stable fre - quency. the rtc oscillator circuit can be controlled to oscillate quickly by setting the qosc bit (bit 4 of rtcc). it is recommended to turn on the quick oscillating function upon power on, and turn it off after 2 seconds. the wdt oscillator is a free running on-chip rc oscillator, and no external components are required. although the system enters the power down mode, the system clock stops, and the wdt oscillator still works with a period of approximately 78 s. the wdt oscillator can be disabled by mask option to conserve power. ' $ rtc oscillator 1+ < +/<< + / << # $ ,&& system oscillator HT49C50 17 august 18, 1999 watchdog timer wdt the wdt clock source is implemented by a ded - icated rc oscillator (wdt oscillator) or an in - struction clock (system clock/4) or a real time clock oscillator (rtc oscillator). the timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. the wdt can be disabled by mask option. but if the wdt is dis - abled, all executions related to the wdt lead to no operation. after the wdt clock source is selected, the time-out period is f s /2 15 ~f s /2 16 . if the wdt clock source chooses the internal wdt oscillator, the time-out period may vary with temperature, vdd, and process variations. on the other hand, if the clock source selects the instruction clock and the halt instruction is exe - cuted, wdt may stop counting and lose its pro - tecting purpose, and the logic can only be restarted by an external logic. when the device operates in a noisy environ - ment, using the on-chip rc oscillator (wdt osc) is strongly recommended, since the halt can stop the system clock. the wdt overflow under normal operation initializes a chip reset and sets the status bit to . in the halt mode, the overflow initializes a warm reset , and only the pc and sp are reset to zero. to clear the contents of the wdt, there are three methods to be adopted, i.e., external reset (a low level to res ), software instruction, and a halt instruction. there are two types of software instructions; clr wdt and the other set clr wdt1 and clr wdt2 . of these two types of instruction, only one type of instruction can be active at a time depending on the mask option clr wdt times selection option .ifthe clr wdt is selected (i.e., clr wdt times equal one), any execution of the clr wdt instruction clears the wdt. in the case that clr wdt1 and clr wdt2 are chosen (i.e., clr wdt times equal two), these two instructions have to be ex - ecuted to clear the wdt; otherwise, the wdt may reset the chip due to time-out. multi-function timer the HT49C50 provides a multi-function timer for the wdt, time base and rtc but with different time-out periods. the multi-function timer con - sists of a 7-stage divider and an 8-bit prescaler, with the clock source coming from the wdt osc or rtc osc or the instruction clock (i.e.., system clock divided by 4). the multi-function timer also provides a selectable frequency signal (ranges from f s /2 2 to f s /2 8 ) for lcd driver circuits, and a selectable frequency signal (ranges from f s /2 2 to f s /2 9 ) for the buzzer output by mask option. it is recommended to select a near 4khz signal to lcd driver circuits for proper display. 1+ < /= $ & ?0 +/ < % & < += . </ %& => @ ')34> @ ! ! : - + " 2 3 HT49C50 18 august 18, 1999 time base the time base offers a periodic time-out period to generate a regular internal interrupt. its time-out period ranges from f s /2 12 to f s /2 15 se - lected by mask option. if time base time-out oc - curs, the related interrupt request flag (tbf; bit 5 of intc1) is set. but if the interrupt is en - abled, and the stack is not full, a subroutine call to location 14h occurs. the time base time-out signal also can be applied to be a clock source of timer/event counter 1 for getting a longer timer-out period. real time clock rtc the real time clock (rtc) is operated in the same manner as the time base that is used to supply a regular internal interrupt. its time-out period ranges from f s /2 8 to f s /2 15 by software programming . writing data to rt2, rt1 and rt0 (bit2, 1, 0 of rtcc;09h) yields various time-out periods. if the rtc time-out occurs, the related interrupt request flag (rtf; bit 6 of intc1) is set. but if the interrupt is en - abled, and the stack is not full, a subroutine call to location 18h occurs. the real time clock time-out signal also can be applied to be a clock source of timer/event counter 0 for getting a longer time-out period. rt2 rt1 rt0 rtc clock divided factor 000 2 8 001 2 9 010 2 10 011 2 11 100 2 12 101 2 13 110 2 14 111 2 15 power down operation halt the halt mode is initialized by the halt instruction and results in the following. the system oscillator turns off but the wdt oscillator keeps running (if the wdt oscilla - tor or the real time clock is selected). the contents of the on-chip ram and of the registers remain unchanged. the wdt is cleared and start recounting (if the wdt clock source is from the wdt oscil- lator or the real time clock oscillator). & ?0 += . +/ < += . + + - . 6 " 8 2 & & ? 6 " 8 -@@6 " 8 4 5 time base & ?0 4 -9d +/ < -. 2 " real time clock HT49C50 19 august 18, 1999 all i/o ports maintain their original status. the pd flag is set but the to flag is cleared. lcd driver is still running (if the wdt osc or rtc osc is selected). the system quits the halt mode by an external reset, an interrupt, an external falling edge sig - nal on port a, or a wdt overflow. an external re - set causes device initialization, and the wdt overflow performs a warm reset . after examin - ing the to and pd flags, the reason for chip re - set can be determined. the pd flag is cleared by system power-up or by executing the clr wdt instruction, and is set by executing the halt instruction. on the other hand, the to flag is set if wdt time-out occurs, and causes a wake-up that only resets the pc (program counter) and sp, and leaves the others at their original state. the port a wake-up and interrupt methods can be considered as a continuation of normal exe - cution. each bit in port a can be independently selected to wake up the device by mask option. awakening from an i/o port stimulus, the pro - gram resumes execution of the next instruc - tion. on the other hand, awakening from an interrupt, two sequences may occur. if the re- lated interrupt is disabled or the interrupt is enabled but the stack is full, the program re- sumes execution at the next instruction. but if the interrupt is enabled, and the stack is not full, the regular interrupt response takes place. when an interrupt request flag is set before en- tering the halt status, the system cannot be awaken using that interrupt. if wake-up events occur, it takes 1024 t sys (sys - tem clock period) to resume normal operation. in other words, a dummy period is inserted af - ter the wake-up. if the wake-up results from an interrupt acknowledgment, the actual inter - rupt subroutine execution is delayed by more than one cycle. however, if the wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before enter - ing the halt status. reset there are three ways in which reset may occur. res is reset during normal operation res is reset during halt wdt time-out is reset during normal operation the wdt time-out during halt differs from other chip reset conditions, for it can perform a warm reset that resets only the pc and sp and leaves the other circuits at their original state. some registers remain unaffected during any other reset conditions. most registers are reset to the initial condition once the reset conditions are met. examining the pd and to flags, the program can distinguish between dif - ferent chip resets . to pd reset conditions 0 0 res reset during power-up uu res reset during normal operation 0 1 res wake-up halt 1u wdt time-out during normal operation 1 1 wdt wake-up halt note: u means unchanged * ,&& reset circuit HT49C50 20 august 18, 1999 to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the system awakes from the halt state or during power up. awaking from the halt state or system power-up, the sst delay is added. an extra sst delay is added during the power-up period, and any wake-up from the halt may enable only the sst delay. the functional unit chip reset status is shown below. pc 000h interrupt disabled prescaler, divider cleared wdt, rtc, time base cleared. after master reset, wdt starts counting timer/event counter off input/output ports input mode sp points to the top of the stack * ,&& : - .+ reset timing chart %& > %& : - + *9 < * <0 + b : & / :a ..< - % + reset configuration HT49C50 21 august 18, 1999 the states of the registers are summarized below: register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* tmr0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0c 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u--- tmr1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr1c 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u--- program counter 000h 000h 000h 000h 000h mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu rtcc --00 0111 --00 0111 --00 0111 --00 0111 --uu uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu notes: * refers to warm reset u means unchanged x means unknown HT49C50 22 august 18, 1999 timer/event counter two timer/event counters are implemented in the HT49C50. both of them contain an 8-bit programmable count-up counter. the timer/event count 0 clock source may come from the system clock or system clock/4 or rtc time-out signal or external source. system clock source or system clock/4 is selected by mask option. the timer/event count 1 clock source may come from tmr0 overflow or system clock or time base time-out signal or system clock/4 or exter - nal source, and the three former clock source is selected by mask option. the external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. the two timer/event counters are operated al - most in the same manner, except the clock source and related registers. there are two registers related to the timer/event counter 0, i.e., tmr0 ([0dh]) and tmr0c ([0eh]), and two registers related to the timer/event counter 1, i.e., tmr1 ([10h], and tmr1c ([11h]). there are also two physi- cal registers are mapped to tmr0 (tmr1) loca- tion; writing tmr0 (tmr1) places the starting value in the timer/event counter preload regis- ter, while reading it yields the contents of the timer/event counter. tmr0c and tmr1c are timer/event counter control registers used to define some options. the tn0 and tn1 bits define the operation mode. the event count mode is used to count ex - ternal events, which means that the clock source is from an external (tmr0, tmr1) pin. the timer mode functions as a normal timer with the clock source coming from the internal selected clock source. finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr0, tmr1), and the counting is based on the internal selected clock source. in the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at ffh. once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (t0f; bit 6 of intc0, t1f; bit 4 of intc1). in the pulse width measurement mode with the values of the ton and te bits equal to one, after the tmr0 (tmr1) has received a transient from low to high (or high to low if the te bit is 0 ), it will start counting until the tmr0 (tmr1) returns to the original level and resets the ton. the measured re- sult remains in the timer/event counter even if the activated transient occurs again. in other words, only one cycle measurement can be made until the ton is set. the cycle mea- surement will re-function as long as it receives * 1+ < /= -<+% 0 +- 0 < & a-+ < 0 ?< b - . += . </ e (& '& - 1 + < / = $ ? / - < 0 + ? / - timer/event counter 0 HT49C50 23 august 18, 1999 further transient pulse. in this operation mode, the timer/event counter begins counting accord - ing not to the logic level but to the transient edges. in the case of counter overflows, the coun - ter is reloaded from the timer/event counter preload register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. to enable the counting operation, the timer on bit (ton; bit 4 of tmr0c or tmr1c) should be set to 1. in the pulse width measurement mode, the ton is automatically cleared after the measurement cycle is completed. but in the other two modes, the ton can only be reset by instructions. the overflow of the timer/event counter 0/1 is one of the wake-up sources and can also be applied to a pfd (programmable frequency divider) output at pa3 by mask op - tion. only one pfd (pfd0 or pfd1) can be ap - plied to pa3 by mask option . no matter what the operation mode is, writin ga0to et0i or et1i disables the related interrupt service. when the pfd function is selected, executing clr [pa].3 instruction to enable pfd output and executing set [pa].3 instruction to disable pfd output. in the case of timer/event counter off condition, writing data to the timer/event counter preload register also reloads that data to the * 1+ < /= -<+% 0 +- 0 < ? / - < 0 + ? / - & a-+ < 0 ?< b - . += . </ 1 + < / = $ + - ?< b e (& '& timer/event counter 1 label (tmr0c) bits function 0~2 unused bits, read as 0 te 3 to define the tmr0 active edge of timer/event counter (0=active on low to high; 1=active on high to low) ton 4 to enable/disable timer counting (0=disabled; 1=enabled) tn2 5 2 to 1 multiplexer control inputs to select the timer/event counter clock source (0=rtc outputs; 1= system clock or system clock/4) tn0 tn1 6 7 to define the operating mode (tn1, tn0) 01= event count mode (external clock) 10= timer mode (internal clock) 11= pulse width measurement mode (external clock) 00= unused tmr0c register HT49C50 24 august 18, 1999 label (tmr1c) bits function 0~2 unused bits, read as 0 te 3 to define the tmr1 active edge of timer/event counter (0= active on low to high; 1= active on high to low) ton 4 to enable/disable timer counting (0= disabled; 1= enabled) tn2 5 2 to 1 multiplexer control inputs to select the timer/event counter clock source (0= mask option clock source; 1= system clock/4) tn1 tn0 7 6 to define the operating mode 01= event count mode (external clock) 10= timer mode (internal clock) 11= pulse width measurement mode (external clock) 00= unused tmr1c register timer/ event counter. but if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event counter preload register. the timer/event counter still continues its opera - tion until an overflow occurs. when the timer/event counter (reading tmr0/tmr1) is read, the clock is blocked to avoid errors. as this may results in a counting error, blocking of the clock should be taken into account by the programmer. it is strongly recommended to load a desired value into the tmr0/tmr1 register first, then turn on the related timer/event counter for proper operation. because the initial value of tmr0/tmr1 is unknown. due to the timer/event scheme, the program- mer should pay special attention on the instruc - tion to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredicatable result. after this procedure, the timer/event function can be operated normally. the exam - ple given below, using two 8-bit width timer s (timer 0 ;timer 1) cascade into 16-bit width. start: mov a, 09h ; set et0i&emi bits to mov intc0, a ; enable timer 0 and ; global interrupt mov a, 01h ; set et1i bit to enable mov intc1, a ; timer 1 interrupt mov a, 80h ; set operating mode as mov tmr1c, a ; timer mode and select mask ; option clock source mov a, 0a0h ; set operating mode as timer mov tmr0c, a ; mode and select system ; clock/4 set tmr1c.4 ; enable then disable timer 1 clr tmr1c.4 ; for the first time mov a, 00h ; load a desired value into mov tmr0, a ; the tmr0/tmr1 register mov a, 00h ; mov tmr1, a ; set tmr0c.4 ; normal operating set tmr1c.4 ; end HT49C50 25 august 18, 1999 e & ! e & a-+ % . + 0 1+ % =:-.6 <18 % = -<<:-. ") " ) "' += . 6 " ' 7 8 += . ,&& += . 6 " '78 ,&& input/output ports input/output ports there are a 12-bit bidirectional input/output port, an 8-bit input port in the HT49C50, labeled pa, pb and pc which are mapped to [12h], [14h] and [16h] of the ram, respectively. pa0~pa3 can be configured as cmos (output) or nmos (input/output) with or without pull-high resistor by mask option. pa4~pa7 are always pull-high and nmos (input/output). if you choose nmos (input), each bit on the port (pa0~pa7) can be configured as a wake-up input. pb can only be used for input operation, and each bit on the port can be configured with pull-high re - sistor. pc can be configured as cmos output or nmos input/output with or without pull-high re - sistor by mask option. all the port for the input op - eration (pa, pb and pc), these ports are non-latched, that is, the inputs should be ready at the t2 rising edge of the instruction mov a, [m] (m=12h or 14h). for pa, pc output operation, all data are latched and remain unchanged until the output latch is rewritten. when the pa and pc structures are open drain nmos type, it should be noted that, before reading data from the pads, a 1 should be written to the related bits to disable the nmos device. that is executing first the instruction set [m].i (i=0~7 for pa) to disable related nmos device, and then mov a, [m] to get stable data. after chip reset, these input lines remain at the high level or are left floating (by mask option). each bit of these output latches can be set or cleared by the set [m].i and clr [m].i (m=12h or 16h) instructions. some instructions first input data and then fol - low the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or to the ac - cumulator. HT49C50 26 august 18, 1999 $ > ' * * $> $> $'> 2* > 2(> 3 > ' ' ' ' ' display memory lcd display memory the HT49C50 provides an area of embedded data memory for lcd display. this area is lo - cated from 40h to 60h of the ram at bank 1. bank pointer (bp; located at 04h of the ram) is the switch between the ram and the lcd dis - play memory. when the bp is set as 1 , any data written into 40h~60h will effect the lcd display. when the bp is cleared to 0 , any data written into 40h~60h means to access the gen - eral purpose data memory. the lcd display memory can be read and written to only by indi - rect addressing mode using mp1. when data is written into the display data area, it is auto - matically read by the lcd driver which then generates the corresponding lcd driving sig - nals. to turn the display on or off, a 1 or a 0 is written to the corresponding bit of the display memory, respectively. the figure illustrates the mapping between the display memory and lcd pattern for the HT49C50. HT49C50 27 august 18, 1999 ! ! 7 7 , & , & , , & , & , << & 0? - .- + & + + 77+0+a-< <1 & + + +0a< <1 & + + +0a< <1 & + + +0a< & + + 7+0+a< 7+0+a< & + + & + + 7+0+a< 77+0+a< & + + 7 7 << & 0? - .- + , & , & , , & , & , , & , & , , & , & , , & , & , , & , & , , & , & , , & , & , , & , & , , & , & , , & , & , , & , & , , & , & , lcd driver output (1/3 duty, 1/2 bias, r/c type) lcd driver output the output number of the HT49C50 lcd driver can be 33 2or33 3or32 4 by mask option (i.e., 1/2 duty or 1/3 duty or 1/4 duty). the bias type of lcd driver can be r type or c type. if the r bias type is selected, no external capacitor is re - quired. if the c bias type is selected, a capacitor mounted between c1 and c2 pins is needed. the bias voltage of lcd driver can be 1/2 bias or 1/3 bias by mask option. if 1/2 bias is selected, a ca - pacitor mounted between v2 pin and ground is required. if 1/3 bias is selected, two capacitors are needed for v1 and v2 pins. refer to application diagram. buzzer HT49C50 provides a pair of buzzer output bz and bz , which share pins with pa0 and pa1 re - spectively, ad determined by mask option. its output frequency can be selected by mask op - tion. when the buzzer function is selected, setting the pa.0 and pa.1 0 simultaneously, will en - ables the buzzer output and sets the pa.0 1 to disable the buzzer output. HT49C50 28 august 18, 1999 ' & + + +0< 0 ' , & , & , & , ' , & , & , & , ' , & , & , & , ' , & , & , & , ' , & , & , & , lcd driver output (1/4 duty, 1/3 bias, c type) HT49C50 29 august 18, 1999 mask option the following shows 18 kinds of mask options in the HT49C50. all these options should be de - fined in order to ensure proper system function - ing. register bit no. label read/write reset function rtcc (09h) 0~2 rt0 rt1 rt2 r/w 0 8 to 1 multiplexer control inputs to select the real time clock prescaler output 3 unused bits, this bit must dear to 0 4 qosc r/w 0 control the rtc osc to oscillate quickly 0 enable 1 disable 5~7 unused bits, read as 0 rtcc register no. mask option 1 osc type selection. this option is to decide if an rc or crystal oscillator is chosen as sys - tem clock. 2 wdt clock source selection. rtc and time base. there are three types of selection: sys - tem clock/4 or rtc osc or wdt osc. 3 wdt enable/disable selection. wdt can be enabled or disabled by mask option. 4 clr wdt times selection. this option defines how to clear the wdt by instruction. one time means that the clr wdt can clear the wdt. two times means only if both of the clr wdt1 and clr wdt2 have been executed, the wdt can be cleared. 5 time base time-out period selection. the time base time-out period ranges from clock/2 12 to clock/2 15 . clock means the clock source selected by mask option. 6 uzzer output frequency selection. there are eight types of frequency signals for buzzer output: clock/2 2 ~clock/2 9 . clock means the clock source selected by mask option. 7 wake-up selection. this option defines the wake-up capability. external i/o pins (pa only) all have the capability to wake-up the chip from a halt by a falling edge. 8 pull-high selection. this option is to decide whether the pull-high resistance is visible or not on the pa0~pa3 and pc. (pb and pa4~pa7 are always pull-high) 9 pa0~pa3 and pc cmos or nmos selection. the structure of pa0~pa3 and pc each 4 bits can be selected as cmos or nmos individ - ually. when the cmos is selected, the related pins only can be used for output opera - tions. when the nmos is selected, the related pins can be used for input or output operations. (pa4~pa7 are always nmos) HT49C50 30 august 18, 1999 no. mask option 10 clock source selection of timer/event counter 0. there are two types of selection: system clock or system clock/4. 11 clock source selection of timer/event counter 1. there are three types of selection: tmr0 overflow, system clock or time base overflow. 12 i/o pins share with other functions selection. pa0/bz , pa1/bz: pa0 and pa1 can be set as i/o pins or buzzer outputs. pa3/pfd: pa3 can be set as i/o pins or pfd output. 13 lcd common selection. there are three types of selection: 2 common (1/2 duty) or 3 com - mon (1/3 duty) or 4 common (1/4 duty). if the 4 common is selected, the segment output pin seg32 will be set as a common output. 14 lcd bias power supply selection. there are two types of selection: 1/2 bias or 1/3 bias. 15 lcd bias type selection. this option is to decide what kind of bias is selected, r type or c type. 16 lcd driver clock selection. there are seven types of frequency signals for the lcd driver circuits: f s /2 2 ~f s /2 8 . f s means the clock source selection by mask option. 17 pfd selection. if pa3 is set as pfd output, there are two types of selection; one is pfd0 as the pfd out - put, the other is pfd1 as the pfd output. pfd0, pfd1 are the timer overflow signals of the timer/event counter 0, timer/event counter 1 respectively. application circuits HT49C50 31 august 18, 1999 ") " ) # $ ! " " # ! ! " " * ' $ * "' "' , , & * ") " ) * ' $ * "' "' , & , , & * & b -..<1 & b -..<1 ,&& , & ,&& "' "' ,&& d ( d ( d ( d ( d ( d ( instruction set summary mnemonic description flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to register with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry with result in data memory decimal adjust acc for addition with result in data memory z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc z z z z z z z z z z z increment and decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory z z z z HT49C50 32 august 18, 1999 mnemonic description flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc none** none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh none none HT49C50 33 august 18, 1999 mnemonic description flag affected miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode none none none to,pd to*,pd* to*,pd* none none to,pd notes: x: 8-bit immediate data m: 7-bit data memory address a: accumulator i: 0~7 number of bits addr: 10-bit program memory address : flag(s) is affected : flag(s) is not affected *: flag(s) may be affected by the execution status **: for the old version of the e.v. chip, the zero flag (z) can be affected by executing the mov a,[m] instruction. for the new version of the e.v. chip, the zero flag cannot be changed by executing the mov a,[m] instruction. HT49C50 34 august 18, 1999 instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. operation acc acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. operation [m] acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc acc+x affected flag(s) tc2 tc1 to pd ov z ac c HT49C50 35 august 18, 1999 addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logi - cal_and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) tc2 tc1 to pd ov z ac c andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and operation. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c HT49C50 36 august 18, 1999 call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this ad - dress. operation stack pc+1 pc addr affected flag(s) tc2 tc1 to pd ov z ac c clr [m] clear data memory description the contents of the specified data memory are cleared to zero. operation [m] 00h affected flag(s) tc2 tc1 to pd ov z ac c clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to zero. operation [m].i 0 affected flag(s) tc2 tc1 to pd ov z ac c clr wdt clear watchdog timer description the wdt is cleared (re-counting from zero). the power down bit (pd) and time-out bit (to) are cleared. operation wdt 00h pd and to 0 affected flag(s) tc2 tc1 to pd ov z ac c 00 HT49C50 37 august 18, 1999 clr wdt1 preclear watchdog timer description the td, pd flags and wdt are all cleared (re-counting from zero), if the other preclear wdt instruction has been executed. only execution of this in - struction without the other preclear instruction sets the indicated flag which implies that this instruction has been executed and the to and pd flags re - main unchanged. operation wdt 00h* pd and to 0* affected flag(s) tc2 tc1 to pd ov z ac c 0* 0* clr wdt2 preclear watchdog timer description the to, pd flags and wdt are all cleared (re-counting from zero), if the other preclear wdt instruction has been executed. only execution of this in - struction without the other preclear instruction sets the indicated flag which implies that this instruction has been executed and the to and pd flags re - main unchanged. operation wdt 00h* pd and to 0* affected flag(s) tc2 tc1 to pd ov z ac c 0* 0* cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s comple- ment). bits which previously contained a one are changed to zero and vice-versa. operation [m] [m ] affected flag(s) tc2 tc1 to pd ov z ac c HT49C50 38 august 18, 1999 cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1 s comple - ment). bits which previously contained a one are changed to zero and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m ] affected flag(s) tc2 tc1 to pd ov z ac c daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary code decimal) code. the accumulator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the ac - cumulator is greater than 9. the bcd adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0 (acc.3~acc.0)+6, ac1=ac else [m].3~[m].0) (acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4 acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4 acc.7~acc.4+ac1,c=c affected flag(s) tc2 tc1 to pd ov z ac c dec [m] decrement data memory description data in the specified data memory is decremented by one. operation [m] [m] 1 affected flag(s) tc2 tc1 to pd ov z ac c HT49C50 39 august 18, 1999 deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by one, leaving the result in the accumulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) tc2 tc1 to pd ov z ac c halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pd) is set and the wdt time-out bit (to) is cleared. operation pc pc+1 pd 1 to 0 affected flag(s) tc2 tc1 to pd ov z ac c 01 inc [m] increment data memory description data in the specified data memory is incremented by one. operation [m] [m]+1 affected flag(s) tc2 tc1 to pd ov z ac c inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by one, leaving the result in the accumulator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) tc2 tc1 to pd ov z ac c HT49C50 40 august 18, 1999 jmp addr directly jump description the contents of the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation pc addr affected flag(s) tc2 tc1 to pd ov z ac c mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) tc2 tc1 to pd ov z ac c mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc x affected flag(s) tc2 tc1 to pd ov z ac c mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memories). operation [m] acc affected flag(s) tc2 tc1 to pd ov z ac c nop no operation description no operation is performed. execution continues with the next instruction. operation pc pc+1 affected flag(s) tc2 tc1 to pd ov z ac c HT49C50 41 august 18, 1999 or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) tc2 tc1 to pd ov z ac c orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c ret return from subroutine description the program counter is restored from the stack. this is a two-cycle instruc- tion. operation pc stack affected flag(s) tc2 tc1 to pd ov z ac c HT49C50 42 august 18, 1999 ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. operation pc stack acc x affected flag(s) tc2 tc1 to pd ov z ac c reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit (bit 0; register intc). operation pc stack emi 1 affected flag(s) tc2 tc1 to pd ov z ac c rl [m] rotate data memory left description the contents of the specified data memory are rotated one bit left with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 affected flag(s) tc2 tc1 to pd ov z ac c rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated one bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 [m].7 affected flag(s) tc2 tc1 to pd ov z ac c HT49C50 43 august 18, 1999 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated one bit left. bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 c c [m].7 affected flag(s) tc2 tc1 to pd ov z ac c rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated one bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 po - sition. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 c c [m].7 affected flag(s) tc2 tc1 to pd ov z ac c rr [m] rotate data memory right description the contents of the specified data memory are rotated one bit right with bit 0 rotated to bit 7. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 affected flag(s) tc2 tc1 to pd ov z ac c HT49C50 44 august 18, 1999 rra [m] rotate right-place result in the accumulator description data in the specified data memory is rotated one bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 [m].0 affected flag(s) tc2 tc1 to pd ov z ac c rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together ro - tated one bit right. bit 0 replaces the carry bit; the original carry flag is ro - tated into the bit 7 position. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 c c [m].0 affected flag(s) tc2 tc1 to pd ov z ac c rrca [m] rotate right through carry-place result in the accumulator description data of the specified data memory and the carry flag are rotated one bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the con- tents of the data memory remain unchanged. operation acc.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 c c [m].0 affected flag(s) tc2 tc1 to pd ov z ac c HT49C50 45 august 18, 1999 sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag aresubtractedfromtheaccumulator,leaving the result in theaccumulator. operation acc acc+[m ]+c affected flag(s) tc2 tc1 to pd ov z ac c sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+c affected flag(s) tc2 tc1 to pd ov z ac c sdz [m] skip if decrement data memory is zero description the contents of the specified data memory are decremented by one. if the re - sult is zero, the next instruction is skipped. if the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). oth- erwise proceed with the next instruction (one cycle). operation skip if ([m] 1)=0, [m] ([m] 1) affected flag(s) tc2 tc1 to pd ov z ac c sdza [m] decrement data memory and place result in acc, skip if zero description the contents of the specified data memory are decremented by one. if the re - sult is zero, the next instruction is skipped. the result is stored in the accu - mulator but the data memory remains unchanged. if the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). otherwise proceed with the next instruction (one cycle). operation skip if ([m] 1)=0, acc ([m] 1) affected flag(s) tc2 tc1 to pd ov z ac c HT49C50 46 august 18, 1999 set [m] set data memory description each bit of the specified data memory is set to one. operation [m] ffh affected flag(s) tc2 tc1 to pd ov z ac c set [m].i set bit of data memory description bit i of the specified data memory is set to one. operation [m].i 1 affected flag(s) tc2 tc1 to pd ov z ac c siz [m] skip if increment data memory is zero description the contents of the specified data memory are incremented by one. if the re - sult is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper in - struction (two cycles). otherwise proceed with the next instruction (one cy - cle). operation skip if ([m]+1)=0, [m] ([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c siza [m] increment data memory and place result in acc, skip if zero description the contents of the specified data memory are incremented by one. if the re- sult is zero, the next instruction is skipped and the result is stored in the ac- cumulator. the data memory remains unchanged. if the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). otherwise proceed with the next instruction (one cycle). operation skip if ([m]+1)=0, acc ([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c HT49C50 47 august 18, 1999 snz [m].i skip if bit i of the data memory is not zero description if bit i of the specified data memory is not zero, the next instruction is skipped. if bit i of the data memory is not zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). otherwise proceed with the next instruction (one cycle). operation skip if [m].i 0 affected flag(s) tc2 tc1 to pd ov z ac c sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc acc+[m ]+1 affected flag(s) tc2 tc1 to pd ov z ac c subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumula- tor, leaving the result in the data memory. operation [m] acc+[m ]+1 affected flag(s) tc2 tc1 to pd ov z ac c sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc acc+x +1 affected flag(s) tc2 tc1 to pd ov z ac c HT49C50 48 august 18, 1999 swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (one of the data memories) are interchanged. operation [m].3~[m].0 [m].7~[m].4 affected flag(s) tc2 tc1 to pd ov z ac c swapa [m] swap data memory-place result in the accumulator description the low-order and high-order nibbles of the specified data memory are inter - changed, writing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected flag(s) tc2 tc1 to pd ov z ac c sz [m] skip if data memory is zero description if the contents of the specified data memory are zero, the following instruc - tion, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). otherwise proceed with the next instruction (one cycle). operation skip if [m]=0 affected flag(s) tc2 tc1 to pd ov z ac c sza [m] move data memory to acc, skip if zero description the contents of the specified data memory are copied to the accumulator. if the contents is zero, the following instruction, fetched during the current in - struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). otherwise proceed with the next instruction (one cycle). operation skip if [m]=0, acc [m] affected flag(s) tc2 tc1 to pd ov z ac c HT49C50 49 august 18, 1999 sz [m].i skip if bit i of the data memory is zero description if bit i of the specified data memory is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). otherwise proceed with the next instruction (one cycle). operation skip if [m].i=0 affected flag(s) tc2 tc1 to pd ov z ac c tabrdc [m] move the rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclusive_or operation and the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c HT49C50 50 august 18, 1999 xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclusive_or operation. the result is stored in the data memory. the zero flag is affected. operation [m] acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c xor a,x logical xor immediate data to the accumulator description data in the the accumulator and the specified data perform a bitwise logical exclusive_or operation. the result is stored in the accumulator. the zero flag is affected. operation acc acc xor x affected flag(s) tc2 tc1 to pd ov z ac c HT49C50 51 august 18, 1999 HT49C50 52 august 18, 1999 holtek semiconductor inc. (headquarters) no.3 creation rd. ii, science-based industrial park, hsinchu, taiwan, r.o.c. tel: 886-3-563-1999 fax: 886-3-563-1189 holtek semiconductor inc. (taipei office) 5f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan, r.o.c. tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek microelectronics enterprises ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657 copyright 1999 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may pres - ent a risk to human life due to malfunction or otherwise. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. |
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