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| w wm8955l stereo dac for portable audio applications wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ production data, march 2006, rev 4.2 copyright ? 2006 wolfson microelectronics plc description the wm8955l is a low power, high quality stereo dac with integrated headphone and loudspeaker amplifiers, designed to reduce external component requirements in portable digital audio applications. the on-chip headphone amplifiers can deliver 40mw into a 16 ? load. advanced on-chip digital signal processing performs bass and treble tone control. the wm8955l can operate as a master or a slave, and includes an on-chip pll. it can use most master clock frequencies commonly found in portable systems, including usb, gsm, cdma or pdc clocks, or standard 256f s clock rates. different audio sample rates such as 48khz, 44.1khz, 8khz and many others are supported. the wm8955l operates on supply voltages from 1.8v up to 3.6v, although the digital core can operate on a separate supply down to 1.42v, saving power. different sections of the chip can also be powered down under software control. the wm8955l is supplied in a very small and thin 5x5mm qfn package, ideal for use in hand-held and portable systems. features ? dac snr 98db, thd -86db (?a? weighted @ 48khz, 3.3v) ? on-chip 400mw btl speaker driver (mono) ? on-chip headphone driver - 40mw output power on 16 ? / 3.3v - snr 96db, thd ?79db at 20mw with 16 ? load ? stereo and mono line-in mix into dac output ? separately mixed stereo and mono outputs ? digital tone control and bass boost ? low power - down to 7mw for stereo playback (1.8v / 1.5v supplies) - 10 w shutdown mode ? low supply voltages - analogue and digital i/o: 1.8v to 3.6v - digital core: 1.42v to 3.6v ? master clocks supported: gsm, cdma, pdc, usb or standard audio clocks ? audio sample rates supported: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96khz ? 32-lead qfn package, 5x5x0.9mm size, 0.5mm lead pitch applications ? smartphone / multimedia phone ? digital audio player block diagram
wm8955l production data w pd rev 4.2 march 2006 2 table of contents description .......................................................................................................1 features.............................................................................................................1 applications .....................................................................................................1 block diagram .................................................................................................1 table of contents .........................................................................................2 pin configuration...........................................................................................3 ordering information ..................................................................................3 pin description ................................................................................................4 recommended operating conditions .....................................................5 electrical characteristics ......................................................................6 terminology............................................................................................................. 7 output pga?s linearity ......................................................................................... 8 headphone output thd versus power........................................................... 9 speaker thd and noise versus power ......................................................... 10 power consumption ....................................................................................11 audio paths overview .................................................................................12 signal timing requirements .....................................................................13 system clock timing............................................................................................ 13 audio interface timing ? master mode ......................................................... 13 audio interface timing ? slave mode ............................................................ 14 control interface timing ? 3-wire mode ..................................................... 14 control interface timing ? 2-wire mode ..................................................... 15 internal power on reset circuit ..........................................................16 device description .......................................................................................17 introduction.......................................................................................................... 17 signal path ............................................................................................................. 17 line inputs and output mixers ........................................................................ 21 analogue outputs ............................................................................................... 24 digital audio interface...................................................................................... 28 master clock and phase locked loop ......................................................... 31 audio sample rates.............................................................................................. 33 control interface .............................................................................................. 35 power supplies ..................................................................................................... 36 power management ............................................................................................. 37 register map...................................................................................................39 digital filter characteristics ...............................................................40 terminology........................................................................................................... 40 dac filter responses ......................................................................................... 40 applications information .........................................................................42 recommended external components........................................................... 42 minimising pop noise at the analogue outputs ........................................ 43 line output configuration............................................................................... 43 headphone output configuration ................................................................ 44 speaker output configuration...................................................................... 44 package dimensions ....................................................................................45 important notice ..........................................................................................46 address:................................................................................................................... 46 production data wm8955l w pd rev 4.2 march 2006 3 pin configuration top view ordering information order code temperature range package moisture sensitivity level peak soldering temperature wm8955lsefl -25 c to +85 c 32-lead qfn (5x5x0.9mm) (pb-free) msl1 260 o c wm8955lsefl/r -25 c to +85 c 32-lead qfn (5x5x0.9mm) (pb-free, tape and reel) msl1 260 o c note: reel quantity = 3,500 wm8955l production data w pd rev 4.2 march 2006 4 pin description pin no name type description 1 mclk digital input master clock 2 dcvdd supply digital core supply 3 dbvdd supply digital buffer (i/o) supply 4 dgnd supply digital ground (return path for both dcvdd and dbvdd) 5 bclk digital input / output audio interface bit clock 6 dacdat digital input dac digital audio data 7 daclrc digital input / output audio interface left / right clock 8 clkout digital output buffered clock output (from mclk or internal pll) 9 pllgnd supply internally connected to agnd. connect this pin to agnd externally for best pll performance, or leave floating. 10 monoout analogue output mono output 11 out3 analogue output output 3 (can be used as headphone pseudo ground) 12 rout1 analogue output right output 1 (line or headphone) 13 lout1 analogue output left output 1 (line or headphone) 14 hpgnd supply supply for analogue output drivers (lout1/2, rout1/2) 15 rout2 analogue output right output 1 (line or headphone or speaker) 16 lout2 analogue output left output 1 (line or headphone or speaker) 17 hpvdd supply supply for analogue output drivers (lout1/2, rout1/2, monout) 18 avdd supply analogue supply 19 agnd supply analogue ground (return path for avdd) 20 vref analogue output reference voltage decoupling capacitor 21 vmid analogue output midrail voltage decoupling capacitor 22 nc no connect no internal connection 23 hpdetect logic input headphone / speaker switch (referred to avdd) 24 nc no connect no internal connection 25 monoin- analogue input negative end of monoin+, for differential mono signals 26 monoin+ analogue input analogue line-in to mixers (mono channel) 27 lineinr analogue input analogue line-in to mixers (right channel) 28 lineinl analogue input analogue line-in to mixers (left channel) 29 mode digital input control interface selection 30 csb digital input chip select / device address selection 31 sdin digital input/output control interface data input / 2-wire acknowledge output 32 sclk digital input control interface clock input note: it is recommended that the qfn ground paddle should be connected to analogue ground on the application pcb. production data wm8955l w pd rev 4.2 march 2006 5 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max supply voltages -0.3v +4.5v voltage range digital inputs dgnd -0.3v dbvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v operating temperature range, t a -25 c +85 c storage temperature after soldering -65 c +150 c notes 1. analogue and digital grounds must always be within 0.3v of each other. 2. all digital and analogue supplies are completely independent from each other. recommended operating conditions parameter symbol test conditions min typ max unit digital supply range (core) dcvdd 1.42 3.6 v digital supply range (buffer) dbvdd 1.71 3.6 v analogue supplies range avdd, hpvdd 1.8 3.6 v ground dgnd, agnd, hpgnd 0 v wm8955l production data w pd rev 4.2 march 2006 6 electrical characteristics test conditions dcvdd = 1.5v, avdd = hpvdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit dac to line-out (l/rout1 with 10k ? ? ? ? / 50pf load) avdd = 3.3v 98 signal to noise ratio (a-weighted) snr avdd = 1.8v 95 db avdd = 3.3v -86 total harmonic distortion thd avdd = 1.8v -82 db channel separation 1khz signal 100 db analogue mixer inputs (lineinl/r to l/rout1 with 10k ? ? ? ? / 50pf load) avdd = 3.3v 1.0 full-scale input signal level v infs avdd = other avdd/3.3 v rms avdd = 3.3v 98 signal to noise ratio line-in to line-out (a-weighted) snr avdd = 1.8v 95 db avdd = 3.3v -94 db total harmonic distortion thd avdd = 1.8v -90 db pga gain = 0db 20.5 input resistance (signal enters one mixer only) pga gain = +6db 10.5 pga gain = 0db 10.25 input resistance (signal enters two mixers) r linein pga gain = +6db 5.25 k ? monoin- input resistance r monoin- any gain 20 k ? mute attenuation -91 db analogue outputs (lout1/2, rout1/2, monoout) 0db full scale output voltage avdd/3.3 vrms mute attenuation 1khz, full scale signal -94 db channel separation -91 db headphone output (lout1/2, rout1/2 with 16 or 32 ? ? ? ? load) output power per channel p o output power is very closely correlated with thd; see below. hpvdd=1.8v, r l =32 ? p o =5mw 0.018 -75 hpvdd=1.8v, r l =16 ? p o =5mw 0.025 -72 hpvdd=3.3v, r l =32 ? , p o =20mw 0.013 -78 total harmonic distortion thd hpvdd=3.3v, r l =16 ? , p o =20mw 0.011 -79 % db hpvdd = 3.3v 92 96 db signal to noise ratio (a-weighted) snr hpvdd = 1.8v 95 db speaker output (lout2/rout2 with 8 ? ? ? ? bridge tied load, rout2inv=1) output power p o output power is very closely correlated with thd; see below and graphs po=200mw, r l =8 ? , hpvdd=3.3v -63 0.07 total harmonic distortion thd po=400mw, r l =8 ? hpvdd=3.3v -35 1.8 db % signal to noise ratio (a-weighted) snr hpvdd=3.3v, r l =8 ? 95 db production data wm8955l w pd rev 4.2 march 2006 7 test conditions dcvdd = 1.5v, avdd = hpvdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit analogue reference levels midrail reference voltage vmid ?3% avdd/2 +3% v buffered reference voltage vref ?3% avdd/2 +3% v digital input / output input high level v ih 0.7 dbvdd v input low level v il 0.3 dbvdd v output high level v oh i oh = -1ma 0.9 dbvdd v output low level v ol i ol = 1ma 0.1 dbvdd v terminology 1. signal-to-noise ratio (db) - snr is a measure of the difference in level between the full scale output and the output with no signal applied. (no auto-zero or automute function is employed in achieving these results). 2. dynamic range (db) - dr is a measure of the difference between the highest and lowest portions of a signal. normally a thd+n measurement at 60db below full scale. the measured signal is then corrected by adding the 60db to it. (e.g. thd+n @ -60db= -32db, dr= 92db). 3. thd+n (db) - thd+n is a ratio, of the rms values, of (noise + distortion)/signal. 4. channel separation (db) - also known as cross-talk. this is a measure of the amount one channel is isolated from the other. normally measured by sending a full scale signal down one channel and measuring the other. wm8955l production data w pd rev 4.2 march 2006 8 output pga?s linearity output pga gains -70 -60 -50 -40 -30 -20 -10 0 10 40 50 60 70 80 90 100 110 120 130 xxxvol register setting [binary] measured gain [db] monoout rout1 lout1 rout2 lout2 output pga gain step size 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 40 50 60 70 80 90 100 110 120 130 xxxvol register setting [binary] gain step size [db] monoout rout1 lout1 rout2 lout2 production data wm8955l w pd rev 4.2 march 2006 9 headphone output thd versus power headphone power vs thd+n (16 ohm load) -100 -80 -60 -40 -20 0 0 102030405060 power [mw] thd+n [db] avdd=3.3v avdd=2.5v avdd=1.8v headphone power vs thd+n (32 ohm load) -100 -80 -60 -40 -20 0 0 5 10 15 20 25 30 power [mw] thd+n [db] avdd=3.3v avdd=2.5v avdd=1.8v wm8955l production data w pd rev 4.2 march 2006 10 speaker thd and noise versus power wm8955 l/rout2 8r btl speaker load thd+nvpo -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.00 50.00 100.00 150.00 200.00 250.00 300.00 350.00 400.00 450.00 500.00 output power (mw) thd+n (db) thd referenced to 0.95vrms avdd=hpvdd=dbvdd=3.3v dcvdd=1.42 v 1.013khz sinewave input signal, a-weighted production data wm8955l w pd rev 4.2 march 2006 11 power consumption the power consumption of the wm8955l depends on the following factors. ? supply voltages: reducing the supply voltages also reduces supply currents, and therefore results in significant power savings. ? operating mode: power consumption is lower in mono modes than in stereo, as one dac is switched off. unused analogue outputs should be switched off. control register r24 r23 r38 other settings tot. power bit vmidsel vref dacl dacr lout1 rout1 lout2 rout2 mono out3 dacosr vsel dmen pllen clkouten v i (ma) v i (ma) v i (ma) v i (ma) (mw) off 00 0 0 0 0 0 0 0 0 0 0 11 0 0 0 clocks stopped 3.3 0.0001 3.3 0.0103 3.3 0 3.3 0 0.03432 01 0 0 0 2.5 0.0001 2.5 0.0084 2.5 0 2.5 0 0.02125 00 0 0 0 1.8 0.0001 1.5 0.0067 1.8 0 1.8 0 0.01023 low-power standby (lps) 10 1 0 0 0 0 0 0 0 0 0 11 0 0 0 3.3 0.2339 3.3 0.409 3.3 0.0856 3.3 0 2.40405 using 500 kohm vmid string 01 0 0 0 2.5 0.1737 2.5 0.2556 2.5 0.0616 2.5 0 1.22725 00 0 0 0 1.8 0.1208 1.5 0.1416 1.8 0.042 1.8 0 0.50544 playback to line-out 01 1 1 1 0 0 1 1 0 0 0 11 0 0 0 3.3 3.9903 3.3 5.1104 3.3 0.0878 3.3 0.6621 32.50698 01 0 0 0 2.5 2.9459 2.5 3.5193 2.5 0.0632 2.5 0.6553 17.95925 00 0 0 0 1.8 2.0701 1.5 1.9742 1.8 0.0432 1.8 0.3845 7.45734 playback to line-out 01 1 1 1 0 0 1 1 0 0 1 11 0 0 0 3.3 3.7821 3.3 4.2678 3.3 0.0879 3.3 0.6619 29.03901 (64x oversampling mode) 01 0 0 0 2.5 2.7924 2.5 2.9224 2.5 0.0632 2.5 0.6557 16.08425 00 0 0 0 1.8 1.9604 1.5 1.6299 1.8 0.0432 1.8 0.3847 6.74379 playback 01 1 1 1 1 1 0 0 0 0 0 11 0 0 0 3.3 3.9623 3.3 5.0846 3.3 0.0878 3.3 0.6913 32.4258 to 16 ohm headphone 01 0 0 0 2.5 2.946 2.5 3.5187 2.5 0.0632 2.5 0.6691 17.9925 using caps on hpoutl/r 00 0 0 0 1.8 2.0702 1.5 1.9742 1.8 0.04332 1.8 0.3852 7.458996 playback 01 1 1 1 1 1 0 0 0 1 0 11 0 0 0 r24, out3sw=00 3.3 4.0662 3.3 5.1007 3.3 0.0881 3.3 1.172 34.4091 to 16 ohm headphone 01 0 0 0 2.5 2.999 2.5 3.557 2.5 0.064 2.5 1.167 19.4675 capless mode using out3 00 0 0 0 1.8 2.0705 1.5 1.9164 1.8 0.04272 1.8 0.914 8.8857 playback 01 1 1 1 0 0 1 1 0 0 0 11 0 0 0 r24, rout2inv=1 3.3 3.9602 3.3 4.2714 3.3 0.0873 3.3 0.8068 30.11481 to 8 ohm btl speaker 01 0 0 0 2.5 3.1282 2.5 3.5487 2.5 0.0639 2.5 0.8039 18.86175 00 0 0 0 1.8 2.1565 1.5 1.9671 1.8 0.04296 1.8 0.6698 8.115318 headphone amp 01 1 0 0 1 1 0 0 0 0 0 11 0 0 0 clocks stopped 3.3 1.7135 3.3 0.0901 3.3 0 3.3 0.6624 8.1378 line-in to 16 ohm h/phone 01 0 0 0 2.5 1.211 2.5 0.009 2.5 0 2.5 0.6291 4.62275 00 0 0 0 1.8 0.8017 1.5 0.0071 1.8 0 1.8 0.3869 2.15013 speaker amp 01 1 0 0 0 0 1 1 0 0 0 11 0 0 0 r24, rout2inv=1 3.3 1.7132 3.3 0.0905 3.3 0 3.3 1.158 9.77361 line-in to 8 ohm speaker 01 0 0 0 clocks stopped 2.5 1.2631 2.5 0.009 2.5 0 2.5 1.0804 5.88125 00 0 0 0 1.8 0.8881 1.5 0.0071 1.8 0 1.8 0.8733 3.18117 phone call 01 1 0 0 1 1 0 0 1 1 0 11 1 0 0 clocks stopped 3.3 1.9574 3.3 0.0905 3.3 0 3.3 1.1675 10.61082 diff. mono line-in to h/phone, 01 1 0 0 2.5 1.4258 2.5 0.009 2.5 0 2.5 1.1017 6.34125 diff. mono line-out to tx 00 1 0 0 1.8 0.9076 1.5 0.0071 1.8 0 1.8 0.6576 2.82801 pll only 00 0 0 0 0 0 0 0 0 0 0 11 0 1 0 3.3 0.5389 3.3 0.4966 3.3 0.0855 3.3 0 3.6993 01 0 1 0 2.5 0.4554 2.5 0.2774 2.5 0.0616 2.5 0 1.986 00 0 1 0 1.8 0.4034 1.5 0.145 1.8 0.04188 1.8 0 1.019004 pll and clkout 00 0 0 0 0 0 0 0 0 0 0 11 0 1 1 3.3 0.5389 3.3 0.4953 3.3 1.096 3.3 0 7.02966 01 0 1 1 2.5 0.4554 2.5 0.2768 2.5 0.8044 2.5 0 3.8415 00 0 1 1 1.8 0.4034 1.5 0.1448 1.8 0.57264 1.8 0 1.974072 maximum power 01 1 1 1 1 1 1 1 1 1 0 11 1 1 1 r24, rout2inv=1 3.3 4.9869 3.3 5.1538 3.3 1.0972 3.3 1.9463 43.50786 everything on 01 1 1 1 2.5 3.737 2.5 3.544 2.5 0.8044 2.5 1.7684 24.6345 00 1 1 1 1.8 2.6827 1.5 1.97 1.8 0.57348 1.8 1.3114 11.176644 dbvdd hpvdd r43 r25 r26 (1ah) avdd dcvdd table 1 supply current consumption notes: 1. t a = +25 o c, slave mode, fs = 48khz, mclk = 12.288 mhz (256fs), 24-bit data 2. all figures are quiescent, with no signal. 3. the power dissipated in the headphone itself is not included in the above table. wm8955l production data w pd rev 4.2 march 2006 12 audio paths overview production data wm8955l w pd rev 4.2 march 2006 13 signal timing requirements system clock timing mclk t mclkl t mclkh t mclky figure 1 system clock timing requirements test conditions clkdiv2 = 0 , dcvdd = 1.42v, dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode fs = 48khz, mclk = 384fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit system clock timing information mclk system clock pulse width high t mclkl 21 ns mclk system clock pulse width low t mclkh 21 ns mclk system clock cycle time t mclky 54 ns mclk duty cycle t mclkds 60:40 40:60 test conditions clkdiv2 = 1 , dcvdd = 1.42v, dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode fs = 48khz, mclk = 384fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit system clock timing information mclk system clock pulse width high t mclkl 10 ns mclk system clock pulse width low t mclkh 10 ns mclk system clock cycle time t mclky 27 ns audio interface timing ? master mode bclk (output) daclrc (output) dacdat t dst t dht t dl figure 2 digital audio data timing ? master mode (see control interface) test conditions dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit bit clock timing information bclk rise time (10pf load) t bclkr 3 ns bclk fall time (10pf load) t bclkf 3 ns bclk duty cycle (normal mode, bclk = mclk/n) t bclkds 50:50 bclk duty cycle (usb mode, bclk = mclk) t bclkds t mclkds wm8955l production data w pd rev 4.2 march 2006 14 test conditions dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit system clock timing information daclrc propagation delay from bclk falling edge t dl 10 ns dacdat setup time to bclk rising edge t dst 10 ns dacdat hold time from bclk rising edge t dht 10 ns audio interface timing ? slave mode bclk daclrc t bch t bcl t bcy dacdat t lrsu t ds t lrh figure 3 digital audio data timing ? slave mode (see control interface) test conditions dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit system clock timing information bclk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns daclrc setup time to bclk rising edge t lrsu 10 ns daclrc hold time from bclk rising edge t lrh 10 ns dacdat hold time from bclk rising edge t dh 10 ns control interface timing ? 3-wire mode csb sclk sdin t csl t dho t dsu t csh t scy t sch t scl t scs lsb t css figure 4 control interface timing ? 3-wire serial control mode production data wm8955l w pd rev 4.2 march 2006 15 test conditions dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk rising edge to csb rising edge t scs 500 ns sclk pulse cycle time t scy 200 ns sclk pulse width low t scl 80 ns sclk pulse width high t sch 80 ns sdin to sclk set-up time t dsu 40 ns sclk to sdin hold time t dho 40 ns csb pulse width low t csl 40 ns csb pulse width high t csh 40 ns csb rising to sclk rising t css 40 ns pulse width of spikes that will be suppressed t ps 0 5 ns control interface timing ? 2-wire mode sdin sclk t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 9 figure 5 control interface timing ? 2-wire serial control mode test conditions dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk frequency 0 526 khz sclk low pulse-width t 1 1.3 us sclk high pulse-width t 2 600 ns hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sdin, sclk rise time t 6 300 ns sdin, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 0 5 ns wm8955l production data w pd rev 4.2 march 2006 16 internal power on reset circuit vdd t1 gnd avdd dcvdd dgnd internal porb power on reset circuit figure 6 internal power on reset circuit schematic the wm8955 includes an internal power-on-reset circuit, as shown in figure 6, which is used to reset the digital logic into a default state after power up. the power on reset circuit is powered from dcvdd and monitors dcvdd and avdd. it asserts porb low if dcvdd or avdd are below a minimum threshold. figure 7 typical power-up sequence figure 7 shows a typical power-up sequence. when dcvdd and avdd rise above the minimum thresholds, vpord_dcvdd and vpord_avdd, there is enough voltage for the circuit to guarantee the power on reset is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. when dcvdd rises to vpor_dcvdd_on and avdd rises to vpor_avdd_on, porb is released high and all registers are in their default state and writes to the control interface may take place. if dcvdd and avdd rise at different rates then porb will only be released when dcvdd and avdd have both exceeded the vpor_dcvdd_on and vpor_avdd_on thresholds. on power down, porb is asserted low whenever dcvdd drops below the minimum threshold vpor_dcvdd_off or avdd drops below the minimum threshold vpor_avdd_off. symbol min typ max unit v pord_dcvdd 0.4 0.6 0.8 v v por_dcvdd_on 0.9 1.26 1.6 v v por_avdd_on 0.5 0.7 0.9 v v por_avdd_off 0.4 0.6 0.8 v table 2 typical por operation (typical values, not tested) production data wm8955l w pd rev 4.2 march 2006 17 device description introduction the wm8955l is a low power audio dac offering a combination of high quality audio, advanced features, low power and small size. these characteristics make it ideal for portable digital audio applications such as portable music players and smartphones. the device has a configurable digital audio interface where digital audio data is fed to the internal digital filters and then the dac. the interface supports a number of audio data formats including i 2 s, dsp mode (a burst mode in which frame sync plus 2 data packed words are transmitted), left justified and right justified formats, and can operate in master or slave modes. the on-chip digital filters perform tone control and digital volume control according to the user setting, and convert the audio data into oversampled bitstreams, which are passed to the left and right channel dacs. a multi-bit, low-order ? dac architecture with dynamic element matching is used, delivering optimum performance with low power consumption. the dac output signal enters an analogue mixer where analogue input signals can be added to it. the wm8955l has a total of six analogue output pins, which can be configured as stereo line-outs, mono line-outs, differential mono line-outs, stereo headphone outputs or differential mono (btl) speaker outputs. the wm8955l includes an on-chip pll to generate commonly used audio rates, such as 48khz and 44.1khz, from system clocks found in gsm, cdma and pdc phones and other portable systems. to allow full software control over all its features, the wm8955l offers a choice of 2 or 3 wire mpu control interface. it is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and dsps. the design of the wm8955l has given much attention to power consumption without compromising performance. it operates at very low voltages, and includes the ability to power off parts of the circuitry under software control, including standby and power off modes. signal path the wm8955l signal paths consists of digital filters, dacs, analogue mixers and output drivers. each circuit block can be enabled or disabled separately using the control bits in register 26 (see ?power management?). thus it is possible to utilise the analogue mixing and amplification provided by the wm8955l, irrespective of whether the dacs are running or not. the wm8955l receives digital input data on the dacdat pin. the digital filter block processes the data to provide the following functions: ? digital volume control ? tone control and bass boost ? digital mono mix ? sigma-delta modulation two high performance, sigma-delta audio dacs convert the digital data into two analogue signals (left and right). these can then be mixed with analogue signals from the lineinl, lineinr and monoin pins, and the mix is fed to the output drivers, lout1/rout1, lout2/rout2, monoout and out3. ? lout1/rout1: can drive 16 ? or 32 ? stereo headphones or stereo line output. ? lout2/rout2: can drive an 8 ? mono speaker, stereo headphones or a stereo line-out. ? monoout: line output designed to drive a 10k ? load. ? out3: multi-function output, may be used for capacitor-less headphone drive, differential mono-out, line-out or 32 ? earpiece driver. wm8955l production data w pd rev 4.2 march 2006 18 digital volume control the wm8955l has on-chip digital attenuation from ?127db to 0db in 0.5db steps, allowing the user to adjust the volume of each channel separately. the level of attenuation for an eight-bit code x is given by: -0.5 (255 ? x) db for 1 x 255; mute for x = 0 the ldvu and rdvu control bits control the loading of digital volume control data. when ldvu or rdvu are set to 0, the ldacvol or rdacvol control data is loaded into an intermediate register, but the actual gain does not change. both left and right gain settings are updated simultaneously when either ldvu or rdvu are set to 1. register address bit label default description 7:0 ldacvol[7:0] 11111111 ( 0db ) left dac digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db r10 (0ah) left channel digital volume 8 ldvu 0 left dac volume update 0 = store ldacvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = ldacvol, right = intermediate latch) 7:0 rdacvol[7:0] 11111111 ( 0db ) right dac digital volume control similar to ldacvol r11 (0bh) right channel digital volume 8 rdvu 0 right dac volume update 0 = store rdacvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = intermediate latch, right = rdacvol) table 3 digital volume control production data wm8955l w pd rev 4.2 march 2006 19 tone control the wm8955l provides separate controls for bass and treble with programmable gains and filter characteristics. this function operates on digital audio data before it is passed to the audio dacs. bass control can take two different forms: ? linear bass control: bass signals are amplified or attenuated by a user programmable gain. this is independent of signal volume, and very high bass gains on loud signals may lead to signal clipping. ? adaptive bass boost: the bass volume is amplified by a variable gain. when the bass volume is low, it is boosted more than when the bass volume is high. this method is recommended because it prevents clipping, and usually sounds more pleasant to the human ear. treble control applies a user programmable gain, without any adaptive boost function. register address bit label default description 7 bb 0 bass mode 0 = linear bass control 1 = adaptive bass boost 6 bc 0 bass filter characteristic 0 = low cutoff (130 hz at 48khz sampling) 1 = high cutoff (200 hz at 48khz sampling) bass intensity code bb=0 bb=1 0000 +9db 15 (max) 0001 +9db 14 0010 +7.5db 13 ? (1.5db steps) ? 0111 0db 8 ? (1.5db steps) ? 1011-1101 -6db 4-2 1110 -6db 1 (min) r12 (0ch) bass control 3:0 bass 1111 (off) 1111 bypass (off) 6 tc 0 treble filter characteristic 0 = high cutoff (8khz at 48khz sampling) 1 = low cutoff (4khz at 48khz sampling) r13 (0dh) treble control 3:0 trbl 1111 (disabled) treble intensity 0000 or 0001 = +9db 0010 = +7.5db ? (1.5db steps) 1011 to 1110 = -6db 1111 = disable table 4 tone control note: all cut-off frequencies change proportionally with the dac sample rate. wm8955l production data w pd rev 4.2 march 2006 20 digital to analogue converter (dac) treble and linear bass enhancement may produce signals that exceed full-scale. in order to avoid limiting under these conditions, it is recommended to set the dat bit to attenuate the digital input signal by 6db. the gain at the outputs should be increased by 6db to compensate for the attenuation. cut-only tone adjustment and adaptive bass boost cannot produce signals above full- scale and therefore do not require the dat bit to be set. after passing through the tone control filters, digital ?de-emphasis? can be applied to the audio data if necessary (e.g. when the data comes from a cd with pre-emphasis used in the recording). de- emphasis filtering is available for sample rates of 48khz, 44.1khz and 32khz. the wm8955l also has a soft mute function, which gradually attenuates the volume of the digital signal to zero. this function is enabled by default. to play back an audio signal, the wm8955l must first be unmuted by setting the dacmu bit to zero. register address bit label default description 7 dat 0 dac 6db attenuate enable 0 = disabled (0db) 1 = -6db enabled 3 dacmu 1 digital soft mute 1 = mute 0 = no mute (signal active) r5 (05h) dac control 2:1 deemph 00 de-emphasis control 11 = 48khz sample rate 10 = 44.1khz sample rate 01 = 32khz sample rate 00 = no de-emphasis table 5 dac control the digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. the bitstream data enters two multi-bit, sigma-delta dacs, which convert them to high quality analogue audio signals. the multi-bit dac architecture reduces high frequency noise and sensitivity to clock jitter. it also uses a dynamic element matching technique for high linearity and low distortion. in normal operation, the left and right channel digital audio data are converted to analogue in two separate dacs. however, it is also possible to disable one channel, so that the same signal (left or right) appears on both analogue output channels. additionally, there is a mono-mix mode where the two audio channels are mixed together digitally and then converted to analogue using only one dac, while the other dac is switched off. the mono-mix signal can be selected to appear on both analogue output channels (see analogue outputs). the dac output defaults to non-inverted. setting dacinv will invert the dac output phase on both left and right channels. register address bit label default description 5:4 dmonomix[1:0] 00 dac mono mix 00: stereo 01: mono ((l+r)/2) into dacl, ?0? into dacr 10: mono ((l+r)/2) into dacr, ?0? into dacl 11: mono ((l+r)/2) into dacl & dacr r23 (17h) additional (1) 1 dacinv 0 dac phase invert 0: non-inverted 1: inverted table 6 dac mono mix select production data wm8955l w pd rev 4.2 march 2006 21 line inputs and output mixers the wm8955l provides the option to mix the dac output signal with analogue line-in signals from the lineinl, lineinr and monoin+ and monoin- pins. the level of the mixed-in signals can be controlled with pgas (programmable gain amplifiers). lineinl, lineinr, monoin+ and monoin- are high impedance, low capacitance ac coupled analogue inputs. they are biased internally to the reference voltage vref. whenever these inputs are muted or the device placed into standby mode, the inputs remain biased to vref using special anti-thump circuitry. this reduces any audible clicks that may otherwise be heard when re-activating the inputs. the mono mixer is designed to allow a number of signal combinations to be mixed, including the possibility of mixing both the right and left channels together to produce a mono output. to prevent overloading of the mixer when full-scale dac left and right signals are input, the mixer inputs from the dac outputs each have a fixed gain of -6db. the bypass path inputs to the mono mixer have variable gain as determined by r38/r39 bits [6:4]. register address bit label default description 8 ld2lo 0 left dac to left mixer 0 = disable (mute) 1 = enable path 7 li2lo 0 lineinl signal to left mixer 0 = disable (mute) 1 = enable path r34 (22h) left mixer (1) 6:4 li2lovol 101 (-9db) lineinl signal to left mixer volume 000 = +6db ? (3db steps) 111 = -15db 8 rd2lo 0 right dac to left mixer 0 = disable (mute) 1 = enable path 7 mi2lo 0 monoin signal to left mixer 0 = disable (mute) 1 = enable path r35 (23h) left mixer (2) 6:4 mi2lovol 101 (-9db) monoin signal to left mixer volume 000 = +6db ? (3db steps) 111 = -15db table 7 left output mixer control wm8955l production data w pd rev 4.2 march 2006 22 register address bit label default description 8 ld2ro 0 left dac to right mixer 0 = disable (mute) 1 = enable path 7 mi2ro 0 monoin signal to right mixer 0 = disable (mute) 1 = enable path r36 (24h) right mixer (1) 6:4 mi2rovol 101 (-9db) monoin signal to right mixer volume 000 = +6db ? (3db steps) 111 = -15db 8 rd2ro 0 right dac to right mixer 0 = disable (mute) 1 = enable path 7 ri2ro 0 lineinr signal to right mixer 0 = disable (mute) 1 = enable path r37 (25h) right mixer (2) 6:4 ri2rovol 101 (-9db) lineinr signal to right mixer volume 000 = +6db ? (3db steps) 111 = -15db table 8 right output mixer control register address bit label default description 8 ld2mo 0 left dac to mono mixer 0 = disable (mute) 1 = enable path 7 li2mo 0 lineinl signal to mono mixer 0 = disable (mute) 1 = enable path r38 (26h) mono mixer (1) 6:4 li2movol 101 (-9db) lineinl signal to right mono volume 000 = 0db ? (3db steps) 111 = -21db 8 rd2mo 0 right dac to mono mixer 0 = disable (mute) 1 = enable path 7 ri2mo 0 lineinr signal to mono mixer 0 = disable (mute) 1 = enable path r39 (27h) mono mixer (2) 6:4 ri2movol 101 (-9db) lineinr signal to mono mixer volume 000 = 0db ? (3db steps) 111 = -21db table 9 mono output mixer control note: the mono mixer has half the gain of the left and right mixers (i.e. 6db less), to ensure that the left and right channels can be mixed to mono without clipping. production data wm8955l w pd rev 4.2 march 2006 23 differential mono line-in the wm8955l can take either a single-ended or a differential mono signal and mix it into the lout1/2 and rout1/2 outputs. in both cases, lineinl and lineinr still remain available as stereo line-in. differential mono input mode is enabled by setting the dmen bit, as shown below. register address bit label default description r38 (26h) mono mixer (1) 0 dmen 0 differential mono line-in enable 0 = single-ended line-in from monoin+ 1 = differential line-in table 10 differential mono line-in enable dac li2lo mi2lo mi2ro ri2ro li2mo ri2mo ld2lo rd2lo ld2mo rd2mo ld2ro rd2ro left mixer right mixer mono mixer w wm8955l vref lineinl lineinr dac rout1vol lout1vol monovol lout1 rout1 monoout lout2 rout2 -1 rout2 inv loudspeaker l - (-r) = l+r rout2vol lout2vol monoin+ monoin- diff. in device with differential mono output mono out(-) mono out(+) dmen = 1 (on) figure 8 differential mono line-in configuration (dmen=1) dac li2lo mi2lo mi2ro ri2ro li2mo ri2mo ld2lo rd2lo ld2mo rd2mo ld2ro rd2ro left mixer right mixer mono mixer w wm8955l vref lineinl lineinr dac rout1vol lout1vol monovol lout1 rout1 monoout lout2 rout2 -1 rout2 inv loudspeaker l - (-r) = l+r rout2vol lout2vol monoin+ monoin- (connect to vref) diff. in device with single-ended mono output mono out dmen = 0 (off) figure 9 single-ended mono line-in configuration (dmen=0) wm8955l production data w pd rev 4.2 march 2006 24 analogue outputs enabling the outputs each analogue output of the wm8955l can be separately enabled or disabled. the analogue mixer associated with each output is powered on or off along with the output pin. all outputs are disabled by default. to save power, unused outputs should remain disabled. outputs can be enabled at any time, except when the wm8955l is in off mode, as this may cause pop noise (see minimising pop noise at the analogue outputs) register address bit label default description 6 lout1 0 0 = lout1 disabled 1 = lout1 enabled 5 rout1 0 0 = rout1 disabled 1 = rout1 enabled 4 lout2 0 0 = lout2 disabled 1 = lout2 enabled 3 rout2 0 0 = rout2 disabled 1 = rout2 enabled 2 mono 0 0 = monoout disabled 1 = monoout enabled r26 (1ah) power management (2) 1 out3 0 0 = out3 disabled 1 = out3 enabled table 11 analogue output control whenever an analogue output is disabled, it remains connected to vref (pin 20) through a resistor. this helps to prevent pop noise when the output is re-enabled. the resistance between vref and each output can be controlled using the vroi bit in register 27. the default is low (1.5k ? ), so that any capacitors on the outputs can charge up quickly at start-up. if a high impedance is desired for disabled outputs, vroi can then be set to 1, increasing the resistance to about 40k ? . register address bit label default description r27 (1bh) additional (3) 6 vroi 0 vref to analogue output resistance 0: 1.5 k ? 1: 40 k ? table 12 disabled outputs to vref resistance thermal shutdown the speaker and headphone outputs can drive very large currents. to protect the wm8955l from overheating, a thermal shutdown circuit is included. if the device temperature reaches approximately 150 0 c and the thermal shutdown circuit is enabled (tsden = 1 ) then the speaker and headphone amplifiers (outputs out1l/r, out2l/r & out3) will be disabled. register address bit label default description r23 (17h) additional (1) 8 tsden 0 thermal shutdown enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled table 13 thermal shutdown production data wm8955l w pd rev 4.2 march 2006 25 headphone switch the hpdetect pin can be used as a headphone switch control input to automatically disable the speaker output and enable the headphone output e.g. when a headphone is plugged into a jack socket. in this mode, enabled by setting hpswen, hpdetect switches between headphone and speaker outputs (typically, the pin is connected to a mechanical switch in the headphone socket to detect plug-in). the hpswpol bit reverses the pin?s polarity. hpdetect has cmos thresholds at 0.3 avdd / 0.7 avdd. note that the lout1, rout1, lout2 and rout2 bits in register 26 must also be set to enable headphone and speaker outputs (see tables below). register address bit label default description 6 hpswen 0 headphone switch enable 0 : headphone switch disabled 1 : headphone switch enabled 5 hpswpol 0 headphone switch polarity 0 : hpdetect high = headphone 1 : hpdetect high = speaker r24 (18h) additional (1) 3 hpswzc 0 headphone switch zero cross enable 0 : switch immediately 1 : switch on zero crossing only table 14 headphone switch hpswen hpswpol hpdetect (pin23) l/rout1 (reg. 26) l/rout2 (reg. 26) headphone enabled speaker enabled 0 x x 0 0 no no 0 x x 0 1 no yes 0 x x 1 0 yes no 0 x x 1 1 yes yes 1 0 0 x 0 no no 1 0 0 x 1 no yes 1 0 1 0 x no no 1 0 1 1 x yes no 1 1 0 0 x no no 1 1 0 1 x yes no 1 1 1 x 0 no no 1 1 1 x 1 no yes table 15 headphone switch operation figure 10 example headset detection circuit using normally-open switch lr switch opens on insertion + - + - lout1 rout1 hpdetect headphone / speaker switching 33k avdd hpswen = 1 hpswpol = 0 l/rout1 = l/rout2 = 1 figure 11 example headset detection circuit using normally-closed switch wm8955l production data w pd rev 4.2 march 2006 26 lout1/rout1 outputs the lout1 and rout1 pins can drive a 16 ? or 32 ? headphone or a line output (see headphone output and line output sections, respectively). the signal volume on lout1 and rout1 can be independently adjusted under software control by writing to lout1vol and rout1vol, respectively. note that gains over 0db may cause clipping if the signal is large. any gain setting below 0101111 (minimum gain) mutes the output driver. the corresponding output pin remains at the same dc level (the reference voltage on the vref pin), so that no click noise is produced when muting or un-muting. the analogue outputs have a zero cross detect feature to minimize audible cli cks and zipper noise when on gain changes (i.e. the updating of the gain value is delayed until the signal passes through zero). by default, this includes a time-out function, which forces the gain to update if no zero crossing occurs within a certain period of time. register address bit label default description 6:0 lout1vol 1111001 (0db) lout1 volume 1111111 = +6db ? (80 steps) 0110000 = -67db 0101111 to 0000000 = analogue mute 7 lo1zc 0 lout1 zero cross enable 1 = change gain on zero cross only 0 = change gain immediately r2 (02h) lout1 volume 8 lo1vu 0 left volume update 0 = store lout1vol in intermediate latch (no gain change) 1 = update left and right channel gains (left = lout1vol, right = intermediate latch) 6:0 rout1vol 1111001 (0db) rout1 volume similar to lout1vol 7 ro1zc 0 rout1 zero cross enable similar to lo1zc r3 (03h) rout1 volume 8 ro1vu 0 right volume update 0 = store rout1vol in intermediate latch (no gain change) 1 = update left and right channel gains (left = intermediate latch, right = rout1vol) r23 (17h) 0 toen 1 time-out enable for zero-cross detectors 0 = time-out disabled (i.e. gains are never updated if there is no zero crossing) 1 = time-out enabled table 16 lout1/rout1 volume control production data wm8955l w pd rev 4.2 march 2006 27 lout2/rout2 outputs the lout2 and rout2 output pins are essentially similar to lout1 and rout1, but they are independently controlled and can drive an 8 ? mono speaker. for speaker drive, the rout2 signal must be inverted (rout2inv = 1), so that the left and right channel are mixed to mono in the speaker [l?(-r) = l+r]. register address bit label default description 6:0 lout2vol 1111001 (0db) similar to lout1vol 7 lo2zc 0 left zero cross enable 1 = change gain on zero cross only 0 = change gain immediately r40 (28h) lout2 volume 8 lo2vu 0 similar to lo1vu 6:0 rout2vol 1111001 (0db) similar to rout1vol 7 ro2zc 0 right zero cross enable 1 = change gain on zero cross only 0 = change gain immediately r41 (29h) rout2 volume 8 ro2vu 0 similar to ro1vu r23 (17h) 0 toen 1 as for lout1 / rout1 r24 (18h) additional (2) 4 rout2inv 0 rout2 invert 0 = no inversion (0 phase shift) 1 = signal inverted (180 phase shift) table 17 lout2/rout2 control mono output the monoout pin can drive a mono line output. the signal volume on monoout can be adjusted under software control by writing to monooutvol. register address bit label default description 6:0 monoout vol 1111001 (0db) monoout volume 1111111 = +6db ? (80 steps) 0110000 = -67db 0101111 to 0000000 = analogue mute r42 (2ah) monoout volume 7 mozc 0 monoout zero cross enable 1 = change gain on zero cross only 0 = change gain immediately r23 (17h) 0 toen 1 as for lout1 / rout1 table 18 monoout volume control out3 output the out3 pin can drive a 16 ? or 32 ? headphone or a line output or be used as a dc reference for a headphone output. it can be selected to either drive out an inverted rout1 or inverted monoout for e.g. an earpiece drive between out3 and lout1 or differential output between out3 and monoout. out3sw selects the mode of operation required. register address bit label default description r24 (18h) additional (2) 8:7 out3sw 00 out3 select 00 : vref 01 : rout1 10 : monoout 11 : right mixer output table 19 out3 select wm8955l production data w pd rev 4.2 march 2006 28 digital audio interface the digital audio interface is used for feeding audio data into the wm8955l. it uses three pins: ? dacdat: dac data input ? daclrc: dac data alignment clock ? bclk: bit clock, for synchronisation the clock signals bclk and daclrc can be outputs when the wm8955l operates as a master, or inputs when it is a slave (see master and slave mode operation, below). four different audio data formats are supported: ? left justified ? right justified ? i 2 s ? dsp mode all four of these modes are msb first. they are described in audio data formats, below. refer to the electrical characteristic section for timing information. master and slave mode operation the wm8955l can be configured as either a master or slave mode device. as a master device the wm8955l generates bclk and daclrc and thus controls sequencing of the data transfer on dacdat. in slave mode, the wm8955l responds with data to clo cks it receives over the digital audio interface. the mode can be selected by writing to the ms control bit. master and slave modes are illustrated below. bclk dacdat daclrc wm8955l dac dsp / decoder bclk dacdat daclrc wm8955l dac dsp / decoder figure 12 master mode figure 13 slave mode audio data formats in left justified mode, the msb is available on the first rising edge of bclk following a daclrc transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each daclrc transition. figure 14 left justified audio interface (assuming n-bit word length) in right justified mode, the lsb is available on the last rising edge of bclk before a daclrc transition. all other bits are transmitted before (msb first). depending on word length, bclk frequency and sample rate, there may be unused bclk cycles after each daclrc transition. production data wm8955l w pd rev 4.2 march 2006 29 figure 15 right justified audio interface (assuming n-bit word length) in i 2 s mode, the msb is available on the second rising edge of bclk following a daclrc transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next. figure 16 i 2 s justified audio interface (assuming n-bit word length) in dsp mode, the left channel msb is available on either the first or second rising edge of bclk (selectable by lrp) following a rising edge of daclrc. right channel data immediately follows left channel data. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. figure 17 dsp mode audio interface (mode a; lrp = 0) wm8955l production data w pd rev 4.2 march 2006 30 figure 18 dsp mode audio interface (mode b; lrp = 1) audio interface control the register bits controlling audio format, word length and master / slave mode are summarised below. register address bit label default description 1:0 format 10 audio data format select 11 = dsp mode 10 = i 2 s format 01 = left justified 00 = right justified 3:2 wl 10 audio data word length 11 = 32 bits (see note) 10 = 24 bits 01 = 20 bits 00 = 16 bits 4 lrp 0 i 2 s, lj, rj formats 1: invert lrclk polarity 0: normal lrclk polarity dsp format 1: msb available on 1 st bclk rising edge after lrc rising edge 0: msb available on 2 nd bclk rising edge after lrc rising edge 5 lrswap 0 swap left and right channels 0: no swap (l to l, r to r) 1: swap (l to r, r to l) 6 ms 0 master / slave mode control 1: master mode 0: slave mode r7 (07h) digital audio interface format 7 bclkinv 0 bclk invert 1: bclk inverted 0: bclk not inverted table 20 audio data format control note: right justified mode does not support 32-bit data. if wl=11 in right justified mode, the actual word length will be 24 bits. production data wm8955l w pd rev 4.2 march 2006 31 master clock and phase locked loop the wm8955l has an on-chip phase-locked loop (pll) circuit that can be used to: ? generate a master clock for the wm9755l audio function from another external clock, e.g. in telecoms applications. ? generate a clock for another part of the system from an existing audio master clock. the pll circuit is shown below. digital core mclk f/2 pll r = f 2 / f 1 clkout f/2 mclk sel clkout sel mclk div2 clkout div2 f/4 f/2 pllout div2 clkouten f 2 f 1 figure 19 pll circuit register address bit label default description 8 clkoutdiv2 0 clkout divide by 2 0: divide disabled 1: divide enabled r8 (08h) sample rates 6 mclkdiv2 0 mclk divide by 2 0: divide disabled 1: divide enabled 8 mclksel 0 select internal master clock 0: from mclk pin 1: from pll (make sure pllen=1) 7 clkouten 0 clkout enable 0: pin disabled (tri-state) 1: pin enabled 6 clkoutsel 0 select source of clkout 0: from mclk pin 1: from pll (make sure pllen=1) 5 plloutdiv2 0 pll output divide by 2 0: divide disabled 1: divide enabled 4 pll_rb 0 0: pll held in reset 1: pll running (if pllen=1) r43 (2bh) clocking and pll 3 pllen 0 pll enable 0: pll disabled; 1: pll enabled. table 21 pll and clocking control wm8955l production data w pd rev 4.2 march 2006 32 the pll frequency ratio r = f 2 /f 1 (see figure 19) can be set using k and n in registers 44 (2ch) to 46 (2eh): n = int (r) k = int (2 22 (r-n)) example: mclk = 12mhz required clock = 12.288mhz r should be chosen to ensure 5 wm8955l production data w pd rev 4.2 march 2006 34 mclk mclkdiv2=0 mclk mclkdiv2=1 dac sample rate usb sr [4:0] filter type bclk (ms=1) ?normal? clock mode (?*? indicates backward compatibility with wm8711 and wm8721) 8 khz (mclk/1536) 0 00010 * 1 mclk/4 12 khz (mclk/1024) 0 01000 1 mclk/4 16 khz (mclk/768) 0 01010 1 mclk/4 24 khz (mclk/512) 0 11100 1 mclk/4 32 khz (mclk/384) 0 01100 * 1 mclk/4 48 khz (mclk/256) 0 00000 * 1 mclk/4 12.288mhz 24.576mhz 96 khz (mclk/128) 0 01110 * 3 mclk/2 8.0182 khz (mclk/1408) 0 10010 1 mclk/4 11.025 khz (mclk/1024) 0 11000 1 mclk/4 22.05 khz (mclk/512) 0 11010 1 mclk/4 44.1 khz (mclk/256) 0 10000 * 1 mclk/4 11.2896mhz 22.5792mhz 88.2 khz (mclk/128) 0 11110 * 3 mclk/2 8 khz (mclk/2304) 0 00011 * 1 mclk/6 12 khz (mclk/1536) 0 01001 1 mclk/6 16 khz (mclk/1152) 0 01011 1 mclk/6 24 khz (mclk/768) 0 11101 1 mclk/6 32 khz (mclk/576) 0 01101 * 1 mclk/6 48 khz (mclk/384) 0 00001 * 1 mclk/6 18.432mhz 36.864mhz 96 khz (mclk/192) 0 01111 * 3 mclk/3 8.0182 khz (mclk/2112) 0 10011 * 1 mclk/6 11.025 khz (mclk/1536) 0 11001 1 mclk/6 22.05 khz (mclk/768) 0 11011 1 mclk/6 44.1 khz (mclk/384) 0 10001 * 1 mclk/6 16.9344mhz 33.8688mhz 88.2 khz (mclk/192) 0 11111 * 3 mclk/3 usb mode (assumes bclkdiv2=0. ?*? indicates backward compatibility with wm8711 and wm8721) 8 khz (mclk/1500) 1 00010 * 0 mclk 11.0259 khz (mclk/1088) 1 11001 1 mclk 12khz (mclk/1000) 1 01000 0 mclk 16khz (mclk/750) 1 01010 0 mclk 22.0588 khz (mclk/544) 1 11011 1 mclk 24khz (mclk/500) 1 11100 0 mclk 32 khz (mclk/375) 1 01100 * 0 mclk 44.118 khz (mclk/272) 1 10001 * 1 mclk 48 khz (mclk/250) 1 00000 * 0 mclk 88.235khz (mclk/136) 1 11111 * 3 mclk 12.000mhz 24.000mhz 96 khz (mclk/125) 1 01110 * 2 mclk table 25 master clock and sample rates production data wm8955l w pd rev 4.2 march 2006 35 control interface selection of control mode the wm8955l is controlled by writing to registers through a serial control interface. a control word consists of 16 bits. the first 7 bits (b15 to b9) are address bits that select which control register is accessed. the remaining 9 bits (b8 to b0) are register bits, corresponding to the 9 bits in each control register. the control interface can operate as either a 3-wire or 2-wire mpu interface. the mode pin selects the interface format. mode interface format low 2 wire high 3 wire table 26 control interface mode selection 3-wire serial control mode in 3-wire mode, every rising edge of sclk clo cks in one data bit from the sdin pin. a rising edge on csb latches in a complete control word consisting of the last 16 bits. b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 sdin sclk csb control register address control register data bits latch figure 20 3-wire serial control interface 2-wire serial control mode the wm8955l supports software control via a 2-wire serial bus. many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address of each register in the wm8955l). the wm8955l operates as a slave device only. the controller indicates the start of data transfer with a high to low transition on sdin while sclk remains high. this indicates that a device address and data will follow. all devices on the 2-wire bus respond to the start condition and shift in the next eight bits on sdin (7-bit address + read/write bit, msb first). if the device address received matches the address of the wm8955l and the r/w bit is ?0?, indicating a write, then the wm8955l responds by pulling sdin low on the next clock pulse (ack). if the address is not recognised or the r/w bit is ?1?, the wm8955l returns to the idle condition and wait for a new start condition and valid address. once the wm8955l has acknowledged a correct address, the controller sends the first byte of control data (b15 to b8, i.e. the wm8955l register address plus the first bit of register data). the wm8955l then acknowledges the first data byte by pulling sdin low for one clock pulse. the controller then sends the second byte of control data (b7 to b0, i.e. the remaining 8 bits of register data), and the wm8955l acknowledges again by pulling sdin low. the transfer of data is complete when there is a low to high transition on sdin while sclk is high. after receiving a complete address and data sequence the wm8955l returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sdin changes while sclk is high), the device jumps to the idle condition. wm8955l production data w pd rev 4.2 march 2006 36 figure 21 2-wire serial control interface the wm8955l has two possible device addresses, which can be selected using the csb pin. csb state device address low 0011010 high 0011011 table 27 2-wire mpu interface address selection power supplies the wm8955l can use up to four separate power supplies: ? avdd / agnd: analogue supply, powers all analogue functions except the headphone drivers. avdd can range from 1.8v to 3.6v and has the most significant impact on overall power consumption (except for power consumed in the headphone). a large avdd slightly improves audio quality. ? hpvdd / hpgnd: headphone supply, powers the headphone drivers. hpvdd is normally tied to avdd, but it requires separate layout and decoupling capacitors to curb harmonic distortion. if hpvdd is lower than avdd, the output signal may be clipped. ? dcvdd: digital core supply, powers all digital functions except the audio and control interfaces. dcvdd can range from 1.42v to 3.6v, and has no effect on audio quality. the return path for dcvdd is dgnd, which is shared with dbvdd. ? dbvdd: digital buffer supply, powers the audio and control interface buffers. this makes it possible to run the digital core at very low voltages, saving power, while interfacing to other digital devices using a higher voltage. dbvdd draws much less power than dcvdd, and has no effect on audio quality. the return path for dbvdd is dgnd, which is shared with dcvdd. it is possible to use the same supply voltage on all four. however, digital and analogue supplies should be routed and decoupled separately to keep digital switching noise out of the analogue signal paths. production data wm8955l w pd rev 4.2 march 2006 37 power management the wm8955l has two control registers that allow users to select which functions are active. for minimum power consumption, unused functions should be disabled. to avoid any pop or click noise, it is important to enable or disable functions in the correct order (see applications information) register address bit label default description 8:7 vmidsel 00 vmid resistor divider select 00 ? vmid disabled 01 ? 50k ? divider enabled 10 ? 500k ? divider enabled 11 ? 5k ? divider enabled (for fast start-up) r25 (19h) power manageme nt (1) 6 vref 0 vref (necessary for all other functions) 8 dacl 0 dac left enable 0=off 1=on 7 dacr 0 dac right enable 0=off 1=on 6 lout1 0 lout1 output buffer* enable 0=off 1=on 5 rout1 0 rout1 output buffer* enable 0=off 1=on 4 lout2 0 lout2 output buffer* enable 0=off 1=on 3 rout2 0 rout2 output buffer* enable 0=off 1=on 2 mout 0 monoout output buffer and mono mixer enable 0=off 1=on r26 (1ah) power manageme nt (2) 1 out3 0 out3 output buffer enable 0=off 1=on note: * the left mixer is enabled when lout1=1 or lout2=1. the right mixer is enabled when rout1=1 or rout2=1. table 28 power management wm8955l production data w pd rev 4.2 march 2006 38 stopping the master clock in order to minimise power consumed in the digital core of the wm8955l, the master clock should be stopped in standby and off modes. if this is cannot be done externally at the clock source, the digenb bit (r25, bit 0) can be set to stop the mclk signal from propagating into the device core. however, since setting digenb has no effect on the power consumption of other system components external to the wm8955l, it is preferable to disable the master clock at its source wherever possible. register address bit label default description r25 (19h) additional control (1) 0 digenb 0 master clock disable 0: master clock enabled 1: master clock disabled table 29 adc and dac oversampling rate selection note: before digenb can be set, the control bits dacl and dacr must be set to zero and a waiting time of 1ms must be observed. any failure to follow this procedure may prevent dacs and adcs from re-starting correctly. oversampling rate by default, the oversampling rate of the dac digital filters is 128x. however, this can be changed to 64x by writing to the dacosr bit. in the 64x oversampling mode, the digital filters consumes less power. however, the signal-to-noise ratio is slightly reduced. register address bit label default description 0 dacosr 0 dac oversample rate select 1 = 64x (lowest power) 0 = 128x (best snr) table 30 oversampling rate selection saving power at low supply voltages the analogue supplies to the wm8955l can run from 1.8v to 3.6v. by default, all analogue circuitry on the device is optimized to run at 3.3v. this set-up is also good for all other supply voltages down to 1.8v. however, at lower voltages, it is possible to save power by reducing the internal bias currents used in the analogue circuitry. this is controlled as shown below. register address bit label default description r23 (17h) additional control(1) 7:6 vsel[1:0] 11 analogue bias optimization 00 : lowest bias current, optimized for 1.8v 01 : low bias current, optimized for 2.5v 10, 11 : default bias current, optimized for 3.3v table 31 analogue bias selection production data wm8955l w pd rev 4.2 march 2006 39 register map register address (bit 15 ? 9) remarks bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r0 (00h) 0000000 reserved 000000000 r1 (01h) 0000001 reserved 000000000 r2 (02h) 0000010 lout1 lo1vu lo1zc lout1vol r3 (03h) 0000011 rout1 ro1vu ro1zc rout1vol r4 (04h) 0000100 reserved 000000000 r5 (05h) 0000101 dac control 0 dat 0 0 0 dacmu deemph 0 r6 (06h) 0000110 reserved 000000000 r7 (07h) 0000111 audio interface 0 bclkinv ms lrswap lrp wl format r8 (08h) 0001000 sample rates clkout div2 bclk div2 mclk div2 sr usb r9 (09h) 0001001 reserved 000000000 r10 (0ah) 0001010 left gain ldvu ldacvol (right dac digital volume) r11 (0bh) 0001011 right gain rdvu rdacvol (right dac digital volume) r12 (0ch) 0001100 bass 0 bb bc 0 0 bass (bass intensity) r13 (0dh) 0001101 treble 0 0 tc 0 0 trbl (treble intensity) r14 (0eh) 0001110 tbd 000000000 r15 (0fh) 0001111 reset writing 000000000 to this register resets all registers to their default state r16 ? r22 reserved 000000 r23 (17h) 0010111 additional (1) tsden vsel dmonomix 0 0 dacinv toen r24 (18h) 0011000 additional (2) out3sw hpswen hpswpol rout2inv hpswzc 0 0 dacosr r25 (19h) 0011001 pwr mgmt (1) vmidsel vref 0 0 0 0 0 digenb r26 (1ah) 0011010 pwr mgmt (2) dacl dacr lout1 rout1 lout2 rout2 mout out3 0 r27 (1bh) 0011011 additional (3) 0 0 vroi 0 0 0 0 0 0 r28 ? r33 reserved r34 (22h) 0100010 left mix (1) ld2lo li2lo li2lovol 0 0 0 0 r35 (23h) 0100011 left mix (2) rd2lo mi2lo mi2lovol 0 0 0 0 r36 (24h) 0100100 right mix (1) ld2ro mi2ro mi2rovol 0 0 0 0 r37 (25h) 0100101 right mix (2) rd2ro ri2ro ri2rovol 0 0 0 0 r38 (26h) 0100110 mono mix (1) ld2mo li2mo li2movol 0 0 0 dmen r39 (27h) 0100111 mono mix (2) rd2mo ri2mo ri2movol 0 0 0 0 r40 (28h) 0101000 lout2 lo2vu lo2zc lout2vol r41 (29h) 0101001 rout2 ro2vu ro2zc rout2vol r42 (2ah) 0101010 monoout 0 mozc monooutvol r43 (2bh) 0101011 clocking / pll mclksel clkout en clkout sel pllout div2 pll_rb pllen 0 0 0 r44 (2ch) 0101100 pll control (1) n 0 k [21:18] r45 (2dh) 0101101 pll control (2) k [17:9] r46 (2eh) 0101110 pll control (3) k [8:0] r59 (3bh) 0111011 pll control (4) 0 ken 0 0 0 0 0 0 0 wm8955l production data w pd rev 4.2 march 2006 40 digital filter characteristics depending on the mclk frequency and sample rate selected, 4 different types of digital filter can be used in the dac, called type 0, 1, 2 and 3 (see ?master clock and audio sample rates?). the performance of types 0 and 1 is listed in the table below, the responses of all filters is shown in the following pages. parameter test conditions min typ max unit dac filter type 0 (usb mode, 250fs operation) +/- 0.03db 0 0.416fs passband -6db 0.5fs passband ripple +/-0.03 db stopband 0.584fs stopband attenuation f > 0.584fs -50 db dac filter type 1 (usb mode, 272fs or normal mode operation) +/- 0.03db 0 0.4535fs passband -6db 0.5fs passband ripple +/- 0.03 db stopband 0.5465fs stopband attenuation f > 0.5465fs -50 db table 32 digital filter characteristics mode group delay 0 (250 usb) 11/fs 1 (256/272) 16/fs 2 (250 usb, 96k mode) 4/fs 3 (256/272, 88.2/96k mode) 3/fs table 33 dac filters terminology stop band attenuation (db) ? the degree to which the frequency spectrum is attenuated (outside audio band) pass-band ripple ? any variation of the frequency response in the pass-band region dac filter responses -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 22 dac filter frequency response ? type 0 figure 23 dac filter ripple ? type 0 production data wm8955l w pd rev 4.2 march 2006 41 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 24 dac filter frequency response ? type 1 figure 25 dac filter ripple ? type 1 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 response (db) frequency (fs) figure 26 dac filter frequency response ? type 2 figure 27 dac filter ripple ? type 2 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.25 -0.2 -0.15 -0.1 -0.05 0 0 0.05 0.1 0.15 0.2 0.25 response (db) frequency (fs) figure 28 dac filter frequency response ? type 3 figure 29 dac filter ripple ? type 3 wm8955l production data w pd rev 4.2 march 2006 42 applications information recommended external components figure 30 recommended external component diagram production data wm8955l w pd rev 4.2 march 2006 43 minimising pop noise at the analogue outputs to minimise any pop or click noise when the system is powered up or down, the following procedures are recommended. power up ? switch on power supplies. by default the wm8955l is in off mode (i.e. only the control interface is powered up) ? enable the reference voltage vref by setting the wm8955l to standby mode. do not enable any of the analogue outputs at this point. ? allow vref to settle. the settling time depends on the value of the capacitor connected at vmid, and the size of the resistors selected using vmidsel ( = rc). ? enable dacs, etc. as required. ? enable outputs required. ? set dacmu = 0 to soft-un-mute the audio dacs. power down ? set dacmu = 1 to soft-mute the audio dacs. ? disable outputs. ? switch off the power supplies. line output configuration all the analogue outputs, lout1/rout1, lout2/rout2, and monoout, can be used as line outputs. recommended external components are shown below. agnd agnd line-out socket (left) c1 1uf r1 100 ohm lout2 rout2 wm8955l r2 100 ohm line-out socket (right) c2 1uf figure 31 recommended circuit for line output the dc blocking capacitors and the load resistance together determine the lower cut-off frequency, f c . assuming a 10 k ? load and c1, c2 = 1 f: f c = 1 / 2 (r l +r 1 ) c 1 = 1 / (2 x 10.1k ? x 1 f) = 16 hz increasing the capacitance lowers f c , improving the bass response. smaller values of c1 and c2 will diminish the bass response. the function of r1 and r2 is to protect the line outputs from damage when used improperly. wm8955l production data w pd rev 4.2 march 2006 44 headphone output configuration the analogue outputs lout1/rout1, lout2/rout2, and out3 can drive a 16 ? or 32 ? headphone load, either through dc blocking capacitors, or dc coupled without any capacitor. headphone output using dc blocking capacitors dc coupled headphone output (out3sw = 00) wm8955l c2 220uf lout1 rout1 hpgnd = 0v c1 220uf wm8955l hpdcen = 1 lout1 rout1 hpdc = avdd/2 figure 32 recommended headphone output configurations when dc blocking capacitors are used, then their capacitance and the load resistance together determine the lower cut-off frequency, f c . increasing the capacitance lowers f c , improving the bass response. smaller capacitance values will diminish the bass response. assuming a 16 ? load and c1 = 220 f: f c = 1 / 2 r l c 1 = 1 / (2 x 16 ? x 220 f) = 45 hz in the dc coupled configuration, the headphone ?ground? is connected to the out3 pin, which must be enabled by setting out3 = 1 and out3sw = 00. as the out3 pin produces a dc voltage of avdd/2 (=vref), there is no dc offset between lout1/rout1 and out3, and therefore no dc blocking capacitors are required. this saves space and material cost in portable applications. it is recommended to connect the dc coupled headphone outputs only to headphones, and not to the line input of another device. although the built-in short circuit protection will prevent any damage to the headphone outputs, such a connection may be noisy, and may not function properly if the other device is grounded. speaker output configuration lout2 and rout2 can differentially drive a mono 8 ? speaker as shown below. lout2 rout2 wm8955l rout2inv = 1 v spkr = l-(-r) = l+r -1 left mixer right mixer rout2vol lout2vol figure 33 speaker output connection the right channel is inverted by setting the rout2inv bit, so that the signal across the loudspeaker is the sum of left and right channels. production data wm8955l w pd rev 4.2 march 2006 45 package dimensions dm030.e fl: 32 pin qfn plastic package 5 x 5 x 0.9 mm body, 0.50 mm lead pitch notes: 1. dimension b applied to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. dimension l1 repr esents terminal pull back from package side wall. maximum of 0.1mm is acceptable. where terminal pull back exists, only upper half of lead is visible on package side wall due to half etching of leadframe. 2. falls within jedec, mo-220 with the exception of d2, e2: d2,e2: larger pad size chosen which is just outside jedec specification 3. all dimensions are in millimetres 4. this drawing is subject to change without notice. 5. shape and size of corner tie bar may vary with package terminal count. corner tie bar is connected to exposed pad internall y. 6. refer to application note wan_0118 for further information regarding pcb footprints and qfn package soldering. see detail b e2 e2/2 b b 16 15 a 8 9 e 5 corner tie bar b d2 l d2/2 see detail a index area (d/2 x e/2) top view d c aaa 2 x c aaa 2 x e detail b terminal tip r datum e e/2 l1 1 detail a b c bbb m a 32x b l 32x k l1 r 1 1 0 . 5 6 6 m m 0 . 4 3 m m 5 corner tie bar symbols dimensions (mm) min nom max note a a1 a3 b d d2 e e2 e l l1 r 0.85 0.90 1.00 0.05 0.02 0 0.2 ref 0.30 0.23 0.18 5.00 3.4 3.3 3.2 0.5 bsc 0.35 0.4 0.45 0.1 b(min)/2 1 2 2 1 k 0.20 aaa bbb ccc ref: 0.15 0.10 0.10 jedec, mo-220, variation vhhd-2 tolerances of form and position 4.90 5.10 5.00 4.90 5.10 3.4 3.3 3.2 1 17 24 25 32 exposed ground paddle 6 exposed ground paddle bottom view c 0.08 c ccc a a1 c (a3) seating plane 1 side view wm8955l production data w pd rev 4.2 march 2006 46 important notice wolfson microelectronics plc (wm) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. all products are sold subject to the wm terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. wm warrants performance of its products to the specifications applicable at the time of sale in accordance with wm?s standard warranty. testing and other quality control techniques are utilised to the extent wm deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. in order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. wm assumes no liability for applications assistance or customer product design. wm does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of wm covering or relating to any combination, machine, or process in which such products or services might be or are used. wm?s publication of information regarding any third party?s products or services does not constitute wm?s approval, license, warranty or endorsement thereof. reproduction of information from the wm web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this information with alteration voids all warranties provided for an associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. resale of wm?s products or services with statements different from or beyond the parameters stated by wm for that product or service voids all express and any implied warranties for the associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com |
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