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| 2500 mhz to 2900 mhz rx mixer with integrated fractional-n pll and vco ADRF6604 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features rx mixer with integrated fractional-n pll rf input frequency range: 1200 mhz to 3600 mhz internal lo frequency range: 2500 mhz to 2900 mhz input p1db: 14.6 dbm input ip3: 27.5 dbm iip3 optimization via external pin ssb noise figure ip3set pin open: 14.2 db ip3set pin at 3.3 v: 15.4 db voltage conversion gain: 6.3 db matched 200 if output impedance if 3 db bandwidth: 500 mhz programmable via 3-wire spi interface 40-lead, 6 mm 6 mm lfcsp applications cellular base stations general description the ADRF6604 is a high dynamic range active mixer with an integrated fractional-n phase-locked loop (pll) and a voltage- controlled oscillator (vco) for internal mixer lo generation. along with the adrf6601 , adrf6602 , and adrf6603 , the ADRF6604 forms a family of integrated pll/mixers. the ADRF6604 covers the frequency range of 2500 mhz to 2900 mhz. the pll reference input can support input frequencies from 12 mhz to 160 mhz. the pfd output controls a charge pump whose output drives an off-chip loop filter. the loop filter output is then applied to an integrated vco. the vco output at 2 f lo is applied to an lo divider, as well as to a programmable pll divider. the programmable pll divider is controlled by a - modulator (sdm). the modulus of the sdm can be programmed from 1 to 2047. the active mixer converts the single-ended 50 rf input to a 200 differential if output. the if output can operate up to 500 mhz. the ADRF6604 is fabricated using an advanced silicon-germanium bicmos process. it is available in a 40-lead, rohs-compliant, 6 mm 6 mm lfcsp with an exposed paddle. performance is specified over the ?40c to +85c temperature range. table 1. part no. internal lo range 3 db rf input balun range 1 db rf input balun range adrf6601 750 mhz to 1160 mhz 300 mhz to 2500 mhz 450 mhz to 1600 mhz adrf6602 1550 mhz to 2150 mhz 1000 mhz to 3100 mhz 1350 mhz to 2750 mhz adrf6603 2100 mhz to 2600 mhz 1100 mhz to 3200 mhz 1450 mhz to 2850 mhz ADRF6604 2500 mhz to 2900 mhz 1200 mhz to 3600 mhz 1600 mhz to 3200 mhz functional block diagram mux r set cp vtune lodrv_en lon lop ip3set v cc1 2:1 mux vco core rf in temp sensor declvco decl2p5 decl3p3 ifp buffer buffer ifn v cc2 v cc_lo v cc_mix v cc_v2i v cc_lo nc ? + charge pump 250a, 500a (default), 750a, 1000a prescaler 2 le clk spi interface data muxout nc 3.3v ldo 2.5v ldo vco ldo div by 2, 1 pll_en ref_in gnd ADRF6604 internal lo range 2500mhz to 2900mhz 34 19 18 39 3 5 4 8 6 14 13 12 16 38 37 36 7 11 15 20 21 23 24 25 28 30 31 35 32 33 2 9 40 26 29 27 17 10 1 22 phase frequency detector third-order fractional interpolator fraction reg modulus integer reg n counter 21 to 123 2 2 4 0 8553-001 figure 1.
ADRF6604 rev. 0 | page 2 of 2 4 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? rf specifications .......................................................................... 3 ? synthesizer/pll specifications ................................................... 4 ? logic input and power specifications ....................................... 5 ? timing characteristics ................................................................ 5 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 9 ? register structure ........................................................................... 11 ? register 0integer divide control (default: 0x0001c0)..... 11 ? register 1modulus divide control (default: 0x003001) ........ 11 ? register 2fractional divide control (default: 0x001802) ...... 12 ? register 3- modulator dither control (default: 0x 10000b) ................................................................... 12 ? register 4pll charge pump, pfd, and reference path control (default: 0x0aa7e4) ................................................... 13 ? register 5pll enable and lo path control (default: 0x0000e5) ................................................................... 14 ? register 6vco control and vco enable (default: 0x1e2106) ................................................................... 14 ? register 7mixer bias enable and external vco enable (default: 0x000007) .................................................................... 14 ? theory of operation ...................................................................... 15 ? programming the ADRF6604 ................................................... 15 ? initialization sequence .............................................................. 15 ? lo selection logic ..................................................................... 16 ? applications information .............................................................. 17 ? basic connections for operation ............................................. 17 ? evaluation board ............................................................................ 18 ? evaluation board control software ......................................... 18 ? schematics and artwork ........................................................... 20 ? evaluation board configuration options ............................... 22 ? outline dimensions ....................................................................... 23 ? ordering guide .......................................................................... 23 ? revision history 6/10revision 0: initial version ADRF6604 rev. 0 | page 3 of 24 specifications rf specifications vccx = 5 v, ambient temperature (t a ) = 25c, f ref = 38.4 mhz, f pfd = 38.4 mhz, high-side lo injection, f if = 140 mhz, iip3 optimized using cdac = 0xc and ip3set = 3.3 v, unless otherwise noted. table 2. parameter test conditions/comments min typ max unit internal lo frequency range 2500 2900 mhz rf input frequency range 3 db rf input range 1200 3600 mhz rf input at 2360 mhz input return loss relative to 50 (can be improved with external match) ?22 db input p1db 14.8 dbm second-order intercept (iip2) ?5 dbm each to ne (10 mhz spacing between tones) 53.5 dbm third-order intercept (iip3) ?5 dbm each tone (10 mhz spacing between tones) 28.0 dbm single-sideband noise figure ip3set = 3.3 v 15.4 db ip3set = open 14.0 db lo-to-if leakage at 1 lo frequency, 50 termination at the rf port ?44.3 dbm rf input at 2560 mhz input return loss relative to 50 (can be improved with external match) ?22 db input p1db 14.8 dbm second-order intercept (iip2) ?5 dbm each to ne (10 mhz spacing between tones) 56.3 dbm third-order intercept (iip3) ?5 dbm each tone (10 mhz spacing between tones) 27.5 dbm single-sideband noise figure ip3set = 3.3 v 15.6 db ip3set = open 14.3 db lo-to-if leakage at 1 lo frequency, 50 termination at the rf port ?41.9 dbm rf input at 2760 mhz low-side injection input return loss relative to 50 (can be improved with external match) ?20 db input p1db 14.8 dbm second-order intercept (iip2) ?5 dbm each to ne (10 mhz spacing between tones) 66.0 dbm third-order intercept (iip3) ?5 dbm each tone (10 mhz spacing between tones) 27.1 dbm single-sideband noise figure ip3set = 3.3 v 16.0 db ip3set = open 14.7 db lo-to-if leakage at 1 lo frequency, 50 termination at the rf port ?41.2 dbm if output voltage conversion gain differential 200 load 6.3 db if bandwidth small-signal 3 db bandwidth 500 mhz output common-mode voltage external pull-up balun or inductors required 5 v gain flatness over frequency range, any 5 mhz/50 mhz 0.2/1.0 db gain variation over full temperature range 1.0 db output swing differential 200 load 2 v p-p output return loss relative to 200 ?15 db lo input/output (lop, lon) externally applie d 1 lo input, internal pll disabled frequency range 250 6000 mhz output level (lo as output) 1 lo into a 50 load, lo output buffer enabled ?8.7 dbm input level (lo as input) 6 dbm input impedance 50 ADRF6604 rev. 0 | page 4 of 2 4 synthesizer/pll specifications vccx = 5 v, ambient temperature (t a ) = 25c, f ref = 153.6 mhz, f ref power = 4 dbm, f pfd = 38.4 mhz, high-side lo injection, f if = 140 mhz, iip3 optimized using cdac = 0xc and ip3set = 3.3 v, unless otherwise noted. table 3. parameter test conditions/comments min typ max unit synthesizer specifications synthesizer specifications referenced to 1 lo frequency range internally generated lo 2500 2900 mhz figure of merit 1 f ref power = 0 dbm ?221.4 dbc/hz reference spurs f ref = 153.6 mhz f ref /4 ?106 dbc f ref /2 ?106 dbc f ref ?83.9 dbc > f ref ?81 dbc phase noise f lo = 2500 mhz to 2900 mhz, f pfd = 38.4 mhz 1 khz to 10 khz offset ?94.4 dbc/hz 100 khz offset ?96.4 dbc/hz 500 khz offset ?118.9 dbc/hz 1 mhz offset ?127.8 dbc/hz 5 mhz offset ?142.5 dbc/hz 10 mhz offset ?147.8 dbc/hz 20 mhz offset ?150.4 dbc/hz integrated phase noise 1 khz to 40 mhz integration bandwidth 0.6 rms pfd frequency 20 40 mhz reference characteristics ref_in, muxout pins ref_in input frequency 12 160 mhz ref_in input capacitance 4 pf muxout output level v ol (lock detect output selected) 0.25 v v oh (lock detect output selected) 2.7 v muxout duty cycle 50 % charge pump pump current programmable to 250 a, 500 a, 750 a, 1 ma 500 a output compliance range 1 2.8 v 1 the figure of merit (fom) is computed as phase noise (dbc/hz) C 10 log 10(f pfd ) C 20 log 10(f lo /f pfd ). the fom was measured across the full lo range, with f ref = 80 mhz and f ref power = 10 dbm (500 v/s slew rate) with a 40 mhz f pfd . the fom was computed at 50 khz offset. ADRF6604 rev. 0 | page 5 of 24 logic input and power specifications vccx = 5 v, ambient temperature (t a ) = 25c, f ref = 38.4 mhz, f pfd = 38.4 mhz, high-side lo injection, f if = 140 mhz, iip3 optimized using cdac = 0xc and ip3set = 3.3 v, unless otherwise noted. table 4. parameter test conditions/comments min typ max unit logic inputs clk, data, and le pins input high voltage, v inh 1.4 3.3 v input low voltage, v inl 0 0.7 v input current, i inh /i inl 0.1 a input capacitance, c in 5 pf power supplies vcc1, vcc2, vcc_lo, vcc_mix, and vcc_v2i pins voltage range 4.75 5 5.25 v supply current pll only 101 ma external lo mode (internal pll disabled, ip3set = 3.3 v) 179 ma internal lo mode (internal pll enabled, ip3set = 3.3 v) 280 ma power-down mode 30 ma timing characteristics vcc2 = 5 v 5%. table 5. parameter limit unit description t 1 20 ns min le setup time t 2 10 ns min data to clk setup time t 3 10 ns min data to clk hold time t 4 25 ns min clk high duration t 5 25 ns min clk low duration t 6 10 ns min clk to le setup time t 7 20 ns min le pulse width timing diagram clk data le db23 (msb) db22 db2 db1 (control bit c2) (control bit c3) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 08553-002 figure 2. timing diagram ADRF6604 rev. 0 | page 6 of 24 absolute maximum ratings table 6. parameter rating supply voltage, vcc1, vcc2, vcc_lo, vcc_mix, vcc_v2i ?0.5 v to +5.5 v digital i/o, clk, data, le ?0.3 v to +3.6 v ifp, ifn ?0.3 v to vcc_v2i + 0.3 v rf in 18 dbm lop, lon 13 dbm ja (exposed paddle soldered down) 35c/w maximum junction temperature 150c operating temperature range ?40c to +85c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution ADRF6604 rev. 0 | page 7 of 24 pin configuration and function descripti ons pin 1 indicator notes 1. nc = no connect. 2. the exposed paddle should be soldered to a low impedance ground plane. 1 vcc1 2 decl3p3 3 cp 4 gnd 5 r set 6 ref_ in 7 gnd 8 muxout 9 decl2p5 10 vcc2 23 gnd 24 gnd 25 gnd 26 rf in 27 vcc_v2i 28 gnd 29 ip3set 30 gnd 22 vcc_mix 21 gnd 11gnd 12data 13clk 15 gnd 17 v cc_l o 16 pll_en 18 ifp 19 ifn 20 gnd 14 le 33 nc 34 vcc_lo 35 gnd 36 lodrv_en 37 lon 38 lop 39 vtune 40 declvco 32 nc 31 gnd top view (not to scale) ADRF6604 08553-003 figure 3 . pin configuration table 7 . pin function descriptions pin no. mnemonic description 1 vcc 1 power supply for the 3.3 v ldo . power supply voltage range is 4.75 v to 5.25 v. each power supply pin should be decoupled with a 100 p f capacitor and a 0.1 f capacitor located close to the pin. 2 decl3p3 decoupling node for the 3.3 v ldo . connect a 0.1 f capacitor between this pin and ground. 3 cp charge p ump output pin. connect to vtune through the loop filter . 4 , 7 , 11, 15, 20 , 21, 23, 24 , 25, 28, 30 , 31 , 35 gnd ground . connect these pins to a low impedance ground plane. 5 r set c harge pump current . the nominal charge pump current can be set to 250 a, 500 a , 750 a, or 1 ma using bit s[ db1 1: db1 0] in register 4 and by setting bit db18 to 0 (i nternal reference current). in this mode, no external r set is required. if bit db18 is set to 1, the four nominal charge pump currents (i nominal ) can be externally adjusted according to the following equation: ?? ? ? ? ? ? ? ? ? = 8.37 4.217 nominal cp set i i r 6 ref _in reference input . nominal input level is 1 v p- p. input range is 12 mhz to 160 mhz. 8 muxout multiplex er output . this output can be programmed to provide the reference o utput signal or the l ock d etect signal. the output is selected by programming bits[db23:db21] in register 4. 9 decl2p5 decoupling node for the 2.5 v ldo . connect a 0.1 f capacitor between this pin and ground. 10 vcc2 power supply for the 2.5 v ldo. power supply voltage range is 4.75 v to 5.25 v. each power supply pin should be decoupled with a 100 pf capacitor and a 0.1 f capacitor located close to the pin. 12 data serial data input . th e serial data input is loaded msb first ; the three lsbs are the control bits. 13 clk serial clock input . th e serial clock input is used to clock in the serial data to the registers. the data is latched into the 24 - bit shift re gister on the clk rising edge . the m aximum clock frequency is 20 mhz. 14 le load enable . when the le input pin goes high, the data stored in the shift registers is loaded into one of the eight registers. t he relevant latch is selected by the three control bits of the 24 - bit word. 16 pll_en pll enable . switch between i nternal pll and external lo i nput. when this pin is logic high , the mixer lo is automatically switched to the internal pll and the internal pll is powered up. when this pin is logic low , the internal pll is powered down and the external lo input is routed to the mixer lo inputs. the spi can also be used to switch modes. 17, 34 vcc_lo power supply. power supply voltage range is 4.75 v to 5.25 v. each power supply pin should be decoupled with a 100 pf capacitor and a 0.1 f capacitor located close to the pin. 18, 19 ifp , ifn mixer if outputs . these outputs s hould be pulled to vcc _mix with rf c hokes . 22 vcc _mix power supply. power supply voltage range is 4.75 v to 5.25 v. each power supply pin should be decoupled with a 100 pf capacitor and a 0.1 f capacitor located close to the pin. 26 rf in rf input (single - ended, 50 ). ADRF6604 rev. 0 | page 8 of 24 pin no. mnemonic description 27 vcc_v2i power supply. power supply voltage range is 4.75 v to 5.25 v. each power supply pin should be decoupled with a 100 pf capacitor and a 0.1 f capacitor located close to the pin. 29 ip3set connect a resistor from this pin to a 5 v supply to adjust iip3. normally leave open. 32, 33 nc no connection. 36 lodrv_en lo driver enable. together with pin 16 (pll_en), this digital input pin determines whether the lop and lon pins operate as inputs or outputs. lop and lon become in puts if the pll_en pin is lo w or if the pll_en pin is set high with the plen bit (db6 in register 5) set to 0. lop and lon become outputs if either the lodrv_en pin or the ldrv bit (db3 in register 5) is set to 1 while the pll_en pin is set high. the external lo drive frequency must be 1 lo. this pin should not be left floating. 37, 38 lon, lop local oscillator input/output. the internally generated 1 lo is available on these pins. when internal lo generation is disabled, an external 1 lo can be applied to these pins. 39 vtune vco control voltage input. this pin is driven by the output of the loop filter. the nominal input voltage range on this pin is 1.5 v to 2.5 v. 40 declvco decoupling node for the vco ldo. connect a 100 pf capacitor and a 10 f capacitor between this pin and ground. ep epad exposed paddle. the exposed paddle should be soldered to a low impedance ground plane. ADRF6604 rev. 0 | page 9 of 24 typical performance characteristics cdac = 0x1, ip3set = 3.3 v, internally generated lo, rf in = ?10 dbm, f if = 140 mhz, unless otherwise noted. ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 gain (db) 2500 2550 2600 2650 2700 2750 2800 2850 2900 lo frequency (mhz) +25c ?40c +85c 08553-014 figure 4. gain vs. lo frequency 2500 2550 2600 2650 2700 2750 2800 2850 2900 30 40 50 60 70 80 90 lo frequency (mhz) input ip2 (dbm) +25c ?40c +85c 0 8553-015 figure 5. iip2 vs. lo frequency, rf in = ?5 dbm 10 11 12 13 14 15 16 17 18 19 20 lo frequency (mhz) noise figure (db) 2400 2500 2600 2700 2800 2900 3000 +25c ?40c +85c 08553-016 figure 6. noise figure vs. lo frequency 2500 2550 2600 2650 2700 2750 2800 2850 2900 5 10 15 20 25 30 35 40 45 lo frequency (mhz) input ip3 (dbm) +25c ?40c +85c 0 8553-017 figure 7. iip3 vs. lo frequency, rf in = ?5 dbm 2500 2550 2600 2650 2700 2750 2800 2850 2900 0 2 4 6 8 10 12 14 16 18 20 input p1db (dbm) lo frequency (mhz) +25c ?40c +85c 08553-018 figure 8. ip1db vs. lo frequency 2500 2550 2600 2650 2700 2750 2800 2850 2900 ?60 ?50 ?40 ?30 ?20 ?10 0 lo frequency (mhz) lo feedthrough amplitude (dbm) +25c ?40c +85c 08553-019 figure 9. lo-to-if leakage vs. lo frequency, lo output turned off, 50 termination at rf port ADRF6604 rev. 0 | page 10 of 24 phase noise measurements made at if output, unless otherwise noted. ?150 ?140 ?130 ?120 ?110 ?100 ?90 ? 80 lo f requency (mhz) phase noise at different offsets (dbc/hz) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 integrated phase noise (rms) 2500 2900 2850 2800 2750 2700 2650 2600 2550 1khz offset 10khz offset 100khz offset intergrated phase noise 1mhz offset 10mhz offset 08553-020 figure 10. pll spot phase noise at various offsets and integrated phase noise vs. lo frequency ?110 2500 2550 2600 2650 2700 2750 2800 2850 2900 ?105 ?100 ?95 ?90 ?80 ? 70 ?85 ?75 lo f requency (mhz) spurs level (dbc) 1 pfd offset 2 pfd offset 4 pfd offset 0.25 and 0.5 pfd offset 08553-021 figure 11. pll reference spurs vs. lo frequency ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ? 80 1k 1 0k 100k 1m 10m 100m offset frequency (hz) phase noise (dbc/hz) lo = 2902.4mhz lo = 2499.2mhz 08553-022 figure 12. phase noise vs. offset frequency and lo frequency (lo frequency varies from 2500 mhz to 2900 mhz) ADRF6604 rev. 0 | page 11 of 24 register structure this section provides the register maps for the ADRF6604. the three lsbs determine the register that is programmed. register 0integer divide control (default: 0x0001c0) divide mode db23 db22 db21 db20 db19 db18 db1 7 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0000000000000dmid6id5id4id3id2id1id0c3(0)c2(0)c1(0) dm 0 1 id6 id5 id4 id3 id2 id1 id0 0010101 0010110 0010111 0011000 ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0111000 ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1110111 1111000 1111001 1111010 1111011 ... ... 119 120 (integer mode only) integer divide ratio 21 (integer mode only) 22 (integer mode only) 23 (integer mode only) 24 ... ... 56 (default) integer integer divide ratio control bits divide mode fractional (default) 121 (integer mode only) 122 (integer mode only) 123 (integer mode only) reserved 08553-004 figure 13. register 0integer divide control register map register 1modulus divide control (default: 0x003001) modulus value db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db1 3 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 0 md10 md9 md8 md7 md6 md5 md4 md3 md2 md1 md0 c3(0) c2(0) c1(1) md10md9md8md7md6md5md4md3md2md1md0 0 0000000001 0 0000000010 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1000000000 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1111111111 modulus value ... ... 2047 control bits 1 1536 (default) 2 ... ... reserved 08553-005 figure 14. register 1modulus divide control register map ADRF6604 rev. 0 | page 12 of 24 register 2fractional divi de control (default: 0x001802) fd10fd9fd8fd7fd6fd5fd4fd3fd2fd1fd0 0 0000000000 0 0000000001 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0 1100000000 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... fractional value must be less than modulus fractional value 0 1 ... ... 768 (default) ... ... ADRF6604 rev. 0 | page 14 of 24 register 5pll enable and lo path control (default: 0x0000e5) reserved lo div1 pll en lo div1 lo ext lo drv db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 ldv2 db6 db5 db4 db3 db2 db1 db0 cd3 cd2 cd1 cd0 plen ldv1 lxl ldrv c3(1) c2(0) c1(1) ldrv 0 1 lxl 0 1 ldv1 0 1 divide by 1 divide by 2 (default) lo output driver enable driver off (default) driver on plen 0 1 disable enable (default) pll enable external lo drive enable (pin 37, pin 38) internal lo output (default) external lo input divide-by-2 in lo chain enable cap dac control bits cd3 cd2 cd1 cd0 0000 ... ... ... ... min ... capacitor dac control for iip3 optimization 1111 max 000 0 0 000 000 0 08553-009 ldv2 0 1 divide by 1 divide by 2 (default) divide-by-2 or 1 figure 18. register 5pll enable and lo path control register map register 6vco control and vc o enable (default: 0x1e2106) charge pump enable 3.3v ldo enable vco enable vco switch vco bw sw ctrl vbsrc 0 1 vco en vco ldo enable vco amplitude reserved vco band select from spi vbs[5:0] vco band select from spi 0x00 default 0x20 charge pump enable 0x01 ?. 0x00 0 ?. ?. 0x18 24 (default) ?. ?. 0x2b 43 ?. ?. 0x3f 63 (recommended) 0x3f vco bw cal and sw source control band cal (default) vco sw 0 1 vco switch control from spi regular (default) band cal spi vco enable disable enable (default) db22 db21 db20 db19 db18 db17 db1 6 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 control bits db23 cpen l3en vco en vco sw vc5 vc4 vc3 vc2 vc1 vc0 vbsrc vbs5 vbs4 vbs3 vbs2 vbs1 vbs0 c3(1) c2(1) c1(0) lven vc[5:0] vco amplitude 0 1 lven vco ldo enable disable enable (default) 0 1 l3en 3.3v ldo enable disable enable (default) 0 1 cpen disable enable (default) 0 1 000 08553-010 figure 19. register 6vco contro l and vco enable register map register 7mixer bias enable and ex ternal vco enable (default: 0x000007) db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db1 0 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0xvco xvco res mbe0 00000000000000000c3(1)c2(1)c1(1) mixer b_en reserved control bits mbe 0 1 xvco 0 1 internal vco (default) external vco mixer bias enable enable (default) disable external vco 0 8553-011 figure 20. register 7mixer bias enable and external vco enable register map ADRF6604 rev. 0 | page 15 of 24 theory of operation the ADRF6604 integrates a high performance downconverting mixer with a state-of-the-art fractional-n pll. the pll also inte- grates a low noise vco. the spi port allows the user to control the fractional-n pll functions and the mixer optimization functions, as well as allowing for an externally applied lo or vco. the mixer core within the ADRF6604 is the next generation of an industry leading family of mixers from analog devices, inc. the rf input is converted to a current and then mixed down to if using high performance npn transistors. the mixer output currents are transformed to a differential output voltage. the high performance active mixer core results in an excep- tional iip3 and ip1db, with a very low output noise floor for excellent dynamic range. over the specified frequency range, the ADRF6604 typically provides an if input p1db of 14.3 dbm and an iip3 of 31 dbm. improved performance at specific frequencies can be achieved with the use of the internal capacitor dac (cdac), which is programmable via the spi port, and through the use of a resistor to a 5 v supply from the ip3set pin (pin 29). adjustment of the cdac allows increments in phase shift at internal nodes in the ADRF6604, thus allowing cancellation of third-order distortion with no change in supply current. connecting a resistor to a 5 v supply from the ip3set pin increases the internal mixer core current, thereby improving overall iip2 and iip3, as well as ip1db. using the ip3set pin for this purpose increases the overall supply current. the fractional divide function of the pll allows the frequency multiplication value from ref_in to the lo output to be a frac- tional value, rather than being restricted to an integer value as in traditional plls. in operation, this multiplication value is int + ( frac / mod ) where: int is the integer value. frac is the fractional value. mod is the modulus value. the int, frac, and mod values are all programmable via the spi port. in other fractional-n pll designs, fractional multiplication is achieved by periodically changing the fractional value in a deterministic way. the disadvantage of this approach is that there are often spurious components close to the fundamental signal. in the ADRF6604, a - modulator is used to distribute the fractional value randomly, thus significantly reducing the spurious content due to the fractional function. programming the ADRF6604 the ADRF6604 is programmed via a 3-pin spi port. the timing requirements for the spi port are shown in figure 2 . eight pro- grammable registers, each with 24 bits, control the operation of the device. the register functions are listed in table 8 . table 8. ADRF6604 register functions register function register 0 integer divide control for the pll register 1 modulus divide control for the pll register 2 fractional divide control for the pll register 3 - modulator dither control register 4 pll charge pump, pfd, reference path control register 5 pll enable and lo path control register 6 vco control and vco enable register 7 mixer bias enable and external vco enable note that internal calibration for the pll must be run when the ADRF6604 is initialized at a given frequency. this calibration is run automatically whenever register 0, register 1, or register 2 is programmed. because the other registers affect pll performance, register 0, register 1, and register 2 should always be programmed in the order specified in the initialization sequence section. to program the frequency of the ADRF6604, the user typically programs only register 0, register 1, and register 2. however, if registers other than these are programmed first, a short delay should be inserted before programming register 0. this delay ensures that the vco band calibration has sufficient time to com- plete before the final band calibration for register 0 is initiated. software is available on the ADRF6604 product page of the analog devices website ( www.analog.com ) that allows easy programming from a pc running windows? xp or vista. initialization sequence to ensure proper power-up of the ADRF6604, it is important to reset the pll circuitry after the vcc supply rail settles to 5 v 0.25 v. resetting the pll ensures that the internal bias cells are properly configured, even under poor supply start-up conditions. to ensure that the pll is reset after power-up, follow these steps: 1. disable the pll by setting the plen bit to 0 (register 5, bit db6). 2. after a delay of >100 ms, set the plen bit to 1. after this procedure is completed, the other registers should be programmed in the following order: register 7, register 6, register 4, register 3, register 2, register 1. then, after a delay of >100 ms, register 0 should be programmed. ADRF6604 rev. 0 | page 16 of 24 lo selection logic the downconverting mixer in the ADRF6604 can be used without the internal pll by applying an external differential lo to pin 37 (lon) and pin 38 (lop). in addition, when using an lo generated by the internal pll, the lo signal can be accessed directly at these same pins. this function can be used for debugging purposes, or the internally generated lo can be used as the lo for a separate mixer. the operation of the lo generation, as well as whether lop and lon are inputs or outputs, is determined by the logic levels applied at pin 16 (pll_en) and pin 36 (lodrv_en), as well as bit db3 (ldrv) and bit db6 (plen) in register 5. the combination of externally applied logic and internal bits required for particular lo functions is given in table 9 . table 9. lo selection logic pins 1 register 5 bits 1 outputs pin 16 (pll_en) pin 36 (lodrv_en) bit db6 (plen) bit db3 (ldrv) output buffer lo 0 x 0 x disabled external 0 x 1 x disabled external 1 x 0 x disabled external 1 0 1 0 disabled internal 1 x 1 1 enabled internal 1 1 1 x enabled internal 1 x = dont care. ADRF6604 rev. 0 | page 17 of 24 applications information basic connections for operation figure 21 shows the basic connections for the ADRF6604. the six power supply pins should be individually decoupled using 100 pf and 0.1 f capacitors located as close as possible to the device. in addition, the internal decoupling nodes (decl3p3, decl2p5, and declvco) should be decoupled with the capacitor values shown in figure 21 . the rf input is internally ac-coupled and needs no external bias. the if outputs are open-collector, and a bias inductor is required from these outputs to vcc. a peak-to-peak differential swing on rf in of 1 v (0.353 v rms for a sine wave input) results in an if output power of 4.7 dbm. the reference frequency for the pll should be from 12 mhz to 160 mhz and should be applied to the ref_in pin, which should be ac-coupled and terminated with a 50 resistor, as shown in figure 21 . the reference signal, or a divided-down version of the reference signal, can be brought back off chip at the multiplexer output pin (muxout). a lock detect signal and a voltage proportional to the ambient temperature can also be selected on the multiplexer output pin. the loop filter is connected between the cp and vtune pins. when connected in this way, the internal vco is operational. for information about the loop filter components, see the evaluation board configuration options section. operation with an external vco is also possible. in this case, the loop filter components should be referred to ground. the output of the loop filter is connected to the input voltage pin of the external vco. the output of the vco is brought back into the device on the lop and lon pins, using a balun if necessary. 0 8553-024 r28 0 ? (0402) rfin mux r set cp vtune lodrv_en lon lop 2:1 mux vco core temp sensor decl2p5 decl3p3 declvco buffer buffer ifn ifp 2 14 5 3 ip3set rf in ? + charge pump 250a, 500a (default), 750a, 1000a prescaler 2 muxout ref_in ADRF6604 19 5 8 36 11 74 2015 23 21 25 24 30 28 3531 26 phase frequency detector third-order fractional interpolator fraction reg modulus integer reg n counter 21 to 123 2 2 4 divider 2 spi interface c43 10f (0603) c14 22pf (0603) cp test point (orange) c13 6.8pf (0603) c40 22pf (0603) c7 0.1f (0402) vcc red +5v vcc vtune c15 2.7nf (1206) c2 open (0402) c1 100pf (0402) r1 0 ? (0402) r38 0 ? (0402) r37 0 ? (0402) r2 open (0402) c42 10f (0603) c17 0.1f (0402) r63 open (0402) r65 10k ? (0402) r9 10k ? (0402) r12 0 ? (0402) r10 3.0k ? (0603) r62 0 ? (0402) r11 open (0402) rfout c16 100pf (0402) r18 0 ? (0402) c41 open (0603) c11 0.1f (0402) c27 0.1f (0402) c29 0.1f (0402) c12 100pf (0402) r8 0 ? (0402) r16 0 ? (0402) c31 1nf (0402) c6 1nf (0402) r55 open (0402) vcc1 red s1 o pen r56 0 ? (0402) c5 1n f ( 0402) r70 49.9 ? (0402) 4 lo in/out refin refout 3 51 t8 tc1-1-13+ r20 0 ? (0402) r54 10k ? (0402) r19 0 ? (0402) s2 r53 10k ? (0402) r35 0 ? (0402) r30 0 ? (0402) r50 open (0402) r57 0 ? (0402) r36 0 ? (0402) p1 9-pin dsub vcc_lo vcc2 vcc1 pll_en clk data le 27 13 12 c8 100pf (0402) r6 0 ? (0402) c25 0.1f (0402) c24 100pf (0402) r26 0 ? (0402) c23 0.1f (0402) c22 100pf (0402) r25 0 ? (0402) c20 0.1f (0402) c21 100pf (0402) r24 0 ? (0402) c19 0.1f (0402) c18 100pf (0402) r17 0 ? (0402) c9 0.1f (0402) c10 100pf (0402) r7 0 ? (0402) 2 4 6 1357 c32 open (0402) r51 open (0402) c33 open (0402) r52 open (0402) c34 open (0402) 14 div by 4, 2, 1 vcc_mix vcc_v2i vcc_lo r27 0 ? (0402) r43 0 ? (0402) vcc +5v r59 0 ? (0402) 16 2 9 29 18 40 39 3 6 38 37 34 22 17 10 1 89 figure 21. basic connections for operation of the ADRF6604 ADRF6604 rev. 0 | page 18 of 24 evaluation board figure 24 shows the schematic of the rohs-compliant evalu- ation board for the ADRF6604. this board has four layers and was designed using rogers 4350 hybrid material to minimize high frequency losses. fr4 material is also adequate if the design can accept the slightly higher trace loss of this material. the evaluation board is designed to operate using the internal vco of the device (the default configuration) or using an external vco. to use an external vco, r62 and r12 should be removed. place 0 resistors in r63 and r11. the input of the external vco should be connected to the vtune sma connector, and the external vco output should be connected to the lo in/out sma connector. in addition to these hard- ware changes, internal register settings must also be changed to enable operation with an external vco (see the register 6 vco control and vco enable (default: 0x1e2106) section). additional configuration options for the evaluation board are described in table 10 . evaluation board control software software to program the ADRF6604 is available for download from the ADRF6604 product page at www.analog.com . to install the software, download and extract the zip file. then run the adrf6x0x_3p0p0_xp_install.exe installation file. the evaluation board can be connected to the pc using a pc parallel port or a usb port. these options are selectable from the opening menu of the software interface (see figure 22 ). the evaluation board is shipped with a 25-pin parallel port cable for connection to the pc parallel port. to connect the evaluation board to a usb port, a usb adapter board (part no. eval-adf4xxxz-usb ) must be purchased from www.analog.com . this board connects to the pc using a standard usb cable with a usb mini-connector at one end. an additional 25-pin male to 9-pin female adapter is required to mate the eval-adf4xxxz-usb board to the 9-pin d-sub connector on the ADRF6604 evaluation board. 0 8553-025 figure 22. control software opening menu figure 23 shows the main window of the control software with the default settings displayed. ADRF6604 rev. 0 | page 19 of 24 08553-026 figure 23. main window of the ADRF6604 evaluation board software ADRF6604 rev. 0 | page 20 of 24 schematics and artwo rk 08553-023 a g n d a g n d a g n d a g n d a g n d nc a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d e-pad a g n d a g n d a g n d a g n d a g n d a g n d a g n d 1 vcc 1 v cc 2 1 v cc 5 1 v cc _lo1 1 v cc _ bb 1 1 v cc _rf 1 v cc 1 1 v cc _lo 1 v cc 4 1 vco_ldo 1 cp 1 data 1 ip3 se t 1 le 1 cl k 1 2p5v 1 osc_3p3v 1 3p3v1 r10 3k r63 100 k r37 0 dni r11 r12 0 0 r62 10 k r65 r9 10 k 22 pf c40 c14 22 pf c13 6.8pf c15 2.7nf l2 tbd l1 tbd c36 dni c35 dni 0 r66 r67 0 r68 0 dni c41 10 uf 0.1uf c9 10 uf c42 10 uf c43 p1-6 p1-1 1 2 3 4 5 6 7 8 9 p1 amp 745781 -4 tbd r27 ip3 se t c34 100 pf dni 100 pf dni c33 c32 100 pf dni 1k dni r52 r51 1k dni 1k dni r50 c28 10 uf r47 0 0 r48 vcc vcc 1 2 3 4 5 6 7 8 9 10 11 12 15 16 18 20 22 23 24 25 26 27 28 29 30 31 32 3334353637383940 21 13 14 17 19 pad z1 v cc _bb r60 tbd r44 dni vcc 4 6 1 3 2 t3 tc4-1w r59 0 0 r43 0.1uf c29 c25 0.1uf dni r58 1 di g_gnd r36 0 0 r57 1 2 3 s2 r53 10 k 10 k r54 r56 10 k vcc c31 1000 pf r49 dni 1nf c6 c5 1nf lo_extern 0 r33 10 k r55 vcc 3 2 1 s1 ou tp ut_en 0 r30 r19 0 100 pf c10 r18 0 dni r2 c12 100 pf 0 r25 r26 0 0 r38 r8 0 0 r35 1 gnd 0 r29 vc c 1 j1 y1 r1 0 v cc _ se nse sns1 sns vco_ldo lo_extern 2p5v_ldo 3p3v_ldo ag nd v cc _ se nse ag nd vcc 10j1 8j1 r20 0 v cc _bb v cc _lo v cc _rf v cc _bb v cc _lo v cc _lo 0 r28 r14 dni r15 0 c3 10 pf c4 22000 pf 0.1uf c7 0 r6 c2 0.1uf c1 100 pf 100 pf c8 0 r7 c11 0.1uf refin refo ut r16 0 0.1uf c19 100 pf c18 c17 0.1uf c16 100 pf 0 r17 out c21 100 pf r24 0 c20 0.1uf 0.1uf c23 100 pf c22 c24 100 pf 0.1uf c27 rfin vcc 0 r31 r32 0 0 r34 2j1 3j1 4j1 5j1 6j1 7 j1 9j1 1 gnd1 1 gnd2 v cc _rf ifn ifp osc_3p3v vcc p4-t7 p4-t7 p3-t7 p3-t7 p1-t7 p1-t7 p1-t7 lo 0 r69 1 1a 2 2a 3 3a 4 4a 5 5a 6 6a t7 1 5 3 4 2 t8 p3-t7 p4-t7 ou tp ut_en ip3 se t r70 49 .9 3p3v_ldo vco_ldo 2p5v_ldo vtune p1-6 r72 0 p1-1 r71 tbd vcc1 decl3p3 cp gnd r set ref_ in gnd muxout decl2p5 vcc2 gnd gnd gnd rf in vcc_v2i gnd ip3set gnd vcc_mix gnd nc vcc_lo gnd lodrv_en lon lop vtune declvco nc gnd gnd data clk gnd vcc_lo pll_en ifp ifn gnd le figure 24 . evaluation board schematic ADRF6604 rev. 0 | page 21 of 2 4 08553-013 08553-012 figure 25. evaluation board layout (bottom) figure 26. evaluation board layout (top) ADRF6604 rev. 0 | page 22 of 2 4 evaluation board configuration options table 10. component description default condition/ option settings s1, r55, r56, r33 lo select. switch and resistors to ground the lodrv_en pin. the lodrv_en pin setting, in combination with the internal register settings, determines whether the lop and lon pins function as inputs or outputs (see the lo selection logic section for more information). s1 = r55 = open (not installed) r56 = r33 = 0 lodrv_en = 0 v lo in/out sma connector lo input/output. an external 1 lo or 2 lo frequency can be applied to this single-ended input connector. lo input refin sma connector reference input. the input reference frequenc y for the pll is applied to this connector. input impedance is 50 . refout sma connector multiplexer output. the refout connector connects directly to the muxout pin. the on-board multiplexer can be programmed to bring out the following signals: ref_in, 2 ref_in, 0.5 ref_in, 0.25 ref_in. temperature sensor output voltage. lock detect indicator. lock detect cp test point charge pump test point. the unfiltered charge pump signal can be probed at this test point. note that the cp pin should not be probed during critical measurements, such as phase noise. r37, c14, r9, r10, c15, c13, r65, c40 loop filter. loop filter components. r11, r12 loop filter return. when the internal vco is used, the loop filter components should be returned to pin 40 (declvco) by installing a 0 resistor in r12. when an external vco is used, the loop filter components can be returned to ground by installing a 0 resistor in r11. r12 = 0 (0402) r11 = open (0402) r62, r63, vtune sma connector internal vs. external vco. when the internal vco is enabled, the loop filter components are connected directly to the vtune pin (pin 39) by installing a 0 resistor in r62. to use an external vco, r62 should be left open. a 0 resistor should be installed in r63, and the voltage input of the vco should be connected to the vtune sma connector. the output of the vco is brought back into the pll via the lo in/out sma connector. r62 = 0 (0402) r63 = open (0402) r2 connects to r set pin. this pin is unused and should be left open. r2 = open (0402) rfin sma connector rf input. the rf input signal should be appl ied to the rfin sma connector. the rf input of the ADRF6604 is ac-coupled; theref ore, no bias is necessary. t3 if output. the differential if output signals from the ADRF6604 (ifp and ifn) are converted to a single-ended signal by t3. ADRF6604 rev. 0 | page 23 of 2 4 outline dimensions 1 40 10 11 31 30 21 20 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicator 5.75 bsc sq 12 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0.80 max 0.65 typ 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bot tom view) compliant to jedec standards mo-220-vjjd-2 072108-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 27. 40-lead lead frame chip scale package [lfcsp_vq] 6 mm 6 mm body, very thin quad (cp-40-1) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADRF6604acpz-r7 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 ADRF6604-evalz evaluation board 1 z = rohs compliant part. ADRF6604 rev. 0 | page 24 of 24 notes ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08553-0-6/10(0) |
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