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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8019 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 dsl line driver with power-down pin configurations 8 7 6 5 1 2 3 4 ad8019ar ?n1 out1 out2 +in1 ? s +v s ?n2 +in2 14 13 12 11 10 9 8 1 2 3 4 5 6 7 ad8019aru nc = no connect dgnd nc pwdn nc nc nc out1 ?n1 +in1 ? s out2 +v s ?n2 +in2 features low distortion, high output current amplifiers operate from 12 v to 12 v power supplies, ideal for high-performance adsl cpe, and xdsl modems low power operation 9 ma/amp (typ) supply current digital (1-bit) power-down voltage feedback amplifiers low distortion out-of-band sfdr C80 dbc @ 100 khz into 100 line high speed 175 mhz bandwidth (C3 db), g = +1 400 v/ s slew rate high dynamic range v out to within 1.2 v of power supply applications adsl, vdsl, hdsl, and proprietary xdsl usb, pci, pcmcia modems, and customer premise equipment (cpe) product description the ad8019 is a low cost xdsl line driver optimized to drive a minimum of 13 dbm into a 100 ? load while delivering outstand- ing distortion performance. the ad8019 is designed on a 24 v high-speed bipolar process enabling the use of 12 v power supplies or 12 v only. when operating from a single 12 v sup- ply the highly efficient amplifier architecture can typically deliver 170 ma output current into low impedance loads through a 1:2 turns ratio transformer. hybrid designs using 12 v supplies enable the use of a 1:1 turns ratio transformer, minimizing attenu- ation of the receive signal. the ad8019 typically draws 9 ma/ amplifier quiescent current. a 1-bit digital power down feature reduces the quiescent current to approximately 1.6 ma/amplifier. figure 1 shows typical out of band sfdr performance under adsl cpe (upstream) conditions. sfdr is measured while driving a 13 dbm adsl dmt signal into a 100 ? line with 50 ? back termination. the ad8019 comes in thermally enhanced 8-lead soic and 14-lead tssop packages. the 8-lead soic is pin-compatible with the ad8017 12 v line driver. frequency khz 132.5 10db/div 137.5 142.5 80dbc figure 1. out-of-band sfdr; v s = 12 v; 13 dbm output power into 200 ? , upstream 8-lead soic (r-8) 14-lead tssop (ru-14)
rev. 0 C2C ad8019?pecifications parameter conditions min typ max unit dynamic performance C3 db bandwidth g = +5 35 mhz g = +1, v out < 0.4 v p-p, r l = 100 ? 175 180 mhz g = +2, v out < 0.4 v p-p, r l = 100 ? 70 75 mhz 0.1 db bandwidth v out < 0.4 v p-p, r l = 100 ? 6 mhz g = +5, v out < 0.4 v p-p, r l = 100 ? 35 mhz large signal bandwidth v out = 4 v p-p 50 mhz slew rate noninverting, v out = 4 v p-p 450 v/ s rise and fall time noninverting, v out = 2 v p-p 5.5 ns settling time 0.1%, v out = 2 v p-p 40 ns noise/distortion performance distortion v out = 3 v p-p (differential) second harmonic 100 khz, r l(dm) = 50 ? C78 dbc 500 khz, r l(dm) = 50 ? C74 dbc third harmonic 100 khz, r l(dm) = 50 ? C85 dbc 500 khz, r l(dm) = 50 ? C80 dbc out-of-band sfdr 144 khzC1.1 mhz, differential r l = 70 ? C80 dbc mtpr 25 khzC138 khz, differential r l = 70 ? C72 dbc input voltage noise f = 100 khz 8 nv/ hz input current noise f = 100 khz 0.9 pa hz crosstalk f = 1 mhz, g = +2 C80 db dc performance input offset voltage 820mv t min Ct max 10 23 mv input offset voltage match 112mv t min Ct max 217mv open-loop gain v out = 6 v p-p, r l = 25 ? 72 80 db t min Ct max 72 80 db input characteristics input resistance 10 m ? input capacitance 0.5 pf +input bias current C3 +1 +3 a t min Ct max C4 +4 a Cinput bias current C1.5 C0.5 +1.5 a t min Ct max C1.8 +1.8 a +input bias current match C1.0 C0.2 +1.0 a t min Ct max C1.5 +1.5 a Cinput bias current match C0.5 +0.1 +0.5 a t min Ct max C0.8 +0.8 a cmrr ? v cm = C4 v to +4 v 71 74 db input cm voltage range 2 10 v output characteristics output resistance 0.2 ? output voltage swing r l = 25 ? C4.8 +4.8 v output current sfdr C80 dbc into 25 ? at 100 khz 175 200 ma short circuit current 1 400 ma power supply supply current/amp pwdn = 5 v 9 10.5 ma t min Ct max 14.5 ma pwdn = 0 v 0.8 2.0 ma operating range dual supply 4.0 6.0 v power supply rejection ratio ? v s = +1.0 v to C1.0 v 65 68 db logic levels v pwdn = 0 v to 3 v; v in = 10 mhz, g = +5 t on 120 ns t off 80 ns pwdn = 1 voltage 1.8 +v s v pwdn = 0 voltage 0.5 v pwdn = 1 bias current 220 a pwdn = 0 bias current C100 a notes 1 this device is protected from overheating during a short-circuit by a thermal shutdown circuit. specifications subject to change without notice. (@ 25 c, v s = 12 v, r l = 25 , r f = 500 , t min = ?0 c, t max = +85 c, unless otherwise noted.)
rev. 0 C3C ad8019 parameter conditions min typ max unit dynamic performance C3 db bandwidth g = +5 35 mhz g = +1, v out < 0.4 v p-p 175 180 mhz g = +2, v out < 0.4 v p-p 70 75 mhz 0.1 db bandwidth v out < 0.4 v p-p 5.5 mhz large signal bandwidth v out = 4 v p-p 50 mhz slew rate noninverting, v out = 4 v p-p 400 v/ s rise and fall time noninverting, v out = 2 v p-p 5.5 ns settling time 0.1%, v out = 2 v p-p 40 ns noise/distortion performance distortion v out = 16 v p-p (differential) second harmonic 100 khz, r l(dm) = 200 ? C80 dbc 500 khz, r l(dm) = 200 ? C72 dbc third harmonic 100 khz, r l(dm) = 200 ? C85 dbc 500 khz, r l(dm) = 200 ? C80 dbc out-of-band sfdr 144 khzC500 khz, differential r l = 200 ? C80 dbc mtpr 25 khzC138 khz, differential r l = 200 ? C73 dbc input voltage noise f = 100 khz 8 nv/ hz input current noise f = 100 khz 0.9 pa hz crosstalk f = 1 mhz, g = +2 C85 db dc performance input offset voltage 520mv t min Ct max 10 mv input offset voltage match 112mv t min Ct max 218mv open-loop gain v out = 18 v p-p, r l = 100 ? 86 92 db t min Ct max 90 db input characteristics input resistance 10 m ? input capacitance 0.5 pf +input bias current C3 C0.5 +3 a t min Ct max C3.8 +3.8 a Cinput bias current C1.5 C0.2 +1.5 a t min Ct max C1.7 +1.7 a +input bias current match C1.0 +0.2 +1.0 a t min Ct max C2.4 +2.4 a Cinput bias current match C1.0 +0.1 +1.0 a t min Ct max C2.5 +2.5 a cmrr ? v cm = C10 v to +10 v 71 76 db input cm voltage range C10 +10 v output characteristics output resistance 0.2 ? output voltage swing r l = 100 ? C10.8 +10.8 v output current sfdr C80 dbc into 100 ? at 100 khz 125 170 ma short circuit current 1 800 ma power supply supply current/amp pwdn = high 9 10 ma t min Ct max 11.5 ma pwdn = low 0.8 1.75 ma operating range dual supply 4.0 12 v power supply rejection ratio ? v s = +1.0 v to C1.0 v 61 64 db logic levels v pwdn = 0 v to 3 v; v in = 10 mhz, g = +5 t on 120 ns t off 80 ns pwdn = 1 voltage 1.8 +v s v pwdn = 0 voltage 0.5 v pwdn = 1 bias current 220 a pwdn = 0 bias current C100 a notes 1 this device is protected from overheating during a short-circuit by a thermal shutdown circuit. specifications subject to change without notice. (@ 25 c, v s = 12 v, r l = 100 , r f = 500 , t min = ?0 c, t max = +85 c, unless otherwise noted.)
rev. 0 ad8019 C4C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8019 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 v internal power dissipation tssop-14 package 2 . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 w soic-8 package 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 w input voltage (common-mode) . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . v s output short circuit duration . . . . . . . . . . . . . . . . . . . . observe power derating curves storage temperature range . . . . . . . . . . . . C65 c to +125 c operating temperature range . . . . . . . . . . . C40 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device on a four-layer board with 10 inches 2 of 1 oz. copper at 85 c 14-lead tssop package: ja = 90 c/w. 3 specification is for device on a four-layer board with 10 inches 2 of 1 oz. copper at 85 c 8-lead soic package: ja = 100 c/w. maximum power dissipation the maximum power that can be safely dissipated by the ad 8019 is limited by the associated rise in junction temperature. the maximum safe junction temperature for a plastic encapsulated device is determined by the glass transition temperature of the plastic, approximately 150 c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. the output stage of the ad8019 is designed for maximum load current capability. as a result, shorting the output to common can cause the ad8019 to source or sink 500 ma. to ensure proper operation, it is necessary to observe the maximum power derating curves. direct connection of the output to either power supply rail can destroy the device. ambient temperature c maximum power dissipation w 2.5 2.0 1.5 1.0 0.5 0 40 30 20 10 0102030 40 50 60 70 80 soic tssop figure 2. plot of maximum power dissipation vs. temperature for ad8019 for t j = 150 c ordering guide temperature package package model range description option ad8019aru C40 c to +85 c 14-lead tssop ru-14 ad8019aru-reel C40 c to +85 c 14-lead tssop ru-14 reel AD8019ARU-EVAL C40 c to +85 c evaluation board aru-eval ad8019ar C40 c to +85 c 8-lead soic r-8 ad8019ar-reel C40 c to +85 c 8-lead soic r-8 reel ad8019ar-eval C40 c to +85 c evaluation board ar eval
rev. 0 C5C typical performance characteristics ad8019 0.1 f 0.1 f 10 f 10 f 49.9 124 499 r l v out +v s v s + + v in tpc 1. single-ended test circuit; g = +5 time ns v out mv 100 60 80 100 100 0 100 200 300 400 500 600 700 40 20 0 20 40 60 80 tpc 2. 100 mv step response; g = +5, v s = 6 v, r l = 25 ? , single-ended time ns v out volts 3 4 100 0 100 200 300 400 500 600 700 2 1 0 1 2 3 4 tpc 3. 4 v step response; g = +5, v s = 6 v, r l = 25 ? , single-ended 500 50 +v in r l 500 50 v in +v o v o 0.1 f 55 55 0.1 f 0.1 f v s +v s + 47 f tpc 4. differential test circuit; g = +10 time 100ns/div volts mv 80 100 100 0 100 200 300 400 500 600 700 60 40 20 0 20 40 60 80 100 tpc 5. 100 mv step respon se; g = +5, v s = 12 v, r l = 100 ? , single-ended time ns v out volts 3 4 100 0 100 200 300 400 500 600 700 2 1 0 1 2 3 4 tpc 6. 4 v step response; g = +5, v s = 12 v, r l = 100 ? , single-ended
rev. 0 ad8019 C6C 5 frequency mhz 100 0.01 distortion dbc 1 0.1 90 80 70 60 50 40 30 20 3rd 2nd tpc 7. distortion vs. frequency; v s = 12 v, r l = 200 ? , differential, v o = 16 v p-p 100 distortion dbc 90 80 70 60 50 40 30 peak output current ma 50 75 100 125 150 175 200 2nd harmonic 3rd harmonic tpc 8. distortion vs. peak output current; v s = 6 v; r l = 10 ? ; f = 100 khz; single-ended; second harmonic 100 distortion dbc 90 80 70 60 50 40 30 peak output current ma 50 75 100 125 150 175 200 225 250 20 2nd harmonic 3rd harmonic tpc 9. distortion vs. peak output current; v s = 12 v; r l = 25 ? ; f = 100 khz; single-ended; second harmonic 5 frequency mhz 100 0.01 distortion dbc 1 0.1 90 80 70 60 50 40 30 20 3rd 2nd tpc 10. distortion vs. frequency; v s = 6 v, r l = 50 ? , differential, v o = 3 v p-p 100 distortion dbc 90 80 70 60 50 40 30 differential output voltage v p-p 0 246 810 20 12 14 16 18 20 2nd 3rd tpc 11. distortion vs. output voltage; f = 100 khz, v s = 6 v, g = +10, r l = 50 ? , differential 100 distortion dbc 90 80 70 60 50 40 30 differential output voltage v p-p 0246 810 20 12 14 16 18 20 110 10 2nd 3rd tpc 12. distortion vs. output voltage; f = 500 khz, v s = 6 v, g = +10, r l = 50 ? , differential
rev. 0 ad8019 C7C 100 distortion dbc 90 80 70 60 50 40 30 differential output voltage v p-p 0 5 10152025 20 30 35 40 45 50 2nd 3rd tpc 13. distortion vs. output voltage; f = 100 khz, v s = 12 v, g = +10, r l = 200 ? , differential 100 distortion dbc 90 80 70 60 50 40 30 differential output voltage v p-p 0 5 10 15 20 25 20 30 35 40 45 50 110 10 2nd 3rd tpc 14. distortion vs. output voltage; f = 500 khz, v s = 12 v, g = +10, r l = 200 ? , differential 10 0.5 100 1 0.1 0.6 0.8 0.9 1.0 1.1 1.2 load current ma output saturation voltage volts 0.7 1000 40 c +25 c +85 c v ol v oh v oh v oh v ol v ol tpc 15. output saturation voltage vs. load; v s = 12 v, v s = 6 v 1000 frequency mhz 19 1 output voltage dbv 100 10 16 13 10 7 4 1 2 5 8 11 2,7#: $ "
=( ' ) 12 v, r l = 100 ? ; g = +5 1000 frequency mhz 90 1 cmrr db 100 10 80 70 60 50 40 30 0 0.1 0.01 20 10 v in 909 909 909 909 50 50 50 v out tpc 17. cmrr vs. frequency; v s = 12 v, r l = 100 ? 1000 frequency mhz 19 1 output voltage dbv 100 10 16 13 10 7 4 1 2 5 8 11 tpc 18. output voltage vs. frequency; v s = 6 v, r l = 100 ? ; g = +5
rev. 0 ad8019 C8C 1000 frequency mhz 90 1 psrr db 100 10 80 70 60 50 40 30 0.1 0.01 20 10 psrr +psrr tpc 19. psrr vs. frequency; r l = 100 ? 1000 frequency khz 1 100 10 0.1 0.01 i noise v noise +i noise v noise nv hz 1 10 100 0.1 100 10 1 0.1 i noise pa hz tpc 20. noise vs. frequency 20ns/div 2mv/div 0.1% v in v out 1.1k 1.1k v in v out 50 50 50 6.8pf tpc 21. settling time 0.1%; v s = 12 v, r l = 100 ? , v out = 2 v p-p 1000 frequency mhz 90 1 crosstalk db 100 10 80 70 60 50 40 30 0.1 0.01 20 100 tpc 22. crosstalk vs. frequency, v s = 12 v, v s = 6 v; g = +2; v in = 10 dbm frequency mhz 20 0.001 gain db 0 0.01 1000 0.1 1 10 100 10 10 20 30 40 50 60 70 80 90 100 110 120 2k 50 10 500 10 50 50 50 50 a ol phase 45 phase degrees 0 45 90 135 180 225 270 tpc 23. open-loop gain and phase vs. frequency v in 20ns/div 2mv/div 0.1% 1.1k 1.1k v in v out 50 50 50 6.8pf v out tpc 24. settling time 0.1%; v s = 6 v, r l = 100 ? , v out = 2 v p-p
rev. 0 ad8019 C9C frequency mhz 1 output impedance 100 10 0.1 0.01 1 10 100 1000 0.1 0.01 0.001 tpc 25. output impedance vs. frequency; v s = 12 v; v s = 6 v 100 0v 0v 0 100 200 300 400 500 600 700 800 900 v in v out v in = 2v/div v out = 5v/div time ns tpc 26. overload recovery; v s = 12 v, g = +5, r l =100 ? 100 0v 0v 0 100 200 300 400 500 600 700 800 900 v in v out v in = 2v/div v out = 5v/div time ns tpc 27. overload recovery; v s = 12 v, g = +5, r l = 100 ? 200 0v 0 400 800 1200 1600 v in v out v in = 1v/div v out = 2v/div time ns 0v tpc 28. overload recovery; v s = 6 v, g = +5, r l = 100 ? 200 0v 0 400 800 1200 1600 v in = 1v/div v out = 2v/div time ns 0v v in v out tpc 29. overload recovery; v s = 6 v, g = +5, r l = 100 ?
rev. 0 ad8019 C10C 11dbm 1.2 turns ratio n 1.0 mtpr dbc 1.1 80 70 60 50 40 30 20 10dbm 10 0 1.3 1.4 1.5 1.6 1.7 12dbm 13dbm tpc 30. mtpr vs. turns ratio; v s = 6 v, r l = 100 ? line 18dbm 17dbm 1.2 turns ratio n 1.0 mtpr dbc 1.1 80 70 60 50 40 30 1.3 1.4 1.5 1.6 1.7 13dbm 16dbm tpc 31. mtpr vs. turns ratio; v s = 12 v, r l = 100 ? line 1.2 turns ratio n 1.0 sfdr dbc 1.1 90 80 70 60 50 40 30 1.3 1.4 1.5 1.6 1.7 11dbm 12dbm 13dbm 10dbm tpc 32. sfdr vs. turns ratio; v s = 6 v, r l = 100 ? line 1.2 turns ratio n 1.0 sfdr dbc 1.1 90 85 80 75 70 65 1.3 1.4 1.5 1.6 1.7 60 55 50 17dbm 16dbm 13dbm 18dbm tpc 33. sfdr vs. turns ratio; v s = 12 v, r l = 100 ? line
rev. 0 ad8019 C11C r l v s +v o +v s v o +v s v s figure 3. simplified differential driver remembering that each output device only dissipates for half the time gives a simple integral that computes the power for each device: 1 2 2 ? ? ? ? ? ? ? ( C ) () vv v r so o l the total supply power can then be computed as: pvvv ivp tot s o o q s out =??+ + 4 1 2 2 2 (|| ) in this differential driver, v o is the voltage at the output of one amplifier, so 2 v o is the voltage across r l . r l is the total impedance seen by the differential driver, including back termination . now, with two observations the integrals are easily evaluated. first, the integral of v o 2 is simply the square of the rms value of v o . second, the integral of | v o | is equal to the average rectified value of v o , sometimes called the mean average deviation, or mad. it can be shown that for a dmt signal, the mad value is equal to 0.8 times the rms value. pvrmsvvrms r iv p tot o s o l q s out =++ 408 1 2 2 (. C ) for the ad8019 operating on a single 12 v supply and delivering a total of 16 dbm (13 dbm to the line and 3 dbm to the matching network) into 17.3 ? (100 ? reflected back through a 1:1.7 transformer plus back termination), the dissipated power is: = 332 mw + 40 mw = 372 mw using these calculations and a ja of 90 c/w for the tssop package and 100 c/w for the soic, tables i C iv show junc- tion temperature versus power delivered to the line for several supply voltages while operating with an ambient temperature of 85 c. the shaded areas indicate operation at a junction temperature over the absolute maximum rating of 150 c, and should be avoided. table i. junction temperature vs. line power and operating voltage for tssop v supply p line , dbm 12 12.5 13 13 132 134 137 14 134 137 139 15 136 139 141 16 139 141 144 17 141 144 147 18 143 147 150 general information the ad8019 is a voltage feedback amplifier with high output current capability. as a voltage feedback amplifier, the ad8019 features lower current noise and more applications flexibility than current feedback designs. it is fabricated on analog devices proprietary high voltage extra fast complementary bipolar process (xfcb-hv), which enables the construction of pnp and npn transistors with similar f t s in the 4 ghz region. the process is dielectrically isolated to eliminate the parasitic and latch-up problems caused by junction isolation. these features enable the construction of high-frequency, low-distortion amplifiers. power-down feature a digitally programmable logic pin (pwdn) is available on the tssop-14 package. it allows the user to select between two operating conditions, full on and shutdown. the dgnd pin is the logic reference. the threshold for the pwdn pin is typically 1.8 v above dgnd. if the power-down feature is not being used, it is better to tie the dgnd pin to the lowest potential that the ad8019 is tied to and place the pwdn pin at a poten- tial at least 3 v higher than that of the dgnd pin, but lower than the positive supply voltage. power supply and decoupling the ad8019 can be powered with a good quality (i.e., low-noise) supply anywhere in the range from +12 v to 12 v. in order to optimize the adsl upstream drive capability of 13 dbm and maintain the best spurious free dynamic range (sfdr), the ad8019 circuit should be powered with a well-regulated supply. careful attention must be paid to decoupling the power supply. high quality capacitors with low equivalent series resistance (esr) such as multilayer ceramic capacitors (mlccs) should be used to minimize supply voltage ripple and power dissipa- tion. in addition, 0.1 f mlcc decoupling capacitors should be located no more than 1/8 inch away from each of the power supply pins. a large, usually tantalum, 10 f to 47 f capacitor is required to provide good decoupling for lower frequency signals and to supply current for fast, large signal changes at the ad8019 outputs. power dissipation it is important to consider the total power dissipation of the ad8019 in order to properly size the heat sink area of an appli- cation. figure 3 is a simple representation of a differential driver. with some simplifying assumptions we can estimate the total power dissipated in this circuit. if the output current is large compared to the quiescent current, computing the dissipation in the output devices and adding it to the quiescent power dissipa- tion will give a close approximation of the total power dissipation in the package. a factor (~0.6-1) corrects for the slight error due to the class a/b operation of the output stage. it can be estimated by subtracting the quiescent current in the output stage from the total quiescent current and ratioing that to the total quiescent current. for the ad8019, = 0.833.
rev. 0 ad8019 C12C table ii. junction temperature vs. line power and operating voltage for soic v supply p line , dbm 12 12.5 13 13 137 140 143 14 140 142 145 15 142 145 148 16 145 148 151 17 147 150 154 18 150 153 157 table iii. junction temperature vs. line power and operating voltage for tssop v supply p line , dbm +12 +13 13 115 118 14 116 119 15 118 121 16 120 123 table iv. junction temperature vs. line power and operating voltage for soic v supply p line , dbm +12 +13 13 118 121 14 120 123 15 122 125 16 124 128 thermal stitching, which connects the outer layers to the inter- nal ground plane(s), can help to utilize the thermal mass of the pcb to draw heat away from the line driver and other active components. layout considerations as is the case with all high-speed applications, careful attention to printed circuit board layout details will prevent associated board parasitics from becoming problematic. proper rf design technique is mandatory. the pcb should have a ground plane covering all unused portions of the component side of the board to provide a low-impedance return path. removing the ground plane on all layers from the areas near the input and output pins will reduce stray capacitance, particularly in the area of the inverting inputs. the signal routing should be short and direct in order to minimize parasitic inductance and capacitance asso- ciated with these traces. termination resistors and loads should be located as close as possible to their respective inputs and outputs. input and output traces should be kept as far apart as possible to minimize coupling (crosstalk) though the board. wherever there are complementary signals, a symmetrical layout should be provided to the extent possible to maximize balanced performance. when running differential signals over a long distance, the traces on the pcb should be close together or any differential wiring should be twisted together to minimize the area of the loop that is formed. this will reduce the radiated energy and make the circuit less susceptible to rf interference. adherence to stripline design techniques for long signal traces (greater than about 1 inch) is recommended. evaluation board the ad8019 is available installed on an evaluation board for both package styles. figures 8 and 9 show the schematics for the tssop evaluation board. the receiver circuit on these boards is typically unpopulated. requesting samples of the ad8022ar, along with either of the ad8019 evaluation boards, will provide the capability to evaluate the ad8019 along with other analog devices products in a typical transceiver circuit. the evaluation circuits have been designed to replicate the cpe side analog transceiver hybrid circuits. the circuit mentioned above is designed using a 1-transformer transceiver topology including a line receiver, line driver, line matching network, an rj11 jack for interfacing to line simula- tors, and differential inputs. ac-coupling capacitors of 0.1 f, c8, and c10, in combination with 10 k ? , resistors r24 and r25, will form a 1st order high- pass pole at 160 hz. transformer selection customer premise adsl requires the transmission of a 13 dbm (20 mw) dmt signal. the dmt signal has a crest factor of 5.3, requiring the line driver to provide peak line power of 560 mw. 560 mw peak line power translates into a 7.5 v peak voltage on a 100 ? telephone line. assuming that the maximum low distor- tion o utput swing available from the ad8019 line driver on a 12 v supply is 20 v and taking into account the power lost due to the termination resistance, a step-up transformer with turns ratio of 1:1 is adequate for most applications. if the modem designer desires to transmit more than 13 dbm down the twisted pair, a higher turns ratio can be used for the transformer. this trade-off comes at the expense of higher power dissipation by the line driver as well as increased attenuation of the downstream signal that is received by the transceiver. in the simplified differential drive circuit shown in figure 7, the ad8019 is coupled to the phone line through a step-up transformer with a 1:1 turns ratio. r1 and r2 are back termi- nation or line matching resistors, each 50 ? (100 ? /(2 1 2 )) where 100 ? is the approximate phone line impedance. a transformer reflects impedance from the line side to the ic side as a value inversely proportional to the square of the turns ratio. the total differential load for the ad8019, including the termination resistors, is 200 ? . even under these conditions the ad8019 provides low distortion signals to within 2 v of the power supply rails. one must take care to minimize any capacitance present at the outputs of a line driver. the sources of such capacitance can include, but are not limited to emi suppression capacitors, overvoltage protection devices and the transformers used in the hybrid. transformers have two kinds of parasitic capacitances, distributed, or bulk capacitance, and interwinding capacitance. distributed capacitance is a result of the capacitance created between each adjacent winding on a transformer. interwinding capacitance is the capacitance that exists between the windings on the primary and secondary sides of the transformer. the existence of these capacitances is unavoidable, but in specifying
rev. 0 ad8019 C13C a transformer, one should do so in a way to minimize them in order to avoid operating the line driver in a potentially unstable environment. limiting both distributed and interwinding capaci- tance to less than 20 pf each should be sufficient for most applications. stability enhancements voltage feedback amplifiers may exhibit sensitivity to capaci- tance present at the inverting input. parasitic capacitance, as small as several picofarads, in combination with the high-impedance of the input can create a pole that can dramatically decrease the phase margin of the amplifier. in the case of the ad8019, a c ompen- sation capacitor of 10 pf C 20 pf in parallel with the feedback resistor will form a zero that can serve to cancel out the effects of the parasitic capacitance. placing 100 ? in series with each of the noninverting inputs serves to isolate the inputs from each other and from any high frequency signals that may be coupled into the amplifier via the midsupply bias. it may also be necessary to configure the line driver as two sepa- rate, noninverting amplifiers rather than a single differential driver. when doing this, the two gain resistors can share an ac coupling capacitor of 0.1 f to minimize any dc errors. adhering to previously mentioned layout techniques will also be of assistance in keeping the amplifier stable. receive channel considerations a transformer used at the output of the differential line driver to step up the differential output voltage to the line has the inverse effect on signals received from the line. a voltage reduction or attenuation equal to the inverse of the turns ratio is realized in the receive channel of a typical bridge hybrid. the turns ratio of the transformer may also be dictated by the ability of the receive circuitry to resolve low-level signals in the noisy twisted pair tele- phone plant. while higher turns ratio transformers boost transmit signals to the appropriate level, they also effectively reduce the received signal to noise ratio due to the reduction in the received signal strength. using a transformer with as low a turns ratio as possible will limit degradation of the received signal. the ad8022, a dual amplifier with typical rti voltage noise of only 2.5 nv/ hz and a low supply current of 4 ma/amplifier is recommended for the receive channel. dmt modulation, multi-tone power ratio (mtpr) and out-of-band sfdr adsl systems rely on discrete multi-tone (or dmt) modula- tion to carry digital data over phone lines. dmt modulation appears in the frequency domain as power contained in several individual frequency subbands, sometimes referred to as tones or bins, each of which are uniformly separated in frequency. a uniquely encoded, quadrature amplitude modulation (qam)- like signal occurs at the center frequency of each subband or tone. see figure 4 for an example of a dmt waveform in the frequency domain, and figure 5 for a time domain waveform. difficulties will exist when decoding these subbands if a qam signal from one subband is corrupted by the qam signal(s) from other subbands, regardless of whether the corruption comes from an adjacent subband or harmonics of other subbands. conventional methods of expressing the output signal integrity of line drivers such as single tone harmonic distortion or thd, two-tone intermodulation distortion (imd) and third order intercept (ip3) become significantly less meaningful when amplifiers are required to process dmt and other heavily modulated waveforms. a typical adsl upstream dmt signal can contain as many as 27 carriers (subbands or tones) of qam signals. multi-tone power ratio (mtpr) is the relative differ- ence between the measured power in a typical subband (at one tone or carrier) versus the power at another subband specifi- cally selected to contain no qam data. in other w ords, a selected subband (or tone) remains open or void of intentional power (without a qam signal) yielding an empty frequency bin. mtpr, sometimes referred to as the empty bin test, is typically expressed in dbc, similar to express ing the relative difference between single tone fundamentals and second or third harmonic distortion components. measurements of mtpr are typically made on the line side or secondary side of the transformer. frequency khz 80 50 power dbm 60 40 20 0 20 0 100 150 figure 4. dmt waveform in the frequency domain mtpr versus transformer turns ratio is depicted in tpcs 30 and 31 and covers a variety of line power ranging from 10 dbm to 18 dbm. as the turns ratio increases, the driver hybrid can deliver more undistorted power to the load due to the high output current capability of the ad8019. significant degrada- tion of mtpr will occur if the output of the driver swings to the rails, causing clipping at the dmt voltage peaks. driving dmt signals to such extremes not only compromises in band mtpr, but will also produce spurs that exist outside of the frequency s pectrum containing the transmitted signal. out- of-band spurious free dynamic range (sfdr) can be defined as the relative difference in amplitude between these spurs and a tone in one of the upstream bins. compromising out-of-band sfdr is the equivalent of increasing near-end cross talk (next). regardless of terminology, maintaining out-of-band sfdr while reducing next will improve the overall performance of the modems connected at either end of the twisted pair.
rev. 0 ad8019 C14C r1 17.3 r l = 100 r2 17.3 1:1.7 transformer p out 16dbm line power 13dbm 301 301 50 50 0.1 f 10k 10k 0.1 f 0.1 f +12v 100 100 0.1 f v in 6v 0.1 f 10 f figure 6. recommended application circuit for single +12 v supply r1 12.4 r l = 100 r2 12.4 1:1 transformer p out 16dbm line power 13dbm 301 301 50 50 0.1 f 10k 10k 0.1 f +12v 100 100 0.1 f v in 0.1 f 12v 0.1 f 10 f 10 f figure 7. recommended application circuit for 12 v supply 0.25 0.15 0.05 0 time ms 0.10 0.15 0.20 volts 3 2 1 0 1 2 3 4 0.05 0.10 0.20 figure 5. dmt signal in the time domain generating dmt signals at this time, dmt-modulated waveforms are not typically menu-selectable items contained within arbitrary waveform generators. even using (awg) software to generate dmt sig- nals, awgs that are available today may not deliver dmt signals sufficient in performance with regard to mtpr due to limitations in the d/a converters and output drivers used by awg manufacturers. similar to evaluating single-tone distor- tion performance of an amplifier, mtpr evaluation requires a dmt signal generator capable of delivering mtpr performance better than that of the driver under evaluation. generating dmt signals can be accomplished using a tektronics awg 2021 equipped with option 4, (12-/24-bit, ttl digital data out), digitally coupled to analog devices ad9754, a 14-bit txdac ? , buffered by an ad8002 amplifier configured as a differential driver. note that the dmt waveforms, available on the analog devices website, www.analog.com, or similar. wfm files are needed to produce the necessary digital data required to drive the txdac from the optional ttl digital data output of the tek awg2021. txdac is a registered trademark of analog devices, inc.
rev. 0 ad8019 C15C b 3 2 1 jp3 p4 1 +v ? u1 1 2 3 4 5 13 vcc vee ? +v u1 5 3 13 ad8019 ad8019 11 12 10 1 2 a b 2 jp7 vcc-2 c5 0.1 f r28 dni tp6 r20 dni tp7 pr1 a c11 dni c22 dni r3 dni r1 100 1watt r38 dni r8 100 c8 0.1 f tp10 r24 10k r40 dni c28 dni r29 10k r41 dni r14 100 c27 dni r4 dni r21 dni c12 dni r39 dni r37 dni pr2 tp9 b tp8 r30 0 vcc 2 b jp4 3 1 a p4 2 p4 3 s5 s6 vcc vcc s3 p3 1 p3 2 p3 3 u2 u2 ad8022 ad8022 s4 b 3 2 1 jp6 a tb1 2 tb1 3 tb1 1 + + dni r35 dni c29 dni r36 dni c7 dni c9 dni r32 100 nc = 5,6 t1 1 2 3 4 7 8 9 10 tp1 c6 dni p1 1 2 3 4 78 5 6 tp2 tp23 tp24 tp25 tp26 vccin l5 bead l1 bead c4 10 f 25v c21 0.1 f c20 0.1 f c17 dni u1 decoupling u1 decoupling u2 decoupling u2 decoupling c23 dni tp19 tp12 c15 0.01 f c14 10 f 25v c26 0.1 f vcc vee jp5 c18 dni tp4 tp5 vcc-2 c3 dni c16 dni r22 dni r13 dni r10 dni r9 dni c2 dni r23 dni c1 dni r5 dni r6 dni vcc r7 dni r34 dni r33 dni r12 dni vcc;8 vee;4 vcc;8 vee;4 7 5 6 1 2 3 tp18 tp17 vcc-2 c19 0.1 f r17 5k r16 5k tp3 tp11 c10 0.1 f vee r15 50 r31 0 a r42 dni r2 50 r18 301 c13 0.1 f r19 301 a r11 50 * dni : do not install figure 8. tssop noninverting dsl evaluation board schematic
rev. 0 ad8019 C16C vcc r25 val r26 val r27 val c24 val nc4 nc1 nc2 nc3 1714 8 9 6 1 2 3 b jp1 pwdn dgnd u1 ad8019 a figure 9. dsl driver input control circuit figure 10. tssop evaluation board silkscreen top figure 11. tssop evaluation board silkscreen bottom 2 agnd agnd figure 12. tssop evaluation board power plane
rev. 0 ad8019 C17C figure 13. solder mask top figure 14. solder mask bottom figure 15. ground plane bottom figure 16. assembly top
rev. 0 ad8019 C18C figure 17. ground plane top figure 18. assembly bottom
rev. 0 ad8019 C19C figure 19. board fabrication
rev. 0 C20C ad8019 outline dimensions dimensions shown in inches and (mm). 14-lead tssop (ru-14) 14 8 7 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.201 (5.10) 0.193 (4.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 8-lead soic (r-8) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25) 45 8 0 0.102 (2.59) 0.094 (2.39) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 85 4 1 0.1968 (5.00) 0.1890 (4.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0500 (1.27) bsc 0.2440 (6.20) 0.2284 (5.80) c02551C1.5C4/01(0) printed in u.s.a.

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