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1/9 june 2004 STS2DPF80 dual p-channel 80v - 0.21 ? - 2.3a so-8 stripfet? power mosfet rev.0.1 typical r ds (on) = 0.21 ? standard outline for easy automated surface mount assembly description this application specific power mosfet is the second generation of stmicroelectronis unique "single feature size?" strip-based process. the resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproduc- ibility . applications dc/dc converters battery management in nomadic equipment power management in cellular phones and display new generation ordering information type v dss r ds(on) i d STS2DPF80 80 v <0.25 ? 2.3 a sales type marking package packaging sts8dpf80 s8dpf80 so-8 tape & reel so-8 absolute maximum ratings ( ?) pulse width limited by safe operating area. note: for t he p-channel mosfet actual polarity of voltages and current has to be reversed symbol parameter value unit v ds drain-source voltage (v gs = 0) 80 v v dgr drain-gate voltage (r gs = 20 k ? ) 80 v v gs gate- source voltage 20 v i d drain current (continuous) at t c = 25c single operation drain current (continuous) at t c = 100c single operation 2.0 1.3 a a i dm ( ?) drain current (pulsed) 8 a p tot total dissipation at t c = 25c 2.5 w t stg storage temperature -55 to 150 c t j max. operating junction temperature 150 c internal schematic diagram
STS2DPF80 2/9 tab.1 thermal data (*) when mounted on 1 inch 2 fr-4 board, 2 oz of cu and t [ 10 sec. electrical characteristics (t case = 25 c unless otherwise specified) tab.2 off tab.3 on (* ) tab.4 dynamic rthj- pcb (*) thermal resistance junction-pcb 62.5 c/w symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 80 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating v ds = max rating t c = 125c 1 10 a a i gss gate-body leakage current (v ds = 0) v gs = 20 v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs i d = 250 a 24v r ds(on) static drain-source on resistance v gs = 10 v i d = 1 a 0.21 0.25 ? symbol parameter test conditions min. typ. max. unit g fs (*) forward transconductance v ds = 10v i d =1 a 4s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 25v, f = 1 mhz, v gs = 0 739 89.5 31 pf pf pf 3/9 STS2DPF80 tab.5 switching on tab.6 switching off tab.7 source drain diode (*) pulsed: pulse duration = 300 s, duty cycle 1.5 %. ( ? ) pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time v dd = 40 v i d = 1 a r g =4.7 ? v gs = 10 v (resistive load, figure 1) 13.5 18 ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd = 64v i d = 2a v gs =10v (see test circuit, figure 2) 20 2.5 4.9 nc nc nc symbol parameter test conditions min. typ. max. unit t d(off) t f turn-off delay time fall time v dd = 40 v i d = 1 a r g =4.7 ?, v gs = 10 v (resistive load, figure 1) 32 13 ns ns symbol parameter test conditions min. typ. max. unit i sd i sdm ( ? ) source-drain current source-drain current (pulsed) 2.3 9.2 a a v sd (*) forward on voltage i sd = 1 a v gs = 0 1.2 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 2 a di/dt = 100a/s v dd = 40 v t j = 150c (see test circuit, figure 3) 47 87 3.7 ns nc a electrical characteristics (continued) safe operating area thermal impedance STS2DPF80 4/9 output characteristics transfer characteristics transconductance static drain-source on resistance gate charge vs gate-source voltage capacitance variations 5/9 STS2DPF80 normalized gate threshold voltage vs temperature normalized on resistance vs temperature source-drain diode forward characteristics normalized breakdown voltage temperature . . . STS2DPF80 6/9 fig. 2: gate charge test circuit fig. 3: test circuit for diode recovery behaviour fig. 1: switching times test circuits for resistive load 7/9 STS2DPF80 dim. mm inch min. typ. max. min. typ. max. a1.750.068 a1 0.1 0.25 0.003 0.009 a2 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.25 0.5 0.010 0.019 c1 45 (typ.) d 4.8 5.0 0.188 0.196 e 5.8 6.2 0.228 0.244 e1.27 0.050 e3 3.81 0.150 f 3.8 4.0 0.14 0.157 l 0.4 1.27 0.015 0.050 m0.60.023 s8 (max.) 0016023 so-8 mechanical data STS2DPF80 8/9 revision history date revision description of changes wednesday 16 june 2004 0.1 first issue 9/9 STS2DPF80 i nformation furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the con sequence s o f use of such information nor for any infringement of patents or other rights of third parties which may result from its use. n o license is grante d b y implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicatio n are subje ct t o change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics produ cts are n ot a uthorized for use as critical components in life support devices or systems without express writte n approval of stmicroelectron ics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco -singapore - spain - sweden - switzerland - united kingdom - united states. www.st.com |
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