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1 programmable v com calibrator with eeprom ISL24202 the ISL24202 is an 8-bit programmable current sink that can be used in conjunction with an extern al voltage divider to generate a voltage source (v com ) positioned between the analog supply voltage and ground. the current sink?s full-scale range is controlled by an external resistor, r set . with the appropriate choice of external resistors r 1 and r 2 , the v com voltage range can be controlled between any arbitrary voltage range. the ISL24202 has an 8-bit data register and 8-bit eeprom for storing both a volatile and a permanent value for its output, accessible through a single up/down counter interface pin (ctl). after the part is programmed with the desired v com value, the counter enable pin (ce) can be grounded to prevent further changes. on every power-up the eeprom contents are automatically transferred to the data register, and the pre-programmed output voltage appears at the v out pin. the ISL24202 can be used with a high output drive buffer amplifier, which allows it to directly drive the v com input of an lcd panel. the ISL24202 is available in an 8 ld 3mm x 3mm tdfn package. this package has a maximum height of 0.8mm for very low profile designs. the ambient operating temperature range is -40c to +85c . features ? adjustable 8-bit, 256-st ep, current sink output ? on-chip 8-bit eeprom ? up/down counter interface ? guaranteed monotonic over-temperature ? 4.5v to 19.0v analog supply range for norm al operation (10.8v minimum analog supply voltage for programming) ? 2.25v to 3.6v logic supp ly voltage operating range ? pb-free (rohs-compliant) ? ultra-thin 8 ld tdfn (3 x 3 x 0.8mm max) applications ?lcd panel v com generator ? electrophoretic display v com generator related literature ? see an1633 for ISL24202 evalua tion board application note ?ISL24202irtz-evalz evaluation board user guide? (coming soon) micro- controller ISL24202 ce ctl out set v dd av dd 8 5 4 7 6 1 2 r set r 1 r 2 lcd panel v com i/o pin i/o pin* * 0, 1, tri-state el5411t figure 1. typical ISL24202 application march 15, 2011 fn7587.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL24202 2 fn7587.0 march 15, 2011 block diagram pin descriptions pin configuration ISL24202 (8 ld tdfn) top view figure 2. block diagram of the ISL24202 gnd digital interface dac registers 8-bit eeprom ctl dnc ce av dd set 8 2 6 7 4 cs out 1 q1 a1 analog dcp and current sink up/down counter 5 v dd 3 v dd r bias r bias pin name pin # function out 1 adjustable sink current outp ut pin. the sink current into the out pin is equal to the dac setting times the maximum adjustable sink cu rrent divided by 256. see the ?set? pin function description below (pin 8) for setting the maximum adjustable sink current. a vdd 2 high-voltage analog supply. bypass to gnd with 0.1f capacitor. dnc 3 do not connect to external circuitry. it is acceptable to ground this pin. gnd 4 ground connection. v dd 5 digital power supply input. bypass to gnd with 0.1f de-coupling capacitor. ctl 6 up/down control for internal counter and internal eeprom programming control input. when ce is high: a low-to-mid transition increments the 8-bit counter, adding 1 to the dac setting , increasing the out sink current, and lowering the divider voltage at the out pin. a high-to-mid transition decrements the 8-bit counter, subtracting 1 from the dac setting, decreasing the out sink current, and increasing the divider voltage at the out pin. to program the eeprom, take this pin to >4.9v (see ?ctl eeprom programming signal time? in the ?electrical specifications? table on page 5 for details). float when not in use. ce 7 counter enable pin. connect ce to v dd to enable adjustment of the output si nk current. float or connect ce to gnd to prevent further adjustment or programming (note: the ce pin has an internal 500na pull-down sink current). the eeprom value will be copied to the register on a v oh to v ol transition. set 8 maximum sink current adjustment pin. connect a resistor from set to gnd to set the maximum adjustable sink current of the out pin. the maximum adjustable sink current is equal to (av dd /20) divided by r set . pad - thermal pad should be connected to system ground plane to optimize thermal performance. (*connect thermal pad to gnd) out a vdd dnc gnd 1 2 3 4 8 7 6 5 set ce ctl v dd pad
ISL24202 3 fn7587.0 march 15, 2011 ordering information part number (notes 1, 2, 3) part marking interface temp range (c) package (pb-free) pkg. dwg. # ISL24202irtz 202z counter -40 to +85 8 ld 3x3 tdfn l8.3x3a ISL24202irtz-evalz evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page ISL24202 . for more information on msl please see techbrief tb363 .
ISL24202 4 fn7587.0 march 15, 2011 absolute maximum rating s thermal information supply voltage av dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4v input voltage with respect to ground set, ctl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . av dd +0.3v ce and wp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v dd +0.3v output voltage with respect to ground out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . av dd continuous output current out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma esd ratings human body model (tested per jesd22-a114) . . . . . . . . . . . . . . . . . 7kv machine model (tested per jesd22-a115). . . . . . . . . . . . . . . . . . . . 300v charged device model (tested per jesd22-c101). . . . . . . . . . . . . . . 2kv latch up (tested per jesd 78, class ii, level a). . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 8 ld tdfn package (notes 4, 5). . . . . . . . . 53 11 moisture sensitivity (see technical brief tb363) all packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . level 1 maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions operating range av dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 19v v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25v to 3.6v ambient operating temperature . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications test conditions: v dd = 3.3v, av dd = 18v, r set = 5k , r 1 = 10k , r 2 = 10k , (see figure 5). typicals are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c . symbol parameter test conditions min (note 6) typ max (note 6) units dc characteristics v dd v dd supply range - operating 2.25 3.6 v av dd av dd supply range supporting eeprom programming 10.8 19 v av dd av dd supply range for wide-supply operation without eeprom programming 4.5 19 v i dd v dd supply current ctl = 0.5*v dd 40 65 a i avdd av dd supply current ctl = 0.5*v dd 24 38 a out pin characteristics set zse set zero-scale error 3lsb set fse set full-scale error 8lsb v out out voltage range v set + 1.75 av dd v set vd set voltage drift 7v/c i out maximum out sink current 4ma inl integral non-linearity 2lsb dnl differential non-linearity 1lsb eeprom characteristics t prog eeprom programming time (internal) 100 ms up/down counter control inputs (see figure 11) v ih ce and ctl input logic high threshold 0.7*v dd v v il ce and ctl input logic low threshold 0.3*v dd v i cs_pd ce input pull down current sink 0.5 1.5 a i ctl ctl input bias current ctl = gnd (sourcing) 7 15 a ctl = v dd (sinking) 7 15 a t st ce to ctl start delay 50 s t read eeprom recall time (after ce de-asserted) 10 ms
ISL24202 5 fn7587.0 march 15, 2011 t h_rej ctl high pulse rejection width 20 s t l_rej ctl low pulse rejection width 20 s t h_min ctl high minimum valid pulse width 200 s t l_min ctl low minimum valid pulse width 200 s t mtc ctl minimum time between counts 10 s v prog ctl eeprom program voltage (see figure 9) 4.9 19 v t prog ctl eeprom programming signal time 200 s t h_prop ctl high-to-mid to out propagation time 65 s t l_prop ctl low-to-mid to out propagation time 65 s note: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications test conditions: v dd = 3.3v, av dd = 18v, r set = 5k , r 1 = 10k , r 2 = 10k , (see figure 5). typicals are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c . (continued) symbol parameter test conditions min (note 6) typ max (note 6) units
ISL24202 6 fn7587.0 march 15, 2011 application information lcd panels have a v com (common voltage) that must be precisely set to minimize flicker. figure 3 shows a typical v com adjustment circuit using a mechanical potentiometer, and the equivalent circuit replacement using the ISL24202. having a digital counter interface enables automatic, digital flicker minimization during production test and alignment. after programming, the counter interface is not needed again - th e ISL24202 automatically powers up with the correct v com voltage programmed previously. the ISL24202 uses a digitally controllable potentiometer (dcp), with 256 steps of resolution (figure 4) to change the current drawn at the out pin, which then changes the voltage created by the r 1 - r 2 resistor divider (figure 5). the out voltage can then be buffered by an external amplifier (a 2) to generate a buffered output voltage (v com ) capable of driving the v com input of an lcd panel. the amount of current sunk is controlled by the setting of the dcp, which is recalled at power-up from the ISL24202?s internal eeprom. the eeprom is typically programmed during panel manufacture. as noted in the ?e lectrical specifications? section on page 4, the ISL24202 requires a minimum av dd voltage of 10.8v for eeprom programming, but will work in normal operation down to 4.5v after the eeprom has been programmed, with no additional eeprom writing. dcp (digitally controllable potentiometer) the dcp controls the voltage that ultimately controls the set current. figure 4 shows the rela tionship between the register value and the dcp?s tap position. note that a register value of 0 selects the first step of the resist or string. the output voltage of the dcp is given in equation 1: output current sink figure 5 shows the schematic of the out current sink. the combination of amplifier a1, tr ansistor q1, and resistor r set forms a voltage-controlled current source, with the voltage determined by the dcp setting. the external r set resistor sets the full-sca le (maximum) sink current that can be pulled from the ou t node. the relationship between i out and register value is shown in equation 2. the maximum value of i out can be calculated by substituting the maximum register value of 255 into equation 2, resulting in equation 3: equation 2 can also be used to calculate the unit sink current step size per register code, resulting in equation 4: figure 3. mechanical adjustment replacement set ISL24202 r 1 r 2 av dd av dd v com i out v dd r set r a r c av dd v com r b r 1 = r a r 2 = r b +r c r set = r a r b + r a r c 20r b out a2 v dcp registervalue 1 + 256 -------------------------------------------------- - ?? ?? av dd 20 -------------- ?? ?? = (eq. 1) figure 4. simplified schematic of dcp av dd 19r r 0 1 2 255 254 253 252 251 register value av dd 20 v dcp figure 5. current sink circuit a vdd r set v dcp set out a vdd i out r 1 r 2 v sat q1 a1 v out v set = v dcp = i out * r set i out i out v dcp r set ------------- registervalue 1 + 256 -------------------------------------------------- - ?? ?? av dd 20 -------------- ?? ?? 1 r set ------------ - ?? ?? == (eq. 2) i out max () a vdd 20r set -------------------- = (eq. 3) i step av dd 256 () 20 () r set () --------------------------------------------- - = (eq. 4)
ISL24202 7 fn7587.0 march 15, 2011 determination of r set the ultimate goal for the ISL24202 is to generate an adjustable voltage between two endpoints, v com_min and v com_max , with a fixed power supply voltage, av dd . this is accomplished by choosing the correct values for r set , r 1 and r 2 . the exact value of r set is not critical. values from 1k to more than 100k will work under most conditions. the following expression calculates the minimum r set value: note that this is the absolute minimum value for r set . larger r set values reduce quiescent power, since r 1 and r 2 are proportional to r set . the ISL24202 is tested with a 5k r set . determination of r 1 and r 2 with av dd , v com(min) and v com(max) known and r set chosen per the above requirements, r 1 and r 2 can be determined using equations 6 and 7: final transfer function the voltage at the out pin can be calculated from equation 8: with external amplifier a2 in the unity-gain configuration, v out =v com . example as an example, suppose the a vdd supply is 15v, the desired v com_min = 6.5v and the desired v com_max = 8.5v. r set is arbitrarily chosen to be 7.5k . first, verify that our chosen r set meets the minimum requirement described in equation 5: using equations 6 and 7, calculate the values of r 1 and r 2 : table 1 shows the resulting v com voltage as a function of register value for these conditions. output voltage span calculation it is also possible to calculate v com(min) and v com(max) from the existing resistor values. v com_min occurs when the greatest current, i out(max), is drawn from the middle node of the r 1 /r 2 divider. substituting registervalue = 255 into equation 8 gives the following: similarly, registervalue = 0 for v com(max) : by finding the difference of equation 13 and equation 12, the total span of v com can be found: r set min () av dd 16 -------------- v out min () av dd 20 -------------- ? ?? ?? ----------------------------------------------------- - ?? ?? ?? ?? ?? ?? k () = (eq. 5) r 1 5120 r set v com max () v com min () ? 256 v com max () ? v com min () ? -------------------------------------------------------------------------------- - ?? ?? ?? ? = (eq. 6) r 2 5120 r set v com max () v com min () ? 255 av dd ? v com min () 256 v com max () ? ? + -------------------------------------------------------------------------------------------------------------------- - ?? ?? ?? ? = (eq. 7) v out av dd r 2 r 1 r 2 + -------------------- ?? ?? ?? 1 registervalue 1 + 256 -------------------------------------------------- - r 1 20r set -------------------- ?? ?? ?? ? ?? ?? ?? = (eq. 8) 7.5k () r set min () 15 16 ------ - 6.5v 15 20 ------ - ? ?? ?? ------------------------------ ?? ?? ?? ?? ?? 0.163k == ?? ?? ?? ?? ?? > (eq. 9) table 1. example v out vs register value register value v out (v) 08.49 20 8.34 40 8.18 60 8.02 80 7.87 100 7.71 120 7.55 127 7.50 140 7.40 160 7.24 180 7.09 200 6.93 220 6.77 240 6.62 255 6.50 r 1 5120 7500 8.5 6.5 ? 256 8.5 ? 6.5 ? ------------------------------------- - ?? ?? ?? 35.4k == (eq. 10) r 2 5120 7500 8.5 6.5 ? 255 15 ? 6.5 256 8.5 ? ? + ------------------------------------------------------------------ ?? ?? ?? 46.4k == (eq. 11) v com min () av dd r 2 r 1 r 2 + -------------------- ?? ?? ?? 1 r 1 20r set -------------------- ?? ?? ?? ? ?? ?? ?? = (eq. 12) v com max () av dd r 2 r 1 r 2 + -------------------- ?? ?? ?? 1 1 256 ---------- r 1 20r set -------------------- ?? ?? ?? ? ?? ?? ?? = (eq. 13) v com span av dd r 2 r 1 r 2 + -------------------- ?? ?? ?? 1 1 256 ---------- ? ?? ?? r 1 20r set -------------------- ?? ?? ?? = (eq. 14)
ISL24202 8 fn7587.0 march 15, 2011 assuming that the i out (min) = 0 instead of i step , the expression in equation 14 simplifies to: out pin leakage current when the voltage on the out pin is greater than 10v, an additional leakage current flows in to the pin in addition to the i set current. figure 6 shows the i set current and the out pin current for out pin voltage up to 19v. in applications where the voltage on the out pin will be greater than 10v, the actual output voltage will be lower than the voltage calculated by equation 8 due to this extra current. the graph in figure 6 was measured with r set = 4.99k . power supply sequence the recommended power supply sequencing is shown in figure 7. when applying power, v dd should be applied before or at the same time as av dd . the minimum time for t vs is 0s. when removing power, the sequence of v dd and av dd is not important. do not remove v dd or av dd within 100ms of the start of the eeprom programming cycle. removing power before the eeprom programming cycle is completed may result in corrupted data in the eeprom. operating and programming supply voltage and current to program the eeprom, av dd must be 10.8v. if further programming is not required, the ISL24202 will operate over an av dd range of 4.5v to 19v. during eeprom programming, i dd and i avdd will temporarily be 4-5x higher for up to 100ms (t prog ). up/down counter interface the ISL24202 allows the adjustment of the output v com voltage and the programming of the non-volatile memory through a single pin (ctl) when the ce (cou nter enable) pin is high. the ctl pin is biased so that its voltage is set to vdd/2 if the driving circuit is set to tri-state or high impedance (hi-z), allowing up/down operation using common digital i/o logic. ctl pin when a mid-high-mid transition is detected on the ctl pin (see figure 11), the internal register value counts down by one at the trailing (high-mid) edge, and the output v com voltage is increased according to equation 8. similarly, when a mid-low-mid transition is detected on the ctl pin, the internal register value counts up by one at the trailing (low-mid) edge, and the output v com voltage is decreased. once the maximum or minimum value is reached, the counter saturates and will not overflow or underflow beyond those values. ctl should have a noise filter to reduce bouncing or noise on the input that could cause unwanted co unts when the ce pin is high. figure 8 shows a simple debouncing circuit consisting of a series 1k resistor and a shunt 0.01f capacitor connected on the ctl pin. to avoid unintentional adjustment, the ISL24202 guarantees to reject ctl pulses shorter than 20s. this pin is pulled above 4.9v to program the eeprom. see ?programming the eeprom? on page 9 for details. after ce (counter enable) is asserted and after programming eeprom, the very first ctl pulse is ignored (see figure 11) to avoid the possibility of a false count (since ctl state may be unknown after programming). ce pin to change the counter controllin g the output voltage, the ce (counter enable) pin must be pulled high (v dd ). when the ce pin is pulled low, the counter value is loaded from eeprom, which takes 10ms (during which the inputs should remain constant). the ce pin has an internal pull-down to keep it at a logic low v com span r 1 r ? 2 r 1 r 2 + -------------------- ?? ?? ?? av dd 20r set -------------------- ?? ?? ?? r 1 r ? 2 r 1 r 2 + -------------------- ?? ?? ?? i dvrout max () == (eq. 15) figure 6. out pin leakage current 02468101214161820 out pin voltage (v) current (ma) 0.00 0.05 0.10 0.15 0.20 0.25 0.30 out pin current set pin current register = 255 v dd a vdd t vs figure 7. power supply sequence figure 8. external debouncer on ctl pin ISL24202 ctl 0.01f 1k av dd close to eeprom program
ISL24202 9 fn7587.0 march 15, 2011 when not being driven. ce should be pulled low before powering the device down to ensure that an y glitches or transients during power-down will not cause unwanted eeprom overwriting. the ce pin has a schmitt trigger on the input to prevent false triggering during slow transiti ons of the ce pin. the ce pin transition time shou ld be 10s or less. programming the eeprom to program the non-volatile eeprom, pull the ctl pin above 4.9v for more than 200s. the level and timing is shown in figure 9. it then takes a maximum of 100ms after ctl crosses 4.9v for the programming to be completed inside the device. when the part is programmed, the data in the counter register is written into the eeprom. this value will be loaded from the eeprom during subsequent power-ups as well as when the ce pin is pulled low. the ISL24202 is factory-programmed to mid-scale. as with asserting ce, the first pulse after a program operation is ignored. the eeprom contents can be written and verified using the following steps: 1. power-up the ISL24202. the ee prom value will be loaded. 2. set the ce pin to v dd . 3. change the v out voltage using the ctl pin to the desired value, noting that first pulse will be ignored. 4. pull the ctl pin to 4.9v or higher for at least 200s. the counter value will be written to eeprom after 100ms. 5. change the v out value (using the ctl pin) to a different value, noting that first pulse after programming will be ignored. 6. set the ce pin to 0v. the stored output value will be loaded from eeprom after 10ms. 7. verify that the output value is the same value programmed in step 4. the ctl pin should be left fl oating after programming. the voltage at the ctl pin will be internally biased to v dd /2 to ensure that no additional pulses will be seen by the up/down counter. to prevent further changes, ground the ce pin. typical application circuit shown below in figure 10 is a typical circuit that can be used to program the ISL24202 via the up/down counter interface. three momentary push-button switches are required. sw1 connected between ctl and av dd allows the user to bring ctl above v dd for programming the eeprom, sw2 connected to v dd to pull ctl up, and sw3 connected to gnd to pull ctl to down. all the switches should have 1k current-limiting resistors in series. for adjustment and programming to occur, the ce pin has to be set to v dd . this can be achieved by a single-pull double-throw switch (sw4) connected between v dd and gnd. note that pressing the up button increments the counter, but results in v com_out decreasing. similarly, pressing the down button decrements the counter, and results in v com_out increasing. ctl voltage time 4.9v t prog figure 9. eeprom programming >200s 100ms eeprom operation complete figure 10. typical application circuit ISL24202 ctl 0.01f 1k ? v dd close to up program 1k ? av dd down 1k ? eeprom ce set r 1 r 2 r set out v com to lcd panel sw2 sw1 sw3 sw4 av dd v dd av dd gnd v dd av dd 0.01f 0.1f 0.1f enable v dd adjust / program disable el5411t
ISL24202 10 fn7587.0 march 15, 2011 up/down counter waveforms the operation modes of the ISL24202 is shown in table 2. figure 11 shows the associated waveforms. table 2. ISL24202 operation modes input output ctl ce counter v com_out eeprom xlo no change x lo to hi ignore first ctl pulse no change hi to mid hi decrement increase no change lo to mid hi increment decrease no change mid to >4.9v hi no change no change write counter value to eeprom >4.9v to mid hi ignore next ctl pulse no change xhi to loeeprom read value programmed value no change ctl v dd /2 ctl low ctl high ce 78 79 7a 7b 7a counter output t l_min t mtc t h_rej figure 11. counter interface timing diagram vcom t st first pulse after asserting ce is after counter enable is asserted, the first ctl pulse is ignored example post power-up timing note: enable adjustment avdd vdd 7b deasserting ce from eeprom assume counter starts with value 78 v prog = 4.9v t prog t h_min 7a t l_prop t h_prop reloads 7b first pulse after programming is write 7b to eeprom disable adjustment enable adjustment t read t l_rej ignored ignored
ISL24202 11 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7587.0 march 15, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: ISL24202 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/sear revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change 3/15/11 fn7587.0 initial release.
ISL24202 12 fn7587.0 march 15, 2011 package outline drawing l8.3x3a 8 lead thin dual flat no-lead plastic package rev 4, 2/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.20mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 3.00 a b 3.00 (4x) 0.15 6 pin 1 index area pin #1 6x 0.65 1.50 0.10 8 1 8x 0.30 0.10 6 0.75 0.05 see detail "x" 0.08 0.10 c c c ( 2.90 ) (1.50) ( 8 x 0.30) ( 8x 0.50) ( 2.30) ( 1.95) 2.30 0.10 0.10 8x 0.30 0.05 a mc b 4 2x 1.950 (6x 0.65) index area pin 1 compliant to jedec mo-229 weec-2 except for the foot length. 7.

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