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| data sheet, version 4.0, june 07 TDA5230 tda5231 universal low power ask/fsk single conversion multi-channel image-reject receiver with digital baseband processing wireless control components never stop thinking.
edition 2007-06-01 published by infineon technologies ag, am campeon 1-12, 85579 neubiberg, germany ? infineon technologies ag 2007. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or the infineon technologies companies and our infineon technologies representatives worldwide ( www.infineon.com ). warnings due to technical requirements components may contain dan gerous substances. for info rmation on the types in question please contact your neares t infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or sys tem, or to affect the safety or effectiv eness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. data sheet, version 4.0, june 07 TDA5230 tda5231 universal low power ask/fsk single conversion multi-channel image-reject receiver with digital baseband processing wireless control components never stop thinking. tda523x revision history: 2007-06-01 version 4.0 previous version: TDA5230 preliminary data sheet v2.01 page prev. version page current version subjects (changes since previous revision) all all rework of all chapters product description enhanced by additional short form information functional description, explanations added, full sfr information in each chapter reference: some characteristics added, fsk demodulator bw changed to practical measurement method previous version: td a523x data sheet v3.0 page prev. version page current version subjects (changes since previous revision) 4 if mux added in chapter 1 product description , chapter 2.4.8.1 if filter , and dual: aif0 and bif0: conf. a if buffer amplifier enable 51 51 explanation for t on and t off from chapter 2.4.6.2 constant on/off time to chapter 2.4.6.5 permanent wake up search improved 125 127 description digital i/o pins corrected 134 135 reset value for register cmc0 corrected 163 minimum spm cycletime (t on +t off ) specified 4 4 aec q100 added 5 order information added all all spelling corrections we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (includi ng a reference to this document) to: sensors@infineon.com data sheet 1 version 4.0, 2007-06-01 tda523x 1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 order information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.5 target application frequencies for TDA5230 and tda5231 . . . . . . . . . . . 5 1.6 major key-features of TDA5230 and tda5231 . . . . . . . . . . . . . . . . . . . . . 6 1.6.1 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.6.2 baseband processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.6.3 autonomous self polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.6.4 two independent receiver configuration sets . . . . . . . . . . . . . . . . . . . . 8 1.6.5 multi-channel pll receiver supports up to 17 subchannels . . . . . . . . . 8 1.6.6 support software and evaluation boards . . . . . . . . . . . . . . . . . . . . . . . . 9 1.6.6.1 the iaf tda523x configuration tool . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.6.6.2 the tda523x explorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.6.6.3 evaluation boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 pin definition and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4.1.1 supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.2 chip reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.3 system clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4.3.1 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4.3.2 external clock generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.4 rf-pll synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.4.5 master control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4.5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4.5.2 run mode slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4.5.3 hold mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.4.5.4 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.4.5.5 self polling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4.5.6 automatic modulation switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.4.5.7 multi-channel in self polling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.4.5.8 run mode self polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.4.6 polling timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.4.6.1 self polling modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.4.6.2 constant on/off time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.4.6.3 fast fall back to sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.4.6.4 mixed mode (constant on/off time & fast fall back to sleep) . . . . 56 tda523x data sheet 2 version 4.0, 2007-06-01 2.4.6.5 permanent wake up search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.4.6.6 active idle period selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.4.7 rf path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.4.7.1 rx-run/rxd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.4.8 functionality of the if path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.4.8.1 if filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.4.8.2 limiter, rssi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.4.8.3 rssi peak detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.4.9 digital receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.4.9.1 synchronization search ti me and inter-frame time . . . . . . . . . . . . 75 2.4.9.2 data filter and signal detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.4.10 digital fsk demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 2.4.11 clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 2.4.12 wake up generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 2.4.13 frame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 2.4.14 message-id scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 2.4.15 data fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 2.4.16 transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 2.4.17 interrupt generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 2.4.18 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 2.4.19 chip serial number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 2.4.20 digital input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 3.1 detailed register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 4 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 4.1 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 4.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 4.1.2 operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 4.1.3 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 rf characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 if characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 limiter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 crystal oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 digital inputs/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 timing spi-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 4.2 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 4.2.1 serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 4.2.2 serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 4.3 test circuit, evaluation board v2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 4.4 test board layout - evaluation board v2.1 . . . . . . . . . . . . . . . . . . . . . . 177 4.5 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 data sheet 3 version 4.0, 2007-06-01 tda523x 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 tda523x product description data sheet 4 version 4.0, 2007-06-01 1 product description 1.1 overview the tda523x is a family of universal, highly sensitive, low-power single-chip ask/fsk superheterodyne image-reject-receivers for manchester-coded data signals in the ism bands between 302..320 mhz, 433..450 mhz and 865..870 mhz. the chips include fully-integrated digital baseband data processing and produce clean data output via spi, thus significantly reducing the load on the host processor and standby power consumption. the tda523x family of chips offers a high level of integration and needs only few external components for application deployment. the tda523x is able to run in several autonomous self-polling and wake-up modes, scanning the received signal for usable data. interrupts can be initiated based on various criteria, such as the received bit pattern to wake up the host processor. received data can be scanned for certain message contents (ids) and is stored in a fifo data buffer, accessible via the spi host interface. the tda523x is able to scan and receive from different sources with up to two different independent parameter configuration sets. configurations can differ in modulation ask/fsk, data rate, wake up criterion, protocol, etc. additionally, multichannel applications are supported by scanning of up to 3 rf channels in the same band. the tda523x is fully programmable to facilitate quick time to market. 1.2 key features ? fully integrated ask/fsk rf data receiver with data fifo and spi host interface ? high input sensitivity: e.g. typically -108dbm at 2kbit data rate (see specifications ) ? autonomous wake-up and self-polling features allow different modulation for wake-up and data ? two parallel parameter sets for scanning and receiving from different sources ? reduces significantly host processing power, system standby power consumption ? fully integrated multichannel pll synthesizer support up to 17 sub-channels ? image reject mixer prevents interferences on mirror frequency ? if filter multiplexer allows if bandwidth switching ? if-limiting amplifier with rssi-output accessible via dedicated pin or register ? data framer with versatile frame synchronization capability ? message contents (id) scanning ? unique serial-number, accessible via spi ? crystal-oscillator with on chip fine-tuning, clock-output with configurable prescaler ? supply voltage range 3.0 v to 3.6 v and 4.5 v to 5.5 v ? package pg-tssop-28-1 ? operating temperature range -40 to +105c ? qualified according automotive aec-q100 ? evaluation boards, reference designs, and free pc configuration and evaluation tools available 1.3 applications ? tire pressure monitoring systems ? remote keyless entry systems ? remote control systems data sheet 5 version 4.0, 2007-06-01 tda523x product description 1.4 order information 1.5 target application frequencies for TDA5230 and tda5231 the tda523x family of receivers cover a wide range of commonly used receive frequencies within the three major ism-bands used in tpms, rke/pke and remote control system applications. the TDA5230 covers operation in the 433..450 mhz and 865..868 mhz ism bands. the tda5231 covers complementary operation in the 302..320 mhz ism-band. figure 1 identifies the c apabilities of the TDA5230 and tda5231 within the three different frequency bands. figure 1 application frequencies for TDA5230 and tda5231 type ordering code package TDA5230 q62705k 791 pg-tssop28-1 tda5231 sp000202847 pg-tssop28-1 color underlayed text within this document highlights differences in the operation between the TDA5230 (lo-side lo-injecti on) and tda5231 (hi-side lo-injection). TDA5230 433 .. 450 mhz ask fsk ask fsk receive- frequency tda5231 302 .. 320 mhz ask fsk 865 .. 870 mhz tda523x product description data sheet 6 version 4.0, 2007-06-01 1.6 major key-features of TDA5230 and tda5231 1.6.1 typical application circuit figure 2 typical application circuit the tda523x requires only view external components. in noise and emc sensitive applications usage of an input saw filter plus additional matching circuitry is recommended. data sheet 7 version 4.0, 2007-06-01 tda523x product description 1.6.2 baseband processing tda523x has integrated all means to process incoming ask or fsk modulated manchester-coded bit streams, and convert them into pure data, which can be read out via spi by the host processor. figure 3 internal data processing flow the manchester-coded bit stream is dec oded by the manchester decoder into a bit stream containing the wake-up pattern, the tsi (telegram start identifier) and the payload. the framer separates the payload an d stores it in the fifo. an interrupt is generated and data can be read from the fifo by the host processor via spi. 1.6.3 autonomous self polling the tda523x offers a fully autonomous self polling mode, in which the rf input signal is scanned for valid data signals base on programmable timing. the host processor is not burdened with this task, so its full processing power is available for other tasks, or the host processor may stay in a power save, or sleep mode. when valid data has been rf input rf engine: amplifier, down converter, filter demodulator manchester decoder framer fifo down converted rf manchester coded bit stream complete data frames payload data interrupt, spi tda523x product description data sheet 8 version 4.0, 2007-06-01 received, the host processor is alerted by an interrupt, and the data payload is available from the fifo. invalid signals are ignored. the tda523x offers different programmable scanning modes, and criteria to identify valid wake up patterns, tsis, and payloads. selectable wake-up criteria include detection of a valid data rate, a random manchester-coded pattern, a chain of equal manc hester-coded bits, or a specific pattern. before initiating an interrupt also the tsi must match up to a programmed pattern; optionally the data stream may be scanned for up to 16 bytes of a message identifier. 1.6.4 two independent receiver configuration sets figure 4 tda523x two independent receiver configurations (simplified) tda523x has two switchable register sets, allowing scans based on up to two different configurations from different transmitters. transmi ssions may differ in sub-channel, modulation, wake-up criterion, data rate, ts i, message identifier, packet length, etc. in self polling mode configurations are switched autonomously; in slave mode, configurations are switched by changing a single register bit. 1.6.5 multi-channel pll receiver supports up to 17 subchannels tda523x supports up to 17 subchannels: 1 center channel, 8 channels above, and 8 channels below the center channel frequen cy. the frequencies for the channels are fixed and depend on the system frequency and the selected band. additional information is provided in chapter ?rf-pll synthesizer? on page 28 . in self polling mode up to 3 channels per receiver configuration may be scanned automatically. transmitter a transmitter b configuration a configuration b mixer baseband fifo spi data sheet 9 version 4.0, 2007-06-01 tda523x product description 1.6.6 support software and evaluation boards the tda523x includes free downloadable support software. 1.6.6.1 the iaf tda523x configuration tool figure 5 iaf tda523x configuration tool the iaf tda523x configuration tool offers simp le configuration of all register settings. the resulting configuration file may be dire ctly used and downloaded with the tda523x explorer or the configuration content may be copied into the target application software. tda523x product description data sheet 10 version 4.0, 2007-06-01 1.6.6.2 the tda523x explorer figure 6 tda523x explorer the tda523x explorer works with the tda523x evaluation boards. it allows application solutions to be created and checked via a usb connection from a standard pc. the explorer allows the user to write registers, read out the data fifo and related registers. 1.6.6.3 evaluation boards various evaluation boards are available or in development. all evaluation boards have a usb inter face to connect to a standard pc and are supported by the tda523x explorer. data sheet 11 version 4.0, 2007-06-01 tda523x functional description 2 functional description 2.1 pin configuration figure 7 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 19 18 17 16 15 TDA5230 tda5231 20 nint/nstr rx-run/rxd gnda lim-in- vdd5v vddd vddd1v5 ifbuf-out clkout/rxd gndd ifbuf-in lim-in+ xtal1 p-on t2 n.c. if-out t1 sdo xtal2 ncs sck rssi vdda rfin- rfin+ sdi gndrf tda523x functional description data sheet 12 version 4.0, 2007-06-01 2.2 pin definition and functions table 1 pin definition and function pin no. symbol function 1 ifbuf-in input of if buffer amplifier 2 ifbuf-out output of if buffer amplifier 3 gnda analog ground 4 lim-in+ see schematic of pin 1 if limiter input 5 lim-in- see schematic of pin 1 complementary if limiter input 6 vdd5v supply 5 v 7 vddd digital supply 3.3 v 8 vddd1v5 digital supply 1.5 v 9 gndd digital ground lim-in- lim-in+ ifbuf-in 330 ? 330 ? gnda gnda gnda if-buffer limiter limiter ifbuf-out gnda vdda vdda gnda 330 ? = + - gndd vddd vdd5v vreg = + - gndd vdd1v5 vddd vreg data sheet 13 version 4.0, 2007-06-01 tda523x functional description 10 clkout/rxd programmable clock output and alternative rx data output 11 rx-run/rxd run mode output signal and alternative rx data output 12 nint/nstr interrupt output and alternative rx data strobe output 13 p-on power on 14 xtal1 crystal oscillator 15 xtal2 crystal oscillator pin no. symbol function clkout/rxd gndd vddd rx-run/rxd gndd vddd nint/nstr gndd vddd gndd vdd5v gndd vddd p_on xtal1 gndd vddd .... gndd vddd xtal2 gndd vddd .... gndd vddd tda523x functional description data sheet 14 version 4.0, 2007-06-01 16 ncs spi chip select 17 sck spi clock 18 sdi spi serial data input 19 sdo spi serial data output 20 t1 connect to digital ground 21 t2 connect to rf ground 22 rfin- complementary lna input 23 rfin+ lna input 24 gndrf rf ground 25 n.c. do not connect pin no. symbol function gndd vdd5v gndd vddd ncs gndd vdd5v gndd vddd sck gndd vdd5v gndd vddd sdi gndd vddd sdo rfin- gndrf lna lna rfin+ gndrf data sheet 15 version 4.0, 2007-06-01 tda523x functional description 26 rssi rssi output 27 vdda analog supply 3.3 v 28 if-out mixer if output pin no. symbol function gnda vdda rssi gnda vdda = + - gnda vdda vdd5v vreg if-out gnda vdda vdda gnda 330 ? tda523x functional description data sheet 16 version 4.0, 2007-06-01 2.3 functional block diagram figure 8 functional block diagram 2.4 functional block description the rf frontend of the chip contains an lna followed by an image reject mixer that converts the incoming rf-signal down to if wi th adjustable gain from rfin to if-out. channel selection is achieved by up to two ex ternal ceramic if filters, which narrow the channel bandwidth. the multistage amplifier per forms the limitation of the if signal and generation of the rssi signal. the limited if signal at its output drives the input of the digital fsk demodulator. the gain and offset of the generated rssi signal can be digitally adjusted. an a/d converter acts as an interface from the analog rssi signal path to the digital receiver. the digital receiver performs data filter ing, offset cancel lation and manchester decoding of the received signals after they are demodulated. the chip also offers a ir-mixer lna i digital fsk-demodulator digital-receiver if-out id- scanner sfr fifo low-power crystal-oscillator trimming voltage- regulator 5v 3.3v spi-interface brownout- detector rfin+ rfin- 10.7 mhz ceramic-filter ifbuf-in if- driver- amp. 10.7 mhz ceramic-filter ifbuf-ou t lim-in+ rssi-generation if-limiter lim-in- rssi a d i/q- divider q rssi-peak-detectors & signal-mux framer & manchester-decoder ncs sck sdi sdo serial- number ask polling-timer unit master control unit clock- generation- unit sync fsync eom interrupt unit nint/nstr rx-run/rxd clkout/rxd xtal2 xtal1 voltage- regulator 5v 3.3v vdd5v voltage- regulator 3.3v 1.5v vddd vddd1v5 vdda gndd gnda gndrf digital- core power-up reset enable enable enable digital- i/o analog & rf p-on f sys wakeup detector transparent-mode unit rx-run nint f clkout fsk matched data-filter & offset-cancellation data-clock recovery & code-violation detector data-slicer id data wu chip-data vco loop- filter charge- pump pll-divider phase- detector reference- divider data sheet 17 version 4.0, 2007-06-01 tda523x functional description flexible and configurable frame synchronisation and message id scanning feature, supported by special function registers. receiv ed data of an accepted message is stored in a fifo and can be read out via the spi interface. a master control unit (mcu), implemented as a finite state machine and a polling timer unit control all actions of the device and can be configured via special function registers (sfrs). various self-polling mo des can be set up to achieve a maximum of autonomous receiver operation. the transparent mode unit defines the functionality of the pins clkout/rxd, nint/nstr and rx-run/rxd. a fully integrated multi-channel plldrives the lo ports of the image-reject-mixer. within a selected operational frequency band multiple channels are accessible by utilizing the same reference crystal-frequency. the refe rence clock of the pll and the digital section are provided by a pierce type crystal oscillator that offers on chip fine-tuning to trim out crystal tolerances. a programmable clock g eneration unit divides the system clock by a programmable ratio and drives the clkout/rxd pin. on chip voltage regulators generate the required internal supply voltages and allow the ic to be operated at supply voltages between 3 v to 3.6 v and 4.5 v to 5.5 v. the digital supply of the chip is monitored by a brow n out detector and is equipped with a built-in reset generator. every device contains a unique serial number, which can be read out via the spi interface. special function register and control bit symbols figure 9 sfr symbolism the register names, addresses, and control bi ts for each function are listed in a table at the end of this section. functional descript ions of all registers are provided in chapter 3 register descriptions . symbolizes unique sfr or sfr-control bit(s). control control symbolizes sfr or sfr-control bit(s) with dual- configuration capability. the name (if sfr) starts with a or b, depending on the selected configuration. tda523x functional description data sheet 18 version 4.0, 2007-06-01 2.4.1 power supply the chip may be operated within a 5 v or a 3.3 v environment. figure 10 power supply for operation within a 5 v environment, the chip is supplied via the pin vdd5v. in this configuration a 5 to 3.3 v voltage regulator supplies the analog/rf-section (only active in run modes) and a second 5 to 3.3 v voltag e regulator supplies the digital i/o-pads. when operating within a 3.3 v environment, the pins vdd5v, vdda and vddd must be supplied. the 5 to 3.3 v voltage regulators are inactive in this configuration. the internal digital core is suppli ed by an additional 3.3 to 1.5 v regulator. the regulators for the digital section are controlled by the signal at the p_on (power on). a low signal at p_on disables all regu lators and sets the ic into power down mode. a low to high transition at p_on enables the regulators for the digital section and initiates a power on reset. the regulator for the analog section is controlled by the master control unit and is active only when the rf -section is active (rx-run = high). p_on can be used to initiate a reset. the required negative pulse time t p_on is specified in chapter 4 specifications . vdd5v power-up brownout detector reset- circuit rf section analog section vddd vdda gnda gndrf digital-i/o vddd1v5 digital-core gndd p_on internal reset voltage regulator 3.3 1.5 v enable out in voltage regulator 5 3.3 v out in enable voltage regulator 5 3.3 v enable out in enable rx-run data sheet 19 version 4.0, 2007-06-01 tda523x functional description to provide data integrity within the digital uni ts, a brown out detector monitors the digital supply and a detected voltage drop of vddd below approximately 2.45 v initiates a reset. figure 11 illustrates a typical power supply application for a 3.3 v and a 5 v environment. figure 11 supply modes 2.4.1.1 supply current in sleep mode, the master control unit swit ches the crystal oscillator into low power mode (all internal load capacitors are di sconnected) to minimize power consumption. whenever the chip leaves the sleep mode (t 1 ), the crystal oscillator resumes operation in high precision mode and requires t coscsettle to settle at the trimmed frequency. at t 2 the analog signal path (rf and if section) and the rf-pll are activated. at t 3 the chip is ready to receive data. the chip requires t rxstartup from leaving sleep mode and until the receiver is ready to receive data. a transient supply current peak may occur at t 1 , depending on the selected trimming capacitance. the average supply current drawn between during t rfstartupdelay is i vddsleep, high . vdda gnda gndrf vddd vdd5v vddd1v5 gndd supply-application in 3,3v environment TDA5230 3.3v 10 ? 10 ? 100n 100n 100n vdda gnda gndrf vddd vdd5v vddd1v5 gndd TDA5230 5v 100n 100n 100n *) 1 *) 22 ? *) when operating in a 5v environment, the voltage-drop across the voltage regulators 5 ? 3.3v has to be limited, to keep the regulators in a safe operating range. resistive or capacitive loads (in excess to the scheme shown above) on pins vdda and vddd are not recommended. supply-application in 5v environment tda523x functional description data sheet 20 version 4.0, 2007-06-01 figure 12 supply current ramp up/down if the if buffer amplifier or the clock- generation feature (clkout/rxd pin active) is activated, the respective currents must be added. i vddsleep,low i vddsleep,high i vddrun t coscsettle t supply current run mode*) sleep mode t on pin rx-run/rxd t 3 t 2 t 1 *)run mode covers the global chip states: run mode slave / receiver active in self polling mode / run mode self polling t rxstartup t rfstartdelay data sheet 21 version 4.0, 2007-06-01 tda523x functional description 2.4.2 chip reset power down and power on are controlled by the p_on pin. a low at this pin keeps the ic in power down mode. all voltage regulator s and the internal biasing are switched off. a high at the p_on pin activates the appropriate voltage regulators and the internal biasing of the chip. a power up reset is generated at the same time. . figure 13 reset behavior internal reset supply-voltage falls below reset- / brownout-threshold reset- / brownout- threshold (typ. 2.45v) 3v supply-voltage at pin vddd t reset t functional- threshold (typ. 2v) reset- / brownout- threshold (typ. 2.45v) 3v voltage at pin nint/nstr functional- threshold (typ. 2v) a ?low? is generated at pin nint/nstr supply-voltage falls below functional-threshold level on pin nint/nstr is undefined supply-voltage rises above functional-threshold a ?low? is generated at pin nint/nstr c reads interrupt- status-register a ?low? is generated at pin nint/nstr a ?high? is generated at pin nint/nstr t tda523x functional description data sheet 22 version 4.0, 2007-06-01 a second source that can trigger a reset is a brown out event. whenever the integrated brown out detector measures a voltage drop below the brown-out threshold on the digital supply, the integrity of the stored da ta and configuration can no longer be guaranteed; thus, a reset is generated. while the supply voltage stays between the brown out and the functional threshold of the chip, the nint /nstr pin is forced to low. when the supply voltage drops below the functional threshold, t he levels of all digi tal output pins (e.g. nint/nstr) are undefined. when the supply voltage rises above the brown out threshold, the ic generates a high pulse at nint/nstr and remains in the reset state for the duration of t reset . when the ic leaves the reset state, the interrupt status register (is) is set to ff hex and the nint/nstr pin is forced to low. now, the ic starts operation in the sleep mode, ready to receive commands via the spi interface. the nint/nstr pin will go high, when the interrupt status register is read the first time. data sheet 23 version 4.0, 2007-06-01 tda523x functional description 2.4.3 system clock 2.4.3.1 crystal oscillator the reference clock for the digital and the rf section is generated by a pierce-type crystal oscillator. adjustable internal load capacitors are provided that allow the tolerances of the crystal, external load capacitors and the ic itself to be trimmed out. these capacitors are built of binary weighted c-banks and are connected in parallel to the external load capacitors. the internal capacitors are controlled by the crystal oscillator calibration data register (xta lcal). an automatic amplitude regulation allows the oscillator to operate with mi nimal current consumption. all trim capacitors are disconnected in sleep mode (this minimizes current consumption). whenever the tda523x switches from sleep mode to run modes, the master control unit reads out the xtalcal0 and xtalcal1 registers and connects the selected trim capacitors to the crystal. a modification of xtalcal0 or xtalcal1 registers in run modes does not immediate ly alter the setting of the activated trim capacitors unless the sfr control bit xtaltren, is set. figure 14 crystal oscillator crystal selection: the recommended crystal type and manufacturer is listed in the bill of materials in the evaluation board section of this data sheet. this crystal has been released by infineon as well by the crystal manufacturer for optimal operation with tda523x. if additional crystal types are released, this information will be published on the related tda523x product page at www.infineon.com. xtal2 xtal1 oscillator-core (dgnd) binary weighted capacitor-array binary weighted capacitor-array f sys xtalcal0 setting controlled by mcu xtaltren xtalcal1 9 mux tda523x functional description data sheet 24 version 4.0, 2007-06-01 the crystal frequency is calculated: values for a depend on the frequency band: 302...320mhz...a=3 (tda5231), 433...450mhz...a=2, 865...870mhz...a=1 (TDA5230) the crystal frequency is automatically calculated by the iaf tda523x configuration tool. recommended trimming procedure ? set the tda523x to sleep mode ? set the registers xtcal0 and xtcal1 to the expected nominal values ? set the tda523x to slave mode run ? set the register bit xtaltren in register cmc1 ? wait for 0.5ms minimum ? trim the oscillator by increasing an d decreasing the values of xtalcal0/1 ? never change the trim capacitor size by more than 1 pf! ? when the oscillator is trimmed, reset the xaltren bit ? set the tda523x to sleep mode ? add the settings of xtcal0/1 to the configur ation. it must be set after every power up or brown out! using the high precision mode as discussed earlier, the tda523x allows to the crystal oscillator to be trimmed by the use of internal trim c apacitors. it is also possible to use the trim functionality to compensate temperature drift of crystals. during run mode (always when the receiver is active) the capacitors are automatically connected and the oscillator is us ed in the high precision mode. on entering sleep mode, the capacitors are automatically disconnected to save power. if the high precision mode is also required for sleep mode, the automatic disconnection of trim capacitors can be avoided by setting xaltren to 1 (enable xtal trim). setting of xaltren has to be changed only in run-mode! for TDA5230 (lo side lo injection) f sys =a*(f rf -10.7mhz)/64 for tda5231 (hi side lo injection f sys =a*(f rf +10.7mhz)/64 data sheet 25 version 4.0, 2007-06-01 tda523x functional description cmc1 : chip mode control register 1 xtalcal0 : trim xtal frequency, coarse xtalcal1 : trim xtal frequency, fine 2.4.3.2 external clock generation unit the chip provides a programmable clock signal at the clkout/rxd pin that is derived from the internal system clock. to save pow er, this unit can be disabled by the sfr clkouten bit. the clock generation unit di vides the internal clock by an adjustable factor down to the desired clkout frequency. the 20-bit wide division factor, stored in the clockout0, clockout1 and clockout2 registers, allows a clkout- frequency to be generated down to approximately 10 hz. the 1:2 divider following the 20-bit counter creates the final clkout signal with 50% duty cycle. the resulting clkout frequency can be calculated by: addr: 0x03 reset value: 0x00 bit r/w description 4 w xtaltren: xtal trim enable 0: trimming is disabled 1: trimming is enabled addr: 0x61 reset value: 0x10 bit r/w description 4 w xtal_sw_coarse_4: connect trim capacitor: 16 pf 3 w xtal_sw_coarse_3: connect trim capacitor: 8 pf 2 w xtal_sw_coarse_2: connect trim capacitor: 4 pf 1 w xtal_sw_coarse_1: connect trim capacitor: 2 pf 0 w xtal_sw_coarse_0: connect trim capacitor: 1 pf addr: 0x62 reset value: 0x00 bit r/w description 3 w xtal_sw_fine_3: connect trim capacitor: 500 ff 2 w xtal_sw_fine_2: connect trim capacitor: 250 ff 1 w xtal_sw_fine_1: connect trim capacitor: 125 ff 0 w xtal_sw_fine_0: connect trim capacitor: 62.5 ff tda523x functional description data sheet 26 version 4.0, 2007-06-01 figure 15 external clock generation unit the maximum clkout frequency is limited by the driver capability of the clkout/rxd pin and depends on the external load co nnected to this pin. please be aware that large loads and/or high clock frequencies at this pin may interfere with the receiver and reduce performance. after reset the clkout/rxd pin is activated and the division factor initialized to 7 (equals 1 mhz for f sys of 14 mhz). a higher clock output frequency than 1 mhz is not recommended. cmc0 : chip mode control register 0 addr: 0x02 reset value: 0x40 bit r/w description 6 w clkouten: clkout enable 0: disable 1: enable programmable clock output f clkout f sys 2 division factor ? -------------------------------------------- = 20 bit counter divide by 2 f clkout 2 x f clkout f sys clkout0 clkout1 clkout2 clkouten enable enable data sheet 27 version 4.0, 2007-06-01 tda523x functional description clkout0 : clock divider register 0 clkout1 : clock divider register 1 clkout2 : clock divider register 2 addr: 0x13 reset value: 0x07 bit r/w description 7:0 w clkout0: clock out divider: bit 7...bit 0 (lsb) min: 0 00 01h = clock divided by 2 max: 0 00 00h = clock divided by (2^20)*2 addr: 0x14 reset value: 0x00 bit r/w description 7:0 w clkout1: clock out divider: bit 15...bit 8 min: 0 00 01h = clock divided by 2 max: 0 00 00h = clock divided by (2^20)*2 addr: 0x15 reset value: 0x00 bit r/w description 3:0 w clkout2: clock out divider: bit 19 (msb)...bit 16 min: 0 00 01h = clock divided by 2 max: 0 00 00h = clock divided by (2^20)*2 tda523x functional description data sheet 28 version 4.0, 2007-06-01 2.4.4 rf-pll synthesizer the phase locked loop rf sy nthesizer consists of a vco, programmable divider chains, a phase detector, a charge pump and a loop filter. the on chip vco includes a spiral-inductor and varactors. the loop filter is also fully integrated on chip. the vco signal is fed to both the programmable synthesizer divider chain and to a programmable rf divider. this rf divider allows selection between three operational frequency bands and drives a fixed divider by four, which generates the quadrature lo signals for the image reject mixer. figure 16 rf pll selection of a distinct operational frequency band is done via the sfr control bits rfplla. the overall division factor of the pll-loop is determined by the content of the sfr control bits rfpllrx and rfpllsx, which control a programmable tri-modulus divider and a reference frequency divider. depending on the configuration of the multi- channel feature, the effective source of th e control bits rfpllrx can either be rfpllr1, rfpllr2 or rfpllr3 and the sour ce of the control bits rfpllsx can be either rfplls1, rfplls2 or rfplls3. rfplls3 rfplls2 divide by a a = 3 for 302..320 mhz a = 2 for 433..450 mhz a = 1 for 865..870 mhz rf-vco loop- filter phase-detector charge-pump divide by r r = 1 ? 8 divide by n = 256 * r + s s = -1, 0, +1 3 f sys 2 rfplla rfplls1 2 3 r = 1 ... 8 i divide by 4 0 90 q lo-signals rfpllr3 rfpllr2 rfpllr1 data sheet 29 version 4.0, 2007-06-01 tda523x functional description based on the tri-modulus divider concept, up to 17 distinct channels 1) are accessible within the selected operational frequency band by utilizing the same reference crystal frequency. the selected lo-frequency is described by the formula: values for a depend on the frequency band: 302...320mhz...a=3 (tda5231), 433...450mhz...a=2, 865...870mhz...a=1 (TDA5230) values for s are +1, 0, -1 values for r are 1,2,3,4,5,6,7,8 example: a system for 433.92 mhz, having an f sys =13.225625mhz has follo wing available sub- channels: 1) channels with receive frequencies close to the harmonics of the reference crystal frequency should not be used in applications. sr f rf [mhz] 1 1 435.573 1 2 434.747 1 3 434.471 1 4 434.333 1 5 434.251 1 6 434.196 1 7 434.156 1 8 434.127 0 2 433.92 -1 8 433.713 -1 7 433.684 -1 6 433.644 -1 5 433.589 -1 4 433.507 -1 3 433.369 f lo f sys r ----------- 256 r s + ? () 1 4a ? ----------- ?? f sys 4a ? ----------- 256 s r --- - + ?? ?? ? == tda523x functional description data sheet 30 version 4.0, 2007-06-01 calculation of sub-channels is automatically performed by the iaf tda523x configuration tool. when defining a multichannel system, the correct selection of channel spacing is extremely important. a general rule is not possible, but following must be considered: ? if an additional saw filter is used, all channels including thei r tolerances have to be inside the saw filter bandwidth. ? the distance between channels has to be high enough, that no overlapping can happen. strong input signals may still appear as recognizable input signal in the neighboring channel because of the limited s uppression of if filters. example: a typical 280khz if filter has at 10.3 mhz ( 10.7 mhz-0.4 mhz ) only 30 db suppression. a -70 dbm input signal appears like a -100 dbm signal, which is inside the receiver sensitivity. in critical cases the use of tw o if filters must be considered. see also chapter 2.4.8 functionality of the if path -1 2 433.093 -1 1 432.267 for lo side lo injection mode operation: f rf = f lo + 10.7 mhz for hi side lo injection mode operation: f rf = f lo - 10.7 mhz sr f rf [mhz] data sheet 31 version 4.0, 2007-06-01 tda523x functional description d ual: arfpll1 and brfpll1 : conf.a rf pll setting, channel 1 (slave mode & self polling mode) addr: 0x22 and 0x43 reset value: 0x29 bit r/w description 6:5 w rfplla: band selection 00 : select 315 mhz band, a=3 01 : select 434 mhz band, a=2 10 : select 868 mhz band, a=1 4:2 w rfpllr1: channel 1, pll divider factor r 1) 000 : r = 8 001 : r = 1 010 : r = 2 011 : r = 3 100 : r = 4 101 : r = 5 110 : r = 6 111 : r = 7 1) channels with receive frequencies close to the harmoni cs of the reference crystal frequency should not be used in applications. 1:0 w rfplls1: channel 1, pll divider factor s 1) 00 : s = 1 01 : s = 0 10 : s = -1 11 : s = 0 tda523x functional description data sheet 32 version 4.0, 2007-06-01 dual: arfpll2 and brfpll2 : conf. arf pll setting, channel 2 (self polling mode) dual: arfpll3 and brfpll3 : conf.a rf pll setting, channel 3 (self polling mode) addr: 0x23 and 0x44 reset value: 0x08 bit r/w description 4:2 w rfpllr2: channel 2, pll divider factor r 1) 000 : r = 8 001 : r = 1 010 : r = 2 011 : r = 3 100 : r = 4 101 : r = 5 110 : r = 6 111 : r = 7 1:0 w rfplls2: channel 2, pll divider factor s 1) 00 : s = 1 01 : s = 0 10 : s = -1 11 : s = 0 addr: 0x24 and 0x45 reset value: 0x0a bit r/w description 4:2 w rfpllr3: channel 3, pll divider factor r 1) 000 : r = 8 001 : r = 1 010 : r = 2 011 : r = 3 100 : r = 4 101 : r = 5 110 : r = 6 111 : r = 7 1) channels with receive frequencies close to the harmoni cs of the reference crystal frequency should not be used in applications. 1:0 w rfplls3: channel 3, pll divider factor s 1) 00 : s = 1 01 : s = 0 10 : s = -1 11 : s = 0 data sheet 33 version 4.0, 2007-06-01 tda523x functional description 2.4.5 master control unit 2.4.5.1 overview the master control unit controls the operati on modes, the global states, and is generally responsible for automating data reception, veri fication, identificati on, extraction, and storage into the fifo. the data without runin and tsi are read via spi from the fifo by the external microcontroller. the following operational modes and the behavio r of the master control unit are fully automatic and influenced only by sfr settings and by incoming rf streams. the tda523x has two major operational m odes. modes are switched by the sfr bit msel0 in slave mode the device is controlled via spi by the ex ternal microcontroller. this mode supports: ? run mode slave, where the rece iver is continuously active ? sleep mode, where the receiver is switched off for power saving. this mode can also be used to change register settings ? hold mode, allows to register settings to be changed. the change to hold mode and back is faster than changing to sleep mode. switching between configurations and channels, as well as in between run and sleep mode must be initiated by the microcontroller. in self polling mode tda523x autonomously polls for incoming rf signals. the receiver switches automatically between th e two configurations (configuration a and configuration b) and up to 3 channels per co nfiguration (further information is located in chapter 2.4.6 polling timer unit ). between scans, the receiver is automatically switched off to save power. if an incoming signal fulfills the selected wake-up criteria, matches the tsi pattern, and passes the optional message id screening, the payload is loaded into the fifo, and, if not masked, an interrupt is generated. then, the payload data can be read via spi. tda523x functional description data sheet 34 version 4.0, 2007-06-01 cmc0 : chip mode control register 0 figure 17 global state diagram addr: 0x02 reset value: 0x40 bit r/w description 1 w slrxen: slave receiver enable this bit is used only in operating modes run mode slave, sleep mode 0: receiver is in sleep mode 1: receiver is in run mode slave 0 w msel: operating mode 0: run mode slave, sleep mode 1: self polling mode sleep mode chip is idle init initialize rx-part run mode slave chip is permanently active bit:slrxen == 1 bit:msel == 0 init self polling mode bit:slrxen == 0 bit:msel == 0 bit:slrxen == 1 bit:msel == 0 bit:slrxen == 0 bit:msel == 0 bit:slrxen == x bit:msel == 1 bit:slrxen == x bit:msel == 0 bit:slrxen == x bit:msel == 1 chip is periodically active and searching for wu criteria run mode self polling bit:slrxen == x bit:msel == 0 totim timeout == x bit:slrxen == x bit:msel == 1 wuc found == 0 bit:slrxen == 1 bit:msel == 0 bit:slrxen == x bit:msel == 1 bit:slrxen == x bit:msel == 1 wuc found == 1 chip is permanently active initialize rx-part reset bit:slrxen == x bit:msel == 1 totim timeout == 0 bit:slrxen == x bit:msel == 1 totim timeout == 1 bit:slrxen == x bit:msel == 0 bit:slrxen == x bit:msel == 1 bit:slrxen == 0 bit:msel == 0 data sheet 35 version 4.0, 2007-06-01 tda523x functional description 2.4.5.2 run mode slave in run mode slave, the receiver is able to continuously scan for incoming data streams. detection and validation of a wake up pattern are not done, but correct runin and tsi are required. recognition of tsi and validation of the optional mid (message identification) are done automatically. the data payload is extracted from the data stream, and moved to the fifo. the various recognition steps are communicated by interrupts. interrupts are generated at framestart (when a valid tsi has been detected), when a valid mid has been found, and at eom (end of message). run mode slave is entered by setting sfr cm c0 bits msel to 0 and slrxen to 1. configurations are switched via sfr bit rmsl in the cmc0 register. the channel in use is always defined in the arfppll and brfpll sfrs, depending on the selected configuration. the configuration may be changed only in sleep mode or in hold mode. this is necessary to restart the state machine with defi ned settings at a defined state. otherwise the state machine may hang up. re-configuration s using hold mode is faster, because there is no start up sequence. cmc0 : chip mode control register 0 figure 18 illustrates the internal behavior of the fsm (finite state machine) in run mode slave. addr: 0x02 reset value: 0x40 bit r/w description 3 w rmsl: run mode slave configuration this bit is relevant only in slave mode, to select the used configuration 0: config a 1: config b tda523x functional description data sheet 36 version 4.0, 2007-06-01 figure 18 run mode slave check mid setup check the mid setup register wait wait till symbol synchronisation is found wait init mid scanning unit initialize the mid scanning unit mid screening enable == 1 wait till frame start is found symbol sync == 0 frame sync == 0 frame sync == 1 symbol sync == 1 wait store rx data into fifo wait for scan finish mid scanning finished == 0 mid scanning finished == 1 checking id scanning result store rx data into fifo analyze the scanning result symbol sync=0 mid found == 0 eom check store rx data into fifo check for eom mid screening enable == 0 eom found == 1 mid found=1 generating a frame start interrupt if not masked generating a mid found interrupt if not masked generating a eom interrupt if not masked sequencer finished == 0 wait wait till startup sequencer has finished sequencer finished == 1 eom found == 0 fifo locked wait till fifo read out fifolk == 1 fifolk == 0 fifolk == 1 init fifo init fifo = init fifo@fsync init init fifo=init fifo@cyc. init receiver 1 2 4 3 5 6 7 8 9 10 11 hold ready for reconfiguration 12 hold == 1 hold == 0 fifolk == 0 data sheet 37 version 4.0, 2007-06-01 tda523x functional description notes to state diagram run mode slave: 1.) wait: waiting until start up sequencer has completed the power up procedure. 2.) init: the receiver will be initialized and the fifo will be initialized when the sfr control bit initfifo is set. read out the modulation type configuration (ask or fsk), which is defined in the sfr control bits amt/bmt and set the device to the configured mode. set the channel to the corr ect value, which is defined in the arfpll1/brfpll1 register. 3.) fifo locked : when the signal fifolk is set, the chip enters this state and remains there until the signal fifolk is reset. in this state, no further data reception is possible and therefore, no sync or fsync will be generated, even if a data-packet is present in the received data stream. (more information on the fifo behavior can be found in chapter chapter 2.4.15 data fifo ). 4.) wait: wait until symbol synchronization is complete. a loss of symbol synchronization always leads into this state, whatever the current state is. this state is left only, if symbol-synchronization ca n be established on the received data stream. (more information on the synchronization behavior can be found in chapter 2.4.13 frame synchronization ). 5. wait: wait until a start of a data packet (f rame) is detected. all bits received from fsync until the detection of eom will be transferred to the fifo. 6.) init fifo: the fifo will be initialized, if the sfr control bit fsinitfifo is set 7.) check mid setup : check the configuration of the message id unit. depending on the sfr control bit midsen a message id scanning is started or not. if no message id scanning is selected, the next state is the state eom check . otherwise the message id scanning unit is activated to search for a valid message id. 8.) init mid scanning unit: initialize the message id scanning unit. 9.) wait: wait until the message id scanning unit has finished the search for a valid message id. all incoming data is stored in the fifo. 10.) checking id scanning result: the result of a search for a message id is checked. if no valid messageid was found, a search for a new frame is started. be aware that all received bits after fsync were stored in the fifo, even if no message id was found. after a successful search for a message id , the next state will be eom check . 11.) eom check: incoming data bits are tr ansferred to the fifo until an eom is detected. the criteria for eom are defined in the aeomc/beomc register. if the sfr control bit fifolk is set, the signal fifolk will be asserted at eom . depending on the state of fifolk , the next chip state will be fifo locked or wait for symbol synchronization . tda523x functional description data sheet 38 version 4.0, 2007-06-01 2.4.5.3 hold mode this state (item 12 in the state diagram figure 17 ) is used for fast reconfiguration of the chip in slave-mode. this state can be reached after the startup sequencer and initialization of the chip has been finished from any state from 3 to 11. to reconfigure the chip the sfr control bit hold must be s et. after reconfiguration in this state the sfr control bit hold has to be cleared again. a fter leaving the hold state, the init state is entered and the receiver loads the new settings. be aware that the time between changing the configuration and reinitialization of the chip must be at least 40 s. take note that one spi command for clearing the sfr control bit needs 24 bits or 20 s at the highest spi data rate. the remaining 20 s must be guaranteed by the application. figure 19 hold state behavior hold mode should only be entered from run mode slave. configuration changes in self polling mode should be done by switching to sleep mode and returning to self polling mode after reconfiguration cmc1 : chip mode control register 1 . 2.4.5.4 sleep mode the sleep mode is a power save mode. the complete rf part is switched off and the oscillator is in low precision mode. like in hold mode, the chip can be reconfigured. when switching from sleep to run mode slave, the state machine starts with the internal start up sequence. addr: 0x03 reset value: 0x00 bit r/w description 6 w hold: holds the chip in the config state (only in run mode slave) 0: normal operation 1: jump into the config state hold eom-check fsm state address cmc1 0x03 instruction write 0x02 data hold=1 0x40 spi command instruction write 0x02 address rfpll1 0x22 data 0x55 address cmc1 0x03 instruction write 0x02 data hold=0 0x00 hold init wait till ssync 20us @ 1.2mhz 40us data sheet 39 version 4.0, 2007-06-01 tda523x functional description cmc0 : chip mode control register 0 2.4.5.5 self polling mode in self polling mode tda523x autonomously polls for incoming rf wake up data streams. there is no processing load on the host microcontroller. when a wake up criterion has been found, the mode is changed to run mode self polling for automatic verification of tsi, mids and transfer of data to the fifo. self polling mode is entered by setting the register bit msel to 1. configuration changes are allowed only by switching to sleep mode, and returning after reconfiguration. the polling timer unit controls the timing for scanning (on time) and sleeping (off time). two independent configuration sets (a and b) are automatically switched, thus enabling scanning from different transmit source s. additionally, within each configuration as many as 3 different fr equency channels may be scanned to allow multi-channel applications. see also chapter 2.4.6 polling timer unit . the wake up generation unit identifies whether an incoming data pattern matches with the configurable wake up criterion. after receiving the wake up pattern, modulation can be switched. see also chapter 2.4.5.6 automatic modulation switching and chapter 2.4.12 wake up generation unit . addr: 0x02 reset value: 0x40 bit r/w description 1 w slrxen: slave receiver enable this bit is only used in operat ing mode run mode slave / sleep mode 0: receiver is in sleep mode 1: receiver is in run mode slave 0 w msel: operating mode 0: run mode slave / sleep mode 1: self polling mode tda523x functional description data sheet 40 version 4.0, 2007-06-01 cmc0 : chip mode control register 0 rfpllac : rf pll actual channel register dual: amt and bmt : conf.a modulation type register the following state diagrams and explanations help to illustrate the behavior during self polling mode. first, there is a wake up search for a wake up pattern according configuration a on up to three different channels. then, there is an optional search for a wake up pattern according configurati on b, again including up to 3 channels. in applications using only a single configuration, setti ngs are always taken from configuration a addr: 0x02 reset value: 0x40 bit r/w description 2 w dce: dual configuration enable this bit is relevant only in self polling mode. it defines whether both configurations are used. 0: only config a is used 1: first config a is use d; then config b is used addr: 0x06 reset value: 0x00 bit r/w description 1:0 r rfpllacs: actual channel this register is set after a wake up found in the self polling mode 00b: no channel was actually found 01b: channel 1 according to rfpll1 setting was found 10b: channel 2 according to rfpll2 setting was found 11b: channel 3 according to rfpll3 setting was found addr: 0x21 and 0x42 reset value: 0x04 bit r/w description 3:2 w noc: number of channels only used in the self polling mode to define how many channels have to be scanned. in the slave mode there is only 1 channel used, whatever here is configured. min: 01b = 1 channel max: 11b= 3 channels data sheet 41 version 4.0, 2007-06-01 tda523x functional description figure 20 wake up search with configuration a idle chip is idle sequencer finished == 0 wait wait till startup sequencer has finished sequencer finished == 1 wu search cfg a ffts search for a configurated wake up criteria fast fall back init with cfg a initialize rx-part configuration a wu search finished == 0 modulation switching cfg a modulation selection depending on register setting rx-run=0 load s1r1 channel load s2r2 channel load s3r3 channel loop counter == 10 compare compare loop counter against number of channels wu search finished == 1 wu found == 0 increment loop counter incrementation of the loop counter loop counter == 11 store channel store the current channel configuration into actual channel register loop counter <> anoc init loop counter loop counter is initialized initialize rx-part multi channel a initialize rx-part multi channel a initialize rx-part multi channel a counter equal anoc == 1 dual config enable == 1 rx-run == 0 rx-run == 1 to init loop counter of config b from compare o f config b loop counter == anoc dual config enable == 0 wu search finished == 1 wu found == 1 generating wu cfg a interrupt if not masked wu search with configuration a from run mode self polling wu search cfg a coot search for a configurated wake up criteria const on of f const on time on time elapsed == 0 wu found == 0 on time elapsed == x wu found == 1 on time elapsed == 1 wu found == 0 permanent wu search mode enable == 1 permanent wu search mode enable == 0 permanent wu search mode enable == 1 permanent wu search mode enable == 0 fast fall back to sleep 1 2 3 4 5 6 11 11 7 7 9 10 8 run mode self polling chip is permanently active 12 tda523x functional description data sheet 42 version 4.0, 2007-06-01 figure 21 wake up search with configuration b init with cfg b initialize rx-part configurat ion b modulation switching cfg b modulation selection depending on register setting init loop counter loop count er is initialized run mode self polling chip is permanently active from compare of config a to init loop counter of config a wu search with configuration b wu search cfg b ffts search for a configurated wake up criteria fast fall back wu search finished == 0 load s1r1 channel load s2r2 channel load s3r3 channel loop counter == 10 compare compare loop counter a gainst number of channels wu search finished == 1 wu found == 0 increment loop counter incrementation of the loop counter loop counter == 11 store channel store the current channel configuration i nto actual channel register loop counter <> bnoc initialize rx-part multi channel b initialize rx-part multi channel b initialize rx-part multi channel b loop counter == bnoc dual config enable == 0 wu search finished == 1 wu found == 1 generating wu cfg b interrupt if not masked wu search cfg b coot search for a configurated wake up criteria const on of f on time elapsed == 0 wu found == 0 on time elapsed == x wu found == 1 on time elapsed == 1 wu found == 0 const on time permanent wu search mode enable == 1 permanent wu search mode enable == 0 fast fall back to sleep 3 4 5 6 11 7 7 9 10 8 12 11 data sheet 43 version 4.0, 2007-06-01 tda523x functional description notes to self polling modes state diagrams 1.) idle: the state idle is left, when the signal rx-run , which enables the receiver unit, is set by the polling timer unit. t 2. wait: wait until the start up sequencer has fi nished powering up the receiver unit. 3.) init loop counter: the loop counter is reset to c hannel 1 of configuration a. the state of the loop counter determines the selected channel. 4. modulation switching cfg a: the receiver unit is set to the modulation type defined in the sfr control bit mt. 5.) init with cfg a : the receiver unit is initia lized with the settings given in configuration a. 6.) load s1r1 channel: the receive channel is set according to the pll settings given in register arfpll1 and waits for about 40s (9*64/f sys ). 7. wu search cfg a: as determined by the selected self polling mode scheme defined by the sfr control bits spms el and permwusen, the corresponding wu search scheme is activated. if the search for the fulfillment of a wake up criterion complicated successfully, the current receive channel is stored by entering the state store channel . otherwise, the next state is compare . 8.) store channel: in this state, the currently sele cted receive channel (e.g. s1/r1) is stored as the actual c hannel in the register rfpllac. the chip resumes operation in run mode self polling afterwards. 9.) compare: if the loop counter equals the num ber of channels selected by the sfr control bit anoc, the next state of the chip will be the idle state , unless dual configuration is enabled by the sfr control bit dce. in this case, the next state will be init loop counter in figure 21 . in all other cases, the chip resumes operation in the increment loop counter state. 10.) increment loop counter: in this state, the loop counter is incremented. 11.) load s2r2/s3r3 channel: the receive channel is set to the pll settings given by the register arfpll2 and arfpll3 respectively and waits for about 40s(9*64/fsys). 2.4.5.6 automatic modulation switching in self polling mode , the chip is able to automatically change the type of modulation once a wake up criterion has been satisfied in a received data stream. the type of modulation used in the different operational modes is selected by the sfr control bits mt, the types are shown in the following register table. tda523x functional description data sheet 44 version 4.0, 2007-06-01 dual: amt and bmt : conf.a modulation type register 2.4.5.7 multi-channel in self polling mode previously mentioned, in self polling mode tda523x allows up to three channels per configuration to be scanned. channels are defined in registers arfpll1-3 and brfpll1-3. the channel number at which a wake up has been found is available in register rfpllacs. see also chapter 2.4.4 rf-pll synthesizer . dual: amt and bmt : conf.a modulation type register addr: 0x21 and 0x42 reset value: 0x04 bit r/w description 3:2 w noc: number of channels used only in the self polling mode to define how many channels must be scanned. in the slave mode only one channel is used, regardless of the configuration. min: 01b = 1 channel max: 11b= 3 channels 1:0 w mt: modulation type addr: 0x21 and 0x42 reset value: 0x04 bit r/w description 3:2 w noc: number of channels used only in the self polling mode to define how many channels must be scanned. in the slave mode, only one channel is scanned, regardless of the configuration. min: 01b = 1 channel max: 11b= 3 channels run mode slave self polling mode run mode self polling 00b ask ask ask 01b fsk fsk fsk 10b ask fsk ask 11b fsk ask fsk data sheet 45 version 4.0, 2007-06-01 tda523x functional description dual: arfpll1 and brfpll1 : conf.a rf pll setting, channel 1 (slave mode & self polling mode) dual: arfpll2 and brfpll2 : conf. arf pll setting, channel 2 (self polling mode) dual: arfpll3 and brfpll3 : conf.a rf pll setting, channel 3 (self polling mode) rfpllac : rf pll actual channel register addr: 0x22 and 0x43 reset value: 0x29 bit r/w description 4:2 w rfpllr1: channel 1, pll divider factor r 1) 1) 1:0 w rfplls1: channel 1, pll divider factor s 1) addr: 0x23 and 0x44 reset value: 0x08 bit r/w description 4:2 w rfpllr2: channel 2, pll divider factor r 1) 1:0 w rfplls2: channel 2, pll divider factor s 1) addr: 0x24 and 0x45 reset value: 0x0a bit r/w description 4:2 w rfpllr3: channel 3, pll divider factor r 1) 1) channels with receive frequencies close to harmonics of the reference crystal-frequency should not be used in applications. 1:0 w rfplls3: channel 3, pll divider factor s 1) addr: 0x06 reset value: 0x00 bit r/w description 1:0 r rfpllacs: actual channel this register is set after a wake up found in the self polling mode 00b: no channel was actually found 01b: channel 1 wake up according to rfpll1 setting was found 10b: channel 2 wake up according to rfpll2 setting was found 11b: channel 3 wake up according to rfpll3 setting was found tda523x functional description data sheet 46 version 4.0, 2007-06-01 2.4.5.8 run mode self polling the chip enters run mode self polling after a successful fulfillment of a wake up criterion in self polling mode. the following steps are performed automatically, depending on register settings ? modulation switching (see chapter 2.4.5.6 automatic modulation switching ) ? wait for valid tsi (see chapter 2.4.13 frame synchronization ) ? initialize fifo (see chapter 2.4.15 data fifo ) and write data to fifo ? scan for mid?s (see chapter 2.4.14 message-id scanning ) depending on the interrupt masking, the host micro controller is alerted when ? a data frame has started, ? an mid has been found, (if enabled) or ? eom (end of message) has been detected. see also chapter 2.4.17 interrupt generation unit run mode self polling is left, when synchronization is lost and the time out timer (totim) has elapsed, and when the mode is switched to sleep or run mode slave by the host microcontroller. as long as the chip is in run mode self polling, incoming data frames, even without additional wake up patterns, can be received and stored. the data fifo can be either initialized and cleared at ? cycle start, that means whenever run mode self polling is entered or ? frame start, when a tsi has been successfully identified. further information about the data fifo is found in the chapter 2.4.15 data fifo . data sheet 47 version 4.0, 2007-06-01 tda523x functional description cmc0 : chip mode control register 0 cmc1 : chip mode control register 1 addr: 0x02 reset value: 0x40 bit r/w description 7 w initfifo: init fifo at cycle start initialization of the fifo can be configured in both slave mode and self polling mode. in slave mode, this occurs at the beginning of the slave run mode. in self polling mode, initialization is done after a wake up is found (switching from self polling mode to run mode self polling). 0: no init 1: init fifo 5 w totimen: totim timer enable time out timer is used to return from run mode self polling to self polling mode whenever there is no sync for a specific time. 0: disable 1: enable totim timer 4 w fifolk: lock data fifo at eom 0: fifo lock is disabled 1: fifo lock is enabled at eom (see also chapter 2.4.15 data fifo ) addr: 0x03 reset value: 0x00 bit r/w description 3 w fsinitfifo: init fifo at frame start 0: no init 1: init tda523x functional description data sheet 48 version 4.0, 2007-06-01 figure 22 run mode self polling check mid setup check the mid setup register wait start totim timer (if enabled) modulation selection depending on register setting wait init mid scanning unit initialize the mid scanning unit mid screening enable == 1 wait till frame start is found modulation switching all operations are done with the wake up configuration frame sync == 0 fifolk == 1 wait store rx data into fifo wait for scan finish mid scanning finished == 0 mid scanning finished == 1 checking id scanning result store rx data into fifo analyze the scanning result symbol sync=0 mid found == 0 eom check store rx data into fifo check for eom mid screening enable == 0 eom found == 1 mid found == 1 generating a frame start interrupt if not masked generating a mid found interrupt if not masked generating a eom interrupt if not masked totim timeout == 1 symbol sync == x totim timeout == 0 symbol sync == 0 to self polling mode (wu search with configuration a) it is possible to disable the timeout feature fifo locked wait till fifo read out totim timeout == 0 symbol sync == 1 fifolk == 0 fifolk == 1 totim timeout == 1 symbol sync == x frame sync == 1 init fifo init fifo = init fifo@fsync init init fifo = init fifo@cycle start 1 2 4 3 5 7 8 9 10 11 6 fifolk == 0 data sheet 49 version 4.0, 2007-06-01 tda523x functional description notes to state diagram run mode self polling: 1. modulation switching: modulation is set a ccording registers amt and bmt bits mt. 2. init: the receiver will be initialized and the fifo will be initialized and cleared when the sfr control bit initfifo is set. read out the modulation type configuration (ask or fsk), which is defined in the sfr control bits amt/bmt, and set the device to the configured mode. set the channel to the correct value, which is defined in the arfpll1/brfpll1 register. 3. fifo locked : when the signal fifolk is set, the chip enters this state and remains there until the signal fifolk is deasserted. in this state, no further data reception is possible and therefore no sync or fsync will be generated, even if a data packet is present in the received data-stream. (m ore information on the fifo behavior can be found in chapter 2.4.15 data fifo ). 4. wait: wait until symbol synchronization has finished. a loss of symbol synchronization always leads into this state, whatever the current state was. this state is only left, if symbol synchroniz ation could be established on the received data stream. (more information on the sync hronization behavior can be found in chapter 2.4.13 frame synchronization ). 5. wait: wait until a start of a data packet (tsi) is detected. all bits received from fsync until the detection of eom will be transferred to the fifo. 6. init fifo: the fifo will be initialized, if the sfr control bit fsinitfifo is set 7. check mid setup : check the configuration of the message id unit. depending on the sfr control bit midsen, a message id scanning is started or not. if no message- id scanning is selected, the next state is the eom check state. otherwise, the message id scanning unit is activated to search for a valid message-id. 8. init mid scanning unit: initialize the message-id scanning unit. 9. wait: wait until the message-id scanning unit has finished the search for a valid message id. all incoming data is stored in the fifo. 10. checking id scanning result: the result of a search for a message id is checked. if no valid message id was found, a search for a new frame is started. be aware that all received bits after fsync were stored in the fifo, even if no message id was found. after a successful search for a message id , the next state will be eom check . 11. eom check: the reception of the data frame is completed with eom. dependent on register aeomc and beomc, eom can be either sync lost, code violation or number of received bits. tda523x functional description data sheet 50 version 4.0, 2007-06-01 2.4.6 polling timer unit figure 23 polling timer unit the polling timer unit c onsists of a counter stage and a control fsm (finite state machine). the counter stage is divided into three sub-modules. the reference timer is used to divide the state machine clock (fsys/64) into the slower clock required for the spm timers. the on/off timer and the active idle period timer are used to generate the polling signal. the whole unit is controlled by the spm fsm. self-polling- mode (spm) fsm spm reference-timer (8 bit) spm on-off-timer (14 bit) spm active-idle period timer (7 bit) polling mode spmrt spmofft0 spmofft1 spmap spmip f onoff f sys / 64 f rt timer-control timer-control timer-control timer-status timer-status spmc receiver-enable to master-control-unit no wu spmont0 spmont1 data sheet 51 version 4.0, 2007-06-01 tda523x functional description 2.4.6.1 self polling modes three polling modes are available to fit the polling behavior to the expected wake up patterns and to optimize power consumption in self polling mode. the polling modes are selected via the self polling mode control (spmc) register. the following four modes are available: ? constant on/off ? fast fall back to sleep ? mixed mode(cfg.a: constant on/off; cfg.b: fast fall back to sleep) ? permanent wake up search a detected wake up forces the chip into run mode self polling. in all modes, the timing resolution is defined by the reference timer, which scales the incoming frequency (fsys/64) corresponding to the value which is defined in the self polling mode reference timer (spmrt) re gister. changing values of sprmt help to fit the final on/off timing to the calculated idea l timing. use the tda523x iaf configuration tool for optimization. 2.4.6.2 constant on/off time in this mode, there is a constant on and a constant off time. therefore, the resulting master period time is constant. the on and off time are set in the aspmont0, aspmont1, bspmont0, bspmont1, spmofft0 and spmofft1 registers. the on time configuration is done separately for configuration a and b. the selection for single or dual configuration is done in the cmc0 register. when single configuration is selected only configuration a is used. the number of channels is defined in the amt/bmt register. in the case of multi-channel or combination of multi-channel and dual configuration mode, the configured on time is used for each channel in each configuration. the following figur e shows all possible scenarios. tda523x functional description data sheet 52 version 4.0, 2007-06-01 figure 24 constant on/off time calculation example for all calculation examples for on and off time we will use following example data: ? configuration a and b used ? three channels to be scanned in configuration a, two channels in configuration b ? configuration a data rate 10 kb/s, +/- 10%, configuration b data rate 5 kb/s, +/-10% ? length of usable wake up pattern is 2000 bits (for both data rates) ? wake up criterion requires 10 bits equal to 20 chips ?f sys is 13.225625 mhz (used for 433.92 mhz rf), this means receiver start up time is 0.576 ms, channel hop latency is 0.06 ms calculation of the master period time (t masterperiod ). t masterperiod depends on: ? length/duration of transmitted wake up pattern ? data rate and tolerance ? length/duration of wake up criterion ( chapter 2.4.12 wake up generation unit ) imagine, the transmission of the wake up patte rn starts very little time after the receiver starts polling on this channel. using our example data, the receiver recognizes only 19 chips out of the required 20, but then the state machine switches to the next channel. therefore, the master period time has to be short enough that inside of the (shorter) transmitted wake up pattern, this channel can be successfully polled again. 1) calculation of wake up times for each configuration and channel: a 1 a 2 a 3 a 1 t aon t off t masterperiod t aon t aon t aon t off t masterperiod single channel, single config multi channel, single config multi channel, dual config a 1 a 2 a 3 t aon t aon t aon t off t masterperiod b 1 b 2 t bon t bon channels = 1 t masterperiod = t aon + t off channels = m t masterperiod = m*t aon + t off channels config a = m channels config b = n t masterperiod = m*t aon + n*t bon + t off rx polling run mode sleep mode rx polling run mode sleep mode rx polling run mode sleep mode data sheet 53 version 4.0, 2007-06-01 tda523x functional description the wake up time includes receiver start up time for the first channel scanned, or channel hop latency for the following channel s plus 7.625 bits (the 7.625 bits are required for synchronisation and data framer latency) and wake up criterion length at minimal data rate. t wakeup_configachannel1 =0.576 ms+(7.625 bits+10 bits)/(10kb/s*0.9)=2.55 ms t wakeup_configachannel2 =0.06 ms+(7.625 bits+10 bits)/(10kb/s*0.9)=2.02 ms t wakeup_configachannel3 =0.06 ms+(7.625 bits+10 bits)/(10kb/s*0.9)=2.02 ms t wakeup_configbchannel1 =0.06 ms+(7.625 bits+10 bits)/(5kb/s*0.9)=3.98 ms t wakeup_configbchannel2 =0.06 ms+(7.625 bits+10 bits)/(5kb/s*0.9)=3.98 ms 2) calculation of usable wake up pattern time: the wake up pattern time is the mi nimal duration of wake up patterns. t wakeup_patterna =wake up pattern/(data rate*tolerance)=2000/(10 kb/s*1.1)=181.81 ms t wakeup_patternb =2000/(10 kb/s*1.1)=363.62ms note: in many transmit frame descriptions the wa ke up pattern is terminated by a single bit for synchronisation. in this case, the wake up pattern has to be reduced by the number of bits (or chips) used for tsi (see chapter 2.4.13 frame synchronization ). the usable wake up pattern time is the wake up pattern time reduced by the longest wake up time of a channel in the related configuration. this is t wakeup_configachannel1 for configuration a, and for configuration b the scanning of both channels requires the same time. t usable_wakeup_patterna =t wakeup_patterna -t wakeup_configachannel1 =181.81ms-2.55ms=179.26ms t usable_wakeup_patternb =t wakeup_patternb -t wakeup_configbchannel1 =363.62ms-3.98ms=359.64ms 3) calculation of the master period time t masterperiod is smaller then t usable_wakeup_patterna or t usable_wakeup_patternb whichever is shorter. in our example: t masterperiod tda523x functional description data sheet 54 version 4.0, 2007-06-01 calculation of the off time the off time is the master peri od minus the sum of all on times. t off =t masterperiod -3*t on_configa -2*t on_configb =179.26ms-3*2.55ms-2*3.98ms=163.65ms note: use the tda523x iaf configuration t ool to translate the calculated values into register settings. enter on times and off time as calculated. watch the master period and vary off time till the resulting master period is shorter than the result of the calculation. take care that t on must be always longer and t masterperiod always shorter than the calculated values! 2.4.6.3 fast fall back to sleep this mode is used to switch off the receiver as quickly as possible to reduce power consumption. during the search for a wake up pattern, a c heck is performed in parallel to determine, if there is a bit stream, to which it can be syn chronized. if within the limits of the sync search time out there is no synchronization to a bit stream, the wake up search for this channel is stopped. if synchronization to a bit stream is possible (and not lost again), the chip waits if the wake up criterion is fulfilled. if the wake up criterion is not fulfilled, if in worst case, the last bit of an expected wa ke up pattern is wrong, the wake up procedure for this channel is stopped, and the chip tries to synchronize on the next channel, or falls back to sleep. that means, that the effective search time and, consequently, the receiver active time are significantl y shorter, and power consumption is reduced when no input signal is present. calculation of sync search time out is found in chapter 2.4.9.1 synchronization search time and inter-frame time . the on and off time settings are differ ent from the constant on/off time mode. the bspmont register is not used because the whole on time is defined in the aspmont register. regardless of the numbers of chann els and whether dual or single configuration is used, the on time is defined with the confi g a on timer. the deactivation of the receiver can happen at different times, but this event does not influence the timer stage because the on time is still the same. so the master period is constant. the following scenarios are the same as before, but with fast fall back to sleep. data sheet 55 version 4.0, 2007-06-01 tda523x functional description figure 25 fast fall back to sleep calculation example the same example data is used as for constant on/off time: ? configuration a and b used ? three channels to be scanned in configuration a, two channels in configuration b ? configuration a data rate 10 kb/s, +/- 10%, configuration b data rate 5 kb/s, +/-10% ? length of usable wake up pattern is 2000 bits (for both data rates) ? wake up criterion requires 10 bits equal to 20 chips ?f sys is 13.225625 mhz (used for 433.92 mhz rf), this means receiver start up time is 0.576 ms, channel hop latency is 0.06 ms calculation of the master period time (t masterperiod ) the master period time has to be short enough that inside of the (shorter) transmitted wake up pattern, the channel with the longes t wake up sequence can be polled twice. this calculation is equal to the calculation in constant on/off time. 1) calculation of wake up times for each configuration and channel: t wakeup_configachannel1 =0.576 ms+(7.625 bits+10 bits)/(10kb/s*0.9)=2.55 ms t wakeup_configachannel2 =0.06 ms+(7.625 bits+10 bits)/(10kb/s*0.9)=2.02 ms t wakeup_configachannel3 =0.06 ms+(7.625 bits+10 bits)/(10kb/s*0.9)=2.02 ms t wakeup_configbchannel1 =0.06 ms+(7.625 bits+10 bits)/(5kb/s*0.9)=3.98 ms t wakeup_configbchannel2 =0.06 ms+(7.625 bits+10 bits)/(5kb/s*0.9)=3.98 ms a 1 a 2 a 3 t aon t off t masterperiod t aon t off t masterperiod single channel, single config multi channel, single config multi channel, dual config t aon t off t masterperiod channels = 1 t masterperiod = t aon + t off channels = m t masterperiod = t aon + t off channels config a = m channels config b = n t masterperiod = t aon + t off rx polling run mode sleep mode rx polling sleep mode rx polling sleep mode a 1 a 1 a 2 a 3 b 1 b 2 run mode run mode tda523x functional description data sheet 56 version 4.0, 2007-06-01 2) calculation of usable wake up pattern time: the wake up pattern time is the mi nimal duration of wake up patterns. t wakeup_patterna =wake up pattern/(data rate*tolerance)=2000/(10 kb/s*1.1)=181.81 ms t wakeup_patternb =2000/(10 kb/s*1.1)=363.62ms t usable_wakeup_patterna =t wakeup_patterna -t wakeup_configachannel1 =181.81ms-2.55ms=179.26 ms t usable_wakeup_patternb =t wakeup_patternb -t wakeup_configbchannel1 =363.62ms-3.98ms=359.64 ms 3) calculation of the master period t masterperiod is smaller then t usable_wakeup_patterna or t usable_wakeup_patternb whichever is shorter. in our example: t masterperiod data sheet 57 version 4.0, 2007-06-01 tda523x functional description t on for configuration a is calculated according const on/off rules, t on for configuration b is calculated according fast fall back to sleep rules. figure 26 mixed mode calculation example the same example data is used as for constant on/off time: ? configuration a and b used ? three channels to be scanned in configuration a, two channels in configuration b ? configuration a data rate 10 kb/s, +/- 10%, configuration b data rate 5 kb/s, +/-10% ? length of usable wake up pattern is 2000 bits (for both data rates) ? wake up criterion requires 10 bits equal to 20 chips ?f sys is 13.225625 mhz (used for 433.92 mhz rf), this means receiver start up time is 0.576 ms, channel hop latency is 0.06 ms calculation of the master period time (t masterperiod ) the master period time has to be short enough that inside of the (shorter) transmitted wake up pattern, the channel with the longes t wake up sequence can be polled twice. this calculation is equal to the calculation in constant on/off time. 1) calculation of wake up times for each configuration and channel: t wakeup_configachannel1 =0.576 ms+(7.625 bits+10 bits)/(10kb/s*0.9)=2.55 ms t wakeup_configachannel2 =0.06 ms+(7.625 bits+10 bits)/(10kb/s*0.9)=2.02 ms t wakeup_configachannel3 =0.06 ms+(7.625 bits+10 bits)/(10kb/s*0.9)=2.02 ms t wakeup_configbchannel1 =0.06 ms+(7.625 bits+10 bits)/(5kb/s*0.9)=3.98 ms a 1 a 2 a 3 a 1 t aon t off t masterperiod t aon t aon t aon t off t masterperiod single channel, single config multi channel, single config multi channel, dual config a 1 a 2 a 3 t aon t aon t aon t off t masterperiod b 1 b 2 channels = 1 t masterperiod = t aon + t bon + t off channels = m t masterperiod = m*t aon + t bon + t off channels config a = m channels config b = n t masterperiod = m*t aon + t bon + t off t bon t bon t bon rx polling run mode sleep mode rx polling run mode sleep mode rx polling run mode sleep mode tda523x functional description data sheet 58 version 4.0, 2007-06-01 t wakeup_configbchannel2 =0.06 ms+(7.625 bits+10 bits)/(5kb/s*0.9)=3.98 ms 2) calculation of usable wake up pattern time: the wake up pattern time is the mi nimal duration of wake up patterns. t wakeup_patterna =wake up pattern/(data rate*tolerance)=2000/(10 kb/s*1.1)=181.81 ms t wakeup_patternb =2000/(10 kb/s*1.1)=363.62ms t usable_wakeup_patterna =t wakeup_patterna -t wakeup_configachannel1 =181.81ms-2.55ms=179.26 ms t usable_wakeup_patternb =t wakeup_patternb -t wakeup_configbchannel1 =363.62ms-3.98ms=359.64 ms 3) calculation of the master period t masterperiod is smaller then t usable_wakeup_patterna or t usable_wakeup_patternb whichever is shorter. in our example: t masterperiod data sheet 59 version 4.0, 2007-06-01 tda523x functional description the beginning (config a, channel 1) until the on ti me has elapsed. the timing calculation can be seen in the next figure. note that permanent wake up search makes sense only in the const on/off mode. figure 27 permanent wake up search note: calculation of on/off time and master period is equal to fast fall back to sleep wake up mode. 2.4.6.6 active idle period selection this is used to deactivate some polling per iods. normally, the polling starts again after the t masterperiod . with this active-idle period selectio n, some of the polling periods can be deactivated independently from the polling m ode. the active and idle sequences are set with the spmap and the spmip registers. th e values of these registers determine the factors m and n. a 1 a 2 a 3 t on t off t masterperiod t on t off t masterperiod single channel, single config multi channel, single config multi channel, dual config t on t off t masterperiod b 2 channels = 1 t masterperiod = t on + t off channels = m tmasterperiod = t on + t off t on = m*t ao n channels config a = m channels config b = n tmasterperiod = t on + t off t on = m*t aon + n*t bon a 1 a 2 a 3 b 1 a 1 rx polling run mode sleep mode rx polling run mode sleep mode rx polling run mode sleep mode a 1 a 1 a 1 a 1 a 1 a 1 a 2 a 3 a 1 a 1 a 2 tda523x functional description data sheet 60 version 4.0, 2007-06-01 figure 28 active idle period including fast fall back to sleep spmc : self polling mode control register spmrt : self polling mode reference timer addr: 0x07 reset value: 0x00 bit r/w description 3 w permwusen: permanent wake up search enable during on time 0: disabled 1: enabled 2 w spmaien: self polling mode active idle enable 0: disabled 1: enabled 1:0 w spmsel: self polling mode selection 00b: constant on/off time 01b: fast fall back to sleep 10b: mixed mode(conf.a: const on/off, conf.b: fast fall back to sleep) addr: 0x08 reset value: 0x01 bit r/w description 7:0 w spmrt: set value self polling mode reference timer the output of this timer is used as input for the on/off timer incoming periodic time = 64/fsys output periodic time= t rt = (64 * spmrt) /fsys min: 01h = (64*1)/fsys max: 00h = (64 * 256)/fsys sleep mode rx polling run mode t on t off t masterperiod n*t masterperiod m*t masterperiod active idle data sheet 61 version 4.0, 2007-06-01 tda523x functional description spmofft0 : self polling mode off time register0 spmofft1 : self polling mode off time register1 spmap : self polling mode active periods reg. spmip : self polling mode idle periods register addr: 0x09 reset value: 0x01 bit r/w description 7:0 w spmofft: set value self polling mode off time: bit 7...bit 0(lsb) off time = t rt *spmofft min: 0001h = 1*t rt reg.value 3fffh = 16383*t rt max: 0000h = 16384*t rt addr: 0x0a reset value: 0x00 bit r/w description 5:0 w spmofft: set value self polling mode off time: bit 13(msb)...bit 8 off time = t rt *spmofft min: 0001h = 1*t rt reg.value 3fffh = 16383*t rt max: 0000h = 16384*t rt addr: 0x0b reset value: 0x01 bit r/w description 4:0 w spmap: set value self polling mode active periods. min: 01h = 1 (master) period max: 1fh = 31 (master) periods reg.value 00h = 256 (master) periods addr: 0x0c reset value: 0x01 bit r/w description 7:0 w spmip: set value self polling mode idle periods. min: 01h = 1 (master) period max: 00h = 256 (master) periods tda523x functional description data sheet 62 version 4.0, 2007-06-01 2.4.7 rf path figure 29 rf path rfin+ and rfin- are inputs to the on chip lna. rf is usually connected to rfin+, and rfin- is grounded. if a filter with differential outputs is used, such as a saw filter, the di fferential inputs may be used accordingly. the lna directly drives the two in quadrature driven rf mixers. the outputs of the two mixers are fed to a polyphase filter that pr ovides active suppres sion of input signals at the image frequency of the desired input signal. the center frequency of the polyphase filter and the following blocks at the if frequency is 10.7 mhz. the polyphase filter is followed by a digitally adjustable if attenuator. this allows the production spread of the on chip signal strip, of external lna and matching circuitry and rf saw and ceramic if filters to be tri mmed out. the attenuator offers a programmable attenuation range of 12 db, programmable in 16 steps and is controlled via the sfr control bits ifatt. an if driver amplif ier with a characteristic output impedance of 330 ? allows simple interfacing to external ceramic if filters. for adjustment of the rssi offset the complete rf path can be switched off via the sfr control bit rfoff. the rf mixer and poly phase filter are capa ble to support a hi-side and a lo-side lo injection mode. selection of the lo injection mode is controlled via the sfr-control bit ssbsel. poly- phase filter sum- amplifier lna rf-mixer rfin+ if-out rfin- lo-signals iq digitally adjustable if-attenuator 0 .. -12 db if- driver- amp. 4 ifatt 1 ssbsel data sheet 63 version 4.0, 2007-06-01 tda523x functional description selection of if attenuation use always minimum if attenuation (0db). on ly if there is an external lna used, if attenuation should be set to the gain of the external lna. if there is one or more saw filters, the insertion loss should be reduced from the external lna gain. if strong out of band disturbers are expected, an increase of if attenuation may increase large signal immunity, at the cost of slight reduction in sensitivity. rfc : rf control register loc : local oscillator control register 2.4.7.1 rx-run/rxd pin the receiver enable signal is offered at the dedicated rx-run/rxd pin to control external components such as an external ln a. whenever the receiver is active, the rx- run output is high. note that the same output pin may be also configured to provide the received data in transparent mode. addr: 0x12 reset value: 0x00 bit r/w description 4 w rfoff: switch off rf path (for rssi trimming) 0: rf path enabled 1: rf path off 3:0 w ifatt: adjust if attenuation in 16 steps to trim the gain rfin --> if-out 0000: 0 db attenuation 1111: 12 db attenuation addr: 0x16 reset value: 0x00 bit r/w description 7:5 w always set to 0 4 w ssbsel: local oscillator injection mode selection 0: lo-side lo injection .. use for TDA5230 1: hi-side lo injection .. use for tda5231 3:0 w always set to 0 tda523x functional description data sheet 64 version 4.0, 2007-06-01 cmc1 : chip mode control register 1 addr: 0x03 reset value: 0x00 bit r/w description 0 w rxrunrxdsel: rx-run/rxd pin function 0: rx-run signal out at pin rx-run/rxd 1: rx-data out at pin rx-run/rxd data sheet 65 version 4.0, 2007-06-01 tda523x functional description 2.4.8 functionality of the if path 2.4.8.1 if filter the output of the image reject mixer is buffered by the if driver amplifier. the signal is then filtered by one or (alternatively ) two external 10.7 mhz if filters. figure 30 if path for operation with one if filter, this filter must be connected to the pins if-out and lim- in+. for the two filter option, the first if filter must be connected to the pins if-out and ifbuf-in and the second filter to the pins ifbuf-out and lim-in+. the if buffer amplifier is enabled by the bit ifbuf to drive the second if filter. the if mux allows to bypass the second if filter, and therefore to switch in between two different if filter bandwidths. the if mux is switched by using the bit ifmux. all input and output impedances seen by the if filters (if driver amplifier, if buffer amplifier and if limiter input) are designed to 330 ? . selection of the if filter the construction of the tda523x allows the use low-cost standard ceramic if filters with a center frequency of 10.7 mhz, and an input and output impedance of 330 ? . the recommended if filter bandwidth is 280 khz. see also (bill of material of the evaluation board). wider if fil ter bandwidth is required if transmitters with high tolerance are used. narrower if filter bandwidth will increase immunity to noise and improve channel separation in multichannel systems. if- mux rssi-generation a d ifbuf-in ifbuf-out lim-in+ lim-in- rssi if- buffer- amp. if-limiter to digital fsk-demodulator and digital bb- processing ifb uf if m u x 1 limgain limoffs tda523x functional description data sheet 66 version 4.0, 2007-06-01 if bandwidth switching is required, the first if filter is wideband, and is used if the if mux is switched to ifbuf-in. the second if filter is narrowband, if the if mux is switched to lim-in+, the narrow characteristic of this fi lter overrides the wide first if filter. figure 31 external if filter configurations dual: aif0 and bif0 : conf.a if buffer amplifier enable 2.4.8.2 limiter, rssi the limiter is an ac coupled multistage am plifier with a wide bandpass characteristic centered around 10.7 mhz. the limited if si gnal is fed to the digital fsk demodulator. the limiter circuit also acts as a receive signal strength indicator (rssi) generator that produces a voltage signal proportional to the logarithm of the input signal level. addr: 0x3f and 0x60 reset value: 0x00 bit r/w description 1 w ifbuf: enable if buffer amplifier 0: buffer disabled, used for single if filter 1: buffer enabled, used for dual if filter configuration 0 w ifmux: select if-limiter input 0: use pin lim-in+ as input 1: use pin ifbuf-in as input ifbuf-in ifbuf-out lim-in+ if-out one-filter application two-filter application optional one-filter application (2nd if-filter disabled) data sheet 67 version 4.0, 2007-06-01 tda523x functional description the rssi signal is used to determine the relative rf input signal power of a received signal or data transmission, and for exampl e, to estimate the transmitter distance. rssi can be read either from the analog output as described below, or digitally via the peak detector registers, which are described in chapter 2.4.8.3 rssi peak detector . to achieve a well-defined rssi response, t he offset and the gain of the rssi generation unit can be trimmed via the sfr control bits limgain and limoffs as described later. the bandwidth of the rssi signal can be adapted to the data rate. it is controlled by the sfr control bits aafilt. this rssi signal can be fed to the pin rssi via a buffer amplifier. to enable this buffer the sfr control bit rssimone must be set. figure 32 if path, rssi rssi is derived from four signals. any of these four signals (rssi+, rssi-, ref+ and ref-) may be routed to the pin rssi. rssi+ is the real rssi signal derived from the input signal voltage, while rssi- is an internal offset, and ref+/- is the internal voltage reference. the selection of the signal routed to pin rssi is done by the sfr control bits rssimtr. typical values are: rssi-...1.55 v, ref+...1.8 v, ref-...1.3 v; these values are not infl uenced by trimming. the following figure shows the behavior of rssi+ over an input signal power sweep. the four curves show the trimming range in between minimum offset/maximum gain and maximum offset/minimum gain, the typical rssi+ using recommended default setting of minimum offset / minimum gain (if rssi trimming is not used), and the fourth curve represents a typical trimmed rssi+ rssi-generation a d ifbuf-in ifbuf-out lim-in+ lim-in- rssi 1 if- buffer- amp. if-limiter to digital fsk-demodulato r and digital bb- processing ifbuf limgain 5 limoffs 4 rssimone aafilt 2 mux rssimtr rssi- rssi+ ref - ref + tda523x functional description data sheet 68 version 4.0, 2007-06-01 figure 33 typical rssi+ over input signal power the true rssi signal is calculated by the following rule: the result of this calculation is about -1 for no input signal (=noise), and about +1 for large input signals (e.g. -10 dbm). the rssi signals are also sampled by an ad converter, with four differential input signals for the rssi and the rssi voltage reference. the true rssi is automatically calculated, using the following formula and the result stretched to values from 0 to 255. the digital output of the adc is used for processing ask modulated data, and for two peak detectors, which are accessible via sfrs and are described in chapter 2.4.8.3 rssi peak detector . the range of the adc is smaller than the range of real rssi. it is important that the true rssi level at noise is >- 0.92, which means it is clearly inside the adc range. otherwise, small input signals are not recognized and sensitivity is decreased. typical rssi+ over input signal power 0,50 v 1 ,00 v 1 ,50 v 2,00 v 2,50 v -1 25 -1 1 5-1 05 -95 -85 -75 -65 -55 -45 -35 -25 input signal pow er [dbm] rssi+ [v] m i n i m u m o f f s e t , m a x i m u m g a i n m a x i m u m o f f s e t , m i n i m u m g a i n trimmed m i n i m u m o f f s e t , m i n i m u m g a i n rssi rssi+ rssi- ? ref+ ref- ? ------------------------------------------------- ?? ?? = rssi rssi+ rssi- ? ref+ ref- ? ------------------------------------------------- ?? ?? 1 + ?? ?? 1 2 -- -255 = data sheet 69 version 4.0, 2007-06-01 tda523x functional description accuracy is optimized by trimming true rssi at noise level (no input signal) to a calculated value of -0.92 to 0.90 and at strong input signals (about -10 dbm) to +1. it is recommended either to use rssi with the default settings (m inimum offset, minimum gain) or to use the following trim proc edure. this guarantees optimal ask sensitivity. it is not recommended to use trimming to increase rssi resolution or slope. recommended analog trimming procedure: ? download configuration file ? send 0x35 to the register limc1; this enables the rssi buffer, selects rssi-, and sets the rssi offset to a middle value ? measure rssi- voltage at rssi pin (26) ? send 0x55 to the register limc1, ref+ is selected ? measure ref+ voltage at rssi pin (26) ? send 0x75 to the register limc1, ref- is selected ? measure ref- voltage at rssi pin (26) ? send 0x15 to the register limc1, rssi+ is selected ? measure a rssi voltage curve at rssi pin (26) from noise or (no input signal) to a high signal (about -10 dbm) using a continuous wave input signal. ? normalize the curve using the formula for true rssi earlier in this chapter ? change limoffs (limc1, bit 0..3) until true rssi without input signal is between - 0.92 and -0.9 ? change limgain (limc0, bit 0..4) until true rssi at -10 dbm is smaller but next to +1 ? the new values for limgain and limoffs must be added to the configuration! see also the recommended digital trimming procedure in chapter 2.4.8.3 rssi peak detector . if trimming is required it is only nec essary to do either analog or digital trimming, but results of the two tri mming procedures are slightly different. usually, it is recommended to use the digital rssi. recommended applications for the analog rssi are: ? debugging and watching rf traffic ? external ask demodulation ? relative signal power measurements if optimal accuracy is required and to reduce thermal drift, it is recommended to read all four rssi signals (rssi+, rssi-, ref+ and ref-) within a few seconds. tda523x functional description data sheet 70 version 4.0, 2007-06-01 limc0 : trim rssi gain limc1 : trim rssi offset, enable rssi pin dual: adigrxc and bdigrxc : global settings addr: 0x1b reset value: 0x0c bit r/w description 4:0 w limgain: trim the rssi gain (slope) min: 00h = minimum gain max: 1fh = maximum gain iaf tda523x config tool sets this value to 00h by default addr: 0x1c reset value: 0x15 bit r/w description 6:5 w rssimtr: select signal for rssi pin 00b: rssi+ 01b: rssi- (reference) 10b: ref+ (reference) 11b: ref- (reference) 4 w rssimone: enable buffer for rssi pin 0: buffer off 1: buffer on 3:0 w limoffs: trim the rssi offset min: 0h = minimum offset max: fh= maximum offset iaf tda523x config tool sets this value to 0h by default addr: 0x6c and 0x8c reset value: 0x00 bit r/w description 2:1 w aafilt: anti aliasing filter 00b: 40 khz use for data rates >9.6 kb/s 01b: 13.6 khz use for data rates >3 kb/s 10b: 5 khz use for data rates >2 kb/s 11b: 3.6 khz use for data rates <=2 kb/s the anti aliasing filter corner fr equency can be changed to achieve better performance. note that the corner frequency and the data rate must be set together. this value is automatically created by the iaf tda523x config tool 0 w datinv ... used by data filter data sheet 71 version 4.0, 2007-06-01 tda523x functional description 2.4.8.3 rssi peak detector as mentioned earlier, rssi is also sampled by an adc, delivering an 8-bit resolution. all four rssi signals are connected to the differ ential inputs, and true rssi with optimal temperature compensation is automatically generated. the chip possesses two digital rssi peak level detectors. the rssi level from the adc is averaged over four samples before it is sent to the two peak detectors. this reduces the influence of singl e noise peaks. figure 34 peak detector unit peak detector 1 is used to measure the input signal power of a received and accepted data telegram. it is read via sfr rssi1. observation of the rssi signal starts at the detection of a tsi (fsync) and ends with the detection of eom. the internal rssi1 value is cleared after fsync. the evaluated rssi peak level rssi1 is transferred to the rssi1 register at eom. starting the observation of the rssi level can be delayed by a selectable number of data bits and is controlled by the register pkbitpos. a l atency in the generation of fsync and eom of approx. 2..3 bits in relation to the contents of the peak detector must be considered. within the boundaries described, the register rssi1 always contains the peak value of the last completely received data telegram. the register rssi1 is reset to 0 at power up reset only. a d from rssi- generator rssi i&d-averaging filter adcsplrdiv adc sampling- clock generation pkbitpos f sys divide by 4 integrate dump to data-filter f adc f adc/4 peak-detector 2 rssi2 read-access to register rssi2 from spi-controller peak-detector 1 compare rssi1 fsync peak- detector track- control peak-value register update eom update peak- value update load compare peak- value load & from fsm rx-run tda523x functional description data sheet 72 version 4.0, 2007-06-01 peak detector 2 is used to measure rssi independent of a data transfer and to digitally trim rssi. it is read via sfr rssi2. observation of the rssi signal is active whenever the rx-run signal is high. the rssi2 register is refreshed and peak detector 2 is reset after every read access to rssi2. it may be required to read rssi2 twice to obtain the required result. this is because, for example, during a trim procedure input signal power is reduced, after reading rssi2, the peak detector will still hold the higher rssi level. after reading rssi2 the lower rssi level is loaded into the peak detector, an d can be read by reading rssi2 again. when the rx-run signal is inactive, a re ad access has no influence to the peak detector value. the register rssi2 is reset to 0 at power up reset. figure 35 peak detector behavior the following figure shows the typical behavio r of the digital rssi. three curves show the typical trimming range, the typical de fault rssi, and the fourth curve shows a typically trimmed rssi. d0 tsi run-in d1 .... dn .... reset fsync eom internal rssi n = pkbitpos run-in eom fsync input data-pattern noise noise dn -1 fsync clears the internal rssi1 rssi1 register internal rssi internal rssi2 = rssi2 register spi read out rssi1 & rssi2 spi internal rssi1 dn +1 dn +2 dn +3 *1 *1 *1 *1 computation delay due to filtering and signal calculation. tsi *1 d0 d1 .... data sheet 73 version 4.0, 2007-06-01 tda523x functional description typical figure 36 typical digital rssi over input signal power recommended digital trimming procedure: ? download configuration file (r un mode slave, limgain, limoffs set to minimum) ? switch off rf path by setti ng register rfc to 0x1f. ? read rssi2 eleven times (minimum 10 ms in between readings), use average of last ten readings (always) ? change limoffs till rssi2 readings with no input signal are between 0x02 and 0x05 or closest to the upper value ? set register rfc to 0x0 z to switch on rf-path ( z stands for the selected value for if attenuation. see chapter 2.4.7 rf path . if if attenuation is trimmed, this has to be done before trimming of rssi.). ? change limgain till rssi2 readings at -10 dbm are between 0xfc and 0xfe or closest to the lower value. ? the new values for limgain and limoffs have to be added to the configuration! it is only necessary to use either analog or digital trimming. the results between analog and digital trimming may differ. therefor e the same procedure should always be used. typical rssi2 over input signal power 0 50 100 150 200 250 -125 -115 -105 -95 -85 -75 -65 -55 -45 -35 -25 input signal pow er [dbm ] register rssi2 [lsb] m i n i m u m o f f s e t , m a x i m u m g a i n m a x i m u m o f f s e t , m i n i m u m g a i n t r i m m e d m i n i m u m o f f s e t , m i n i m u m g a i n tda523x functional description data sheet 74 version 4.0, 2007-06-01 rssi1 : peak detector 1 read register rssi2 : peak detector 2 read register addr: 0xac reset value: 0x00 bit r/w description 7:0 r rssi1: peak level during payload tracking started after fsync + pkbitpos set at eom cleared at reset and fsync addr: 0xad reset value: 0x00 bit r/w description 7:0 c rssi2: peak level. tracking is active when digital receiver is enabled set at higher peak levels than stored cleared at reset and spi read out data sheet 75 version 4.0, 2007-06-01 tda523x functional description 2.4.9 digital receiver the functionality of the digital receiver (digrx ) is divided into three consecutive data processing stages: the data filter, the clock and data recovery and the framer synchronization unit. the arch itecture of the digital receiver is optimized for processing manchester-coded data streams. the figure below shows all the symbol combinations. digital 0 and 1 are coded with the change of the amplitude in the middle of the symbol period. the code violations (cv) m (mark) and s (space), are c oded as low/high signal levels. generally, the digital receiver can handle one single cv following four valid manchester-coded data bits figure 37 manchester code the basic structure of a telegram frame is shown in the figure below. the protocol starts with runin. the runin with the minimum length of four manchester coded symbols is used for internal filter setting and frequency adjustment. the tsi (telegram start identifier), which is used as framing wo rd, follows the runin sequence. the payload contains the effective data. the length of the valid payload data is defined as the length itself or additional criteria (e.g. loss of sync). figure 38 frame 2.4.9.1 synchronization search time and inter-frame time two important system parameters will be descr ibed in this chapter: the synchronization search time out (sysrct0) and the inter-frame time. the processing sequence of a telegram is shown below. 0 1 sm 1st chip 2nd chip 1st chip 2nd chip 1st chip 2nd chip 1st chip 2nd chip runin tsi payload tda523x functional description data sheet 76 version 4.0, 2007-06-01 figure 39 data latency the synchronization search time t 3 is the time the receiver requires for a search for a pattern in an incoming data stream. the minimum value of the search time out length is the consequence of the system latency time t 1 and runin length. the overall system latency time is calculated in two steps: t 1 is the delay between adc input and the filter output (chip data available), and t 2 is the time between the slicer input and the framer output (decoded data available). t 1 latency time include: (t 1 = 2 2/16 t + 0.5 t) 1) ? matched filter computation time ? signal detector delay t 2 latency time include: (t 2 = 1.5 t to 2.0 t) ? data slicer computation time ? framer computation time. the 0.5 t spread is caused by the inter nal framer circuit quantization behavior. this means, that for the minimum length of the sysrct0, the value 2 2/16 bits plus 0.5 bits, plus the runin length, which is set in the cdr2 register, plus 1.5 bits (to consider worst case runin patterns) have to be used. to reach all data rate and duty cycle errors 10% of the overall sum must be added. 1) t..nominal duration of one data bit runin tsi input data tsi t 1 t 2 data available t 3 tsi chip-data available runin runin runin eom eom eom t 2 t 2 pll re-synchronization sysrct0 roundup runin 2 ,125 2 ++ () 16 ? () 1,1 ? () = data sheet 77 version 4.0, 2007-06-01 tda523x functional description based on the recommended value of 3.5 bits for the runin, the recommended setting for sysrtc0 = 0x87. this value is automatically used by the iaf tda523x configuration tool! dual: asysrct0 & bsysrct0 : synchronization search time out a second important system parameter which must be considered, is the minimal inter- frame time (time in between two data frames). this time is equal to the t 2 time and has a length of 2 bits. the eom to pll re-synchronization time is negligible (this time is t/16 bit), and the system delay t 1 is irrelevant, because of the eom signal is used for pll re- synchronization only. note that the described inter-frame time is based on the input pattern with equal signal power in the following telegram, in other cases the inter-frame time can vary from the calculated value. 2.4.9.2 data filter and signal detection the digital receiver processes input signal s from the digital fsk demodulator as well as from the a/d-converted output signal of the rssi generator used for ask modulated data signals. input selection of the digital receiver is done by a multiplexer, which is controlled by the master control unit via the control signal modu lation type. an optional pre-slicer unit may be activated in cer tain ask applications to further increase the jammer performance of the receiver. addr: 0x76 & 0x96 reset value: 0x00 bit r/w description 7:0 w syncto: synchroniz ation search time out 1) ffh: 15 15/16 bit 00h: 0 bit 1) the value should be set in t/16 steps tda523x functional description data sheet 78 version 4.0, 2007-06-01 figure 40 ad-control and matched-filter ad converter: the ad sampling rate division factor adcdiv is always a multiple of 16 times of the data rate, and in a range from 96 khz to 320 khz. for example for a 2 kb/s data rate the adc sampling rate has to be a multiple of 32 kh z, the optimal adc sampling rate is 320 khz. because of f sys and the used clock divider, not all adc sampling rates are possible. therefore, there is an ideal sample rate (e.g. 320 khz) and finally a real sample rate (322.576 khz, note: values slightly higher than 320 khz are tolerated if calculated by the iaf tool). the difference between the ideal and the real sample rate should not be more than 2%. for better performance, the highest possible adc sampling rate should be set. for data rates lower or equal to 1.1kb/s a maximum sample rate of 120 khz should be selected. a data decimation is required to correct the values which are dependent on the factor of oversampling. the calculation formulas for adcdiv / askdec factors: the following calculations are fully supported by the iaf tda523x configuration tool! mux dif from fsk- demodulator a d from rssi- generator rssi1 peak detector soc eoc rssi-track a/d control-unit cic filter scaling decimation datfilt1 (askdec) clock-generation f sys t nom / 16 unsliced data at rate t nom / 16 to signal detection eom t nom / 16 from master-control-unit modulation-type rssi-clear adcdiv rssi2 pre slicer pslc datfilt0 data sheet 79 version 4.0, 2007-06-01 tda523x functional description dual: adcsplrdiv and bdcsplrdiv : adc dividing factor dual: adatfilt0 and bdatfilt0 : matched filter scaling and delay dual: adatfilt1 and bdatfilt1 : matched filter decimation matched data filter the cic filter together with the dc-offset c anceller (realized as differentiator) is a matched filter for one manchester coded bit. the matched data filter has two major ta sks: to reconstruct manchester-coded data of the correct data rate, and to deliver a ?quality? value, the so-called asknp value. addr: 0x6d and 0x8d reset value: 0x00 bit r/w description 7:0 w adcdiv: adc sampling rate division factor. addr: 0x6f and 0x8f reset value: 0x00 bit r/w description 5:3 w asksca: cic-filter input scaling factor 1) 000b: default 1) use default value 2:0 w askdel: cic-filter co mb section delay factor 1)2) use always 110b 2) the cic filter delay = askdel + 1 addr: 0x70 and 0x90 reset value: 0x00 bit r/w description 5:0 w askdec: cic filter decimation factor adcdiv round f sys f adc ------------ ?? ?? 1 ? = f adc 96 320khz [] = askdec round f adc 16 f ? data --------------------- ?? ?? 1 ? = f adc f sys adcdiv 1 + ---------------------------------- - = tda523x functional description data sheet 80 version 4.0, 2007-06-01 the higher the output of asknp, the better the reliability of the related data bit. the signal detector uses this value to distingui sh between acceptable data and unacceptable data (e.g. noise). figure 41 matched filter, signal/noise detection and slicer units the polarity of the manchester code can be in verted by setting the sfr control bit datinv. signal and noise detector the signal and the noise detector compare the outputs of asknp and fsknp (see fsk demodulator) with configurable thresholds. the signal detection mode must be configured based on whether ask or fsk modulation is used: ? signal power detection (=squelch) only (related registers sigdet0, sigdet1 and asknp). this mode is generally used for ask and recommended for fsk. ? noise power detection only (related registers ndthres and fsknp). ? signal and noise power detection simultaneously. ? signal and noise power detecti on simultaneously, but the fsk noise detect signal is valid only if the sigdetlo threshold is exceeded. this is the recommended fsk mode, if minimum fsk deviation is not suffi cient to use signal power detection only. signal power meter matched filter data slicer (+1 0 -1) clock recovery slicer chip data decoder threashold + signal power detector shift register data data delayed data enable threshold from mux to clock recovery to framer recovered clock sigdet0 sigdet1 datfilt0 datfilt1 ndsel pdsr asknp datinv t nom / 16 t nom / 16 t nom / 16 f sys t nom / 16 f sys from limiter fsk noise power meter p o w e r m e t e r s e l e c t i o n sigdetlo sigdetsel ndthres data sheet 81 version 4.0, 2007-06-01 tda523x functional description the next diagram shows the system charac teristics to consider in choosing the best signal detector level. on the one hand, achieving good far (false alarm rate) performance that a higher threshold level must be set, but the mer/ber (message error rate/bit error rate) performance (high sigdet level signal) will decrease. on the other hand, the mer/ber performance can be increa sed by setting smaller threshold levels but then the far performance (low sigdet level signal) will worsen. figure 42 signal detection threshold level quick procedure to determine signal and noise detector thresholds: preparation a set up is required with original rf hardware as in the final application. the values of asknp and fsknp can be read via the final app lication or using the tda523x explorer. a complete configuration file using ri ght modulation, data rate and run mode slave, must be prepared using the iaf tda523x configuration tool and downloaded to the tda523x. signal detector threshold for ask take 500 readings of asknp (50 are also possible, but this leads to less accurate results) with no rf input signal applied (= noise only). calculate average and standard deviation (automatically done by tda523x expl orer). signal detector threshold is average plus 2 times the sta ndard deviation. to load the si gdet register the calculated value must be rounded and converted to hexade cimals. for a final application, the signal detector threshold should be varied to optimize the false alarm rate and the sensitivity. signal and noise detector thresholds for fsk signal detector threshold telegram better far performance better mer performance high sdthr level low sdthr level optional bridged by the sigdet counter signal power input data sdthr level area tda523x functional description data sheet 82 version 4.0, 2007-06-01 do 500 (50) readings of asknp with no rf input signal applied (=noise only). calculate average and standard deviation (automatica lly done by tda523x explorer). signal detector threshold is average plus 2 times th e standard deviation. of course this value has to be rounded and converted to hexadec imals. for a final application the signal detector threshold should be varied to optimize the false alarm rate and the sensitivity. verification if squelch only is possible apply a bit pattern (e.g.prbs9) with corr ect data rate at about -80 dbm input signal power and minimum fsk deviation to the rf input. do 500 (50) readings of asknp calculate average minus three times the s tandard deviation. this value should be higher than the calculated signal detector threshol d calculated above. if this is not the case, signal detector and noise detector must be used. noise detector threshold do 500 (50) readings of fsknp with no rf input signal applied (=noise only). calculate average and standard deviation. noise d etector threshold is average minus the standard deviation. round this value and co nvert it to hexadecimals. for a final application, the noise detector threshold shou ld be varied to optimize false alarm rate and sensitivity. signal detector low threshold: the signal detector low threshold is alwa ys required in combination with the noise detector. set register bit sdlore to 1. apply a bit pattern (e.g.prbs9) at correct data rate at about -80 dbm input signal power and minimu m fsk deviation to the rf input. do 500 (50) readings of asknp calculate average. c hange sdsello till average is smaller than 50d (0x32). sigdetlo = 0.8 * (average - 3 * standard deviation). set register sdlore back to 0. the last setting of sdse llo has also to be used for configuration! verification threshold settings should be verified by testing receiver sensitivity over the input frequency range, with a steps size of 100hz, at minimum fsk deviation with all combinations of minimum and maximum data rate and duty cycle. a detailed description of the suggested pr ocedure to determine the signal and noise detector thresholds for user specific app lications can be found in the application notes ?how to choose an application specific sign al detection threshol d for tda523x based ask mode applications? and ?how to choose an application specific signal- and noise- detection threshold for tda523x based fsk mode applications? . data sheet 83 version 4.0, 2007-06-01 tda523x functional description dual: asigdet0 and bsigdet0 : signal detector (run mode) dual: asigdet1 and bsigdet1 : signal detector (wake up) dual: andconfig and bndconfig : fsk noise detector configuration addr: 0x71 and 0x91 reset value: 0x00 bit r/w description (for detailed procedur e, refer to application note.) 7:6 w sdcnt: signal detector threshold counter (run mode) 00b: disabled 5:0 w sdthr: signal detector threshold level (run mode) addr: 0x72 and 0x92 reset value: 0x00 bit r/w description (for detailed procedur e, refer to application note.) 7:6 w sdcnt: signal detector threshold counter (run mode) 00b: disabled 5:0 w sdthr: signal detector threshold level (wake up) addr: 0x81 and 0xa1 reset value: 0x00 bit r/w description 5:4 w ndsel: fsk noise detector selection 00b: squelch only (signal power) 01b: fsk noise detector only (noise power) 10b: both (squelch and fsk noise detector) 11b: squelch and (fsk noise detector and sigdetlo threshold) 3:2 w nd(3:2): fsk noise detector configuration:: threshold level always 01b 1:0 w nd(1:0) fsk noise detector configuration: peak detector slew rate always 11b tda523x functional description data sheet 84 version 4.0, 2007-06-01 dual: asigdetlo and bsigdetlo : signal detector threshold low level dual: asigdetsel and bsigdetsel : signal detector factor selection addr: 0xb6 and 0xb7 reset value: 0x00 bit r/w description (for detailed procedure refer to application note.) 7 w sdlore: source selection of ask noise power status register 0: ask noise for sigdet0/1 1: signal for sigdetlo if enabled, the sigdetlo level can be read out with asknp status register 6 w sdsel: manual selection of sigdet range 0: disable (default) - sigdet0/1 r ange selection factor automatically done; depending on datarate 1: enable - use sigdetsel control to set the valid range 5:0 w sdlothr: signal detector threshold low level. this threshold level is only valid, if the fsk noise detector selection in the ndconfig register is set to ?11b? addr: 0xb8 and 0xb9 reset value: 0x0a bit r/w description 3:2 w sdsello: sigdetlo range selection factor 00b: 2 01b: 4 10b: 6 (default value) 11b: 8 the selected signal detector value is divided by the 2^range selection factor. use the correct setting to fit the measured asknp value. 1:0 w sdsel: sigdet0/1 range selection factor 00b: 4 01b: 6 10b: 8 (default value) 11b: 10 the selected signal detector value is divided by the 2^range selection factor. use the correct setting to fit the measured asknp value. data sheet 85 version 4.0, 2007-06-01 tda523x functional description 2.4.10 digital fsk demodulator figure 43 digital fsk demodulator the digital fsk demodulator has three major units: ? digital down converter ? cic filter ? demodulator digital down converter the output signal of the limiter amplifie r at an if-center-frequency from 10.7 mhz is converted to near baseband by an i/q mixer, driven from a programmable direct digital synthesizer. the programming of the direct digital sy nthesizer is done with the registers fsknco0, fsknco1 and fsknco2. nco value calculation: TDA5230: for lo-side lo injection mode operation: direct digital synthesizer from if-limiter fsknco0 fsknco1 fskfilbw0 q i fskdembw0 decim ation to digital- receive r fskfilbw1 fskdembw1 digital-down-converter fsknco2 cic decimator scaling q i scalin g demodulator dam fskdembw2 filter cic decimator scaling noise detection ndthres ndconfig fsknp ? ? ? ? ? ? ? ? ? ? ? ? = sys if sys sys dec f f f f round nco ) ( 4 * 2 24 tda523x functional description data sheet 86 version 4.0, 2007-06-01 this value must be converted to hex format and written to the registers fsknco2 fsknco1 and fsknco0, where fsknco2 is the msb register. the calculation above is fully automatically performed by the iaf tda523x configuration tool! dual: afsknco0 and bfsknco0 : fsk dds nco frequency offset dual: afsknco1 and bfsknco1 : fsk dds nco frequency offset dual: afsknco2 and bfsknco2 : fsk dds nco frequency offset cic filter the cic decimation filter is used for ban dwidth reduction. the selectable pre-filter bandwidths are identified in the following table: tda2531: for hi-side lo injection mode operation: addr: 0x78 and 0x98 reset value: 0x00 bit r/w description 7:0 w ncoinc: fsk nco register bits (7:0) lsb addr: 0x79 and 0x99 reset value: 0x00 bit r/w description 7:0 w ncoinc: fsk nco register bits (15:8) addr: 0x7a and 0x9a reset value: 0x00 bit r/w description 7:0 w ncoinc: fsk nco register bits (23:16) msb nco value calculation (for the register fsknco0, fsknco1 and fsknco2) ? ? ? ? ? ? ? ? ? ? ? = sys if sys dec f f f round nco 4 * 5 * 2 24 data sheet 87 version 4.0, 2007-06-01 tda523x functional description the selection is done with the registers fskfilbw0 and fskfilbw1. the cic-filter also requires a comb delay a nd a scaling. for the comb delay, a value of 8 must be used. the scaling is calculated as below: sca... scaling r...decimation factor(=fskfilbw0+1) m...comb delay value(=8 +1= 9) the calculation above is fully automatically performed by the iaf tda523x configuration tool! dual: afskfilbw0 and bfskfilbw0 : fsk pre filter decimation setting typical 3db bandwidth 1) 1) values are only ?about? values and should be used for orientation only. bandwidth is also dependent on if filter, fsk deviation, data rate and different configuration settings. fskdec setting +/-250 +/-80khz 0001b recommended +/-125 +/-50khz 0011b +/-62.5 +/-40khz 0111b +/-31.25 +/-20khz 1111b addr: 0x7b and 0x9b reset value: 0x00 bit r/w description 3:0 w fskdec: fsk pre filter decimation factor 0001b: 250 prefilter bandwidth .. recommended 0011b: 125 prefilter bandwidth 0111b: 62.5 prefilter bandwidth 1111b: 31.25 prefilter bandwidth [ ] 4 ) * ( log 14 2 + ? = m r round sca tda523x functional description data sheet 88 version 4.0, 2007-06-01 dual: afskfilbw1 & bfskfilbw1 : fsk pre filter scaling fsk demodulator: the fsk demodulator is based on a delay and multiply principle (dam). the required settings are the dam delay, the decimation fa ctor (iddec) of the data filter and a final scaling (id scaling). id decimation: iddec...integrate and dump decimation rfskcic...decimation factor fsk cic filter(=fskfilbw0+1) rdatafilter...decimation factor data filter(=datfilt1+1) f data ...datarate id scaling: idsca...integrate and dump scaling iddec...integrate and dump decimation(=fskdembw1) the calculations above are fully automatically performed by the iaf tda523x configuration tool! addr: 0x7c & 0x9c reset value: 0x00 bit r/w description 6:4 w fsksca: fsk pre filter scaling 3:0 w fskdel: fsk pre filter comb delay setting use 1000b 1 * * * 16 ? ? ? ? ? ? ? ? ? = data datafilter fskcic sys f r r f round iddec )) 1 ( (log 2 + = iddec floor idsca data sheet 89 version 4.0, 2007-06-01 tda523x functional description dual: afskdembw0 and bfskdembw0 : fsk demodulator sensitivity dual: afskdembw1 and bfskdembw1 : fsk dam output decimation dual: afskdembw2 and bfskdembw2 : fsk dam output scaling noise detector: to decide whether there is a data signal or simply noise at the output of the demodulator, there is a noise detector implemented. the prin ciple is based on a power measurement of the demodulated signal. the current noise powe r is stored in the fsknp register and is updated at every spi controller access. the noise detector is useful if data signal is transmitted with small fsk deviations. further information about the use of the noise detector is found in chapter 2.4.9.2 data filter and signal detection . 2.4.11 clock recovery the clock recovery uses the peak from th e matched filter as reference and generates the recovered clock. the second main functionality is the generation of the symbol synchronization found indication. this gener ally happens within the first 4 bits. addr: 0x7d and 0x9d reset value: 0x00 bit r/w description 7:4 w not used 3:0 w damdly: fsk demodulator sensitivity use 0100b addr: 0x7e and 0x9e reset value: 0x00 bit r/w description 7:0 w damdec: fsk dam decimation addr: 0x7f and 0x9f reset value: 0x00 bit r/w description 3:0 w damsca: fsk dam output scaling tda523x functional description data sheet 90 version 4.0, 2007-06-01 figure 44 clock recovery (adpll) clock-recovery is realized as standard adpll 1) pi-regulator with ti ming-extrapolation unit for fast setting. the clock recovery locks after 4 correct manchester coded bits, independent of duty cycle (35%, 65%) and data rate (+10%, -10%). after locking, the clock must be stable and has to follow the reference input. therefore, a rapid setting procedure and a slow pll are achieved. if the pll is locked the reference signal from th e clock recovery slicer is used in the phase detector block to compute the actual error. the error is used in the pi loop filter to set the digital controlled oscillator running frequency. for the p, i and timing extrapolation unit settings the default valu es for the cdr0 and cdr1 control registers should be used. in the unlocked state, the timing extrapol ation unit calculates the frequency offset for the incoming data stream. if 4 correct manche ster coded bits are detected, the runin length can be set in the cdr2 register, the i-pa rt and the pll oscillator will be set and the pll will be locked. 1) all digital pll timing extrapolation from slicer symbol sync found eom cdr2 (runlen) tsimode (tsigrsyn) recovered clock phase detector loop filter digital controlled oscillator tvwin tsigap (gapval) cdr0 cdr1 t nom / 16 t nom / 2 t nom / 2 data sheet 91 version 4.0, 2007-06-01 tda523x functional description the pll will be unlocked if a code violation of more than the defined length is detected, which is set in the tvwin control register. an other criterion for pll re-synchronization is an end of message (eom) signalled by the framer block. the pll oscillator generates the manchester clock (2 * f data ). the internal pll lock signal used by the framer is generated up to 1 bit before runin ends. the timing extrapolation unit counts the incoming edges and interprets the delay between two edges as a bit or a chip. due to the fact that the first edge of a low bit, coded as ?0? and ?1,? rises one chip later than a ?hig h? bit, the pll locks later in this cases. this can be seen in the figure below. the real needed runin time can be shorter than the configured runin length in the cdr2 regis ter by up to two chips. this should be considered when setting the tsi patt ern and/or tsi length. see also chapter 2.4.13 frame synchronization figure 45 runin generation principle number of required runin bits: the number of runin bits specified in sfr runlen must always be 3.5. this setting defines the duration of the internal synchr onisation. because of internal processing delays, the pattern length that must be reserved for runin is longer. the ideal runin pattern is a series of either 1?s or 0?s. this pattern includes the highest number of edges that can be used for synchronisation. in this case the number of runin bits is 4. for any other runin pattern, 5.5 bits should be reserved for runin. 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 runin first edge 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 runin first edge 0 1 4 bits detected 4 bits detected tda523x functional description data sheet 92 version 4.0, 2007-06-01 tvwin cv window length the pll unlocks if the reference signal is lo st for more than the time defined in the tvwin register. during the tsi gap (see tsi gap mode) the pll and the tvwin are frozen. the tvwin time is the time that digrx s hould stay locked without incoming signal edges detected. the time resolution is t/16. tvwin is calculated as follows: cv is the number of code violations in a block. this calculation is done by iaf tda523x configuration tool, if the number of cv?s is entered. dual: acdr0 and bcdr0 : clock recovery p parameters dual: acdr1 and bcdr1 : clock recovery i parameters addr: 0x73 and 0x93 reset value: 0x00 bit r/w description 7:6 w pdsr: peak detector slew rate use 11b 5 w phden(1): phase detector er ror (pde) outer tolerance range use 1b 4 w phden(0): phase detector error (pde) inner tolerance range use 0b 3:2 w pval: p value use 01b 1:0 w psat: p value saturation use 10b addr: 0x74 and 0x94 reset value: 0x00 bit r/w description 7:6 w corsat: correlator output value (timing extrapolation unit) use 01b 5:4 w lfsat: loop filter saturation use 10b tvwin round 8 16 cv ? 8 ++ () 1,25 ? () = data sheet 93 version 4.0, 2007-06-01 tda523x functional description dual: acdr2 and bcdr2 : clock recovery runin length dual: atvwin and btvwin : cv window length 3:2 w ival: i value use 01b 1:0 w isat: i value saturation use 01b addr: 0x75 and 0x95 reset value: 0x00 bit r/w description 1:0 w runlen: runin length use 01b: 3 1/2 bit addr: 0x77 and 0x97 reset value: 0x00 bit r/w description 7:0 w tvwin: cv window length 28h: 40/16 bits ffh: 255/16 bits addr: 0x74 and 0x94 reset value: 0x00 bit r/w description tda523x functional description data sheet 94 version 4.0, 2007-06-01 2.4.12 wake up generation unit figure 46 wake up generation unit the wake up generation unit is used only in the self polling mode for the detection of a predefined wake up criterion in the receiv ed pattern. all sfrs configuring the wake up generation unit support the dual configuration capability (config a and b). the search for wake up criteria is started if symbol sy nchronization is given within the duration of four symbols (runin); otherwise the wake up search is aborted. during the observation period, the wake up search is aborted immediately if symbol synchronization is lost. if this is not the case, the wake up search will last for the number of chips defined in the register wubcnt. the wake up window (wuw) chip counter counts the number of received chips and compares this number vs. the number of chips defined in the register wubcnt. the code violation detector checks the in coming chip data stream for being manchester coded. a code violation is given if three consecutive chips are ?one? or ?zero? 16-chips shift register pattern detector bit change detector wakeup window chip counter wuc wubcnt wupat0 wupat1 chip data chip data clock ssync wu wakeup generation fsm no wu ssync search time elapsed code violation detector 015 2 wuw chip counter elapsed code violation detected bit change detected pattern detected 3 16 data sheet 95 version 4.0, 2007-06-01 tda523x functional description the bit change detector checks the incoming manchester coded bit data stream for changes from 'zero' to 'one' or 'one' to 'zero'. this is the case if two consecutive chips are ?one? or ?zero?. the pattern detector is searching for a pattern with 16 chips length within the wake up window. the pattern is configurable via the register wupat0 and wupat1. the selection of 1 out of 4 wake up criteria is done via the wuc register: the four wake up criteria are in detail: pattern detection the incoming signal must match a dedicated pattern of up to 8 bits or 16 chips. when the wuw chip counter elapses, the search is stopped. the higher the setting of wubcnt the longer it is possible to search for the wake up pattern. the minimum for the wubcnt is 0x11! the pattern detection is stopped either when wuw elapses, or symbol synchronization is lost. equal bits detection wake up condition is fulfilled if all received bits inside of wuw are either 0 or 1. wubcnt holds the number of required eq ual bits. the higher the setting of wubcnt the lower the number of wrong wake ups. equal bits detection is stopped if a wrong bit has been detected, or symbol synchronization is lost. random bits detection wake up condition is fulfilled if there is no code violation inside of wuw. wubcnt holds the number of required manchester coded bi ts. the higher the setting of wubcnt, the lower the number of wrong wake ups. random bits detection is stopped if a code violation has been detected, or symbol synchronization is lost. valid data rate detection wake up condition is fulfilled if symbol sy nchronization is possible inside of sync search time out, which is by default 7.625 dat a bits long. wubcnt is not used. this is the weakest wake up criterion, and should be avoided. tda523x functional description data sheet 96 version 4.0, 2007-06-01 figure 47 wake up criteria search dual: awuc and bwuc : conf.a wake up control register dual: awupat0 and bwupat0 : conf.a wake up detection pattern0 addr: 0x25 and 0x46 reset value:0x00 bit r/w description 1:0 w wucrt: wake up criteria 00b: pattern detection 01b: random bits 10b: equal bits 11b: wake up on symbol sync, valid data rate; the wubcnt register has no meaning in this mode. addr: 0x26 and 0x47 reset value:0x00 bit r/w description 7:0 w wupat0: wake up detection pattern: bit 7...bit 0(lsb) (in chips) reset wu= 0 no wu=0 idle pattern detection random bits detection equal bits detection ssync=1 wakeup crit eria=random bits detect ion no wake-up wu= 1 no wu=0 wake-up ssync search time elapsed =1 wu= 0 no wu=1 wu= 0 no wu=0 ssync=1 wakeup criteria=pattern detection ssync=0 ssync=0 wu= 0 no wu=0 wu= 0 no wu=0 init wakeup unit pattern match=1 wuw chip counter < wubcnt ssync=0 cv=1 wuw chip counter < wubcnt wuw chip count er tda523x functional description data sheet 98 version 4.0, 2007-06-01 2.4.13 frame synchronization the frame synchronization unit (framer) synchronizes to a specific pattern to identify the exact start of a data frame. this pattern is called tsi (telegram start identifier). there are different tsi modes se lectable via the configuration: ? tsi mode 16-bit, supporting a tsi length up to 16 bits or 32 chips ? tsi mode 8-bit, supporting two indepe ndent tsi pattern of up to 8 bits length ? tsi gap mode 8-bit, supporting the tsi gap mode ? tsi mode 8-bit extended, identical to ts i mode 8-bit, but identifies which pattern matches by adding a single bit to the data frame all sfr configuring the frame synchronizat ion generation unit are supporting the dual configuration capability (config a and b). the framer starts working in slave mode after symbol sync found and in self polling mode after wake up found and searches for a frame until tsi is found or synchronization is lost. the input of the framer is a sequence of manchester coded data (chips). basicall y the framer consists of two identical correlators of 16 chips in length. it allows a telegram start identifier (tsi) to be composed of manchester coded ?zeros? and ?ones?. the active length of each of the 16 chips correlators is defined independently in the tsilena and tsilenb registers. the pattern to match is defined as sequence of chips in the tsipta0, tsipta1, tsiptb0 and tsiptb1 registers. note that the runin length shown in the figures below is the maximum needed runin with the length of 8 chips set in the register. the needed runin time of the receiver can be shorter by 1-2 chips. it depends on the expected data rate error, duty cycle error, and the starting chip sequence of the protocol. data sheet 99 version 4.0, 2007-06-01 tda523x functional description figure 48 frame synchronisation unit the two independent correlators can be configure d in the tsimode register to work in one of the following four modes: 16-bit mode: as a single correlator of up to 32 chips the length of the tsilena register has to be set to 16d whenever tsilenb is higher than 0. chip-data from cr delay-line 16-bit mrb lrb correlator a 16-bit tsipta0 tsi data-pattern msb lsb mux tsipta1 tsi data-pattern msb lsb delay-line 16-bit mrb lrb correlator b 16-bit tsiptb0 tsi data-pattern msb lsb tsiptb1 tsi data-pattern msb lsb chip-data clock correlator b controller tsilenb tsimode fsync eom-detector eom emdatlen emcv emsylo cv sync select correlator a controller frame synchronization controller tsilena corramatch tsigap manchester- decoder code-violation detector from data-slicer eomdtlen data clock data data clock data tsi wild card tsimode(6:3) tda523x functional description data sheet 100 version 4.0, 2007-06-01 figure 49 tsi mode 16-bit 8-bit mode: as two correlators working simultaneously in parallel of up to 16 chips length each in the following example, tsi pattern b matched first and generates a fsync. the lengths of both tsi patterns ar e now independently from each other. figure 50 tsi mode 8-bit 8-bit gap mode: as two sequentially working correlators of up to 16 chips length each this mode is only used in combination with the tsi gap mode! this mode is used to define a gap between the two patterns which is preset in the tsigap register.to identify exactly the beg inning of the gap it would be helpful on occasion to place the first cv of the gap into the tsi pattern a. in this case, the gap length needed for the tsigap register must be shortened and the tvwin length must be extended (see also chapter 2.4.13 frame synchronization ). incoming pattern 0 0 0 0 manchester coded 0 1 0 1 0 0 0 1 1 1 1 1 0 1 0 0 1 0 tsi pattern match 01010101011001100101011010101010011001011001 runin 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 1 0 1 1 0 0 fsync data into fifo 1 0 1 0 0 1 0 tsilena = 16d, tsilenb = 6d 543210 6 7 13121110 9 8 14 15 tsipta 543210 tsiptb incoming pattern manchester coded tsi pattern b match 0101010101100110011001011001 runin 0 0 0 1 1 1 fsync data into fifo 543210 tsiptb tsilena = 16d, tsilenb = 6d 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 data sheet 101 version 4.0, 2007-06-01 tda523x functional description figure 51 tsi mode 8-bit gap 8-bit extended mode: as two correlators working simultaneously in parallel of up to 16 chips length each, with matching information insertion this bit is inserted at the beginning of the payload. ?0? is inserted, when correlator a has matched and ?1? when correlator b has matched. figure 52 tsi mode 8bit extended selection of a tsi pattern: tsi patterns must be different to the wake up bit stream and the runin to clearly mark the start of the following data frame. it shou ld be considered that the sychronization has a tolerance of about one bit. in addition, synchro nization is related to data chips, and may occur in the middle of a data bit. this all must be tolerated by the data framer. ideal tsi patterns have at their end a unique bit combination, which may also contain a number of code violations (cvs). incoming pattern 0 0 0 0 manchester coded 0 1 0 1 0 0 0 1 1 1 1 1 0 1 tsi pattern match 01010101011001000000010101011001010110101010100110 runin 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 1 0 fsync data into fifo 1 0 1 tsilena = 8d, tsilenb = 12d tsigrsyn = 1 0 0 0 0 runin gap 1 1 s 0 0 543210 6 7 1110 9 8 tsiptb 543210 tsipta 6 7 incoming pattern 0 0 0 0 manchester coded 0 1 0 1 0 1 0 0 1 0 tsi pattern b match 0101010101100110011001011001 runin fsync data into fifo 1 0 1 0 0 1 0 tsilena = 16d, tsilenb = 6d 1 matching information inserted 0 0 0 1 1 1 543210 tsiptb tda523x functional description data sheet 102 version 4.0, 2007-06-01 some examples of tsi patterns: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 when cvs are used: 0 0 0 0 0 0 0 0 0 0 0 0 0 m 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 m 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 m note: cvs in a tsi are practical for better differentiation to the real data, especially if repetition of data frames is used for wake up. end of message (eom) detection an end of message (eom) detection feature is provided by the eom detector. three criteria can be selected to indicate eom. the first is based on the number of received bits since frame synchronization. the number of expected bits is preset in the eomdtlen register. sending fewe r bits as defined in the register will result in no eom. the eom counter will be reset after new fram e synchronization. the second criterion is the detection of a manchester code violation. the third criterion is the loss of symbol- synchronization. depending on the tvwin register , the sync signal persists for a certain amount of time after the end of the pattern has been reached. therefore, more bits could be written into the fifo than sent. all three eom criteria can be combined with each other. if one of the selected eom criteria is fulfilled an eom signal will be generated. dual: atsimode and btsimode : tsi detection mode addr: 0x82 and 0xa2 reset value: 0x00 bit r/w description 7 w tsigrsyn: tsi gap resync mode (for detailed information, see atsigap/btsigap register description) 0: off 1: pll reset after tsi gap 6:3 w tsiwca: wild cards for correlator a data sheet 103 version 4.0, 2007-06-01 tda523x functional description dual: atsilena and btsilena : tsi a length dual: atsilenb and btsilenb : tsi b length 2 w mancpaj: manchester code phase readjustment 0: disabled - manchester code polarity is defi ned by the tsi pattern. 1: enabled - the code phase readjustm ent will be done with each ?1001? or ?0110? manchester data change. 1:0 w tsidetmod: tsi detection mode 00b: 16-bit mode - tsi configuration a and b valid (sequentially), b is valid if the atsilenb >0 01b: 8-bit mode - tsi configurations a or b (parallel) 10b: 8-bit gap mode- tsi configurations a and b with gap (sequentially with gap between tsia & tsib) 11b: 8-bit extended mode - tsi confi gurations a or b (parallel with matching information), synchronization will be done on full tsi length, dependent on found tsi a or b, 1 or 0 will be send as 1st received bit. addr: 0x83 and 0xa3 reset value: 0x00 bit r/w description 4:0 w tsi a length (in chips): (0x11 up to 0x1f not used) min: 00h = 0 bit; works only in 16-bit mode: fsync will be generated after symbol synchronization. in other modes, the smallest possible value to generate a fsync will be 01h. be aware that such small values makes it impossible to find the right phase of the pattern in the data stream and therefore incorrect data and code violations can be generated. max: 10h = 16 chips = 8 bit addr: 0x84 and 0xa4 reset value: 0x00 bit r/w description 4:0 w tsi b length (in chips): (0x11 up to 0x1f not used) min: 00h =0 bit (see also atsilena) max: 10h = 16 chips = 8 bit addr: 0x82 and 0xa2 reset value: 0x00 bit r/w description tda523x functional description data sheet 104 version 4.0, 2007-06-01 dual: atsipta0 and btsipta0 : tsi data reference low byte a dual: atsipta1 and btsipta1 : tsi data reference high byte a dual: atsiptb0 and btsiptb0 : tsi data reference low byte b dual: atsiptb1 and btsiptb1 : tsi data reference high byte b dual: aeomc and beomc : eom control addr: 0x86 and 0xa6 reset value: 0x00 bit r/w description 7:0 w tsipta0: data pattern for tsi comparison: bit 7...bit 0(lsb) (in chips) addr: 0x87 and 0xa7 reset value: 0x00 bit r/w description 7:0 w tsipta1: data pattern for tsi comparison: bit 15(msb)...bit 8 (in chips) addr: 0x88 and 0xa8 reset value: 0x00 bit r/w description 7:0 w tsiptb0: data pattern for tsi comparison (in chips) addr: 0x89 and 0xa9 reset value: 0x00 bit r/w description 7:0 w tsiptb1: data pattern for tsi comparison (in chips) addr: 0x8a and 0xaa reset value: 0x00 bit r/w description 3 w not used: always set to 0 2 w emsylo: eom by sync loss 1) 1) the eom criteria can be combined. 1 w emcv: eom by code violation 1) 0 w emdatlen: eom by data length 1) data sheet 105 version 4.0, 2007-06-01 tda523x functional description dual: aeomdtlen and beomdtlen : eom data length limit tsi gap mode the tsi gap mode is only used if tsi patterns contain a gap that is not synchronous to the data rate, e.g. if a gap is 7.7 data bits, or if a gap is longer than 10 data bits. in all other cases, gaps should be included in the tsi pattern as code violations. because of its complexity in configuration, tsi gap mode should be used only in applications as noted above! for these special protocols, it is possible to lock the actual frequency during a long code violation period inside a tsi (tsigap must possess a minimum of 8 chips). after the lock period, two different re-synch ronization modes are available: ? preferred: phase readjustment only, tsigrsyn = 0. in this mode, the gapval value is used to correct the phase after the gap phase. overall gap time can be defined in t/16 steps. the 5 msb bits define the real gap time and the 3 lsb bits (gapval) the dco phase correction value. figure 53 clock recovery gap re-synchronization mode 0 ? frequency readjustment (in thi s case, pll starts from the beginning), tsigrsyn = 1. in this mode the t/2 gap resolution can be set in the 5 msb tsigap register bits. gapval (3 lsb register bi ts) value is not used. addr: 0x8b and 0xab reset value: 0x00 bit r/w description 7:0 w datlen: length of data field in telegram counting starts after the last tsi bit min: 00h = the next bit after tsi found (w hen eom criterion is emdatlen) will generate eom max: ffh tsi a tsi gap gapsync tsi b valid data valid data all space or all mark clock recovery phase readjustment start point pll sync runin < 1bit tda523x functional description data sheet 106 version 4.0, 2007-06-01 figure 54 clock recovery gap re-synchronization mode 1 when the time tsi gap in the start s equence of the transmitted tel egram has elapsed, the receiver needs a certain time (gapsync = 5...6 chips) to readjust the pll settings. behavior of the system at the starting position of the tsi b: the starting position (tsi b start) for the tsi b comparison is independent from the runin settings (cdr2 register) and the re- synchronization mode (tsimode register): the incoming chips at tsi b start and the following incoming chips are compared with the contents of the register ts i b. please notice that the receiver?s pll runs at the data rate determined before the gap. therefore, the receiver calculates the gap based on this data rate. behavior of the system at the ending position of tsi b: the system checks for the tsi b to match withi n a limited time. if there is no match within this time, then the receiver starts again to search for the tsi a pattern at the following incoming chips: for a successful tsi b pattern match, the defined tsi b pattern must be between ?start of tsib? and ?stop of tsi b?. in the example be low, the earliest possible start position would be the 18 th chip and the latest possible start position would be the 22 nd chip. please note that after a gap the internal tsi comparison register is cleared (all chips set to ?0?). in this case, a tsi b criteria of ?0000? would always match at the beginning. to avoid such an unwanted matching, set the highest tsi b match chip to ?1?. tsi a tsi gap tsi b valid data valid data a l l s p a c e o r a l l m a r k clock recovery reset start point pll sync internal pll sync runin gapsync < 1bit < 1bit t sibstart chips [] tsigap chips [] 6 8 + = tsibstop chips [] tsigap chips [] tsilenb chips [] 11 ++ = data sheet 107 version 4.0, 2007-06-01 tda523x functional description figure 55 tsigap tsib timing the next figure shows the tvwin and tsigap dependency. figure 56 tvwin and tsigap dependency example tvwin calculation for pattern without gap time: the entire tvwin time is made up of the cv 1) number itself, the half bit before cv and the half bit after the cv. to reach all frequency and duty cycle errors, 25% of the overall sum must be added. tvwin calculation with gap time: 1) cv...number of bits contai ning manchester code violations incoming pattern[bits] ... 0 0 1 0 1 0 0 0 1 1 1 1 1 runin 0 0 0 0 gapsync tsigap=10 chips s tsia _ _ _ _ _ tsibstart 1 start of tsib comparison 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 tsib 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 stop of tsib comparison cv tvwin tvwin gap tvwin tsia tvwin without gap tvwin with gap int. delay runin/ tsig rsyn = 1 tvwin round 8 16 cv ? 8 ++ () 1,25 ? () = tda523x functional description data sheet 108 version 4.0, 2007-06-01 dual: atsimode and btsimode : tsi detection mode dual: atsigap and btsigap : tsi gap addr: 0x82 and 0xa2 reset value: 0x00 bit r/w description 7 w tsigrsyn: tsi gap resync mode (for detailed information, see atsigap/btsigap register description) 0: off 1: pll reset after tsi gap 2 w mancpaj: manchester code phase readjustment 0: disabled - manchester code polarity is defined by the tsi pattern. use as default, if tsi 8bit gap mode is not used 1: enabled - the code phase readjustm ent will be done with each ?1001? or ?0110? manchester data change. use for tsi 8bit gap mode addr: 0x85 and 0xa5 reset value: 0x00 bit r/w description 7:3 w tsigap: tsi gap (t/2 bit resolution) 1fh: 15 1/2 bit gap 00h: 0 bit gap tsigap is used to lock the pll after tsi a is found, if the tsi detection mode 10b is selected. 2:0 w gapval: tsi gap (t/16 bit resolution) 111b: 7/16 bit gap 000b: 0 bit gap gapval is used to correct the dco phase after tsigap time, if the tsimode.tsigrsyn is disabled tvwin round max 8 16 cv ? 8 ++ () 1,25 ? () 816tsia ? cv 16 1 ? 8 +++ () 1,25 ? , {} () = data sheet 109 version 4.0, 2007-06-01 tda523x functional description pre-slicer setting: during the gap time there is high sensitivity to jammer, especially if the jammer is close to the bit rate or 1/2 bit rate. the pre-slicer helps to suppress jammer during the gap time. therefore, in tsi gap mode, and in tsi gap mode only should the pre-slicer be enabled using the default settings. dual: apslc and bpslc : pre slicer control addr: 0xb4 and 0xb5 reset value: 0x00 bit r/w description 7 w pslcda: pre-slicer disable 0: pre-silcer enable...use only for tsi gap mode 1: pre-slicer disable (default) 6:5 w pslchys: pre-slicer hysteresis use 01b 4:0 w pslcthr: pre-slicer disable threshold use 10010 (0x12) tda523x functional description data sheet 110 version 4.0, 2007-06-01 2.4.14 message-id scanning hardware description this unit is used to define an id or specia l combination of bits in the data stream, which identifies the pattern. all sfrs configuring the message id scanning unit feature the dual configuration capability. furthermore, it is available in the slave and self polling mode. the mid unit can be mainly configur ed in 2 modes: 4-byte and 2-byte organized message id. for each configuration there are 20 8-bit registers designed for id storage (mid0...mid19). the midc0 and midc1 are used to configure the mid unit: enabling of the mid scanning, setting of the id storage organization, the starting position of the comparison and number of bytes to scan. when the message id scanning unit is activated by the midc1, the incoming data stream is compared bit-wise serially with all stored ids. if the scan end position is reached and all received data have matched the observed part of at least one mid, the message id scanning unit indicates success ful mid scanning to the master fsm, which generates a mid interrupt. please note that the default register value of the mid registers is set to 0x00. all mid registers must be set to a pattern value to avoid matching to default value 0x00. if the mid unit finishes id matching without success, the data receiving is stopped and the fsm waits again for a frame start criterion. the received bits are still stored in the fifo. for details see also chapter 2.4.15 data fifo . data sheet 111 version 4.0, 2007-06-01 tda523x functional description 4-byte organized message id in this mode four bytes are merged to define an id pattern. this does not mean that the id must be exactly four bytes long. the nu mber of bytes used there is defined in the midc1 register. up to 5 id patterns are available. figure 57 4-byte message-id scanning line selector combiner line number mid0 8 mid1 8 mid2 8 mid3 8 mid4 8 mid5 8 mid6 8 mid7 8 mid8 8 mid9 8 mid10 8 mid11 8 mid12 8 mid13 8 mid14 8 mid15 8 mid16 8 mid17 8 mid18 8 mid19 8 32 mid0:mid3 32 mid4:mid7 32 mid8:mid11 32 mid12:mid15 32 mid16:mid19 control- fsm data clock midc0 midc1 mid scanning finished bit counter s c a n n e r bit0 bit31 scan start position reached scan end position reached mid found enable mid scanning init mid scanner interface to master fsm data from digital-receiver mid match number to scan organization number of startbit enab le scanner tda523x functional description data sheet 112 version 4.0, 2007-06-01 4-byte organized message id in this mode two bytes are merged to define an id pattern. up to 10 patterns are possible. figure 58 2-bytes message id scanning id position configuration line selector combiner lin e nu mber mid0 8 mid1 8 mid2 8 mid3 8 mid4 8 mid5 8 mid6 8 mid7 8 mid8 8 mid9 8 mid10 8 mid11 8 mid12 8 mid13 8 mid14 8 mid15 8 mid16 8 mid17 8 mid18 8 mid19 8 control- fsm data clock midc0 midc1 mid scanning finished bit counter s c a n n e r bit0 bit15 scan start position reached scan end position reached mid found enable mid scanning init mid scanner interface to master fsm data from digital-receiver mid match number to s ca n organization number of startbit enable scanner 16 mid0:mid1 16 mid2:mid3 16 mid4:mid5 16 mid6:mid7 16 mid8:mid9 16 mid10:mid11 16 mid12:mid13 16 mid14:mid15 16 mid16:mid17 16 mid18:mid19 data sheet 113 version 4.0, 2007-06-01 tda523x functional description it is possible to choose which part of the incoming data stream is compared against the stored mids. the register midc0 contains th e scan start position (bit 0 to bit 127). if the bit counter detects the scan start position the control fsm enables the scanner. the register midc1 contains the number of by tes to scan (byte 0 to byte 3). during the observation period, the message id scanning is aborted immediately by the master fsm if symbol synchronization is lost or an eom (end of message) is detected. example: start selection: 0010001b number to scan: 00b, 01b, 10b, 11b figure 59 id scanning the starting position in this case is bit 17. depending on the number to scan, the corresponding number of bytes is compared with the stored mids. dual: amid0 - amid19 and bmid0 - bmid19 : conf.a message id register0 dual: amidc0 and bmidc0 : conf.a message id control register0 addr: 0x29 - 0x3c and 0x4a - 0x5d reset value:0x00 bit r/w description 7:0 w mid0: message id register addr: 0x3d and 0x5e reset value:0x00 bit r/w description 6:0 w sp: mid scan start position min: 00h = comparison starts one bit after fsync max: 7f = comparison starts 128 bits after fsync 012 byte0 fsync byte2 byte3 start mid scan number to scan=00b number to scan=01b number to scan=10b number to scan=11b bit 17 18 24 25 26 27 33 34 35 36 42 43 44 45 51 52 53 byte0 byte0 byte0 byte1 byte1 byte2 first data bit byte1 tda523x functional description data sheet 114 version 4.0, 2007-06-01 dual: amidc1 and bmidc1 : conf.a message id control register1 addr: 0x3e and 0x5f reset value:0x00 bit r/w description 3 w midsen: enable id screening 0: disabled 1: enabled 2 w midbo: message id organization 0: 2-byte 1: 4-byte 1:0 w midnts: message id number of bytes to scan min: 00b = 1 byte to scan max for 2-byte organization: 01b: 2 bytes to scan. higher values than 01b will be mapped automatically to 2 bytes to scan max for 4-byte organization: 11b= 4 bytes to scan data sheet 115 version 4.0, 2007-06-01 tda523x functional description 2.4.15 data fifo the data fifo is the storage for the received data frames. it is written during data reception. the host microcontroller is able to start reading via spi right after frame sync (interrupt). the fifo can store up to 128 received data bits. if the expected data transmission contains more bits (note that in tsi 8-bit mode extended the first bit is used to indicate which of the two tsi pattern has matched), reading must start after frame sync to prevent an overrun. architecture: the 128-bit data fifo is based on a bit addressable 2-port memory architecture. figure 60 data fifo the write port is controlled by the digital receiver using the write address pointer. writing data into the fifo starts with the detection of a tsi. the write address pointer is incremented with each data clock signal gene rated by the digital receiver. the read port is controlled by the spi controller using the read address pointer. each bit read from the spi controller increments the read address pointer. the read and write write address pointer (up-counter) 1 of 8 decoder 1 of 16 decoder byte 0 reset byte 3 byte 2 byte 1 byte 4 byte 7 byte 6 byte 5 byte 8 byte 11 byte 10 byte 9 byte 12 byte 15 byte 14 byte 13 out 0 1 2 3 4 5 6 7 bit-address 0 1 2 3 4 5 6 7 in from digital- receiver data clock fsync data eom 1 of 16 decoder 8 to 1 mux read address pointer (up-counter) reset bit-address sclk write-port read-port enable sdo sdo-frame generator to spi-bus fifo- controller enable fifo-overflow # of valid bits fifolk 128-bit memory-array from digital- receiver initfifo initfifo fsinitfifo from fsm fifolk to fsm tda523x functional description data sheet 116 version 4.0, 2007-06-01 address pointers jump from their maximum value (127 d ) to address zero. writing to the fifo stops at eom or after sync loss. fifo lock behavior the fifo possesses a lock mechanism that is enabled via the sfr control bit fifolk in cmc0 register. if this mechanism is enabled , the fifo will enter a fifo lock state at the detection of the eom criterion. during the time that the fifo is locked, it is not possible for additional data to be received in the run mode self polling. this means that it is only possible to detect another wake up in the self polling mode, but no more data in the run mode self polling. this will guarantee that only the first complete data packet is stored in the fifo. the fifo will remain locked unless one of three conditions occurs: 1.) the remaining contents of the fifo are completely read out via the spi 2.) the sfr control bit fifolk is cleared. 3.) initfifo at cycle start is set in the cmc0 register and a) fsm is switched to run mode slave or b) fsm switches from self polling mode to run mode self polling figure 61 fifo lock behavior wait till fifo is empty write data into fifo fifo lock eom=0 initfifo (init fifo@ cycle start) = 1 accept data fifo empty=1 fifolk=0 eom=1 fifolk=1 eom=1 fifolk=0 fifo empty = 0 fifolk=1 data sheet 117 version 4.0, 2007-06-01 tda523x functional description known problem on using fifo lock in combination with eom interrupt in run mode slave: indifferent to the described behavior in run mode slave, the nint sticks low for low active interrupt or high for high active in terrupt, after an eom interrupt, if fifo lock is enabled. nint is reset after reading the fifo. see also chapter 2.4.17 interrupt generation unit . fifo status word the fifo status word is mixed to fifo spi transmission, and shows if there was an overflow, and how many valid data bits are tr ansmitted. the number of valid fifo bits is indicated at bit positions s0 to s5. s6 of the status word is always undefined. figure 62 spi data fifo read if the write address pointer outruns the read address pointer, an overflow is indicated in the fifo overflow status bit in the fifo read status word at position s7. all 32 fifo bits and the bits s5 to s0 of the status wo rd are undefined while the overflow status bit is set. if a tsi is detected after an overflow, the fifo overflow status bit is cleared and the entire data fifo is initialized. initialization additionally there are two possibilities to initialize the data fifo. ? if the initfifo bit is set in the cmc0 register(?init fifo at cycle start?) the entire data fifo is always initialized a.) after switching to run mode slave or b.) switching from self polling mode to run mode self polling. ? if the fsinitfifo-bit in cmc1 register is set, the entire data fifo is initialized when a tsi is detected and the data fifo is not locked (?init fifo at frame start?). 32 fifo bits sdi sdo high impedance z d0 d1 d30 d31 i7 i6 i1 i0 s7 s6 s1 s0 status word tda523x functional description data sheet 118 version 4.0, 2007-06-01 cmc0 : chip mode control register 0 cmc1 : chip mode control register 1 2.4.16 transparent mode in addition to the fifo functionality, the TDA5230 offers the received data in a transparent mode. in this mode, the manches ter decoded data is available at an external pin. this is the same data that is written into the fi fo. this means that data is only available after a frame synchronization. wake up pattern, runin and tsi are not visible. if the fifo is locked, no data will be written in the tranparent mode. two pins can be configur ed to act as the rx data output (clkout/rxd or alternatively rx-run/rxd). the pin nint/nstr acts as a data strobe signal. the strobe signal is active high and has a delay of tbit/16 relati ve to the data bit and a duration of tbit/16. configuration of the transparent m ode is done in the cmc1 register. addr: 0x02 reset value: 0x40 bit r/w description 7 w initfifo: init fifo at cycle start this initialization of the fifo can be configured in both slave mode and self polling mode. in slave mode, this occurs at the beginning of the slave run mode. in self polling mode, the initialization is done after wake up found (switching from self polling mode to run mode self polling). 0: no init 1: init fifo 4 w fifolk: lock data fifo at eom 0: fifo lock is disabled 1: fifo lock is enabled at eom (see also chapter fifo) addr: 0x03 reset value: 0x00 bit r/w description 3 w fsinitfifo: init fifo at frame start 0: no init 1: init data sheet 119 version 4.0, 2007-06-01 tda523x functional description figure 63 transparent mode cmc1 : chip mode control register 1 addr: 0x03 reset value: 0x00 bit r/w description 2 w clkrxdsel: clkout/rxd pin function 0: clkout at pin clkout/rxd 1: rx-data out at pin clkout/rxd 1 w nintnstrsel: nint/nstr pin function 0: interrupt out at pin nint/nstr 1: rx-data strobe out nint/nstr 0 w rxrunrxdsel: rx-run/rxd pin function 0: rx-run signal out at pin rx-run/rxd 1: rx-data out at pin rx-run/rxd d n d n+1 t bit /16 t bit /16 rxd nstr tda523x functional description data sheet 120 version 4.0, 2007-06-01 2.4.17 interrupt generation unit the interrupt generation unit receives all possible interrupts and sets the nint signal based on the configuration of the interrupt mask register (im). the interrupt status register is set from the interrupt generati on unit, depending on which interrupt occurred. the polarity of the interrupt that is routed to the nint/nstr pin is defined in the cmc1 register. please note that during power up and brown out reset, the polarity of the nint/nstr pin is always as described in chapter 2.4.2 chip reset . a reset event has the highest priority. it sets all bits in the status re gister to ?1? and sets the interrupt pin to ?0?. the first interrupt after the reset event will clear the status register and will set the interrupt pin to ?1?, even if this interrupt is masked. a wake up interrupt clears the fsynca, fsyncb and the complementary wake up flag. a fsync interrupt clears the eoma, eomb, mi da, midb and the complementary fsync flag. the interrupt status register is always cleared after it is read via spi. it is not possible to disable the power on reset indicator interrupt using the interrupt mask register. figure 64 interrupt generation unit is interrupt-mask interrupt-signalling im data clock wake up cfg a eom cfg a message id cfg a fsync cfg a wake up cfg b eom cfg b message id cfg b fsync cfg b power-up / brown out nintpol data strobe reset eomb wub fsyncb midb eoma wua fsynca mida pin function from digital receiver nint nint/nstr pin nintnstrsel data sheet 121 version 4.0, 2007-06-01 tda523x functional description figure 65 interrupt generation waveform known problem on using eom interrupt in combination with fifo lock in run mode slave: in difference to the described behavior in run mode slave nint sticks low for low active interrupt or high for high active interrupt, a fter an eom interrupt, if fifo lock is enabled. nint is reset after reading the fifo. see also chapter 2.4.15 data fifo . cmc1 : chip mode control register 1 addr: 0x03 reset value: 0x00 bit r/w description 5 w nintpol: invert nint polarity 0: the interrupt is active low 1: the polarity of the interrupt is inverted (active high) 1 w nintnstrsel: nint/nstr pin function 0: interrupt out at pin nint/nstr 1: rx-data strobe out nint/nstr fsync(a,b) reset wu(a,b) mid(a,b) eom(a,b) nint/nstr cmc1/nintpol cmc1/nintnstrsel is x ff 01 03 07 0f 1c 30 70 f0 spi read is 00 configb configa tda523x functional description data sheet 122 version 4.0, 2007-06-01 is : interrupt status register im : interrupt mask register addr: 0x04 reset value: 0xff bit r/w description 7 c eomb: end of message config.b reset event sets all bits to 1 6 c midfb: message id found config.b reset event sets all bits to 1 5 c fsyncb: frame sync config.b reset event sets all bits to 1 4 c wucfb: wake up criteria found config.b reset event sets all bits to 1 3 c eoma: end of message config.a reset event sets all bits to 1 2 c midfa: message id found config.a reset event sets all bits to 1 1 c fsynca: frame sync config.a reset event sets all bits to 1 0 c wucfa: wake up criteria found config.a reset event sets all bits to 1 addr: 0x05 reset value: 0x00 bit r/w description 7 w imeomb: mask end of message config.b 0: no mask(active) 1: mask(inactive) 6 w immidfb: mask message id found config.b 0: no mask(active) 1: mask(inactive) 5 w imfsyncb: mask frame sync config.b 0: no mask(active) 1: mask(inactive) 4 w imwucfb: mask wake up criteria found config.b 0: no mask(active) 1: mask(inactive) data sheet 123 version 4.0, 2007-06-01 tda523x functional description 2.4.18 spi interface general information ? ncs: select input, active low ? sck: clock input. data bits on sdi are read at rising sck edges and written out on sdo at falling sck edges. ? sdi: data input ? sdo: data output level definition: logic 0 = low voltage level logic 1 = high voltage level note: it is possible to send multiple frames wh ile the device is selected. it is also possible to change the access mode while the device is selected by sending a different instruction. note: in all bus transfers msb is sent first, except the received data read out from the fifo. there the bit order is giv en as first bit that is receiv ed is also the first bit that is transferred via the bus. 3 w imeoma: mask end of message config.a 0: no mask(active) 1: mask(inactive) 2 w immidfa: mask message id found config.a 0: no mask(active) 1: mask(inactive) 1 w imfsynca: mask frame sync config.a 0: no mask(active) 1: mask(inactive) 0 w imwucfa: mask wake up criteria found config.a 0: no mask(active) 1: mask(inactive) addr: 0x05 reset value: 0x00 bit r/w description tda523x functional description data sheet 124 version 4.0, 2007-06-01 read register figure 66 read register to read from the device, the chip must be selected first. therefore, the master must set the ncs line to low. after this, the instructi on byte and the address byte are shifted in on sdi and stored in the internal instruction and address register. the data byte at this address is then shifted out on sdo. after completing the read operation the master sets the ncs line to high. write register figure 67 write register to write to the device, the chip must be selected first. therefore the master must set the ncs line to low. after this, the instruction byte and the address byte are shifted in on sdi and stored in the internal instruction and address register. the following data byte is then stored at this address. after completing the write operation, the master sets the ncs line to high. use of the spi trace registers: the received address byte is stored into the register spiat and the received data byte is stored into the register spidt. these two trace registers are readable. therefore, an external controller is able to check the correct address and data transmission by reading out these two registers after each write instruction. the trace registers are updated at every write instruction, so only the last transmission can be checked by a read out of these two registers. data out sdi sdo high impedance z sck ncs d7 d6 d5 d4 instruction i7 i6 i3 i2 register address i1 i0 frame i5 i4 a7 a6 a3 a2 a1 a0 a5 a4 d3 d2 d1 d7 d6 d5 d4 instruction register address d3 d2 d1 d0 data out frame 181818181818 d0 i7 i6 i3 i2 i1 i0 i5 i4 a7 a6 a3 a2 a1 a0 a5 a4 sdi sdo high impedance z sck ncs instruction frame 18 i7 i6 i3 i2 i1 i0 i5 i4 d7 d6 d5 d4 d1 d0 d3 d2 register address 18 data byte 18 instruction frame 18 register address 18 data byte 18 a7 a6 a3 a2 a1 a0 a5 a4 i7 i6 i3 i2 i1 i0 i5 i4 d7 d6 d5 d4 d1 d0 d3 d2 a7 a6 a3 a2 a1 a0 a5 a4 data sheet 125 version 4.0, 2007-06-01 tda523x functional description spiat : spi address tracer spidt : spi data tracer read fifo figure 68 read fifo to read the fifo, the chip must be selected first. therefore, the master must set the ncs line to low. after this, the instruction byte is shifted in on sdi and stored in the internal instruction register. the data bits of the fifo are then shifted out on sdo. the following byte is a status word that contains the number of valid bits in the data packet. after completing the read operation, the master sets the ncs line to high. instruction set addr: 0x00 reset value: 0x00 bit r/w description 7:0 r address tracer register addr: 0x01 reset value: 0x00 bit r/w description 7:0 r data tracer register instruction description instruction format wr write to chip 0000 0010 rd read from chip 0000 0011 rdf read fifo from chip 0000 0100 32 fifo bits sdi sdo high impedance z sck ncs d0 d1 d30 d31 instruction i7 i6 i1 i0 s7 s6 s1 s0 status word instruction i7 i6 i1 i0 32 fifo bits d0 d1 d30 d31 s7 s6 s1 s0 status word frame frame 18132181813218 tda523x functional description data sheet 126 version 4.0, 2007-06-01 2.4.19 chip serial number every device contains a unique, preprogram med 32-bit wide serial number. this number can be read out as registers sn0, sn 1, sn2 and sn3 via the spi interface. figure 69 chip serial number table 2 serial number register sn0 : serial number register0 sn1 : serial number register1 sn2 : serial number register2 control register address description sn0 sn1 sn2 sn3 0x0e 0x0f 0x10 0x11 serial number of the ic addr: 0x0e reset value: sn bit r/w description 7:0 r sn: serial number: bit 7...bit 0(lsb) addr: 0x0f reset value: sn bit r/w description 7:0 r sn: serial number: bit 15...bit 8 addr: 0x10 reset value: sn bit r/w description 7:0 r sn: serial number: bit 23...bit 16 fuses ...... fuse- readout- interface sn0 sn1 sn2 ...... sn3 data sheet 127 version 4.0, 2007-06-01 tda523x functional description sn3 : serial number register3 2.4.20 digital input/output pins as long as the pin p_on is high, all digita l output pins operate as described. if the pin p_on is low, all digital output pins are switched to a high output impedance mode. interfacing to 3.3v logic: the tda523x is able to interface directly to any 3.3 v logic, in 3.3 v operation mode as well as in 5 v operation mode. interfacing to 5v logic: in 5 v operation mode, all digital inputs ar e 5 v tolerant and can be directly connected to 5 v logic outputs. the digital outputs are able to deliver minimal 2.6 v output voltage at 500a load current. this output level fits to ttl compatible cmos logic inputs (e.g. 74hctxxx). if a higher output voltage level is required, levelshifters have to be used. emc reduction of digital io?s: because emc noise generated by the digi tal signals may influence the receiver sensitivity, it is recommended that all inputs ar e filtered by adding an rc circuit such as in the evaluation board using 10 pf and 100 ? . addr: 0x11 reset value: sn bit r/w description 7:0 r sn: serial number: bit 31 (msb)...bit 24 tda523x register descriptions data sheet 128 version 4.0, 2007-06-01 3 register descriptions due to the variety of device funct ions and protocols, several re gisters and register bits have dedicated functions according to the selected operation mode. modification of register settings, unless otherwise noted, is only allowed in sleep and hold mode. registers that are defined independently for eac h configuration a and b are marked with ?dual?. registers marked with ?r? are read only, ?w? are write only and ?c? are cleared after read. settings for all registers are supported by the iaf tda523x configuration tool! table 3 register descriptions name addr. r/w def. description page spiat 0x00 r 0x00 spi address tracer 135 spidt 0x01 r 0x00 spi data tracer 135 cmc0 0x02 w 0x40 chip mode control register 0 135 cmc1 0x03 w 0x00 chip mode control register 1 136 is 0x04 c 0xff interrupt status register 137 im 0x05 w 0x00 interrupt mask register 138 rfpllac 0x06 r 0x00 rf pll actual channel register 138 spmc 0x07 w 0x00 self polling mode control register 139 spmrt 0x08 w 0x01 self polling mode reference timer 139 spmofft0 0x09 w 0x01 self polling mode off time register 0 139 spmofft1 0x0a w 0x00 self polling mode off time register 1 140 spmap 0x0b w 0x01 self polling mode active periods reg. 140 spmip 0x0c w 0x01 self polling mode idle periods register 140 sn0 0x0e r fuse serial number register 0 140 sn1 0x0f r fuse serial number register 1 140 sn2 0x10 r fuse serial number register 2 141 sn3 0x11 r fuse serial number register 3 141 rfc 0x12 w 0x00 rf control register 141 clkout0 0x13 w 0x07 clock divider register 0 141 clkout1 0x14 w 0x00 clock divider register 1 141 clkout2 0x15 w 0x00 clock divider register2 142 data sheet 129 version 4.0, 2007-06-01 tda523x register descriptions loc 0x16 w 0x00 local oscillator control register 142 limc0 0x1b w 0x0c trim rssi gain 142 limc1 0x1c w 0x15 trim rssi offset, enable rssi pin 142 aspmont0 0x1f w 0x01 conf. a self polling mode on time reg.0 143 aspmont1 0x20 w 0x00 conf. a self polling mode on time reg.1 143 amt 0x21 w 0x04 conf. a modulation type register 144 arfpll1 0x22 w 0x29 conf. a rf pll setting, channel 1 (slave mode & self polling mode) 144 arfpll2 0x23 w 0x08 conf. a rf pll setting, channel 2 (self polling mode) 145 arfpll3 0x24 w 0x0a conf. a rf pll setting, channel 3 (self polling mode) 146 awuc 0x25 w 0x00 conf. a wake up control register 146 awupat0 0x26 w 0x00 conf. a wake up detection pattern 0 146 awupat1 0x27 w 0x00 conf. a wake up detection pattern 1 147 awubcnt 0x28 w 0x00 conf. a wake up bit count register 147 amid0 0x29 w 0x00 conf. a message id register 0 147 amid1 0x2a w 0x00 conf. a message id register 1 147 amid2 0x2b w 0x00 conf. a message id register 2 147 amid3 0x2c w 0x00 conf. a message id register 3 147 amid4 0x2d w 0x00 conf. a message id register 4 147 amid5 0x2e w 0x00 conf. a message id register 5 147 amid6 0x2f w 0x00 conf. a message id register 6 147 amid7 0x30 w 0x00 conf. a message id register 7 147 amid8 0x31 w 0x00 conf. a message id register 8 147 amid9 0x32 w 0x00 conf. a message id register 9 147 amid10 0x33 w 0x00 conf. a message id register 10 147 amid11 0x34 w 0x00 conf. a message id register 11 147 amid12 0x35 w 0x00 conf. a message id register 12 147 amid13 0x36 w 0x00 conf. a message id register 13 147 table 3 register descriptions name addr. r/w def. description page tda523x register descriptions data sheet 130 version 4.0, 2007-06-01 amid14 0x37 w 0x00 conf. a message id register 14 147 amid15 0x38 w 0x00 conf. a message id register 15 147 amid16 0x39 w 0x00 conf. a message id register 16 147 amid17 0x3a w 0x00 conf. a message id register 17 147 amid18 0x3b w 0x00 conf. a message id register 18 147 amid19 0x3c w 0x00 conf. a message id register 19 147 amidc0 0x3d w 0x00 conf. a message id control register 0 147 amidc1 0x3e w 0x00 conf. a message id control register 1 148 aif0 0x3f w 0x00 conf. a if buffer amplifier enable 148 bspmont0 0x40 w 0x01 conf. b self polling mode on time reg.0 143 bspmont1 0x41 w 0x00 conf. b self polling mode on time reg.1 143 bmt 0x42 w 0x04 conf. b modulation type register 144 brfpll1 0x43 w 0x29 conf. a rf pll setting, channel 1 (slave mode & self polling mode) 144 brfpll2 0x44 w 0x08 conf. a rf pll setting, channel 2 (self polling mode) 145 brfpll3 0x45 w 0x0a conf. a rf pll setting, channel 3 (self polling mode) 146 bwuc 0x46 w 0x00 conf. b wake up control register 146 bwupat0 0x47 w 0x00 conf. b wake up detection pattern 0 146 bwupat1 0x48 w 0x00 conf. b wake up detection pattern 1 147 bwubcnt 0x49 w 0x00 conf. b wake up bit count register 147 bmid0 0x4a w 0x00 conf. b message id register 0 147 bmid1 0x4b w 0x00 conf. b message id register 1 147 bmid2 0x4c w 0x00 conf. b message id register 2 147 bmid3 0x4d w 0x00 conf. b message id register 3 147 bmid4 0x4e w 0x00 conf. b message id register 4 147 bmid5 0x4f w 0x00 conf. b message id register 5 147 bmid6 0x50 w 0x00 conf. b message id register 6 147 bmid7 0x51 w 0x00 conf. b message id register 7 147 table 3 register descriptions name addr. r/w def. description page data sheet 131 version 4.0, 2007-06-01 tda523x register descriptions bmid8 0x52 w 0x00 conf. b message id register 8 147 bmid9 0x53 w 0x00 conf. b message id register 9 147 bmid10 0x54 w 0x00 conf. b message id register 10 147 bmid11 0x55 w 0x00 conf. b message id register 11 147 bmid12 0x56 w 0x00 conf. b message id register 12 147 bmid13 0x57 w 0x00 conf. b message id register 13 147 bmid14 0x58 w 0x00 conf. b message id register 14 147 bmid15 0x59 w 0x00 conf. b message id register 15 147 bmid16 0x5a w 0x00 conf. b message id register 16 147 bmid17 0x5b w 0x00 conf. b message id register 17 147 bmid18 0x5c w 0x00 conf. b message id register 18 147 bmid19 0x5d w 0x00 conf. b message id register 19 147 bmidc0 0x5e w 0x00 conf. b message id control register 0 147 bmidc1 0x5f w 0x00 conf. b message id control register 1 148 bif0 0x60 w 0x00 if buffer amplifier enable, b 148 xtalcal0 0x61 w 0x10 trim xtal frequency, coarse 148 xtalcal1 0x62 w 0x00 trim xtal frequency, fine 149 totim 0x6b w 0xff time out timer register 149 digital receiver a global register adigrxc 0x6c w 0x00 global settings 149 adcsplrdiv 0x6d w 0x00 adc dividing factor 150 apkbitpos 0x6e w 0x00 rssi detector start-up delay 150 data filter related register adatfilt0 0x6f w 0x00 matched filter scaling and delay 150 adatfilt1 0x70 w 0x00 matched filter decimation 151 asigdet0 0x71 w 0x00 signal detector (run mode) 151 asigdet1 0x72 w 0x00 signal detector (wake up) 151 additional data filter rel ated registers see end of table clock recovery related register table 3 register descriptions name addr. r/w def. description page tda523x register descriptions data sheet 132 version 4.0, 2007-06-01 acdr0 0x73 w 0x00 clock recovery p parameters 153 acdr1 0x74 w 0x00 clock recovery i parameters 154 acdr2 0x75 w 0x00 clock recovery runin length 154 asysrct0 0x76 w 0x00 synchronization search time out 154 atvwin 0x77 w 0x00 cv window length 155 fsk related register afsknco0 0x78 w 0x00 fsk dds nco frequency offset 155 afsknco1 0x79 w 0x00 fsk dds nco frequency offset 155 afsknco2 0x7a w 0x00 fsk dds nco frequency offset 155 afskfilbw0 0x7b w 0x00 fsk pre filter decimation 155 afskfilbw1 0x7c w 0x00 fsk pre filter scaling 156 afskdembw0 0x7d w 0x00 fsk demodulator sensitivity 156 afskdembw1 0x7e w 0x00 fsk dam output decimation 156 afskdembw2 0x7f w 0x00 fsk dam output scaling 156 andthres 0x80 w 0x00 fsk noise detector threshold 157 andconfig 0x81 w 0x00 fsk noise detector configuration 157 framer related register atsimode 0x82 w 0x00 tsi detection mode 158 atsilena 0x83 w 0x00 tsi a length 158 atsilenb 0x84 w 0x00 tsi b length 159 atsigap 0x85 w 0x00 tsi gap 159 atsipta0 0x86 w 0x00 tsi data reference low byte a 159 atsipta1 0x87 w 0x00 tsi data reference high byte a 159 atsiptb0 0x88 w 0x00 tsi data reference low byte b 160 atsiptb1 0x89 w 0x00 tsi data reference high byte b 160 aeomc 0x8a w 0x00 eom control 160 aeomdtlen 0x8b w 0x00 eom data length limit 160 digital receiver b global register bdigrxc 0x8c w 0x00 global settings 149 table 3 register descriptions name addr. r/w def. description page data sheet 133 version 4.0, 2007-06-01 tda523x register descriptions bdcsplrdiv 0x8d w 0x00 adc dividing factor 150 bpkbitpos 0x8e w 0x00 rssi detector start-up delay 150 data filter related register bdatfilt0 0x8f w 0x00 matched filter scaling and delay 150 bdatfilt1 0x90 w 0x00 matched filter decimation 151 bsigdet0 0x91 w 0x00 signal detector (run mode) 151 bsigdet1 0x92 w 0x00 signal detector (wake up) 151 additional data filter rel ated registers see end of table clock recovery related register bcdr0 0x93 w 0x00 clock recovery p parameters 153 bcdr1 0x94 w 0x00 clock recovery i parameters 154 bcdr2 0x95 w 0x00 clock recovery runin length 154 bsysrct0 0x96 w 0x00 synchronization search time out 154 btvwin 0x97 w 0x00 cv window length 155 fsk related register bfsknco0 0x98 w 0x00 fsk dds nco frequency offset 155 bfsknco1 0x99 w 0x00 fsk dds nco frequency offset 155 bfsknco2 0x9a w 0x00 fsk dds nco frequency offset 155 bfskfilbw0 0x9b w 0x00 fsk pre filter decimation 155 bfskfilbw1 0x9c w 0x00 fsk pre filter scaling 156 bfskdembw0 0x9d w 0x00 fsk demodulator sensitivity 156 bfskdembw1 0x9e w 0x00 fsk dam output decimation 156 bfskdembw2 0x9f w 0x00 fsk dam output scaling 156 bndthres 0xa0 w 0x00 fsk noise detector threshold 157 bndconfig 0xa1 w 0x00 fsk noise detector configuration 157 framer related register btsimode 0xa2 w 0x00 tsi detection mode 158 btsilena 0xa3 w 0x00 tsi a length 158 btsilenb 0xa4 w 0x00 tsi b length 159 btsigap 0xa5 w 0x00 tsi gap 159 table 3 register descriptions name addr. r/w def. description page tda523x register descriptions data sheet 134 version 4.0, 2007-06-01 btsipta0 0xa6 w 0x00 tsi data reference low byte a 159 btsipta1 0xa7 w 0x00 tsi data reference high byte a 159 btsiptb0 0xa8 w 0x00 tsi data reference low byte b 160 btsiptb1 0xa9 w 0x00 tsi data reference high byte b 160 beomc 0xaa w 0x00 eom control 160 beomdtlen 0xab w 0x00 eom data length limit 160 status register rssi1 0xac r 0x00 peak-detector 1 read register 161 rssi2 0xad c 0x00 peak-detector 2 read register 161 fsknp 0xaf r 0x00 fsk noise power 161 asknp 0xb0 r 0x00 ask noise power 161 additional data filter related registers apslc 0xb4 w 0x00 pre slicer control 152 bpslc 0xb5 w 0x00 pre slicer control 152 asigdetlo 0xb6 w 0x00 signal detector threshold low level 152 bsigdetlo 0xb7 w 0x00 signal detector threshold low level 152 asigdetsel 0xb8 w 0x0a signal detector factor selection 153 bsigdetsel 0xb9 w 0x0a signal detector factor selection 153 table 3 register descriptions name addr. r/w def. description page data sheet 135 version 4.0, 2007-06-01 tda523x register descriptions 3.1 detailed register descriptions spiat : spi address tracer spidt : spi data tracer cmc0 : chip mode control register 0 addr: 0x00 reset value: 0x00 bit r/w description 7:0 r address tracer register addr: 0x01 reset value: 0x00 bit r/w description 7:0 r data tracer register addr: 0x02 reset value: 0x40 bit r/w description 7 w initfifo: init fifo at cycle start this initialization of the fifo can be configured in both slave mode and self polling mode. in slave mode, this ha ppen at the beginning of the slave run mode. in self polling mode, initialization is done after wake up found (switching from self polling mode to run mode self polling). 0: no init 1: init fifo 6 w clkouten: clkout enable 0: disable 1: enable programmable clock output 5 w totimen: totim timer enable time out timer is used to return from run mode self polling to self polling mode whenever there is no sync for a specific time. 0: disable 1: enable totim timer 4 w fifolk: lock data fifo at eom 0: fifo lock is disabled 1: fifo lock is enabled at eom tda523x register descriptions data sheet 136 version 4.0, 2007-06-01 cmc1 : chip mode control register 1 3 w rmsl: run mode slave configuration this bit is only relevant in slave mode, used to define the configuration 0: configuration a 1: configuration b 2 w dce: dual configuration enable this bit is only relevant in self polling mode, to define whether both configurations are used. 0: only configuration a is used 1: first configuration a and then configuration b is used 1 w slrxen: slave receiver enable this bit is only used in operat ing mode run mode slave/sleep mode 0: receiver is in sleep mode 1: receiver is in run mode slave 0 w msel: operating mode 0: run mode slave/sleep mode 1: self polling mode addr: 0x03 reset value: 0x00 bit r/w description 6 w hold: holds the chip in the config state (only in run mode slave) 0: normal operation 1: jump into the config state hold 5 w nintpol: invert nint polarity 0: the interrupt is active low 1: the polarity of the interrupt is inverted (active high) 4 w xtaltren: xtal trim enable 0: trimming is disabled 1: trimming is enabled 3 w fsinitfifo: init fifo at frame start 0: no init 1: init 2 w clkrxdsel: clkout/rxd pin function 0: clkout at pin clkout/rxd 1: rx-data out at pin clkout/rxd addr: 0x02 reset value: 0x40 bit r/w description data sheet 137 version 4.0, 2007-06-01 tda523x register descriptions is : interrupt status register 1 w nintnstrsel: nint/nstr pin function 0: interrupt out at pin nint/nstr 1: rx-data strobe out nint/nstr 0 w rxrunrxdsel: rx-run/rxd pin function 0: rx-run signal out at pin rx-run/rxd 1: rx-data out at pin rx-run/rxd addr: 0x04 reset value: 0xff bit r/w description 7 c eomb: end of message config.b reset event sets all bits to 1 6 c midfb: message id found config.b reset event sets all bits to 1 5 c fsyncb: frame sync config.b reset event sets all bits to 1 4 c wucfb: wake up criteria found config.b reset event sets all bits to 1 3 c eoma: end of message config.a reset event sets all bits to 1 2 c midfa: message id found config.a reset event sets all bits to 1 1 c fsynca: frame sync config.a reset event sets all bits to 1 0 c wucfa: wake up criteria found config.a reset event sets all bits to 1 addr: 0x03 reset value: 0x00 bit r/w description tda523x register descriptions data sheet 138 version 4.0, 2007-06-01 im : interrupt mask register rfpllac : rf pll actual channel register addr: 0x05 reset value: 0x00 bit r/w description 7 w imeomb: mask end of message config.b 0: no mask (active) 1: mask (inactive) 6 w immidfb: mask message id found config.b 0: no mask (active) 1: mask (inactive) 5 w imfsyncb: mask frame sync config.b 0: no mask (active) 1: mask (inactive) 4 w imwucfb: mask wake up criteria found config.b 0: no mask (active) 1: mask (inactive) 3 w imeoma: mask end of message config.a 0: no mask (active) 1: mask (inactive) 2 w immidfa: mask message id found config.a 0: no mask (active) 1: mask (inactive) 1 w imfsynca: mask frame sync config.a 0: no mask (active) 1: mask (inactive) 0 w imwucfa: mask wake up criteria found config.a 0: no mask (active) 1: mask (inactive) addr: 0x06 reset value: 0x00 bit r/w description 1:0 r rfpllacs: actual channel this register is set after a wake up is found in the self polling mode 00b: no channel was actually found 01b: channel 1 wake up according to rfpll1 setting was found 10b: channel 2 wake up according to rfpll2 setting was found 11b: channel 3 wake up according to rfpll3 setting was found data sheet 139 version 4.0, 2007-06-01 tda523x register descriptions spmc : self polling mode control register spmrt : self polling mode reference timer spmofft0 : self polling mode off time register 0 addr: 0x07 reset value: 0x00 bit r/w description 3 w permwusen: permanent wake up search enable during on-time 0: disabled 1: enabled 2 w spmaien: self polling mode active idle enable 0: disabled 1: enabled 1:0 w spmsel: self polling mode selection 00b: constant on/off 01b: fast fall back to sleep 10b: mixed mode (conf. a: const on/off, conf. b: fast fall back to sleep) addr: 0x08 reset value: 0x01 bit r/w description 7:0 w spmrt: set value self polling mode reference timer the output of this timer is used as the input for the on/off timer incoming periodic time = 64/fsys output periodic time= t rt = (64 * spmrt) /fsys min: 01h = (64*1)/fsys max: 00h = (64 * 256)/fsys addr: 0x09 reset value: 0x01 bit r/w description 7:0 w spmofft: set value self polling mode off time: bit 7...bit 0(lsb) off-time = t rt *spmofft min: 0001h = 1*t rt reg.value 3fffh = 16383*t rt max: 0000h = 16384*t rt tda523x register descriptions data sheet 140 version 4.0, 2007-06-01 spmofft1 : self polling mode off time register 1 spmap : self polling mode active periods reg. spmip : self polling mode idle periods register sn0 : serial number register 0 sn1 : serial number register 1 addr: 0x0a reset value: 0x00 bit r/w description 5:0 w spmofft: set value self polling mode off time: bit 13(msb)...bit 8 off-tim = t rt *spmofft min: 0001h = 1*t rt reg.value 3fffh = 16383*t rt max: 0000h = 16384*t rt addr: 0x0b reset value: 0x01 bit r/w description 4:0 w spmap: set value self polling mode active periods. min: 01h = 1 (master) period max: 1fh = 31 (master) periods reg.value 00h = 256 (master) periods addr: 0x0c reset value: 0x01 bit r/w description 7:0 w spmip: set value self polling mode idle periods. min: 01h = 1 (master) period max: 00h = 256 (master) periods addr: 0x0e reset value: sn bit r/w description 7:0 r sn: serial number: bit 7...bit 0(lsb) addr: 0x0f reset value: sn bit r/w description 7:0 r sn: serial number: bit 15...bit 8 data sheet 141 version 4.0, 2007-06-01 tda523x register descriptions sn2 : serial number register 2 sn3 : serial number register 3 rfc : rf control register clkout0 : clock divider register 0 clkout1 : clock divider register 1 addr: 0x10 reset value: sn bit r/w description 7:0 r sn: serial number: bit 23...bit 16 addr: 0x11 reset value: sn bit r/w description 7:0 r sn: serial number: bit 31 (msb)...bit 24 addr: 0x12 reset value: 0x00 bit r/w description 4 w rfoff: switch off rf-path (for rssi trimming) 0: rf-path enabled 1: rf-path off 3:0 w ifatt: adjust if attenuation in 16 steps to trim the gain rfin --> if-out 0000: 0 db attenuation 1111: 12 db attenuation addr: 0x13 reset value: 0x07 bit r/w description 7:0 w clkout0: clock out divider: bit 7...bit 0 (lsb) min: 0 00 01h = clock divided by 2 max: 0 00 00h = clock divided by (2^20)*2 addr: 0x14 reset value: 0x00 bit r/w description 7:0 w clkout1: clock out divider: bit 15...bit 8 min: 0 00 01h = clock divided by 2 max: 0 00 00h = clock divided by (2^20)*2 tda523x register descriptions data sheet 142 version 4.0, 2007-06-01 clkout2 : clock divider register2 loc : local oscillator control register limc0 : trim rssi gain limc1 : trim rssi offset, enable rssi pin addr: 0x15 reset value: 0x00 bit r/w description 3:0 w clkout2: clock out divider: bit 19 (msb)...bit 16 min: 0 00 01h = clock divided by 2 max: 0 00 00h = clock divided by (2^20)*2 addr: 0x16 reset value: 0x00 bit r/w description 7:5 w always set to 0 4 w ssbsel: local oscillator injection mode selection 0: lo-side lo injection..use for TDA5230 1: hi-side lo injection..use for tda5231 3:0 w always set to 0 addr: 0x1b reset value: 0x0c bit r/w description 4:0 w limgain: trim the rssi gain (slope) min: 00h = minimum gain max: 1fh = maximum gain addr: 0x1c reset value: 0x15 bit r/w description 6:5 w rssimtr: select signal for rssi pin 00b: rssi+ 01b: rssi- (reference) 10b: ref+ (reference) 11b: ref- (reference) data sheet 143 version 4.0, 2007-06-01 tda523x register descriptions dual: aspmont0 and bspmont0 : conf. a self polling mode on time reg.0 dual: aspmont1 and bspmont1 : conf. a self polling mode on time reg.1 4 w rssimone: enable buffer for rssi pin 0: buffer off 1: buffer on 3:0 w limoffs: trim the rssi offset min: 0h = minimum offset max: fh= maximum offset addr: 0x1f and 0x40 reset value: 0x01 bit r/w description 7:0 w spmont: set value self polling mode on time: bit 7...bit 0(lsb) on-tim = t rt *spmont min: 0001h = 1*t rt reg.value: 3fffh = 16383*t rt max: 0000h = 16384*t rt addr: 0x20 and 0x41 reset value: 0x00 bit r/w description 5:0 w spmont: set value self polling mode on time: bit 13(msb)...bit 8 on-tim = t rt * spmont min: 0001h = 1*t rt reg.value: 3fffh = 16383*t rt max: 0000h = 16384*t rt addr: 0x1c reset value: 0x15 bit r/w description tda523x register descriptions data sheet 144 version 4.0, 2007-06-01 dual: amt and bmt : conf. a modulation type register dual: arfpll1 and brfpll1 : conf. a rf pll setting, channel 1 (slave mode & self polling mode) addr: 0x21 and 0x42 reset value: 0x04 bit r/w description 3:2 w noc:: number of channels only used in the self polling mode to define how many channels are to be scanned. in the slave mode, only one channel used, regardless of the configuration. min: 01b = 1 channel max: 11b= 3 channels 1:0 w mt: modulation type addr: 0x22 and 0x43 reset value: 0x29 bit r/w description 6:5 w rfplla: band selection 00 : select 315 mhz band, a=3 01 : select 434 mhz band, a=2 10 : select 868 mhz band, a=1 run mode slave self polling mode run mode self polling 00b ask ask ask 01b fsk fsk fsk 10b ask fsk ask 11b fsk ask fsk data sheet 145 version 4.0, 2007-06-01 tda523x register descriptions dual: arfpll2 and brfpll2 : conf. a rf pll setting, channel 2 (self polling mode) 4:2 w rfpllr1: channel 1, pll divider factor r 1) 000 : r = 8 001 : r = 1 010 : r = 2 011 : r = 3 100 : r = 4 101 : r = 5 110 : r = 6 111 : r = 7 1:0 w rfplls1: channel 1, pll divider factor s 1) 00 : s = 1 01 : s = 0 10 : s = -1 11 : s = 0 1) channels with receive frequencies close to the harmoni cs of the reference crystal frequency should not be used in applications. addr: 0x23 and 0x44 reset value: 0x08 bit r/w description 4:2 w rfpllr2: channel 2, pll divider factor r 1) 000 : r = 8 001 : r = 1 010 : r = 2 011 : r = 3 100 : r = 4 101 : r = 5 110 : r = 6 111 : r = 7 1:0 w rfplls2: channel 2, pll divider factor s 1) 00 : s = 1 01 : s = 0 10 : s = -1 11 : s = 0 addr: 0x22 and 0x43 reset value: 0x29 bit r/w description tda523x register descriptions data sheet 146 version 4.0, 2007-06-01 dual: arfpll3 and brfpll3 : conf. a rf pll setting, channel 3 (self polling mode) dual: awuc and bwuc : conf. a wake up control register dual: awupat0 and bwupat0 : conf. a wake up detection pattern 0 addr: 0x24 and 0x45 reset value: 0x0a bit r/w description 4:2 w rfpllr3: channel 3, pll divider factor r 1) 000 : r = 8 001 : r = 1 010 : r = 2 011 : r = 3 100 : r = 4 101 : r = 5 110 : r = 6 111 : r = 7 1) channels with receive frequencies close to the harmoni cs of the reference crystal frequency should not be used in applications. 1:0 w rfplls3: channel 3, pll divider factor s 1) 00 : s = 1 01 : s = 0 10 : s = -1 11 : s = 0 addr: 0x25 and 0x46 reset value:0x00 bit r/w description 1:0 w wucrt: wake up criteria 00b: pattern detection 01b: random bits 10b: equal bits 11b: wake up on symbol sync, vali d data rate; the wubcnt register is not used in this mode. addr: 0x26 and 0x47 reset value:0x00 bit r/w description 7:0 w wupat0: wake up detection pattern: bit 7...bit 0(lsb) (in chips) data sheet 147 version 4.0, 2007-06-01 tda523x register descriptions dual: awupat1 and bwupat1 : conf. a wake up detection pattern 1 dual: awubcnt and bwubcnt : conf. a wake up bit count register dual: amid0 - amid19 and bmid0 - bmid19 : conf. a message id register 0 dual: amidc0 and bmidc0 : conf. a message id control register 0 addr: 0x27 and 0x48 reset value:0x00 bit r/w description 7:0 w wupat1: wake up detection pattern: bit 15(msb)...bit 8 (in chips) addr: 0x28 and 0x49 reset value:0x00 bit r/w description 6:0 w wubcnt: wake up bit count register counter register to define the maximum counts of chips for wake up detection. min: 00h = 0 chips to count in ?random bits? or ?equal bits? mode, this will cause a wake up immediately after symbol synchronization is found. in ?pattern detection? mode this will cause no wake up found. in this mode, a minimum of 11h= 17 chips= 8 1/2 bits is needed to shift one pattern through the entire pattern detector because comparison can only be started when at least the comparison register is fully filled. max: 7fh: 127 chips to count after symbol sync found addr: 0x29 - 0x3c and 0x4a - 0x5d reset value:0x00 bit r/w description 7:0 w mid0: message id register addr: 0x3d and 0x5e reset value:0x00 bit r/w description 6:0 w sp: mid scan start position min: 00h = comparison starts one bit after fsync max: 7f = comparison starts 128 bits after fsync tda523x register descriptions data sheet 148 version 4.0, 2007-06-01 dual: amidc1 and bmidc1 : conf. a message id control register 1 dual: aif0 and bif0 : conf. a if buffer amplifier enable xtalcal0 : trim xtal frequency, coarse addr: 0x3e and 0x5f reset value:0x00 bit r/w description 3 w midsen: enable id screening 0: disabled 1: enabled 2 w midbo: message id organization 0: 2-byte 1: 4-byte 1:0 w midnts: message id number of bytes to scan min: 00b = 1 byte to scan max for 2-byte organization: 01b: 2 bytes to scan. higher values than 01b will be mapped automatically to 2 bytes to scan max for 4-byte organization: 11b= 4 bytes to scan addr: 0x3f and 0x60 reset value: 0x00 bit r/w description 1 w ifbuf: enable if-buffer amplifier 0: buffer disabled 1: buffer enabled 0 w ifmux: select if-limiter input 0: use pin lim-in+ as input 1: use pin ifbuf-in as input addr: 0x61 reset value: 0x10 bit r/w description 4 w xtal_sw_coarse_4: connect trim capacitor: 16 pf 3 w xtal_sw_coarse_3: connect trim capacitor: 8 pf 2 w xtal_sw_coarse_2: connect trim capacitor: 4 pf 1 w xtal_sw_coarse_1: connect trim capacitor: 2 pf 0 w xtal_sw_coarse_0: connect trim capacitor: 1 pf data sheet 149 version 4.0, 2007-06-01 tda523x register descriptions xtalcal1 : trim xtal frequency, fine totim : time out timer register dual: adigrxc and bdigrxc : global settings addr: 0x62 reset value: 0x00 bit r/w description 3 w xtal_sw_fine_3: connect trim capacitor: 500 ff 2 w xtal_sw_fine_2: connect trim capacitor: 250 ff 1 w xtal_sw_fine_1: connect trim capacitor: 125 ff 0 w xtal_sw_fine_0: connect trim capacitor: 62.5 ff addr: 0x6b reset value: 0xff bit r/w description 7:0 w to_timer: set value time out timer timer is used to return from run mode self polling to the self polling mode whenever there is no symbol synchronization. timer is set back after eom. totim must be enabled in the cmc0 register. timeout= (totim * 64 * 512) / fsys min: 01h = (1 * 64 *512)/ fsys max: 00h= (256 * 64 * 512) / fsys addr: 0x6c and 0x8c reset value: 0x00 bit r/w description 2:1 w aafilt: anti aliasing filter 00b: 40khz (default) 01b: 13.6khz 10b: 5khz 11b: 3.6khz the anti-aliasing filter corner frequ ency can be changed to achieve better performance. note that the corner frequency and the data rate must be set together. 0 w datinv 0: default 1: invert data polarity tda523x register descriptions data sheet 150 version 4.0, 2007-06-01 dual: adcsplrdiv and bdcsplrdiv : adc dividing factor dual: apkbitpos and bpkbitpos : rssi detector start-up delay dual: adatfilt0 and bdatfilt0 : matched filter scaling and delay addr: 0x6d and 0x8d reset value: 0x00 bit r/w description 7:0 w adcdiv: adc sampling rate division factor. the adc sampling rate factor must be calculated together with askdec. note that for better performance, the highest possible adc sampling rate should be set. addr: 0x6e and 0x8e reset value: 0x00 bit r/w description 7:0 w rssi detector start-up delay 1) min: 00h: 0 bit delay (start with first bit after fsync) max: ffh: 255 bits delay 1) due to filtering and signal computation the latency t 1 and t 2 must be added (see also chapter 2.4.9.1 ) addr: 0x6f and 0x8f reset value: 0x00 bit r/w description 5:3 w asksca: cic-filter input scaling factor 1) 000b: default 1) use default value 2:0 w askdel: cic-filter cmb section delay factor 1)2) 110b: default for better performance from reduce d duty and data rate errors set 111b. 2) the cic filter delay = askdel + 1 adcdiv round f sys f adc ------------ ?? ?? 1 ? = f adc 96 320khz [] = data sheet 151 version 4.0, 2007-06-01 tda523x register descriptions dual: adatfilt1 and bdatfilt1 : matched filter decimation dual: asigdet0 and bsigdet0 : signal detector (run mode) dual: asigdet1 and bsigdet1 : signal detector (wake up) addr: 0x70 and 0x90 reset value: 0x00 bit r/w description 5:0 w askdec: cic-filter decimation factor: choose the highest possible adc samp ling rate for the best performance addr: 0x71 and 0x91 reset value: 0x00 bit r/w description (for detailed procedure refer to application notes.) 7:6 w sdcnt: signal detector threshold counter (run mode) use 00b: disabled 5:0 w sdthr: signal detector threshold level (run mode) 1) see application notes ?how to choose an application specific signal detection threshold for tda523x based ask mode applications? and ?how to choose an application specific signal- and noise-de tection threshold for tda523x based fsk mode applications? for specific procedure to determine this threshold by application . 1) for threshold calculation use the asknp: ask noise power register. addr: 0x72 and 0x92 reset value: 0x00 bit r/w description (for detailed procedure refer to application notes.) 7:6 w sdcnt: signal detector threshold counter (wake up) use 00b: disabled 5:0 w sdthr: signal detector threshold level (wake up) see application notes ?how to choose an application specific signal detection threshold for tda523x based ask mode applications? and ?how to choose an application specific signal- and noise-de tection threshold for tda523x based fsk mode applications? for specific procedure to determine this threshold by application . askdec round f adc 16 f ? data --------------------- ?? ?? 1 ? = f adc f sys adcdiv 1 + ---------------------------------- - = tda523x register descriptions data sheet 152 version 4.0, 2007-06-01 dual: apslc and bpslc : pre slicer control dual: asigdetlo and bsigdetlo : signal detector threshold low level addr: 0xb4 and 0xb5 reset value: 0x00 bit r/w description 7 w pslcda: pre-slicer disable 0: pre-slicer enable: only used in combination with tsi gap mode using standard settings as below! 1: pre-slicer disable (default) 6:5 w pslchys: pre-slicer hysteresis use 01b 4:0 w pslcthr: pre-slicer disable threshold use 10010 (0x12). addr: 0xb6 and 0xb7 reset value: 0x00 bit r/w description (for detailed procedure refer to application note.) 7 w sdlore: source selection of ask noise power status register 0: ask noise for sigdet0/1 1: signal for minimal usable fsk deviation if enabled, the sigdet low level can be read out from asknp register 6 w sdsel: manual selection of sigdet range 1) 0: disable(default) - sigdet0/1 range selection factor automatically done; depending on data rate 1: enable - use sigdetsel control to set the valid range 1) use default value 5:0 w sdlothr: signal detecto r threshold low level. this threshold level is only valid if the fsk noise detector selection in the ndconfig register is set to ?11b? see application notes ?how to choose an application specific signal detection threshold for tda523x based ask mode applications? and ?how to choose an application specific signal- and noise-de tection threshold for tda523x based fsk mode applications? for specific procedure to determine this threshold by application . data sheet 153 version 4.0, 2007-06-01 tda523x register descriptions dual: asigdetsel and bsigdetsel : signal detector factor selection dual: acdr0 and bcdr0 : clock recovery p parameters addr: 0xb8 and 0xb9 reset value: 0x0a bit r/w description 3:2 w sdsello: sigdetlo range selection factor 00b: 2 01b: 4 10b: 6 (default value) 11b: 8 the selected signal detector value is divided by the 2^range selection factor. use the right setting sui table to the measured asknp value. 1:0 w sdsel: sigdet0/1 range selection factor 00b: 4 01b: 6 10b: 8 (default value) 11b: 10 the selected signal detector value is divided by the 2^range selection factor. use the right setting sui table to the measured asknp value. addr: 0x73 and 0x93 reset value: 0x00 bit r/w description 7:6 w pdsr: peak-detector slew rate use 11b 5 w phden(1): phase detector er ror (pde) outer tolerance range use 1b 4 w phden(0): phase detector error (pde) inner tolerance range use 0b 3:2 w pval: p value use 01b 1:0 w psat: p value saturation use 10b tda523x register descriptions data sheet 154 version 4.0, 2007-06-01 dual: acdr1 and bcdr1 : clock recovery i parameters dual: acdr2 and bcdr2 : clock recovery runin length dual: asysrct0 and bsysrct0 : synchronization search time out addr: 0x74 and 0x94 reset value: 0x00 bit r/w description 7:6 w corsat: correlator output value (timing extrapolation unit) use 01b 5:4 w lfsat: loop filter saturation use 10b 3:2 w ival: i value use 01b 1:0 w isat: i value saturation use 01b addr: 0x75 and 0x95 reset value: 0x00 bit r/w description 1:0 w runlen: runin length use 01b: 3 1/2 bits (default) addr: 0x76 and 0x96 reset value: 0x00 bit r/w description 7:0 w syncto: synchroniz ation search time out ffh: 15 15/16 bits 00h: 0 bit data sheet 155 version 4.0, 2007-06-01 tda523x register descriptions dual: atvwin and btvwin : cv window length dual: afsknco0 and bfsknco0 : fsk dds nco frequency offset dual: afsknco1 and bfsknco1 : fsk dds nco frequency offset dual: afsknco2 and bfsknco2 : fsk dds nco frequency offset dual: afskfilbw0 and bfskfilbw0 : fsk pre filter decimation addr: 0x77 and 0x97 reset value: 0x00 bit r/w description 7:0 w tvwin: cv window length 28h: 40/16 bits ffh: 255/16 bits the minimal value for the tvwin register must be configured to 1 cv=28h ((8 + 16 *cv + 8)*1.25). note that if the tsigap framer mode is used (e.g. 8-bit gap protocol) the value must be higher and is dependent on other tsi framer settings. addr: 0x78 and 0x98 reset value: 0x00 bit r/w description 7:0 w ncoinc: fsk nco register bits (7:0) lsb addr: 0x79 and 0x99 reset value: 0x00 bit r/w description 7:0 w ncoinc: fsk nco register bits (15:8) addr: 0x7a and 0x9a reset value: 0x00 bit r/w description 7:0 w ncoinc: fsk nco register bits (23:16) msb addr: 0x7b and 0x9b reset value: 0x00 bit r/w description 3:0 w fskdec: fsk pre-filter decimation factor 0001b: 250 pre-filter bandwidth (recommended) 0011b: 125 pre-filter bandwidth 0111b: 62.5 pre-filter bandwidth 1111b: 31.25 pre-filter bandwidth tda523x register descriptions data sheet 156 version 4.0, 2007-06-01 dual: afskfilbw1 and bfskfilbw1 : fsk pre filter scaling dual: afskdembw0 and bfskdembw0 : fsk demodulator sensitivity dual: afskdembw1 and bfskdembw1 : fsk dam output decimation dual: afskdembw2 and bfskdembw2 : fsk dam output scaling addr: 0x7c and 0x9c reset value: 0x00 bit r/w description 6:4 w fsksca: fsk pre-filter scaling 3:0 w fskdel: fsk pre-filter comb delay setting use 1000b: default addr: 0x7d and 0x9d reset value: 0x00 bit r/w description 7:4 w not used 3:0 w damdly: fsk demodulator sensitivity use 0100b: default addr: 0x7e and 0x9e reset value: 0x00 bit r/w description 7:0 w damdec: fsk dam decimation addr: 0x7f and 0x9f reset value: 0x00 bit r/w description 3:0 w damsca: fsk dam output scaling fsksca dec 14 round ? fskfilbw0 1 + () 9 ? () log 2 () log --------------------------------------------------------------------- -4 + ?? ?? ?? ?? = damdec dec round f sys fskfilbw0 1 + () datfilt1 1 + () f data 16 ??? ---------------------------------------------------------------------------------------------------------------------------- - ?? ?? 1 ? = damsca dec rounddown fskdembw1 1 + () log 2 () log ------------------------------------------------------------- - ?? ?? = data sheet 157 version 4.0, 2007-06-01 tda523x register descriptions dual: andthres and bndthres : fsk noise detector threshold dual: andconfig and bndconfig : fsk noise detector configuration addr: 0x80 and 0xa0 reset value: 0x00 bit r/w description (for detailed procedure refer to application note.) 7:0 w ndthres: fsk noise detector threshold 1) see application notes ?how to choose an application specific signal detection threshold for tda523x based ask mode applications? and ?how to choose an application specific signal- and noise-de tection threshold for tda523x based fsk mode applications? for specific procedure to determine this threshold by application. 1) for threshold calculation use the fsknp: fsk noise power register. addr: 0x81 and 0xa1 reset value: 0x00 bit r/w description 5:4 w ndsel: fsk noise detector selection 00b: squelch only (signal power) ? signal power detection only (related registers dual: asigdet0 and bsigdet0: signal detector (run mode) , dual: asigdet1 and bsigdet1: signal detector (wake up) and asknp: ask noise power ). this mode should be used for ask and fsk. 01b: fsk noise detector only (noise power) ? noise power detection only (related registers dual: andthres and bndthres: fsk noise detector threshold and fsknp: fsk noise power ). this mode should be used for fsk signals with small deviations. 10b: both (squelch and fsk noise detector) ? signal and noise power detection simultaneous. 11b: squelch and (fsk noise detector and sigdetlo threshold) ? signal and noise power detection simultaneous but the fsk noise detect signal is valid if the sigdetlo threshold is exceeded only. this mode is used for fsk with low fsk deviations. 3:2 w nd(3:2): fsk noise detector configuration: threshold level use 01b: 1:0 w nd(1:0) fsk noise detector c onfiguration: peak-detector slew rate use 11b tda523x register descriptions data sheet 158 version 4.0, 2007-06-01 dual: atsimode and btsimode : tsi detection mode dual: atsilena and btsilena : tsi a length addr: 0x82 and 0xa2 reset value: 0x00 bit r/w description 7 w tsigrsyn: tsi gap resync mode (for detailed information, see atsigap/btsigap register description) 0: off (default) 1: pll reset after tsi gap 6:3 w tsiwca: wild cards for correlator a 2 w mancpaj: manchester code phase readjustment 0: disabled - manchester code polarity is defi ned by the tsi pattern. 1: enabled - the code phase readjustm ent will be done with each ?1001? or ?0110? manchester data change. 1:0 w tsidetmod: tsi detection mode 00b: 16-bit mode - tsi configuration a and b valid (sequentially), b is valid if the atsilenb >0 01b: 8-bit mode - tsi configurations a or b (parallel) 10b: 8-bit gap mode- tsi configurations a and b with gap (sequentially with gap between tsia & tsib) 11b: 8-bit extended mode - tsi confi gurations a or b (parallel with matching information), synchronization will be done on full tsi length, dependent on found tsi a or b, 0 or 1 will be sent as 1st received bit. addr: 0x83 and 0xa3 reset value: 0x00 bit r/w description 4:0 w tsi a length (in chips): (0x11 up to 0x1f not used) min: 00h = 0 bit; does only work in 16-bit mode: fsync will be generated after symbol synchronizati on. in other modes the smallest possible value to generate a fsync will be 01h. be aware that such small values makes it impossible to find the correct phase of the pattern in the data stream and, therefore, wrong data and code violations can be generated. max: 10h = 16 chips = 8 bits data sheet 159 version 4.0, 2007-06-01 tda523x register descriptions dual: atsilenb and btsilenb : tsi b length dual: atsigap and btsigap : tsi gap dual: atsipta0 and btsipta0 : tsi data reference low byte a dual: atsipta1 and btsipta1 : tsi data reference high byte a addr: 0x84 and 0xa4 reset value: 0x00 bit r/w description 4:0 w tsi b length (in chips): (0x11 up to 0x1f not used) min: 00h =0 bit (see also atsilena) max: 10h = 16 chips = 8 bits addr: 0x85 and 0xa5 reset value: 0x00 bit r/w description 7:3 w tsigap: tsi gap (t/2 bit resolution) 1fh: 15 1/2 bits gap 00h: 0 bit gap tsigap is used to lock the pll after tsi a is found, if the tsi detection mode 10b is selected. 2:0 w gapval: tsi gap (t/16 bit resolution) 111b: 7/16 bit gap 000b: 0 bit gap gapval is used to correct the dco phase after tsigap time, if the tsimode.tsigrsyn is disabled addr: 0x86 and 0xa6 reset value: 0x00 bit r/w description 7:0 w tsipta0: data pattern for tsi comparison : bit 7...bit 0(lsb) (in chips) addr: 0x87 and 0xa7 reset value: 0x00 bit r/w description 7:0 w tsipta1: data pattern for tsi comparison: bit 15(msb)...bit 8 (in chips) tda523x register descriptions data sheet 160 version 4.0, 2007-06-01 dual: atsiptb0 and btsiptb0 : tsi data reference low byte b dual: atsiptb1 and btsiptb1 : tsi data reference high byte b dual: aeomc and beomc : eom control dual: aeomdtlen and beomdtlen : eom data length limit addr: 0x88 and 0xa8 reset value: 0x00 bit r/w description 7:0 w tsiptb0: data pattern for tsi comparison (in chips) addr: 0x89 and 0xa9 reset value: 0x00 bit r/w description 7:0 w tsiptb1: data pattern for tsi comparison (in chips) addr: 0x8a and 0xaa reset value: 0x00 bit r/w description 3 w not used: always set to 0 2 w emsylo: eom by sync loss 1) 1) the eom criteria can be combined. 1 w emcv: eom by code violation 1) 0 w emdatlen: eom by data length 1) addr: 0x8b and 0xab reset value: 0x00 bit r/w description 7:0 w datlen: length of data field in telegram counting starts after the last tsi bit min: 00h = the next bit after tsi found (when eom criteria is emdatlen) will generate eom max: ffh data sheet 161 version 4.0, 2007-06-01 tda523x register descriptions fsknp : fsk noise power asknp : ask noise power rssi1 : peak-detector 1 read register rssi2 : peak-detector 2 read register addr: 0xaf reset value: 0x00 bit r/w description 7:0 r fsk noise power the read only register contains the ac tual noise power that should be used to set the dual: andthres and bndthres: fsk noise detector threshold register. addr: 0xb0 reset value: 0x00 bit r/w description 5:0 r ask noise power the read only register contains the ac tual noise power that should be used to set the dual: asigdet0 and bsigdet0: signal detector (run mode) and dual: asigdet1 and bsigdet1: signal detector (wake up) register. addr: 0xac reset value: 0x00 bit r/w description 7:0 r rssi: peak level during payload tracking started after fsync + pkbitpos set at eom cleared at reset addr: 0xad reset value: 0x00 bit r/w description 7:0 c rssi: peak level. tracking is active when digital receiver is enabled set at higher peak levels than stored cleared at reset and spi read out tda523x specifications data sheet 162 version 4.0, 2007-06-01 4 specifications 4.1 electrical data 4.1.1 absolute maximum ratings attention: the ac/dc characteristic limits are not guaranteed. the maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as latch-up or permanent damage to the ic may result. table 4 absolute maximum ratings, t amb = -40 c ? +105 c # parameter symbol limit values unit min. max. a.1 voltage range at pin vdd5v v vccmax -0,3 6 v a.2 voltage range at pin vddd, vdda v vccmax -0,3 4 v a.3 voltage between voltage-regulator terminals vdd5v vs. vddd and vdd5v vs.vdda v vccmax -0,3 4 v a.4 storage ambient temperature t storage -40 150 c a.5 thermal resistance junction to air r th(ja) 140 k/w a.6 total power dissipation at tamb=105c p tot 100 mw a.7 rf input power (500 ? source between pin rfin+ and pin rfin-) p rfin 0dbm a.8 esd classification: human body model v hbm 2kv a.9 maximum input voltage at digital input pins v inmax -0,3 vdd5v + 0,5 or 6 (whichever is lower) v a.10 high level dc-output current (digital output pins) 1 pin all pins i oh1 i ohall -1 -4 ma ma a.11 low level dc-output current (digital output pins) 1 pin all pins i ol1 i olall 1 4 ma ma a.12 maximum current to digital input and output pins i iomax 4ma data sheet 163 version 4.0, 2007-06-01 tda523x specifications 4.1.2 operating ratings table 5 operating ratings 4.1.3 ac/dc characteristics table 6 ac/dc characteristics, ta = -40 to 105 c, vdd5v = 5 v or vdd5v = vdda = vddd = 3,3 v # parameter symbol limit values unit min. typ. max. a.13 operating ambient temperature t amb -40 105 c a.14 supply voltage range 1 at pin vdd5v v dd5v 4.5 5.5 v a.15 supply voltage range 2 at pin vdd5v=vddd=vdda v dd3v3 3.0 3.6 v a.16 percentage of operating time of lifetime condition: t amb = -40 c t amb = 25 c t amb = 85 c t amb = 105 c t mission_profile 6 20 65 9 % % % % a.17 useful lifetime t life 15 years # parameter symbol limit values unit test conditions * min. typ. max. general b.1 TDA5230 supply current in run mode (excluding if buffer) i vddrun,ask 7.6 9.6 ma 2 kbit; ask; pin < -50 dbm b.1e tda5231 supply current in run mode (excluding if buffer) i vddrun31,ask 8.0 10.1 ma 2 kbit; ask; pin < -50 dbm b.2 TDA5230 supply current in run mode (excluding if buffer) i vddrun,fsk 8.0 10 ma 2 kbit; fsk; pin < -50 dbm b.2e tda5231 supply current in run mode (excluding if buffer) i vddrun31,fsk 8.4 10.5 ma 2 kbit; fsk; pin < -50 dbm b.3 supply current in sleep mode t amb = 25 c t amb = 85 c t amb = 105 c i vddsleep,low 40 60 90 50 90 140 a a a crystal oscillator in low precision mode; clock generation unit off b.4 supply current in sleep mode and crystal oscillator in high precision mode i vddsleep,high 220 a ctrim = 32 pf; clock generation unit off tda523x specifications data sheet 164 version 4.0, 2007-06-01 b.5 supply current in power down mode t amb = 25 c t amb = 85 c t amb = 105 c i vddpdwn 0.6 3 6 1.5 12 25 a a a vdd5v = vdda = vddd = 3.6 v b.6 supply current in power down mode t amb = 25 c t amb = 85 c t amb = 105 c i vddpdwn 0.8 2.5 5 1.5 10 20 a a a vdd5v = 5.5 v b.7 supply current of if buffer- amplifier i buff 0.5 0.7 ma p in < -50 dbm b.8 supply current of clock generation unit i vddclock 20 25 a f clkout =1 khz c load =10 pf b.9 receiver reset time t reset 0,8 5 ms b.10 brownout threshold v bor 2,45 v b.11 receiver startup time t rxstartup 119 note 1 119 64*t sys note 2 time to startup rf-frontend (comprises time required to switch crystal oscillator from low power to high precision mode) ? b.12 channel hop latency time and configuration change latency time (configuration a to b) t chhop 12 note 1 12 64*t sys time to switch rf-pll between different rf- channels. (does not include settling of the data clock recovery.) * b.13 rf-frontend startup delay t rfstartdelay 72 note 1 72 64*t sys delay of startup of rf-frontend * b.14 interrupt duration t int 1note 1 note 3 1 64*t sys pulse width of interrupt * b 15 p_on minimal pulse width t p_on 100 s minimum pulse width to reset the chip * b 16 minimal t masterperiod t masterperiod 5 note 4 ms minimal masterperiod for stable operation * rf characteristics c.1 TDA5230 rf-pll operational frequency band 1 operational frequency band 2 f band1 f band2 433 865 450 870 mhz mhz lo-side lo injection # parameter symbol limit values unit test conditions * min. typ. max. data sheet 165 version 4.0, 2007-06-01 tda523x specifications c.1e tda5231 rf-pll operational frequency band 1 f band1,31 302 320 mhz hi-side lo injection c.2 receiver input impedance f rf = 315 mhz f rf = 434 mhz f rf = 868 mhz r rfin315 c rfin315 r rfin434 c rfin434 r rfin868 c rfin868 610 0.8 550 0.6 620 0.5 ? pf ? pf ? pf parallel equivalent circuit; differentially between rfin+ vs. rfin-; run-mode * c.3 voltage gain rfin if-out rf-in matched to 50 ? if-out loaded with 330 ? g rf,min_att 41 db min. if attenuation c.4 1db compression point rfin if-out rf-in matched to 50 ? if-out loaded with 330 ? p 1db,min_att -33 dbm min. if attenuation * c.5 input 3rd order intercet point rfin if-out rf-in matched to 50 ? if-out loaded with 330 ? iip3 min_att -22 dbm min. if attenuation * c.6 voltage gain rfin if-out rf-in matched to 50 ? if-out loaded with 330 ? g rf,max_att 29 db max. if attenuation c.7 1db compression point rfin if-out rf-in matched to 50 ? if-out loaded with 330 ? p 1db,max_att -21 dbm max. if attenuation * c.8 input 3rd order intercet point rfin if-out rf-in matched to 50 ? if-out loaded with 330 ? iip3 max_att -13 dbm max. if attenuation * c.9 image rejection (cw-image at df = 2?10.7 mhz) a image 30 db pin = -50 dbm c.10 if output impedance (if-out) z ifout 330 ? * # parameter symbol limit values unit test conditions * min. typ. max. tda523x specifications data sheet 166 version 4.0, 2007-06-01 c.11 emission at pins rfin+ and rfin- f rf = 315 mhz f rf = 434 mhz f rf = 868 mhz p lo315 p 4lo315 p vco315 p lo434 p 4lo434 p vco434 p lo868 p vco868 -106 -108 -84 -91 -102 -88 -84 -79 dbm dbm dbm dbm dbm dbm dbm dbm single ended matching of input pins to 50 ? ; measured at 50 ? * if characteristics d.1 if buffer amplifier center frequency f if 10.7 mhz d.2 if buffer amplifier bandwidth b if 600 khz d.3 if buffer amplifier gain g if 7db d.4 if buffer amplifier input impedance z ifin 330 ? * d.5 if buffer amplifier output impedance z ifin 330 ? * limiter characteristics e.1 limiter center frequency f lim 10.7 mhz e.2 limiter bandwidth b lim 600 khz e.3 limiter input impedance between lim-in+ and lim-in- z lim 330 ? * e.4 rssi dynamic range 65 70 db pin rssi; true rssi-signal e.5 rssi linear dynamic range dp rssi 70 db t amb = 25 c; pin rssi; nonlinearity of true rssi-signal < 1db * e.6 rssi temperature drift within linear dynamic range drssi temp -2 2 db pin rssi; true rssi-signal * e.7 rssi error untrimmed drssi untrim -6 6 db t amb = 25 c; pin rssi; true rssi-signal; 2 mveff at pins lim-in- vs. lim-in+ # parameter symbol limit values unit test conditions * min. typ. max. data sheet 167 version 4.0, 2007-06-01 tda523x specifications e.8 rssi error user trimmed via sfrs limgain and limoffs drssi offtrim -1 1 db t amb = 25 c; pin rssi; true rssi-signal; 2 mveff at pins lim-in- vs. lim-in+ * e.9 rssi slope untrimmed du rssi /dp i untrim 11 14.5 18 mv/db t amb = 25 c; pin rssi; 2 mveff at pins lim-in- vs. lim-in+ e.10 rssi slope user trimmed via sfrs limgain and limoffs du rssi /dp i trim 13.5 14.5 15.5 mv/db t amb = 25 c; pin rssi; 2 mveff at pins lim-in- vs. lim-in+ * e.11 resistive load at pin rssi r l,rssimax 100 k ? * e.12 capacitive load at pin rssi c l,rssi 20 pf * crystal oscillator characteristics f.1 TDA5230 crystal frequency f xtal 13.1 13.75 mhz f.1e tda5231 crystal frequency f xtal31 14.65 15.5 mhz f.2 shunt capacitance c 0 2pf * f.3 motional capacitance c 1 3610ff * f.4 load capacitance c l 12 pf * f.5 trimming range of frequency df trim -50 50 ppm f.6 trimming steps df trim_step 4 ppm * f.7 oscillator untrimmed tolerance, not incl. crystal tolerance -25 30 ppm trim capacitor default settings, usage of recommended crystal * f.8 crystal oscillator settling time (switching from low power to high precision mode) t coscsettle 110 note 1 110 64*t sys * f.9 clock output frequency at pin clkout/rxd f clock_out 0.5 f sys 10 pf load digital inputs/outputs # parameter symbol limit values unit test conditions * min. typ. max. tda523x specifications data sheet 168 version 4.0, 2007-06-01 * not subject to production test - verified by characterization/design note 1: timings are generated by finite st ate machine and are therefore exact values. absolute timing tolerances are only influenced by oscillator tolerance. g.1 high level input voltage v ih 0.7? vddd vdd5v +0.1 v g.2 low level input voltage (except pin p_on) v il 00.8v g.3 low level input voltage at pin p_on v il,p_on 00.5v g.4 high level input leakage current i lih 5a g.5 low level input leakage current i lil -5 a g.6 high level output voltage (ioh=-500 a) v oh vddd- 0.4v vddd v g.7 low level output voltage (iol=500 a) v ol 00.4v timing spi-bus g.1e clock frequency f c 1.2 mhz g.2e clock high time t ch 400 ns * g.3e clock low time t cl 400 ns * g.4e active setup time t ssu 400 ns * g.5e not active hold time t cs 400 ns * g.6e active hold time t sho 400 ns * g.7e not active setup time t nsc 400 ns * g.8 deselect time t ds 1us * g.9 sdi setup time t sdisu 100 ns * g.10 sdi hold time t sdiho 170 ns * g.11 clock low to sdo valid @ 80 pf load t cdov 350 ns * g.12 clock low to sdo valid @ 10 pf load t cdov 270 ns g.13 sdo rise time @ 80 pf load t sdori 80 ns * g.14 sdo fall time @ 80 pf load t sdofa 80 ns * g.15 sdo rise time @ 10 pf load t sdori 10 ns * g.16 sdo fall time @ 10 pf load t sdofa 10 ns * g.17 sdo disable time t nsdoz 270 ns * # parameter symbol limit values unit test conditions * min. typ. max. data sheet 169 version 4.0, 2007-06-01 tda523x specifications note 2: t sys = 1 / f sys = 1 / f xtal note 3: if eom interrupt is used in combinati on with fifo lock in run mode slave, the interrupt line is not reset till fifo is read. see also chapter 2.4.15 and chapter 2.4.17 . note 4: t masterperiod limitation is only valid for tda523x c1 and c2. mask steps c3 and c4 and higher have no limitation. the mask step is visible on the component stamping. tda523x specifications data sheet 170 version 4.0, 2007-06-01 unless explicitly otherwise noted, the follo wing test conditions apply to the given specification values in tables 7..12: TDA5230: * hardware: testboard tda523x v2.1 * single-ended matching for 433.92 mhz * receive frequency 433.92 mhz; lo-side lo-injection * reference-clock: xtal=13.225625 mhz; rf-pll: r=2, s=0 tda5231: * hardware: testboard tda523x v2.1 * single-ended matching for 315.00 mhz * receive frequency 315.00mhz; hi-side lo-injection * reference-clock: xtal=15.2671875 mhz; rf-pll: r=2, s=0 TDA5230 and tda5231: * if-gain: attenuation set to minimum * if-filter: center=10.7mhz; bw=280khz; connected between if-out and lim-in+ * received-signal at zero offset to if center frequency * rssi trimmed * fsk-demodulator pre-filter bw +/-250 * no spi-traffic during telegram reception, clkout disabled * specification values are in respec t to manchester-coded reference protocol (11 bits '0' ,1 bit ?1' , prbs5 (31 bit), 1 bit 'm') according to figure 37 * dre ... data-rate error of received telegram vs. adjusted data-rate * dc ... duty-cycle (duration of first chip of manchester-coded bit in respect to duration of complete bit according to figure 37 ) * mer ... message error rate [mer = 1 - (number_of_correctly_received_m essages / number_of_transmitted messages)] * far ... false alarm rate [far = number_of_mistakenly_wake_ups / number_of_periods_searching_for_data_on_channel] * mmr ... missed message rate [mmr = number_of_mistakenly_missed_wake_up_patterns / number_of_periods_with_wake_up_pattern_tr ansmitted_and_searching_for_wake_up_pattern] data sheet 171 version 4.0, 2007-06-01 tda523x specifications table 7 characteristics of digital data filter and data clock recovery the following specification values are evaluated with ask 2kbit, ask 9.6 kbit, fsk 9.6 kbit & d 35 khz. acceptance criteria is: mer < 10 % table 8 characteristics of digital fsk-demodulator the following specification values are evaluated with fsk 9.6kbit & d 35 khz . # parameter symbol limit values unit test case * min. typ. max. h.1 data-rate of received telegram (nominal) b 0.5 20 kbit/s * h.2 data-rate error of received telegram (adjusted data-rate vs. data-rate of received telegram) * sensitivity loss < 1 db db -10 10 % dre -10% & dc 50% dre 0% & dc 50% dre +10% & dc 50% h.3 duty-cycle error of manchester coding of received telegram (value describes duration of first chip in respect to bit duration ) * sensitivity loss < 1 db tolmanchester1 45 55 % dre -10% & dc 45% dre -10% & dc 55% dre 0% & dc 45% dre 0% & dc 55% dre +10% & dc 45% dre +10% & dc 55% sensitivity loss < 3 db tolmanchester2 35 65 % dre -10% & dc 35% dre -10% & dc 65% dre 0% & dc 35% dre 0% & dc 65% dre +10% & dc 35% dre +10% & dc 65% # parameter symbol limit values unit test case * min. typ. max. i.1 fsk demodulator center frequency (nominal) f fskcenter 10.7 mhz * i.2 fsk demodulator input range (offset from nominal if center frequency, where signal-power at output of matched data filter (average of 500 readouts of value in register asknp) does not decrease by more than 3db from signal-power at if center frequency) d ffskspan -100 100 khz dre 0% & dc 50% 10 mveff at pins lim- in- vs. lim-in+ * tda523x specifications data sheet 172 version 4.0, 2007-06-01 i.3 fsk demodulator input bandwidth (offset from nominal if center frequency where sensitivity is not lower than 3db compared to sensitivity at center frequency) d ffskspan -90 90 khz dre 0% & dc 50% rf signal supplied at pins lim-in- vs. lim- in+ to avoid influence of if filter * i.4 maximum recommended fsk deviation f fsk-d +/-150 khz valid for all data rates * # parameter symbol limit values unit test case * min. typ. max. data sheet 173 version 4.0, 2007-06-01 tda523x specifications table 9 sensitivity of receiver the following specification values are evaluated for the data-rates given below. acceptance criteria is: mer < 10 % table 10 dynamic range of receiver the following specification values are evaluated for the data-rates given below. acceptance criteria are: mer < 1e-3, far < 1e-5, mmr < 1e-4 (criteria 8 equal bits) # parameter symbol limit values unit test case * min. typ. max. j.1 sensitivity limit ask-mode dre 0% & dc 50% * data rate 0.5 kbit/s data rate 2 kbit/s data rate 9.6 kbit/s data rate 20 kbit/s sask1 sask2 sask3 sask4 -111 -108 -104 -102 -106 -103 -99 -97 dbm peak dbm peak dbm peak dbm peak j.2 sensitivity limit fsk-mode dre 0% & dc 50% * data rate 0.5 kbit/s, deviation d 1.25 khz data rate 2 kbit/s, deviation d 10 khz data rate 2 kbit/s, deviation d 35 khz data rate 9.6 kbit/s, deviation d 35 khz data rate 20 kbit/s, deviation d 50 khz sfsk1 sfsk2 sfsk3 sfsk4 sfsk5 -102 -103 -108 -104 -103 -97 -98 -103 -99 -98 dbm dbm dbm dbm dbm # parameter symbol limit values unit test case * min. typ. max. k.1 dynamic range ask, modulation index 100% dre 0% & dc 50% * data rate 2 kbit/s data rate 9.6 kbit/s dr2,ask100 dr96,ask100 -10 -10 -98 -95 dbm peak dbm peak k.2 dynamic range ask, modulation index 50% dre 0% & dc 50% * data rate 2 kbit/s data rate 9.6 kbit/s dr2,ask50 dr96,ask50 -45 -60 -92 -89 dbm peak dbm peak k.3 dynamic range fsk 9.6 kbit & d 35 khz dre 0% & dc 50% * 0% am-modulation 90% am-modulation, 100 hz dr96,am0 dr96,am90 -10 -10 -96 -80 dbm dbm tda523x specifications data sheet 174 version 4.0, 2007-06-01 table 11 ask sensitivity of receiver in other frequency bands the following specification values are evaluated for fsk 2kbit. acceptance criteria is: mer < 10 % * not subject to production test - verified by characterization/design table 12 fsk sensitivity of receiver in other frequency bands * not subject to production test - verified by characterization/design # parameter symbol limit values unit test case * min. typ. max. l.1 sensitivity limit dre 0% & dc 50% * TDA5230 868.3 mhz, matching to 868.3 mhz, xtal=13.4 mhz s868ask -108 -103 dbm peak # parameter symbol limit values unit test case * min. typ. max. m. 1 sensitivity limit fsk-mode 868.3 mhz, matching to 868.3 mhz, xtal=13.4 mhz dre 0% & dc 50% * data rate 2 kbit/s, deviation d 10 khz data rate 2 kbit/s, deviation d 35 khz data rate 9.6 kbit/s, deviation d 35 khz data rate 20 kbit/s, deviation d 50 khz s868fsk1 s868fsk2 s868fsk3 s868fsk4 -100 -108 -103.5 -102 -95 -103 -98.5 -97 dbm dbm dbm dbm data sheet 175 version 4.0, 2007-06-01 tda523x specifications 4.2 timing diagrams 4.2.1 serial input timing figure 70 serial input timing 4.2.2 serial output timing figure 71 serial output timing ncs sdi t sdiho t sdisu t cs t nsc t sho sdo high impedance z t ds sck t ch t cl t ssu z sdo sdi z addr lsb ncs sck t cdov t nsdoz t sdori t sdofa t ch t cl t cdov tda523x specifications data sheet 176 version 4.0, 2007-06-01 4.3 test circuit, evaluation board v2.1 figure 72 test circuit schematic data sheet 177 version 4.0, 2007-06-01 tda523x specifications 4.4 test board layout - evaluation board v2.1 figure 73 test board layout , top view figure 74 test board layout , bottom view tda523x specifications data sheet 178 version 4.0, 2007-06-01 figure 75 test board layout, component view data sheet 179 version 4.0, 2007-06-01 tda523x specifications 4.5 bill of materials pos. part value package device / type tolerance manufacturer remark 1ic1 TDA5230 / tda5231 pg-tssop-28 smd infineon 2 r1 10 ohm/ open 0603 +/-5% 3.3 v / 5 v environment 3 r2 10 ohm/ open 0603 +/-5% 3.3 v / 5 v environment 4r30 ohm/ 22 ohm 0603 +/-5% 3.3 v / 5 v environment 5 c1 3.9 pf 0603 c0g +/-0.1 pf crystal oscillator load 6 c2 3.9 pf 0603 c0g +/-0.1 pf crystal oscillator load 7 c3 100 nf 0603 x7r +/-10% 8 c4 100 nf 0603 x7r +/-10% 9 c5 100 nf / 1 f 0603 x7r / x5r +/-10% 3.3 v / 5 v environment 10 c6 100 nf 0603 x7r +/-10% 11 c7 1.8 pf 0603 c0g +/-0.1 pf matching for 315 mhz 1.2 pf 0603 c0g +/-0.1 pf matching for 434 mhz open 0603 c0g +/-0.1 pf matching for 868 mhz 12 c8 open 0603 c0g +/-0.1 pf matching for 315 mhz open 0603 c0g +/-0.1 pf matching for 434 mhz 1.5 pf 0603 c0g +/-0.1 pf matching for 868 mhz 13 c9 10 f 293b tantal +/-10% 14 l1 68 nh 0603 simid0603-c +/-2% epcos matching for 315 mhz 47 nh 0603 simid0603-c +/-2% epcos matching for 434 mhz 27 nh 0603 simid0603-c +/-2% epcos matching for 868 mhz 15 q1 15.2671875 mhz nx5032sd c0= 1.3 pf c1= 5.0 ff cl=12 pf ndk, (frischer electronic), exs00a-03513 smd-crystal for 315.0 mhz (hi-side lo injection) 13.225625 mhz nx5032sd c0= 1.3 pf c1= 4.8 ff cl=12 pf ndk, frischer electronic, exs00a-3512 smd-crystal for 433.92 mhz (lo-side lo injection) 13.4 mhz nx5032sd c0= 1.3 pf c1= 3.7 ff cl=12 pf ndk, frischer electronic, exs00a-3514 smd-crystal for 868.3 mhz (lo-side lo injection) 16 q2 10.7 mhz (bw=280 khz) sfelf10m7f a00-b0 murata 1. if filter tda523x specifications data sheet 180 version 4.0, 2007-06-01 interface / optional 17 ic2 74hc08 / 74hct08 so14 smd and gates (3.3 v / 5 v environment) 18 ic3 74hc08 / 74hct08 so14 smd and gates (3.3 v / 5 v environment) 19 r4 0 ohm 0603 +/-5% common supply for tda523x and buffer ics 20 r5 100 ohm 0603 +/-5% 21 r6 100 ohm 0603 +/-5% 22 r7 100 ohm 0603 +/-5% 23 r8 10 kohm 0603 +/-5% 24 c10 10 f 293b tantal +/-10% 25 c11 100 nf 0603 x7r +/-10% 26 c12 100 nf 0603 x7r +/-10% 27 c13 10 pf 0603 x7r +/-10% 28 c14 10 pf 0603 x7r +/-10% 29 c15 10 pf 0603 x7r +/-10% 30 c16 100 nf 0603 x7r +/-10% 31 q3 10.7 mhz (bw=280 khz) sfelf10m7f a00-b0 murata 2. if-filter, optional 32 x1 sma socket pcb mounting rf input 33 x2 2 pins chip supply 34 x3 2 pins buffer supply 35 x4 3 pins soldering jumper if filter selection (default: connect 1 filter) 36 x5 2x20 pins female connector coded connection to pc / c / interface 37 x6 1 pin measurement point rssi 38 x7 2 pins soldering jumper select external supply by c(default: closed) 39 x8 2 pins gnd 40 board material 0.8mm fr4 with 35 m copper on both sides pos. part value package device / type tolerance manufacturer remark data sheet 181 version 4.0, 2007-06-01 tda523x package outlines 5 package outlines figure 76 pg-tssop-28-1 package outlines does not include dambar protrusion does not include plastic or metal protrusion of 0.15 max. per side 1 28 index marking 1) ?.1 9.7 a 14 15 0.1 m 28x ac 0.65 0.22 2) -0.03 +0.08 0.1 ?.05 c 0.1 +0.05 -0.2 1.2 max. 1 -0.035 b 0.125 +0.075 ?.1 4.4 1) ...8? +0.15 0.6 0? 0.2 6.4 -0.1 2 8x b 1) 2) y ou can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm smd = surface mounted device www.infineon.com published by infi neon technologies ag |
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