ICS552A-01 mds 552a-01 b 1 revision 010906 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com oscillator, multiplier, and buffer with 8 outputs description the ICS552A-01 produces 8 low-skew copies of the multiple input clock or fundamental, parallel-mode crystal. unlike other clock drivers, these parts do not require a separate oscillator for the input. using ics? patented phase-locked loop (pll) to multiply the input frequency, it is ideal for generating and distributing multiple high-frequency clocks. this is a single chip used for 3 different applications: 1) ICS552A-01 (a mode) ? an oscillator mutiplier 2) ICS552A-01 (b mode) ? a dual 1:4 buffer 3) ICS552A-01 (c mode) ? a 1:8 oscillator buffer features (all) ? packaged as 20-pin ssop (qsop) ? pb-free packaging available ? operating voltages of 3.0 v to 5.5 v ? industrial temperature available features (specific) ICS552A-01 (for a mode) ? contains on-chip multiplier with selections of x1, x1.33, x2, x2.66, x3, x3.33, x4, x4.66, x5, and x6 ? power-down and tri-state modes ICS552A-01 (for b mode) ? up to 200 mhz clock input/output at 3.3 v ? low skew of 250 ps maximum for any bank of four ? inputs can be connected together for a 1 to 8 buffer with 250 ps skew between any outputs ? non-inverting buffer mode ? ideal for clock networks ? output enable mode tri-states outputs ? full cmos output swing with 25 ma output drive capability at ttl levels ? advanced, low power, sub-micron cmos process ICS552A-01 (for c mode) ? use with 25 mhz crystal for networking ? use with 27 mhz crystal for mpeg ICS552A-01 (for a and c modes) ? input frequency of 10.0 to 27.0 mhz ? provides 8 low-skew outputs (<250 ps) ? output clock duty cycle of 40/60 at 3.3 v block diagram (ICS552A-01?a mode) crystal buffer/ crystal oscillator gnd vdd pll multiplier s3:s0 clk1 clk8 clk7 clk6 clk5 clk4 clk3 clk2 4 x2 10.0 to 27.0 mhz crystal or clock input external capacitors are required with a crystal input. x1
oscillator, multiplier, and buffer with 8 outputs mds 552a-01 b 2 revision 010906 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ICS552A-01 pin assignment (ICS552A-01?a mode) multiplier select table pin descriptions (ICS552A-01?a mode) 16 1 15 2 14 dc s0 3 13 x2 4 12 x1/iclk dc 5 11 s2 6 7 vdd 8 gnd s3 vdd gnd clk1 clk5 clk2 clk6 9 10 clk3 clk7 clk4 clk8 20 19 18 17 20-pin (150 mil) ssop (qsop) s1 s3 s2 s1 s0 multiplier 0 0 0 0 power down 0001 x1 0010 x1.333 0011 x2 0100 x2.666 0101 x3 0110 x3.333 0111 x4 1000 x5 1 0 0 1 x4.66 1010 x6 1 1 0 1 tri-state all pin number pin name pin type pin description 1 dc ? do not connect. 2 x2 xo crystal connection. connect to a 10 - 27 mhz fundamental mode crystal. 3x1/iclkxi crystal connection. connect to a 10 - 27 mhz fundamental mode crystal or clock. 4 vdd power connect to +3.3 v or 5 v. decouple with pin 6. must be same as other vdds. 5 s2 input multiplier select pin 2 per table above. 6 gnd power connect to ground. 7 clk1 output output clock 1. 8 clk2 output output clock 2. 9 clk3 output output clock 3. 10 clk4 output output clock 4. 11 s1 input multiplier select pin 1 per table above 12 clk5 output output clock 5. 13 clk6 output output clock 6. 14 gnd power connect to ground. 15 s3 input multiplier select pin 3 per table above 16 vdd power connect to +3.3 v or 5 v. decouple with pin 14. must be same as other vdds. 17 clk7 output output clock 7. 18 clk8 output output clock 8. 19 dc ? do not connect. 20 s0 input multiplier select pin 0 per table above
oscillator, multiplier, and buffer with 8 outputs mds 552a-01 b 3 revision 010906 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ICS552A-01 block diagram (ICS552A-01?b mode) pin assignment (ICS552A-01?b mode) clock output select table (ICS552A-01?b mode) s1 s0 mode 0 0 qa1:4 and qb1:4 running 01 test mode 1 0 oe. all outputs in high impedance 1 1 qa1:4 only. qb1:4 stopped low control logic ina qa1 qb4 qb3 qb2 qb1 qa4 qa3 qa2 inb s1 s0 16 1 15 2 14 ina s0 3 13 dc 4 12 dc inb 5 11 vdd 6 7 vdd 8 gnd vdd vdd gnd qa1 qb1 qa2 qb2 9 10 qa3 qb3 qa4 qb4 20 19 18 17 20-pin (150 mil) ssop (qsop) s1
oscillator, multiplier, and buffer with 8 outputs mds 552a-01 b 4 revision 010906 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ICS552A-01 pin descriptions (ICS552A-01?b mode) key: ci = clock input with pull-up resistor; i = input with internal pull-up resistor. pin number pin name pin type pin description 1 ina ci input to buffer a. out puts qa1:4 will be the same frequency. internal pull-up resistor. 2 dc ? do not connect. 3 dc ? do not connect. 4 vdd power connect to +3.3 v or 5.0 v. must be same as other vdds. 5vddpower connect to +3.3 v or 5.0 v. must be same as other vdds. 6 gnd power connect to ground. 7 qa1 output output 1 from buffer a. 8 qa2 output output 2 from buffer a. 9 qa3 output output 3 from buffer a. 10 qa4 output output 4 from buffer a. 11 s1 i mode select pin 1. selects mode for outputs. must be at gnd for all clocks on. internal pull-up resistor. 12 qb1 output output 1 from buffer b. 13 qb2 output output 2 from buffer b. 14 gnd power connect to ground. 15 vdd power connect to +3.3 v or 5.0 v. must be same as other vdds. 16 vdd power connect to +3.3 v or 5.0 v. must be same as other vdds. 17 qb3 output output 3 from buffer b. 18 qb4 output output 4 from buffer b. 19 inb ci input to buffer b. outputs qa1:4 will be th e same frequency. internal pull-up resistor. 20 s0 i mode select pin 0. selects mode for outputs. must be at gnd for all clocks on. internal pull-up resistor.
oscillator, multiplier, and buffer with 8 outputs mds 552a-01 b 5 revision 010906 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ICS552A-01 block diagram (ICS552A-01?c mode) pin assignment (ICS552A-01?c mode) crystal oscillator gnd vdd clk1 clk8 clk7 clk6 clk5 clk4 clk3 clk2 5 x2 10.0 to 27.0 mhz crystal input external capacitors are required with a crystal input. x1 3 16 1 15 2 14 dc vdd 3 13 x2 4 12 x1 dc 5 11 gnd 6 7 vdd 8 gnd vdd vdd gnd clk1 clk5 clk2 clk6 9 10 clk3 clk7 clk4 clk8 20 19 18 17 20-pin (150 mil) ssop (qsop) vdd
oscillator, multiplier, and buffer with 8 outputs mds 552a-01 b 6 revision 010906 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ICS552A-01 pin descriptions (ICS552A-01?c mode) pin number pin name pin type pin description 1 dc ? do not connect. 2 x2 xo crystal connection. connect to a 10 - 27 mhz fundamental mode crystal. 3 x1 xi crystal connection. connect to a 10 - 27 mhz fundamental mode crystal. 4 vdd power connect to +3.3 v or 5 v. decouple with pin 6. must be same as other vdds. 5gndpower connect to ground. 6 gnd power connect to ground. 7 clk1 output output clock 1. 8 clk2 output output clock 2. 9 clk3 output output clock 3. 10 clk4 output output clock 4. 11 vdd power connect to +3.3 v or 5 v. must be same as other vdds. 12 clk5 output output clock 5. 13 clk6 output output clock 6. 14 gnd power connect to ground. 15 vdd power connect to +3.3 v or 5 v. must be same as other vdds. 16 vdd power connect to +3.3 v or 5 v. decouple with pin 14. must be same as other vdds. 17 clk7 output output clock 7. 18 clk8 output output clock 8. 19 dc ? do not connect. 20 vdd power connect to +3.3 v or 5 v. must be same as other vdds.
oscillator, multiplier, and buffer with 8 outputs mds 552a-01 b 7 revision 010906 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ICS552A-01 external components series termination resistor clock output traces over one inch should use series termination. to series terminate a 50 ? trace (a commonly used trace impedance), place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . decoupling capacitors as with any high-performance mixed-signal ic, the ICS552A-01 must be isolated from system power supply noise to perform optimally. decoupling capacitors of 0.01f must be connected between each vdd and gnd on pins 4 and 6, and 16 and 14. other vdds and gnds can be connected to these pins or directly to their respective ground planes. crystal load capacitors the device crystal connections should include pads for small capacitors from x1 to ground and from x2 to ground. these capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very shor t pcb traces (and no vias) been the crystal and device. crystal capacitors must be connected from each of the pins x1 and x2 to ground. the value (in pf) of these crystal caps should equal (c l -12 pf)*2. in this equation, c l = crystal load capacitance in pf. example: for a crystal with a 18 pf load capacitance, two 12 pf capacitors should be used. for a clock input, connect it x1/iclk and leave x2 unconnected (floating). pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between decoupling capacitor and vdd pin. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. 2) the external crystal should be mounted just next to the device with short traces. the x1 and x2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) to minimize emi, the 33 ? series termination resistor (if needed) should be placed close to the clock output. 4) an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers.
oscillator, multiplier, and buffer with 8 outputs mds 552a-01 b 8 revision 010906 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ICS552A-01 absolute maximum ratings stresses above the ratings listed below can cause pe rmanent damage to the ICS552A-01. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics unless stated otherwise, vdd = 3.3 v or 5 v , ambient temperature -40 to +85 c parameter condition min. typ. max. units supply voltage, vdd referenced to gnd 7 v inputs referenced to gnd -0.5 vdd+0.5 v clock outputs referenced to gnd -0.5 vdd+0.5 v storage temperature -65 150 c soldering temperature max 10 seconds 260 c junction temperature 125 c parameter min. typ. max. units ambient operating temperature (commercial) 0 +70 c ambient operating temperature (industrial) -40 +85 c parameter symbol conditions min. typ. max. units operating voltage vdd 3.0 5.5 v input high voltage v ih iclk vdd/2+1 vdd/2 v input low voltage v il iclk vdd/2 vdd/2-1 v input high voltage v ih s3:s0 2 v input low voltage v il s3:s0 0.8 v output high voltage v oh vdd = 3.3 v, i oh = -8 ma 2.4 v output low voltage v ol vdd = 3.3 v, i ol = 8 ma 0.4 v output high voltage v oh vdd = 3.3 v or 5 v, i oh = -8 ma vdd-0.4 v short circuit current i os vdd = 3.3 v, each output 50 ma
oscillator, multiplier, and buffer with 8 outputs mds 552a-01 b 9 revision 010906 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ICS552A-01 ac electrical characteristics unless stated otherwise, vdd = 3.3 v or 5 v , ambient temperature -40 to +85 c thermal characteristics operating supply current i dd at 3.3 v, no load, 25 mhz in, x4 35 ma operating supply current i dd at 5 v, no load, 25 mhz in, x4 59 ma power-down supply current i dd s3:s0 = 0 (gnd) 55 a parameter symbol conditions min. typ. max. units input frequency f in fundamental crystal 10 27 mhz input clock 10 27 mhz output rise time t or 0.8 to 2.0 v 1.5 ns output fall time t of 2.0 to 0.8 v 1.5 ns duty cycle at vdd/2 40 50 60 % output-to-output skew all modes, rising edges at vdd/2 250 ps absolute jitter mode a, deviation from mean 75 ps one sigma clock period jitter mode a 25 ps parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 135 c/w ja 1 m/s air flow 93 c/w ja 3 m/s air flow 78 c/w thermal resistance junction to case jc 60 c/w parameter symbol conditions min. typ. max. units
oscillator, multiplier, and buffer with 8 outputs mds 552a-01 b 10 revision 010906 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ICS552A-01 package outline and package dimensions (20-pin ssop, 150 mil. wide body) package dimensions are kept current with jedec publication no. 95 ordering information parts that are ordered with a "lf" suffix to the part nu mber are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringemen t of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. part / order number marking shipping packaging package temperature ics552ar-01 ics552ar-01 tubes 20-pin ssop 0 to +70 c ics552ar-01t ics552ar-01 tape and reel 20-pin ssop 0 to +70 c ics552ar-01lf 552ar-01lf tubes 20-pin ssop 0 to +70 c ics552ar-01lft 552ar-01lf tape and reel 20-pin ssop 0 to +70 c ics552ari-01 ics552ari01 tubes 20-pin ssop -40 to +85 c ics552ari-01t ics552ari01 tape and reel 20-pin ssop -40 to +85 c ics552ari-01lf 552ari01lf tubes 20-pin ssop -40 to +85 c ics552ari-01lft 552ari01lf tape and reel 20-pin ssop -40 to +85 c index area 1 2 20 d e1 e seating plane a1 a a2 e - c - b aaa c c l millimeters inches symbol min max min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 -- 1.50 -- 0.059 b 0.20 0.30 0.008 0.012 c 0.18 0.25 0.007 0.010 d 8.55 8.75 0.337 0.344 e 5.80 6.20 0.228 0.244 e1 3.80 4.00 0.150 0.157 e .635 basic .025 basic l 0.40 1.27 0.016 0.050 0 8 0 8 aaa -- 0.10 -- 0.004
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