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vga/svga/xga 24-bit receiver description CXB1456R is the 1 chip deserializer for vga/svga/ xga 24-bit color digital rgb, and meet to the gigabit video interface specification. features 1 chip receiver for serial transmission of 24-bit color vga/svga/xga picture on chip pll circuit for data and clock recovery on chip panel mode automatically selectable circuit ttl compatible i/o support 1 pixel/shiftclock mode with 1 chip and 2 pixel/shiftclock mode with 2 chip +3.3v single power supply low power consumption 64pin plastic lqfp package with body size 10mm 10mm application gigabit video interface structure bi-cmos ic block digagram & pin out absolute maximum ratings supply voltage vcc 4.2 v storage temperature tstg ?5 to +150 ? allowable power dissipation p d 650 mw recommended operating condition supply voltage 3.3 0.3 v operating temperature topr 0 to +80 ? ?1 e98y04d1z-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXB1456R 64 pin lqfp (plastic) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 rext panel0 panel1 los testdt ce refrqp sdatap sdatan refrqn testexn v cc a v ee a v ee s lpfa lpfb v dd g0 g1 g2 g3 g4 g5 gnd v dd g6 g7 b0 b1 b2 b3 gnd clkpol r0 r1 gnd v dd v ee v cc r2 r3 r4 r5 gnd v dd r6 r7 gnd cntl de sftclk gnd v dd v ee v cc hsync vsync b7 b6 gnd v dd b5 b4 v dd serial to parallel converter decoder cdr pll fig. 1. block diagram & pin out
2 CXB1456R pin list table 1. power/ground pin name v dd gnd v cc v ee v cc a v ee a v ee s 8, 16, 20, 28, 53, 61, 64 1, 9, 17, 21, 29, 52, 60 26, 55 27, 54 44 45 46 mos power supply, should be connected to 3.3v 0.3v mos ground, connected to 0v ecl power supply, connected to 3.3v 0.3v ecl ground, connected to 0v analog power supply, connected to 3.3v 0.3v analog ground, connected to 0v substrate gnd, connected to 0v pin number descriptions table 2. digital signals pin name sftclk red (7 to 0) grn (7 to 0) blu (7 to 0) hsync vsync cntl de los panel (1, 0) clkpol ce testexn testdt 51 18, 19, 22, 23, 24, 25, 30, 31 6, 7, 10, 11, 12, 13, 14, 15 58, 59, 62, 63, 2, 3, 4, 5 56 57 49 50 36 35, 34 32 38 43, 37 ttl out ttl out ttl out ttl out ttl out ttl out ttl out ttl in ttl in ttl in ttl in shift clock, for the data fetch at falling or rising edge pixel data hsync data vsync data control data display enable data los of signal panel mode select switch trigger edge select switch chip enable reversed for test under fabrication pin number type descriptions equivalent circuit v dd gnd v cc a ttl-in v ee s v dd ttl-out gnd
3 CXB1456R table 3. special pin name 33 47, 48 external register external loop filter pin number descriptions equivalent circuit rext lpfa/b table 2. digital signals (cont.) pin name sdatap/n refrqp/n 40, 41 39, 42 rx rx serial input refclk request pin number type descriptions equivalent circuit v cc a sdatap/n v ee a refrqp/n v dd gnd v cc a lpfa v ee a v dd gnd lpfb v cc v ee gnd rext v dd
4 CXB1456R electrical characteristics table 4. absolute maximum rating description power supply voltage ttl dc input voltage ttl output current (high) ttl output current (low) serial input pin voltage refreq output pin voltage storage temperature v cc v i _t i oh _t i ol _t vsdin v rq out tstg 0.3 0.5 10 0 0.5 0.5 65 4.2 4.6 0 10 v cc + 0.5 v cc + 0.5 150 v v ma ' ma v v c symbol min. typ. max. unit comments table 5. recommended operating conditions description power supply voltage ambient temperature v cc ta 3.0 0 3.3 3.6 80 v c symbol min. typ. max. unit comments table 6. dc characteristics (under the recommended conditons. see tab. 5) description input high voltage (ttl) input low voltage (ttl) input high current (ttl) input low current (ttl) output high voltage (ttl) output low voltage (ttl) output high current (refreq) output low current (refreq) input dynamic range (sdata) input dynamic range (sdata) supply current v ih _t v il _t i ih _t i il _t v oh _t v ol _t i oh _rq i ol _rq v im _sd v id _sd i cc 2 0 10 2.4 0.1 7.8 v cc 0.4 0.5 0 138 77 v cc 0.8 10 0.4 +0.1 11 v cc + 0.2 +0.5 173 104 v v a a v v ma ma v v ma ma v in = v cc v in = 0 i oh = 3ma i ol = 3ma see fig. 3, 4 rext = 5.6k ? common mode voltage differential voltage c l = 8pf, f = 65mhz see fig. 9, 10 symbol min. typ. max. unit conditions worst case 16 grayscale
5 CXB1456R 37 38 43 39 42 testdt CXB1456R v cc ce testexn refrqp 150 ? 50 ? 50 ? 150 ? refrqn v dd /v cc /v cc a gnd/v ee /v ee a a a fig. 3. i oh _rq and i ol _rq dc measurement testdt ce testexn fig. 4. i oh _rq and i ol _rq dc measurement setting
6 CXB1456R table 7. ac characteristics (under the recommended conditons. see tab. 5) description minimum sftclk frequency maximum sftclk frequency sftclk duty factor pixel/sync/cntl/de setup to sftclk pixel/sync/cntl/de hold to sftclk sftclk rise time sftclk fall time pixel/sync/cntl/de rise time pixel/sync/cntl/de fall time clock mode assert time clock mode deassert time los signal assert time los signal deassert time fsftclk dsftclk tsetup thold torc tofc tord tord taclk tdclk talos tdlos 65.0 35 17 9 4.5 16 9 4.5 0.5 20 0.5 0.15 25.0 65 5 3 5 3 mhz mhz % ns ns ns ns ns ns ns ns ns ns s s s s vth = 1.4v, c l = 8pf vth = 1.4v, c l = 8pf 25mhz 40mhz 65mhz vth = 1.4v, c l = 8pf 25mhz 40mhz 65mhz 0.8v to 2.0v, c l = 8pf 2.0v to 0.8v, c l = 8pf 0.8v to 2.0v, c l = 8pf 2.0v to 0.8v, c l = 8pf symbol min. typ. max. unit conditions CXB1456R ttlout cprobe cl' + cprobe = 8pf oscillo- scope v cc cl' v dd /v cc /v cc a gnd/v ee /v ee a fig. 5. pixel/sync/cntl/de waveform measurement
7 CXB1456R timing chart sftclk torc tsetup tofc thold tord 2.0v 2.0v 0.8v 0.8v vth 1/fsftclk redxx setup/hold time is referred from rising edge in clkpol = gnd falling edge in clkpol = v dd grnxx bluxx h/vsync cntl de tofd dsftclk/fsftclk fig. 7. refclk request timing pixel sync/cntl/de sftclk refrqp refrqn sdatap sdatan taclk indefinite indefinite tdclk error fig. 8. idle mode timing los sdatap sdatan tdlos talos nrz data fig. 6. ttl output timing
8 CXB1456R fig. 9. worst case test pattern sftclk rgb <7, 5, 3, 1> rgb <6, 4, 2, 0> f f/2 f/2 fig. 10. 16 grayscale test pattern sftclk rgb <7> rgb <6> f f/8 f/16 f/2 f/4 fix low fix low fix low fix low rgb <4> rgb <5> rgb <3> rgb <2> rgb <1> rgb <0>
9 CXB1456R clkpol pin control the clkpol pin is used to select the sftclk trigger edge. (see table 8.) the clkpol pin is open high-impedance ttl input, and this should not be left open for use. (see fig. 12. recommended application circuit.) table 8. sftclk polarity panel1 l l h h l h l h vga (640 480) svga (800 600) xga (1024 768) vga to xga panel0 supporting panel size 25mhz 40mhz 65mhz 25mhz to 65mhz shift clock 750mbps 1200mbps 1950mbps 750mbps to 1950mbps serial rate clkpol l h rising edge falling edge receiver operation trigger table 9. panel mode los pin output the los pin shows the absence of proper level of sdata signal. the los pin is high when the connector is disconnected or the transmitter is idle. the los pin is ttl output. panel1 and 0 pin control the panel1 and 0 pins are used to select the panel mode. (see table 9.) for the normal use, the all frequencies of sftclk (25mhz to 65mhz) can be covered by fixing both panel1 and 0 to high. the panel1 and 0 pins are open high-impedance ttl inputs, and they should not be left open for use. (see fig. 12. recommended application circuit.) test pin control the testexn and testdt pins are for test only. select normal mode. (see table 11.) the testexn and testdt pins are open high-impedance ttl inputs, and they should not be left open for use. ce pin control the ce pin is used to select the standby mode. (see table 10.) the ce pin is open high-impedance ttl input, and this should not be left open for use. (see fig. 12. recommended application circuit.) table 10 table 11. test mode testexn l h testdt x x test mode normal mode operation mode ce l h standby mode, all ttl outputs fixed to low (excluding los) normal mode operation mode
10 CXB1456R applications CXB1456R gvif receiver is applied to the digital rgb signal transmission for p/c with lcd monitor video on demand system monitoring system graphical controller projector digital tv monitor car navigation system with gvif transmitter, cxb1455r. cxb1455r gvif transmitter CXB1456R gvif receiver parallel to serial converter cable driver pll red (7 to 0) grn (7 to 0) blu (7 to 0) sync/ de/cntl shiftclock red (7 to 0) grn (7 to 0) blu (7 to 0) sync/ de/cntl shiftclock stp or twin axial 8 8 8 4 encoder serial to parallel converter pll decoder 8 8 8 fig. 11. block diagram of gvif transceiver chip set
11 CXB1456R application cicuit 5.6k (1) (1) chip resistor (1%) (2) chip capacitor (3) formed by the printed circuit pattern (l = 0.5 to 1.0mm/w = 0.5 to 1.0mm) h: falling edge trigger l: rising edge trigger 100 (1) 150 (1) 150 (1) 47p (2) 47p (2) 0.1 (2) 0.1 to 0.4n (3) 0.1 to 0.4n (3) 0.1 to 0.4n (3) 33 16v v cc v cc v cc 0.1 (2) v cc differential cable 47 (1) 470p (2) 47 (1) 330 330 330 connector 0.1 (2) 0.1 (2) 0.1 (2) 7 v cc 0.1 (2) 0.1 (2) 0.1 (2) 6 5 4 red data 3 2 1 0 msb lsb v cc v cc v cc 0.1 (2) 0.1 (2) 7 6 5 4 green data 3 2 1 0 msb lsb 7 6 5 4 blue data 3 cntl sftclk hsync vsync de 2 1 0 msb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 cntl de sftclk gnd v dd v ee v cc hsync vsync CXB1456R b7 b6 gnd v dd b5 b4 v dd gnd b3 b2 b1 b0 g7 g6 v dd gnd g5 g4 g3 g2 g1 g0 v dd lpfb lpfa v ee s v ee a v cc a testexn refrqn sdatan sdatap refrqp ce testdt los panel1 panel0 rext clkpol r0 r1 gnd v dd v ee v cc r2 r3 r4 r5 gnd v dd r6 r7 gnd sw1 e e e v cc application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same . fig. 12. recommended application circuit
12 CXB1456R recommended printed circuit board structure l1 : cu plate (18 m) + solder coat l1 : fiber-glass epoxy core (0.3mm) l2 : cu plate (36 m) l2 : fiber-glass epoxy core (0.8mm) l3 : cu plate (36 m) l3 : fiber-glass epoxy core (0.3mm) l4 : cu plate (18 m) + solder coat recommended printed circuit board pattern power and special signal routing example cntl de sftclk gnd v dd v ee v cc hsync vsync b7 b6 gnd v dd b5 b4 v dd gnd b3 b2 b1 b0 g7 g6 v dd gnd g5 g4 g3 g2 g1 g0 v dd lpfb lpfa v ee s v ee a v cc a testexn refrqn sdatan sdatap refrqp ce testdt los panel1 panel0 rext clkpol r0 r1 gnd v dd v ee v cc r2 r3 r4 r5 gnd v dd r6 r7 gnd d d d d d d d d g g g g g 1 64 49 16 17 32 33 48 0.5mm l2 doesn't have plane in this area g g g through hole to the gnd plane (l2) through hole to the v cc plane (l3) through hole to the v dd plane (l3) chip capacitor chip resistor g e d e g g e fig. 13. recommended printed circuit board structure fig. 14. recommended printed circuit board pattern
13 CXB1456R micro strip line for maximum performance, the impedance between the pins sddatap/n of the lsi and the footprint of the connector should be 50 ? using a micro strip line. 50 ? impedance can be reached when using 0.5mm width pattern lines on l1 using this circuit board structure. the length of the lines should be identical and through- hole should not be used. l2 is recommended as the large ground plane. terminators terminators (100 ? resistor) should be located as close to the lsi as possible. filter devices and reference registors capacitors and resistors which are connected to lpfa/b and rext are filters and reference resistors. the region of layer 2 (l2) is under the device and conductive patterns. the ground plane should be taken off in order to reduce parasitic capacitors. bypass capacitors bypass capacitors (0.1f smd type) should be located as close to the pins as possible. refer to the recommendation.
14 CXB1456R recommendation for cable and connector characteristics the gvif system uses terminators at both ends (transmitter and receiver), a cable equalizer and a small amplitude differential signal. in order to solve the problems of high speed data transmission such as signal reflection, reduce the signal level and emi. in order to achieve the best solution, note the following: tx lsi rx lsi tx termination 50 ? tx termination 100 ? microstrip line (50 ? ) microstrip line (50 ? ) foot print foot print cable (diff. 100 ? ) connector connector it is important to note the following issues for a good data transmission system: good impedance matching differential impedance should be fit to the recommended template on the next page. cable loss should be small and the loss curve should be smooth. maximum loss should be less than 6db at 1ghz. see the next page. skew of pos/neg (differential signal) should be small less than 12% of 1-bit time or 160ps@vga, 100ps@svga, 60ps@xga. good emi performance cable and connectors. in order to satisfy these issues, the recommendations are as follows: use the differential cable which provides good controlled impedance, low loss and good skew matching. a shielded twisted pair (stp) cable is recommended. use a low reflectance connector. to minimize interference from other signals, high speed signal lengths should be identical. use double shielded cable.
15 CXB1456R recommended transmission path : differential impedance template 150 zo ( ? ) 110 106 94 90 75 microstrip line microstrip line foot print foot print connector < 500ps < 500ps connector recommended transmission path : attennation characteristics loss < 6db measured curve fitting curve 2db 1ghz frequency
16 CXB1456R ttl output waveform with c l = 8pf 1.00v/div 1.00v/div 5ns/div t sftclk 65mhz ttl output b0 65mbps ttl output atten 10db rl 0dbm center 65.00mhz rbw 100khz span 10.00mhz swp 50.0ms vbw 100khz 10db/ sftclk power spectrum d center 65.00mhz
17 CXB1456R package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin copper alloy package structure 48pin lqfp (plastic) 9.0 0.2 ? 7.0 0.1 1 12 13 24 25 36 37 48 (0.22) 0.18 ?0.03 + 0.08 0.2g lqfp-48p-l01 p-lqfp48-7x7-0.5 (8.0) 0.5 0.2 0.127 ?0.02 + 0.05 a 1.5 ?0.1 + 0.2 0.1 palladium plating note: dimension ? does not include mold protrusion. 0.1 0.1 0.5 0.2 0? to 10? detail a 0.13 m 0.5 s s b detail b : palladium 0.127 0.04 0.18 0.03 sony corporation

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