View WM8900LGEFKRV_317590.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

w
DESCRIPTION
The WM8900 is designed for portable multimedia applications requiring low power consumption, high performance audio and a compact form factor. Pop and click optimised ground referenced headphone amplifiers provide high quality audio performance and improved bass response whilst also eliminating bulky headphone capacitors. Headphone amplifier playback power consumption is minimised by implementing an efficient class G amplifier powered by adaptive charge pump technology. Flexible analogue signal routing and digital signal processing capabilities enable advanced audio signal manipulation for fully featured multimedia applications whilst minimising power consumption. Stereo 24bit multi-bit sigma-delta ADCs and DACs are used with over-sampling digital interpolation and decimation filters. The master clock can be input directly or generated internally by an integrated low power FLL. WM8900 operates at analogue supply voltages down to 2.4v. The digital core can operate at voltages down to 1.8v to save power. Different sections of the chip can also be powered down under software control. The WM8900 is supplied in a very small and thin 5x5x0.55mm QFN package, ideal for use in hand-held and portable systems Low power, high performance audio features can be realized with a minimal set of small form factor external components, reducing BOM costs and PCB dimensions *
WM8900
Ultra Low Power CODEC for Portable Multimedia Applications Featuring Class G Ground Referenced Headphone Driver
FEATURES
* * * * * DAC to HP SNR 97dB (`A' weighted, 2.4V) DAC to HP THD -82dB at 48kHz Fs, 2.4V ADC SNR 95dB (`A' weighted, 3.3V) ADC THD -84dB at 48kHz Fs, 2.4V Highly Flexible Input and Output Configuration - 2 single ended or pseudo differential mic inputs - 2 stereo line inputs (eg. Line In / FM tuner) - Up to +48dB microphone/line input gain - Stereo output mixers with -15dB to +6dB gain range; mixing DAC outputs, line, auxiliary and mic inputs Class-G Ultra-low Power Headphone Driver - Up to 12.4mW per channel output power into 32 at 3.3V - Up to 6.6mW per channel output power into 32 at 2.4V - Ground referenced outputs - Pop and click suppression circuitry Soft Mute Control Low Power Consumption with User Selectable Modes - 9 mW stereo headphone playback (32) (AVDD = 2.4V, DCVDD = 1.8V, 48k fs) - 6 mW stereo headphone playback (32) (AVDD = 2.4V, DCVDD = 1.8V, 8k fs, quiescent) - 5 mW bypass mode. Line in to stereo headphone playback (32) (AVDD = 2.4V, DCVDD = 1.8V) Low Supply Voltages - Analogue: 2.4V to 3.3V - Digital core: 1.8V to 3.3V - Digital I/O: 1.8V to 3.3V - Charge Pump High: 2.4V to 3.3V - Charge Pump Low: 1.6V to 3.3V Low Power FLL - Supports MCLK input up to 19.2MHz or DACLRC input down to 8kHz TDM Mode - dual data time slots for ADC and DAC Audio Sample Rates (kHz): 8, 11.025, 16, 22.05, 24, 32, 44.1, 48 generated internally from master clock 5 x 5 x 0.55mm 40 lead QFN package -25 C - +85C temperature range
*
* *
*
* *
* *
APPLICATIONS
* * * MP3 players Portable Multimedia Applications Multimedia Handsets
WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/
Production Data , August 2008, Rev 4.0
Copyright (c)2008 Wolfson Microelectronics plc
WM8900
Production Data
BLOCK DIAGRAM
1uF 10uF AUX / LCOM DGND DCVDD DBVDD CPVDDHI CPVDDLO CFB1 CFB2 VNEG 10uF VPOS CPGND
W WM8900
LINPUT3/JD LINPUT2
-12 to +19dB, 1dB steps -12 -> 6dB, 3dB steps, mute -12 -> 6dB, 3dB steps, mute
-15 to +6dB, 3dB steps
-15 to +6dB, 3dB steps
-57 to +6dB, 1dB steps, mute
LINEOUT1L
-57 to +6dB, 1dB steps, mute
LINEOUT2L 0.47uF
+ vmid -
+
0, 13, 20, 29dB, mute -12 -> 6dB, 3dB steps, mute -12 -> 6dB, 3dB steps, mute
ADC
ADC DIGITAL FILTERS VOLUME DAC DIGITAL FILTERS VOLUME
-15 to +6dB, 3dB steps
+
DAC
-15 to +6dB, 3dB steps
LEFT MIXER
HPVP
HPINL HPL
LINPUT1
RINPUT1
vmid
INPUT PGAs
+
-12 to +19dB, 1dB steps
SYSCLK
-15 to +6dB, 3dB steps
Charge Pump
RIGHT MIXER
HPVN
0, 13, 20, 29dB, mute
HPGND
HPVP
+
-12 -> 6dB, 3dB steps, mute -12 -> 6dB, 3dB steps, mute
ADC
DAC
-15 to +6dB, 3dB steps
+
HPR
HPVN
HPGND
HPINR 0.47uF LINEOUT2R
RINPUT2
-15 to +6dB, 3dB steps -15 to +6dB, 3dB steps
-57 to +6dB, 1dB steps, mute
RINPUT3/JD
SYSCLK
-57 to +6dB, 1dB steps, mute
MICBIAS
50K 50K
ADCREF DACREF
DIGITAL AUDIO INTERFACE
GPIO
LINEOUT1R CONTROL INTERFACE
FLL
AGND
VMID
BCLK ADCLRC/GPIO ADCDAT DACLRC DACDAT
w
SCLK SDIN CSB/GPIO MODE/GPIO
4.7uF
AVDD
MCLK
PD, August 2008, Rev 4.0 2
Production Data
WM8900 TABLE OF CONTENTS
DESCRIPTION ............................................................................................. 1 FEATURES .................................................................................................. 1 APPLICATIONS ........................................................................................... 1 BLOCK DIAGRAM ....................................................................................... 2 TABLE OF CONTENTS ............................................................................... 3 PIN CONFIGURATION................................................................................. 5 ORDERING INFORMATION ........................................................................ 5 PIN DESCRIPTION ...................................................................................... 6 ABSOLUTE MAXIMUM RATINGS............................................................... 7 RECOMMENDED OPERATING CONDITIONS ........................................... 7 ELECTRICAL CHARACTERISTICS ............................................................ 8 POWER CONSUMPTION .......................................................................... 14 DAC TO HEADPHONE POWER CONSUMPTION .................................... 15 EXTERNAL COMPONENTS...................................................................... 18 RECOMMENDED TEST METHOD FOR TESTING AUDIO OUTPUTS..... 19 AUDIO PATHS OVERVIEW....................................................................... 21
SYSTEM CLOCK TIMING..................................................................................22
AUDIO INTERFACE TIMING ..................................................................... 23
MASTER MODE.................................................................................................23 SLAVE MODE....................................................................................................24
CONTROL INTERFACE TIMING ............................................................... 25
2-WIRE MODE...................................................................................................25 3-WIRE MODE...................................................................................................26
INTERNAL POWER ON RESET CIRCUIT ................................................ 27 POP-CLICK MINIMISATION CONTROL REGISTERS.............................. 29 DEVICE DESCRIPTION ............................................................................. 30
INTRODUCTION................................................................................................30 INPUT SIGNAL PATH........................................................................................30 ANALOGUE TO DIGITAL CONVERTER (ADC).................................................38 DIGITAL MIXING................................................................................................41 DIGITAL TO ANALOGUE CONVERTER (DAC).................................................44 OUTPUT SIGNAL PATH ....................................................................................48 ULTRA-LOW POWER GROUND-REFERENCED HEADPHONE OUTPUT.......56 MASTER BIAS ...................................................................................................57 OPTIMAL PLAYBACK POWER CONSUMPTION ..............................................58 VOLUME UPDATES ..........................................................................................59 HEADPHONE JACK DETECT ...........................................................................61 THERMAL SHUTDOWN ....................................................................................62 GENERAL PURPOSE INPUT/OUTPUT.............................................................63 DIGITAL AUDIO INTERFACE ............................................................................64 AUDIO INTERFACE CONTROL ........................................................................71 CLOCKING AND SAMPLE RATES....................................................................75 FLL.....................................................................................................................81 CONTROL INTERFACE.....................................................................................84 READBACK IN 2-WIRE MODE ..........................................................................86
RESETTING THE CHIP.............................................................................. 87 POWER MANAGEMENT ........................................................................... 87 STOPPING THE MASTER CLOCK ........................................................... 89 REGISTER MAP ........................................................................................ 90
w
PD, August 2008, Rev 4.0 3
WM8900
Production Data
DIGITAL FILTER CHARACTERISTICS................................................... 106
ADC FILTER RESPONSES .............................................................................107 ADC FILTER RESPONSES .............................................................................107 DAC FILTER RESPONSES .............................................................................107 DE-EMPHASIS FILTER RESPONSES ............................................................108 ADC HIGH PASS FILTER RESPONSES .........................................................109
APPLICATIONS INFORMATION ............................................................. 110
RECOMMENDED PATHS................................................................................110 RECOMMENDED POWER DOWN SEQUENCE .............................................115
IMPORTANT NOTICE .............................................................................. 117
ADDRESS:.......................................................................................................117
w
PD, August 2008, Rev 4.0 4
Production Data
WM8900
PIN CONFIGURATION
ORDERING INFORMATION
ORDER CODE WM8900LGEFK/V WM8900LGEFK/RV TEMPERATURE RANGE -25C to +85C -25C to +85C PACKAGE 40-lead QFN (5x5x0.55mm) (Pb-free) 40-lead QFN (5x5x0.55mm) (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL3 MSL3 PEAK SOLDERING TEMPERATURE 260C 260C
Note: Reel quantity = 3500 Tube quantity = 95
w
PD, August 2008, Rev 4.0 5
WM8900 PIN DESCRIPTION
PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NAME MICBIAS LINPUT1 RINPUT1 LINPUT2 RINPUT2 LINPUT3 / JD RINPUT3 / JD MODE / GPIO DBVDD DGND MCLK DCVDD BCLK ADCDAT ADCLRC / GPIO DACDAT DACLRC SDIN SCLK CSB / GPIO CPVDDLO CPVDDHI CFB1 VPOS CPGND CFB2 VNEG HP_R HP_L HPGND HP_INL HP_INR LINEOUT_2R LINEOUT_2L AVDD VMID AGND LINEOUT_1L LINEOUT_1R AUX / LCOM TYPE Analogue Output Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Digital Input / Output Supply Supply Digital Input Supply Digital Input / Output Digital Output Digital Input / Output Digital Input Digital Input / Output Digital Input/Output Digital Input Digital Input / Output Supply Supply Analogue Output Analogue Output Supply Analogue Output Analogue Output Analogue Output Analogue Output Analogue Input Analogue Input Analogue Input Analogue Output Analogue Output Supply Analogue Output Supply Analogue Output Analogue Output Analogue Input Microphone Bias Left Channel Input 1 (inverting) Right Channel Input 1 (inverting) Left Channel Input 2 (non-inverting) Right Channel Input 2 (non-inverting) DESCRIPTION
Production Data
Left Channel Input 3 or Jack Detect (non-inverting) Right Channel Input 3 or Jack Detect (non-inverting) 2-wire / 3-wire control interface mode select or GPIO Digital Buffer (I/O) Supply Digital Ground (return path for both DCVDD and DBVDD) Master Clock Digital Supply (Digital Core and FLL Digital) Audio Interface Bit Clock ADC Digital Audio Data Audio Interface ADC Left/Right Clock or GPIO pin DAC Digital Audio Data Audio Interface DAC Left / Right Clock Control Interface Data Input / 2-wire Acknowledge output Control Interface Clock Input Chip select or GPIO Lower Supply for charge pump typically 1.8v Supply for charge pump 2.4 to 3.3v Flyback capacitor connection 1 Headphone positive supply decoupling capacitor Ground for Headphone Charge Pump Flyback capacitor connection 2 Headphone negative supply decoupling capacitor Right headphone output Left headphone output Headphone ground reference Left channel input to headphone driver Right channel input to headphone driver Right channel line output 2 Left channel line output 2 Analogue Supply (DAC, ADC, Input Amps, Lineout, Mixers & FLL Analogue) Midrail Voltage Decoupling Capacitor Analogue Ground Left channel line output 1 Right channel line output 1 Aux Mono Input / Low noise Line input ground connection
Note: It is recommended that the PCB is laid out with a single ground plane. The QFN ground paddle should be tracked directly to AGND on the application PCB.
w
PD, August 2008, Rev 4.0 6
Production Data
WM8900
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION Supply voltages Voltage range digital inputs Voltage range analogue inputs Operating temperature range, TA Storage temperature after soldering Notes 1. 2. 3. 4. 5. Analogue and digital grounds must always be within 0.3V of each other.
MIN -0.3V DGND -0.3V AGND -0.3V -25C -65C
MAX +3.63V DBVDD +0.3V AVDD +0.3V +85C +150C
All digital and analogue supplies are completely independent from each other (i.e. not internally connected). DCVDD must be <= DBVDD. DBVDD and DCVDD must be <= AVDD. CPVDDLO must be <= CPVDDHI
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range (Core) Digital supply range (Buffer) Analogue supply AVDD Charge Pump Analog Supply Charge Pump Analog Supply Ground DCVDD DBVDD AVDD CPVDDLO CPVDDHI DGND, AGND, CPGND SYMBOL MIN 1.7 1.7 2.28 1.6 2.28 0 TYP MAX 3.6 3.6 3.6 3.6 3.6 V V V V V V UNIT
w
PD, August 2008, Rev 4.0 7
WM8900 ELECTRICAL CHARACTERISTICS
Test Conditions
Production Data
DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=CPGND=HPGND=0V, AVDD=CPVDDHI=2.4V, CPVDDLO=1.8V; TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER Full-scale Input Signal Level - AVDD = 3.3v VINFS is proportional to AVDD VINFS = (AVDD/3.3) x 1Vrms SYMBOL VINFS TEST CONDITIONS L/RINPUT1 Single-ended L/RINPUT2/3 Differential MIC L/RINPUT2/3 Boost or bypass path L/RINPUT3 Boost + bypass path Full-scale Input Signal Level - AVDD = 3.0v VINFS L/RINPUT1 Single-ended L/RINPUT2/3 Differential MIC L/RINPUT2/3 Boost or bypass path L/RINPUT3 Boost + bypass path Full-scale Input Signal Level - AVDD = 2.4v VINFS L/RINPUT1 Single-ended L/RINPUT2/3 Differential MIC L/RINPUT2/3 Boost or bypass path L/RINPUT3 Boost + bypass path Mic PGA equivalent input noise 0 to 20kHz, +19dB gain MIN TYP 1.0 0 0.5 -6 1.0 0 1.0 0 0.9091 -0.828 0.455 -6.84 0.9091 -0.828 0.9091 -0.828 0.727 -2.77 0.364 -8.79 0.727 -2.77 0.727 -2.77 150 MAX UNIT Vrms dBV Vrms dBV Vrms dBV Vrms dBV Vrms dBV Vrms dBV Vrms dBV Vrms dBV Vrms dBV Vrms dBV Vrms dBV Vrms dBV uV Analogue Inputs (LINPUT1, RINPUT1, LINPUT2, LINPUT3, RINPUT2, RINPUT3)
w
PD, August 2008, Rev 4.0 8
Production Data
WM8900
Test Conditions DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=CPGND=HPGND=0V, AVDD=CPVDDHI=2.4V, CPVDDLO=1.8V; TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER Input resistance (Note that input boost and bypass path resistances will be seen in parallel with PGA input resistance when these paths are enabled) SYMBOL RINPUT1 TEST CONDITIONS +19dB PGA gain Differential or singleended MIC configuration 0dB PGA gain Differential or singleended MIC configuration -12dB PGA gain Differential or singleended MIC configuration (Constant for all gains) Differential MIC configuration Max boost gain L/RINPUT2/3 to boost 0dB boost gain L/RINPUT2/3 to boost Min boost gain L/RINPUT2/3 to boost Max bypass gain L/RINPUT2/3 to bypass Min bypass gain L/RINPUT2/3 to bypass Max boost gain AUX to boost 0dB boost gain AUX to boost Min boost gain AUX to boost Max boost gain AUX to bypass 0dB boost gain AUX to bypass Min boost gain AUX to bypass MIN TYP 2 MAX UNIT k
RINPUT1
10
k
RINPUT1
16
k
RINPUT2, RINPUT3 RINPUT2, RINPUT3 RINPUT2, RINPUT3 RINPUT2, RINPUT3 RINPUT3 RINPUT3 RAUX RAUX RAUX RAUX RAUX RAUX Input capacitance MIC Programmable Gain Amplifier (PGA) Programmable Gain Programmable Gain Step Size Mute Attenuation Selectable Input Gain Boost Gain Boost Steps
20
k
7.5 15 60 10 112 4.4 8.61 34.3 5.75 11.41 63.65 10 -12 +19 1 100
k k k k k k k k k k k pF dB dB dB dB dB
Guaranteed monotonic
Input from PGA Input from L/RINPUT2 or L/RINPUT3
0, 13, 20, 29, MUTE -12, -6, 0, 6, MUTE
w
PD, August 2008, Rev 4.0 9
WM8900
Production Data
Test Conditions DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=CPGND=HPGND=0V, AVDD=CPVDDHI=2.4V, CPVDDLO=1.8V; TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER Signal to Noise Ratio (A-weighted) Signal to Noise Ratio (Unweighted) Total Harmonic Distortion SYMBOL SNR TEST CONDITIONS AVDD=3.3V AVDD = 2.4V SNR AVDD=3.3V AVDD = 2.4V THD -1dBFs input, AVDD = 3.3V -1dBFs input, AVDD = 2.4V Total Harmonic Distortion + Noise THD+N -1dBFs input, AVDD = 3.3V -1dBFs input, AVDD = 2.4V ADC Channel Separation 1kHz full scale signal into ADC via L/RINPUT1, MIC amp (single-ended) and boost 1kHz full scale signal into ADC via L/RINPUT1/2, MIC amp (differential) and boost 1kHz full scale signal into ADC via L/RINPUT2 and boost 1kHz full scale signal into ADC via L/RINPUT3 and boost Line Input / MIC Separation (Quiescent input to ADC via boost; Output on ADC; 1kHz on L/RINPUT3 to HP out via bypass path) Boost / Bypass Separation (Quiescent L/RINPUT3 to HP outputs via bypass) Single-ended MIC input on L/RINPUT1 Differential MIC input using L/RINPUT2 1kHz on LINPUT2 to ADC via boost only 1kHz on LINPUT1 to ADC via single-ended MIC PGA & boost 1kHz signal SNR THD THD+N AVDD=2.4V AVDD=2.4V AVDD=2.4V 90 83 MIN TYP 95 91 93 90 -84 -84 -82 -82 90 -73 dB -76 dB dB dB MAX UNIT dB Analogue Inputs (LINPUT1, RINPUT1, LINPUT2, RINPUT2, LINPUT3, RINPUT3) to ADC Out
90
dB
90
dB
90
dB
90 90 90 90
dB dB dB dB
Channel Matching Signal to Noise Ratio (A-weighted) Total Harmonic Distortion Total Harmonic Distortion + Noise
0.2 97 -89 -88 -80 -79
dB dB dB dB
DAC to Line-Out (LINEOUT_1L / LINEOUT_1R or LINEOUT_2L / LINEOUT_2R with 10k / 50pF load)
DAC to Line-Out (LINEOUT_1L / LINEOUT_1R or LINEOUT_2L / LINEOUT_2R with 10k / 50pF load) - Reduced Power Mode (DAC_BIAS = 01 = Half Bias) Signal to Noise Ratio (A-weighted) Signal to Noise Ratio (Unweighted) Total Harmonic Distortion Total Harmonic Distortion + Noise SNR SNR THD THD+N AVDD = 2.4V AVDD = 2.4V AVDD = 2.4V AVDD = 2.4V 92 89 -83 -81 dB dB dB dB
w
PD, August 2008, Rev 4.0 10
Production Data
WM8900
Test Conditions DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=CPGND=HPGND=0V, AVDD=CPVDDHI=2.4V, CPVDDLO=1.8V; TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER Channel Separation L/RINPUT3 to HP_L / HP_R via bypass path Channel Separation DAC to LINEOUT_2L / LINEOUT_2R to HP_L / HP_R Signal to Noise Ratio (A-weighted) Total Harmonic Distortion Total Harmonic Distortion + Noise SNR THD THD+N AVDD = 2.4V AVDD = 2.4V AVDD = 2.4V 90 97 -92 -90 -82 -80 dB dB dB 85 dB SYMBOL TEST CONDITIONS 1kHz signal MIN TYP 100 MAX UNIT dB
DAC to LINEOUT_2L / LINEOUT_2R to HP_L / HP_R - Reduced Power Mode (DAC_BIAS = 01 = Half Bias) 0dB Full scale output voltage Mute attenuation Signal to Noise Ratio (A-weighted) Signal to Noise Ratio (Unweighted) Total Harmonic Distortion SNR SNR THD 1kHz, full scale signal AVDD = 2.4V AVDD = 2.4V AVDD=2.4V, RL=32, PO= 5mW AVDD=2.4V, RL=16, PO= 5mW Total Harmonic Distortion + Noise THD+N AVDD=2.4V, RL=32, PO=5mW AVDD=2.4V, RL=16, PO= 5mW PGA for LINEOUT_2L and LINEOUT_2R (can be used to control HP_L and HP_R amplitude or as a separate LINE OUT) Minimum Gain Maximum Gain Programmable Gain Step Size PGA for LINEOUT_1L and LINEOUT_1R Minimum Gain Maximum Gain Programmable Gain Step Size Analogue Reference Levels Midrail Reference Voltage Buffered Reference Voltage Microphone Bias Bias Voltage VMICBIAS 3mA load current MBSEL = 0 3mA load current MBSEL = 1 Bias Current Source Output Noise Voltage IMICBIAS Vn 1kHz to 20kHz MICB_LVL = 0 1K to 20kHz MICB_LVL = 1 Digital Input / Output Input HIGH Level Input LOW Level Output HIGH Level Output LOW Level VIH VIL VOH VOL IOL=1mA IOH-1mA 0.9xDBVDD 0.7xDBVDD -5% -5% VMID VREF -3% -3% Guaranteed monotonic Guaranteed monotonic
AVDD/3.3 90 92 90 -86 -82 -84 -80
Vrms dB dB dB dB dB dB dB
-57 +6 1
dB dB dB
-57 +6 1 AVDD/2 AVDD/2 0.9xAVDD 0.65xAVDD +3% +3% + 5% + 5% 3 25 17
dB dB dB V V V V mA nV/Hz nV/Hz
V 0.3xDBVDD 0.1xDBVDD V V V
w
PD, August 2008, Rev 4.0 11
WM8900
Test Conditions
Production Data
DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=CPGND=HPGND=0V, AVDD=CPVDDHI=2.4V, CPVDDLO=1.8V; TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER Input capacitance Input leakage FLL Lock Time See note 3 Lock FLL_SLOW_LOCK_REF =0 FLL_SLOW_LOCK_REF =1 Reference Clock Frequency Output Clock Frequency Charge Pump Efficiency Startup Time High Input Low Input VPOS VNEG Charge Pump output switching frequency Internal clock (SYSCLK) when using charge pump Current consumption CPEFF CPST CPVDDHI CPVDDLO VPOS VNEG CPFREQ SYSCLK Using analog bypass e.g. See note 2 LRIN1 to HP out 12 Using CPVDDHI Using CPVDDLO Using CPVDDHI Using CPVDDLO 2.4 1.6 CPVDDHI/2 CPVDDLO/2 -CPVDDHI/2 -CPVDDLO/2 1.536 MHz MHz V 90 500 3.3 3.3 % us V V V FREF FOUT LRCLK_REF_ENA = 0 LRCLK_REF_ENA = 1 48kHz 8 10 509 49 19.2MHz 48 20 kHz MHz Reference Clock Periods SYMBOL TEST CONDITIONS MIN TYP 10 1 MAX UNIT pF uA
Standby mode (All modules powered down, clocks stopped) Idd (standby) 75 150 uA Table 1 Electrical characteristics (see Note 1)
w
PD, August 2008, Rev 4.0 12
Production Data
WM8900
Notes: 1. The bias conditions are explained in Table 45 on page 12. 2. For a given headphone load, it is expected that the HP_L/HP_R output will begin to clip at 6dB lower amplitude for every 50% reduction in charge pump SYSCLK. 3. The FLL lock time is the time from last CSB edge of serial interface write to first clock edge of fOUT from FLL (see Figure 46).
w
PD, August 2008, Rev 4.0 13
WM8900 POWER CONSUMPTION
MODE V Headphone Playback DAC to HP playback 32ohm load, quiescent 8kHz sample rate DAC to HP playback 32ohm load, 0.1mW/channel 8kHz sample rate DAC to HP playback 32ohm load, 2.0mW/channel 8kHz sample rate LINE OUT 1 Playback DAC to Line Out 1 playback 10k load, quiescent 48kHz sample rate DAC to Line Out 1 playback 10k load, quiescent 8kHz sample rate MIC/LINE Record Mic to ADC record, quiescent 48kHz sample rate Mic to ADC record, quiescent 8kHz sample rate Line In to ADC record, quiescent 48kHz sample rate Line In to ADC record, quiescent 8kHz sample rate Bypass Path to Headphone Line In to HP bypass path 32ohm load, quiescent Line In to HP bypass path 32ohm load, 0.1mW/channel Line In to HP bypass path 32ohm load, 2.0mW/channel Table 2 Power Consumption 3.3 3.0 2.4 3.3 3.0 2.4 3.3 3.0 2.4 0.7900 0.7220 0.5870 0.8680 0.7950 0.6540 0.8920 0.8200 0.6840 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 0.5410 0.5400 0.5410 0.5350 0.5350 0.5350 0.5410 0.5410 0.5410 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 0.0086 0.0071 0.0035 0.0086 0.0071 0.0034 0.0087 0.0070 0.0036 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 0.0000 0.0000 0.0000 1.5490 1.5540 1.6410 6.1740 6.2770 6.8540 3.3 3.0 2.4 3.3 3.0 2.4 3.3 3.0 2.4 3.3 3.0 2.4 3.3 3.0 2.4 3.3 3.0 2.4 3.3 3.0 2.4 4.5250 4.3220 3.9280 4.2830 4.1050 3.7540 4.5030 4.3020 3.9100 4.2590 4.0820 3.7360 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 2.4310 2.4380 2.4440 0.4090 0.4100 0.4100 2.4310 2.4370 2.4410 0.4090 0.4100 0.4110 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 0.0451 0.0377 0.0225 0.0077 0.0069 0.0037 0.0467 0.0409 0.0222 0.0074 0.0074 0.0038 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 0.0000 0.0001 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0001 0.0000 0.0000 3.3 3.0 2.4 3.3 3.0 2.4 3.3 3.0 2.4 3.3 3.0 2.4 3.3 3.0 2.4 3.3 3.0 2.4 2.4530 2.2090 1.7340 2.2950 2.0680 1.6240 1.8 1.8 1.8 1.8 1.8 1.8 2.5350 2.5350 2.5350 0.3590 0.3590 0.3590 1.8 1.8 1.8 1.8 1.8 1.8 0.0112 0.0096 0.0046 0.0020 0.0014 0.0007 1.8 1.8 1.8 1.8 1.8 1.8 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 3.3 3.0 2.4 3.3 3.0 2.4 3.3 3.0 2.4 3.3 3.0 2.4 3.3 3.0 2.4 2.2640 2.0490 1.6240 2.3720 2.1480 1.7050 2.3860 2.1620 1.7200 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 0.3600 0.3600 0.3600 0.4160 0.4140 0.4150 0.4140 0.4140 0.4150 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 0.0016 0.0016 0.0007 0.0024 0.0021 0.0012 0.0023 0.0020 0.0009 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 0.0000 0.0000 0.0000 1.6570 1.6620 1.6270 6.7160 6.8210 6.8700 3.3 3.0 2.4 3.3 3.0 2.4 3.3 3.0 2.4 AVDD mA V DCVDD mA V DBVDD mA CPVDDLO V mA
Production Data
CPVDDHI V mA 0.8680 0.7560 0.5560 0.0233 0.0207 0.0156 0.0762 0.0683 0.0534 0.0042 0.0033 0.0019 0.0140 0.0033 0.0019 0.0041 0.0033 0.0019 0.0042 0.0033 0.0018 0.0042 0.0033 0.0019 0.0042 0.0033 0.0018 1.6490 1.4570 1.1010 0.1130 0.1020 0.0801 0.4310 0.3890 0.3070
TOTAL mW 10.9865 9.0659 5.8812 11.6401 10.2466 7.8073 20.9633 19.7174 17.3835 12.6918 11.2171 8.7374 8.2372 6.8626 4.5496 19.4031 17.4323 13.8714 14.8978 13.0753 9.7587 19.3336 17.3761 13.8222 14.8181 13.0070 9.7176 9.0380 7.5219 5.0312 7.0040 6.4639 5.6849 16.4685 15.9121 15.6958
Note: All parameters in this table were measured at default bias conditions, and at 48kHz sample rate unless otherwise stated.
w
PD, August 2008, Rev 4.0 14
Production Data
WM8900
DAC TO HEADPHONE POWER CONSUMPTION
The following tables detail the DAC to Headphone power consumption differences and SNR differences (where applicable) between 4 different playback conditions and 3 different biasing modes. The biasing modes are detailed in Table 45 on page 12.
SUPPLIES MODE Default mode V
AVDD mA 4.11 3.71 2.93 2.57 2.33 1.85 2.09 1.89 1.51 V 3.30 3.00 2.40 3.30 3.00 2.40 3.30 3.00 2.40
DCVDD mA 2.27 2.27 2.27 2.27 2.27 2.27 2.27 2.27 2.27 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80
DBVDD V 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 mA 0.01 0.01 0.00 0.01 0.01 0.01 0.01 0.01 0.00
CPVDDLO V 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 mA 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
CPVDDHI V 3.30 3.00 2.40 3.30 3.00 2.40 3.30 3.00 2.40 mA 1.70 1.49 1.12 1.70 1.49 1.12 1.58 1.39 1.05
TOTAL mW 23.26 19.72 13.82 18.20 15.57 11.22 16.20 13.95 10.24
Reduced power mode
Ultra Low power mode
Table 3 DAC to Headphone Power Consumption: Quiescent (DAC input all zeroes and OUT2VOL PGA set to 0dB) SNR (SEE NOTE 2) (dB) -101 -100 -98 -98 -102 -101 -98. -98 -101 -100 -98 -98
SUPPLIES MODE V
AVDD mA 4.18 3.78 2.99 2.99 2.67 2.42 1.92 1.92 2.20 2.00 1.59 1.59 V 3.30
DCVDD mA 2.56 2.56 2.56 2.57 2.56 2.56 2.56 2.57 2.56 2.56 2.56 2.57 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80
DBVDD V 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 mA 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01
CPVDDLO V 1.80 1.80 1.80 1.60 1.80 1.80 1.80 1.60 1.80 1.80 1.80 1.60 mA 0.40 0.67 0.31 0.29 0.41 0.68 0.31 0.29 0.33 0.56 0.26 0.24
CPVDDHI V 3.30 3.00 2.40 2.40 3.30 3.00 2.40 2.40 3.30 3.00 2.40 2.40 mA 0.06 0.13 0.04 0.04 0.06 0.13 0.04 0.04 0.06 0.13 0.04 0.04
TOTAL mW 15.54 14.51 12.46 12.42 11.92 11.25 9.91 9.87 10.65 10.10 9.01 8.99
Default mode
3.00 2.40 2.40 3.30 3.00 2.40 2.40 3.30 3.00 2.40 2.40
Reduced power mode
Ultra Low power mode
Table 4 DAC to Headphone Power Consumption: -57dB Playback (DAC input 0dBFS 1kHz sine and OUT2VOL PGA set to -57dB)
w
PD, August 2008, Rev 4.0 15
WM8900
Production Data
SUPPLIES MODE V
AVDD mA 4.77 4.08 3.03 3.11 3.28 2.73 1.96 2.05 2.82 2.31 1.63 1.72 V 3.30
DCVDD mA 2.57 2.57 2.57 2.57 2.57 2.57 2.57 2.57 2.57 2.57 2.57 2.57 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80
DBVDD V 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 mA 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01
CPVDDLO V 1.80 1.80 1.80 1.60 1.80 1.80 1.80 1.60 1.80 1.80 1.80 1.60 mA 18.07 16.90 13.90 13.76 18.13 16.97 13.98 13.82 18.13 16.98 13.99 13.83
CPVDDHI V 3.30 3.00 2.40 2.40 3.30 3.00 2.40 2.40 3.30 3.00 2.40 2.40 mA 0.44 0.40 0.31 0.31 0.44 0.40 0.31 0.31 0.44 0.40 0.31 0.31
TOTAL mW 49.66 45.81 37.68 37.59 46.18 42.68 35.27 35.16 45.08 41.70 34.48 34.38
SNR (SEE NOTE 2) (dB) -99 -98 -96 -96 -99 -98 -96 -96 -99 -98 -95 -95
Default mode
3.00 2.40 2.40 3.30 3.00 2.40 2.40 3.30 3.00 2.40 2.40
Reduced power mode
Ultra Low power mode
Table 5 DAC to Headphone Power Consumption: -9dB Playback (DAC input 0dBFS 1kHz sine and OUT2VOL PGA set to -9dB) SNR (SEE NOTE 2) (dB) -95 -94 -92. -92 -94 -93 -91 -91 -93 -93 -91 -91
SUPPLIES MODE V
AVDD mA 5.08 4.48 3.37 3.37 3.59 3.13 2.31 2.31 3.13 2.72 1.98 1.98 V 3.30
DCVDD mA 2.57 2.57 2.57 2.57 2.57 2.57 2.57 2.57 2.57 2.57 2.57 2.57 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80
DBVDD V 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 mA 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01
CPVDDLO V 1.80 1.80 1.80 1.60 1.80 1.80 1.80 1.60 1.80 1.80 1.80 1.60 mA 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
CPVDDHI V 3.30 3.00 2.40 2.40 3.30 3.00 2.40 2.40 3.30 3.00 2.40 2.40 mA 39.87 35.93 27.88 27.86 39.95 36.00 27.92 27.90 39.95 36.00 27.91 27.90
TOTAL mW 112.53 101.62 79.64 79.57 109.13 98.55 77.19 77.14 108.03 97.56 76.39 76.35
Default mode
3.00 2.40 2.40 3.30 3.00 2.40 2.40 3.30 3.00 2.40 2.40
Reduced power mode
Ultra Low power mode
Table 6 DAC to Headphone Power Consumption: 0dB Playback (DAC input 0dBFS 1kHz sine and OUT2VOL PGA set to 0dB)
w
PD, August 2008, Rev 4.0 16
Production Data
WM8900
Notes: 1. Quiescent power consumption with OUT2VOL = 0dB is slightly higher than would be measured under typical listening levels. The headphone amplifier is being powered by CPVDDHI under quiescent test conditions. During typical playback listening levels (no more than 2mW into a 32Ohm headphone load), the headphone amplifier is powered by CPVDDLO, and a more realistic measure of power consumption can be estimated. A typical listening level would result in OUT2VOL being -9dB or lower, as shown in the above table. SNR measured with a -60dBFS DAC input signal. The most accurate measure of SNR is when OUT2VOL = 0dB, as no noise is attenuated.
2.
w
PD, August 2008, Rev 4.0 17
WM8900 EXTERNAL COMPONENTS
Production Data
Figure 1 illustrates the recommended external components for the WM8900. The configuration illustrated shows two pseudo-differential microphone inputs, two line inputs, two line outputs and the ground-referenced headphone output driver. Other configurations may require fewer external components. Table 7 describes the function of each component shown in Figure 1, showing which components are only required for specific input/output signal paths.
Figure 1 External Component Connectivity Note: In order to achieve stability of the Headphone output, the Zobel network (C19, C20, R9, R10) must be fitted.
w
PD, August 2008, Rev 4.0 18
Production Data
WM8900
IDENTIFIER C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 R1 R2 R3 R4 R9 R10
VALUE 0.1 uF 0.1 uF 4.7 uF 4.7 uF 4.7 uF 1 uF 1 uF 4.7 uF 4.7 uF 1 uF 1 uF 1 uF 1 uF 0.47 uF 0.47 uF 1 uF 10 uF 10 uF 22 nF 22 nF 1 uF 1 uF 2.2 k 2.2 k 0 0 49.9 49.9
FUNCTION DBVDD decoupling DCVDD decoupling AVDD decoupling CPVDDLO decoupling CPVDDHI decoupling LINPUT2 DC blocking LINPUT1 DC blocking VMID decoupling MICBIAS decoupling RINPUT2 DC blocking RINPUT1 DC blocking LINPUT3 DC blocking RINPUT3 DC blocking HP_INL DC blocking HP_INR DC blocking Charge Pump capacitor VNEG decoupling VPOS decoupling Headphone zobel network Headphone zobel network LINEOUT_L DC blocking LINEOUT_R DC blocking LINPUT2 Bias Current limit RINPUT2 Bias Current limit LINPUT1 Ground RINPUT1 Ground Headphone zobel network Headphone zobel network
REQUIRED FOR All applications
Ground Referenced Headphone Amplifier Left Microphone Input All applications Right Microphone Input Left Line Input Right Line Input
Ground Referenced Headphone Amplifier
Headphone Amp Left Line Output Right Line Output Left Microphone Input Right Microphone Input Left Microphone Input Right Microphone Input Headphone Amp in Normal mode
Table 7 External Components for WM8900 Please refer to WAN0188 for further details on the selection of external components for WM8900
RECOMMENDED TEST METHOD FOR TESTING AUDIO OUTPUTS
Most modern lab test equipment contains high speed A-D converter circuits hence can be sensitive to frequencies outside of the audio band which appear at their inputs. The software or hardware filters included in such test equipment may not be sufficient to attenuate out of band frequencies from the WM8900 charge pump. Although this does not affect performance within the audio band, false triggering of the test equipment outside the audio band can give inaccurate results. An external filter with a very steep attenuation curve above the audio band is recommended, such as the AUX0025 from Audio Precision (http://www.ap.com), or any filter which has a similar frequency response. The connection method is shown in Figure 2. The 100k resistance at each channel of the Audio Analyzer Input represents the Analyser's input impedance. These resistors are not required as additional components during measurement.
w
PD, August 2008, Rev 4.0 19
WM8900
Production Data
Figure 2 Recommended Filter Connections between WM8900 Audio Outputs and Audio Analyser for Measurement and Testing Only
w
PD, August 2008, Rev 4.0 20
1uF 10uF 10uF
Production Data
AUX / LCOM DGND DCVDD CPVDDHI CFB1 CFB2 VNEG VPOS CPGND DBVDD CPVDDLO
-57 to +6dB, 1dB steps, mute -15 to +6dB, 3dB steps
LINEOUT1L
LINPUT3/JD
IN3L_LMIXOUTL_VOL[2:0] IN4_MIXOUTL_VOL[2:0]
-57 to +6dB, 1dB steps, mute -15 to +6dB, 3dB steps
AGND
VMID
BCLK
ADCDAT
AVDD
DACLRC
DACDAT
MCLK
SCLK
SDIN
4.7uF
CSB/GPIO
PD, August 2008, Rev 4.0
ADCLRC/GPIO
MODE/GPIO
w
OUT1L_VOL[5:0] OUT1L_ENA IN3L_BOOST[2:0] IN3L_TO_MIXOUTL IN4_TO_MIXOUTL
-12 -> 6dB, -15 to +6dB, 3dB steps, mute
LINPUT2
-12 -> 6dB,
3dB steps,
IN2L_BOOST[2:0]
LINEOUT2L
mute
IN3L_ENA DAC_MONO
3dB steps
MIXINL_ENA MIXINL_MIXOUTL_VOL[2:0] MIXINL_TO_MIXOUTL
-12 to +19dB,
IN2L_ENA
1dB steps
OUT2L_VOL[5:0] OUT2L_ENA
0.47uF
HP_IP_ENA
+
+
MIXOUTL_ENA
AUDIO PATHS OVERVIEW
INL_TO_MIXINL
vmid
0, 13, 20, -12 -> 6dB, 3dB steps,
+
MIXL_ENA DACL_TO_MIXOUTL ADCL_ENA ADCL_VOL[7:0]
ADC DAC
MIXER DAC
-15 to +6dB, 3dB steps
LEFT
HPVP
HPINL
29dB, mute mute
INL_MIXINL_BOOST[1:0]
LINPUT1
ADC DIGITAL FILTERS VOLUME
-15 to +6dB, 3dB steps
IN1L_ENA MIXINR_TO_MIXOUTL MIXINR_MIXOUTL_VOL[2:0]
INL_VOL[4:0] INL_MUTE INL_ENA IN4L_BOOST[2:0] IN4R_BOOST[2:0]
-12 -> 6dB, 3dB steps, mute
DAC_MUTE DACL_ENA DACL_VOL[7:0]
HP_OP_ENA
HPL
INPUT
DIGITAL FILTERS VOLUME SYSCLK MIXINL_MIXOUTR_VOL[2:0] MIXINL_TO_MIXOUTR
Charge Pump
HPVN
Figure 3 Signal Path Overview and Control Diagram
HPGND
PGAs
DACR_TO_MIXOUTR
RINPUT1
MIXR_ENA
0, 13, 20,
IN1R_ENA
29dB,
vmid
-
mute
INL_TO_MIXINL
+
ADC
MIXINR_TO_MIXOUTR MIXINR_MIXOUTR_VOL[2:0]
-15 to +6dB, 3dB steps -12 -> 6dB,
DAC
RIGHT
HPVP
+
ADCR_ENA ADCR_VOL[7:0] DAC_MONO
3dB steps, mute
INR_MIXINR_BOOST[1:0]
+
MIXER MIXOUTR_ENA
HP_OP_ENA IN4_TO_MIXOUTR
HPVN
HPR
HPGND
IN2R_ENA
MIXINR_ENA -12 to +19dB,
DAC_MUTE DACR_ENA DACR_VOL[7:0]
IN3R_ENA IN3R_BOOST[2:0]
1dB steps
-12 -> 6dB,
3dB steps,
IN2R_BOOST[2:0]
HP_IP_ENA IN3R_TO_MIXOUTR
-57 to +6dB, 1dB steps,
HPINR
INR_VOL[4:0] INR_MUTE INR_ENA
mute
RINPUT2
IN4_MIXOUTR_VOL[2:0]
3dB steps
0.47uF
mute -15 to +6dB,
OUT2R_VOL[5:0] OUT2R_ENA
-57 to +6dB, 1dB steps, mute
-15 to +6dB, 3dB steps
LINEOUT2R
RINPUT3/JD
IN3R_LMIXOUTR_VOL[2:0]
OUT1R_VOL[5:0]
MICB_LVL
MICB_ENA
ADCREF DACREF
SYSCLK
GPIO
OUT1R_ENA
LINEOUT1R
MICBIAS DIGITAL AUDIO INTERFACE
CONTROL
FLL
50K
50K
INTERFACE
VMID_MOD[1:0] VREF
WM8900
21
WM8900
Production Data
SYSTEM CLOCK TIMING
tMCLKL MCLK tMCLKH tMCLKY
Figure 4 System Clock Timing Requirements
Test Conditions DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=CPGND=HPGND=0V, AVDD=CPVDDHI=2.4V, CPVDDLO=1.6V; TA = +25oC PARAMETER System Clock Timing Information MCLK cycle time (Codec clocked directly) MCLK cycle time (Codec clocked via FLL) MCLK duty cycle TMCLKY TMCLKY TMCLKDS 80 50 60:40 40:60 ns ns SYMBOL CONDITIONS MIN TYP MAX UNIT
w
PD, August 2008, Rev 4.0 22
Production Data
WM8900
AUDIO INTERFACE TIMING
MASTER MODE
The Digital Audio Data timing in Master Mode is illustrated in Figure 5. See "Digital Audio Interface" for further details.
Figure 5 Digital Audio Data Timing - Master Mode
Test Conditions DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=0V, AVDD=2.4V; TA=+25oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information ADCLRC/DACLRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge DACDAT hold time from BCLK rising edge tDL tDDA tDST tDHT 10 10 10 10 ns ns ns ns SYMBOL MIN TYP MAX UNIT
w
PD, August 2008, Rev 4.0 23
WM8900
SLAVE MODE
Production Data
The Digital Audio Data timing in Slave Mode is illustrated in Figure 6. See "Digital Audio Interface" for further details.
Figure 6 Digital Audio Data Timing - Slave Mode
Test Conditions DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=0V, AVDD=2.4V; TA=+25oC, Slave Mode, fs=48kHz, MCLK= 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information BCLK cycle time BCLK pulse width high BCLK pulse width low ADCLRC/DACLRC set-up time to BCLK rising edge ADCLRC/DACLRC hold time from BCLK rising edge DACDAT hold time from BCLK rising edge ADCDAT propagation delay from BCLK falling edge Note: BCLK period should always be greater than or equal to MCLK period. tBCY tBCH tBCL tLRSU tLRH tDH tDD 80 35 35 10 10 10 15 ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
w
PD, August 2008, Rev 4.0 24
Production Data
WM8900
CONTROL INTERFACE TIMING
2-WIRE MODE
t3 SDIN t6 SCLK t1 t9 t7 t2 t5 t4 t8 t3
Figure 7 Control Interface Timing - 2-Wire Serial Control Mode
Test Conditions DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=0V, AVDD=2.4V; TA=+25oC, Slave Mode, fs=48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width of spikes that will be suppressed t1 t2 t3 t4 t5 t6 t7 t8 t9 tps 0 600 900 5 1.3 600 600 600 100 300 300 526 kHz us ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
w
PD, August 2008, Rev 4.0 25
WM8900
3-WIRE MODE
tCSL CSB tSCY tSCH SCLK tSCL tSCS
Production Data
tCSH
tCSS
SDIN tDSU tDHO
LSB
Figure 8 Control Interface Timing - 3-Wire Serial Control Mode
Test Conditions DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=0V, AVDD=2.4V; TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SCLK to SDIN hold time CSB pulse width low CSB pulse width high CSB rising to SCLK rising Pulse width of spikes that will be suppressed tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS tps 80 200 80 80 40 40 40 40 40 0 5 ns ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
w
PD, August 2008, Rev 4.0 26
Production Data
WM8900
INTERNAL POWER ON RESET CIRCUIT
Figure 9 Internal Power on Reset Circuit Schematic
The WM8900 includes an internal Power-On-Reset Circuit, as shown in Figure 9, which is used to reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and monitors DCVDD. It asserts PORB low if AVDD or DCVDD is below a minimum threshold.
Figure 10 Typical Power up Sequence where AVDD is Powered before DCVDD
Figure 10 shows a typical power-up sequence where AVDD comes up first. When AVDD goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Now AVDD is at full supply level. Next DCVDD rises to Vpord_on and PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where AVDD falls first, PORB is asserted low whenever AVDD drops below the minimum threshold Vpora_off.
w
PD, August 2008, Rev 4.0 27
WM8900
Production Data
Figure 11 Typical Power up Sequence where DCVDD is Powered before AVDD
Figure 11 shows a typical power-up sequence where DCVDD comes up first. First it is assumed that DCVDD is already up to specified operating voltage. When AVDD goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD rises to Vpora_on, PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where DCVDD falls first, PORB is asserted low whenever DCVDD drops below the minimum threshold Vpord_off. SYMBOL Vpora Vpora_on Vpora_off Vpord_on Vpord_off MIN 0.4 0.9 0.4 0.5 0.4 TYP 0.6 1.2 0.6 0.7 0.6 MAX 0.8 1.6 0.8 0.9 0.8 UNIT V V V V V
Table 8 Typical POR Operation (typical values, not tested) Notes: 1. If AVDD and DCVDD suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go below Vpora_off or Vpord_off) then the chip will not reset and will resume normal operation when the voltage is back to the recommended level again. The chip will enter reset at power down when AVDD or DCVDD falls below Vpora_off or Vpord_off. This may be important if the supply is turned on and off frequently by a power management system. The minimum tpor period is maintained even if DCVDD and AVDD have zero rise time. This specification is guaranteed by design rather than test.
2.
3.
w
PD, August 2008, Rev 4.0 28
Production Data
WM8900
POP-CLICK MINIMISATION CONTROL REGISTERS
It is recommended that the power management control bits are used to enable/disable the required blocks within the WM8900 according to the desired application or mode. The sequencing of these controls may be important in the reduction of audible pops and clicks. Detailed information is available for specific requirements - see "Applications Information". The additional control bits described in Table 9 are normally set to default only but may be used to control pops and clicks under certain conditions. REGISTER ADDRESS R1 (01h) Power Management 1 BIT 8 LABEL STARTUP_BIAS_ENA DEFAULT 0 DESCRIPTION Bias Startup control. Normally 0 but can be temporarily set to 1 during startup to minimise pops and clicks. Provides VMID to input and output analogue pins when not enabled. Normally 0 but can be temporarily set to 1 during startup to minimise pops and clicks. 1 = Clamps LINEOUT_1L and LINEOUT_1R to GND via 8K resistance 0 = 8k resistance not connected to GND 7 OUT2_DIS 0 1 = Clamps LINEOUT_2L and LINEOUT_2R to GND via 8K resistance 0 = 8k resistance not connected to GND 5 4 VMID_DISCH BIAS_SRC 0 0 Enables fast discharge of Vmid to GND Vmid bias select. Normally 0 but can be temporarily set to 1 during startup to select the soft-start Vmid source. Vmid soft-start control. Normally 0 but can be temporarily set to 1 during startup to ramp Vmid in a controlled manner. Clamps HP_INL and HP_INR to GND Clamps HP_L and HP_R outputs to GND Shorts the inputs to the outputs Shorts the feedback resistor. 0 = Normal operation 1 = Shorts feedback resistor. About 20dB `mute' attenuation
2
VMID_BUF_ENA
0
R30 (1Eh) Additional Control
8
OUT1_DIS
0
3
VMID_SOFTST
0
R58 (3Ah) Headphone Control 1
5 4 3 2
HP_CLAMP_IP HP_CLAMP_OP HP_SHORT HP_SHORT2
0 0 0 0
Table 9 Pop and Click Minimisation Register Settings
w
PD, August 2008, Rev 4.0 29
WM8900 DEVICE DESCRIPTION
INTRODUCTION
Production Data
The WM8900 is an ultra low power audio codec offering a combination of high quality audio, advanced features, low power consumption and small package size. These characteristics make it ideal for portable multimedia applications with stereo headphone outputs such as games consoles, portable media players and multimedia phones. Class G, Stereo ultra low power ground-referenced headphone drivers provide reduced power consumption during DAC playback at typical listening levels, with user selectable low power modes allowing a trade off between optimal audio performance and lowest power consumption . A flexible input configuration includes support for two stereo microphone interfaces (single-ended or pseudo-differential), additional stereo line inputs and auxiliary line input which can also be used a common input ground connection. Up to three stereo analogue input sources are available, removing the need for external analogue switches in many applications. Boost amplifiers are available for additional gain on the microphone inputs and a programmable gain amplifier. The stereo ADC and DAC are of hi-fi quality using a 24-bit, low-order oversampling architecture to deliver optimum performance. A flexible clocking arrangement supports mixed ADC and DAC sample rates. The DAC output signal can be mixed with analogue input signals from the line inputs, auxiliary input, mic boost stage or bypass paths. This mix is available on both headphone and line outputs. The WM8900 has a configurable digital audio interface where ADC data can be read and digital audio playback data fed to the DAC. It supports a number of audio data formats including I2S, DSP Mode (a burst mode in which frame sync plus two data packed words are transmitted), MSB-First, left justified and MSB-First, right justified, and can operate in master or slave modes. In PCM mode A-law and -law companding is supported. The SYSCLK (system clock) provides clocking for the ADCs, DACs, DSP core, integrated charge pump and the digital audio interface. SYSCLK can be derived directly from the MCLK pin or via an integrated FLL, providing flexibility to support a wide range of clocking schemes. All MCLK frequencies typically used in portable systems are supported for sample rates between 8kHz and 48kHz. A flexible switching clock for the ultra low power ground-referenced headphone drivers (synchronous with the audio DSP clocks for best performance) is also derived from SYSCLK. To allow full software control over all its features, the WM8900 uses a 2 or 3 wire control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. Unused circuitry can be disabled via software to save power, while low leakage currents extend standby and off time in portable battery-powered applications.
INPUT SIGNAL PATH
The WM8900 has three stereo analogue input channels which can be configured in many combinations as line inputs, single-ended microphone or differential microphone connections. Line inputs and microphone PGA outputs can be routed to the hi-fi ADCs or directly to the output mixers via a bypass path. Multiple inputs can be connected simultaneously and mixed together or each can be individually enabled or muted as required.
SINGLE-ENDED MICROPHONE INPUTS * LINPUT1 (RINPUT1) only
In this configuration, the microphone signal is connected to LINPUT1 (RINPUT1), and the noninverting input of the input PGA is connected to Vmid. The Left (Right) channel input PGA and boost PGA must both be enabled in this configuration. The gain of the input PGA and boost PGA can be controlled via register settings, as described in Table 14 and Table 15. In this configuration, LINPUT2 (RINPUT2) and LINPUT3 (RINPUT3) must not be connected to the input PGA, but these connections are available for use as Line inputs directly to the input mixers. Note that the input impedance at LINPUT1 (RINPUT1) changes with the input PGA gain setting, as described under "Electrical Characteristics". The input impedance can be determined for any gain setting according to the following formula:
w
PD, August 2008, Rev 4.0 30
Production Data
WM8900
Rin = 20k / [1/GAIN)+1], where GAIN is voltage gain of the input PGA stage. For example, if the input PGA gain is +13dB, then GAIN = 4.47 and Rin = 16.3k. The external connections for this configuration and the required register settings are detailed below:
Figure 12 Single-ended Microphone Configurations
Note that setting IN2L_ENA and IN3L_ENA to 0 automatically causes Vmid to be connected to the non-inverting Left PGA input. Similarly setting IN2R_ENA and IN3R_ENA to 0 automatically causes Vmid to be connected to the non-inverting Right PGA input.
DIFFERENTIAL MICROPHONE INPUTS * * LINPUT1 (RINPUT1) and LINPUT2 (RINPUT2) or LINPUT1 (RINPUT1) and LINPUT3 (RINPUT3)
In this configuration, the non-inverted microphone signal is connected to LINPUT2 (RINPUT2) or LINPUT3 (RINPUT3) and the inverted (or noisy ground) signal is connected to LINPUT1 (RINPUT1). The remaining input must not be connected to the input PGA, and is available for use as an additional Line input. The Left (Right) channel input PGA and boost PGA must both be enabled in this configuration. The gain of the input PGA and Boost PGA can be controlled via register settings, as described in Table 14 and Table 15. Note that the input impedance LINPUT1 (RINPUT1) changes with the input PGA gain setting, as described under "Electrical Characteristics". In this configuration, the input impedance LINPUT2 (RINPUT2) or LINPUT3 (RINPUT3) does not change with the gain setting. The inverting and noninverting inputs are therefore not matched and this configuration is not fully differential. The LINPUT1 (RINPUT1) input impedance can be determined for any gain setting as described above for the Single-Ended configuration. The external connections for this configuration and the required register settings are detailed below:
w
PD, August 2008, Rev 4.0 31
WM8900
Production Data
Figure 13 Differential Microphone Input Configurations
LINE INPUTS * * * LINPUT2 (RINPUT2) LINPUT3 (RINPUT3) AUX
Two pairs of stereo line inputs are available as analogue inputs. Each of these may be an internal source (e.g. FM radio IC) or an external signal source. These can be mixed with the microphone input or can be enabled individually in the ADC input path. The Left (Right) channel boost PGA must be enabled in this configuration. The gain of the boost PGA can be controlled via register settings, as described in Table 16. LINPUT3 (RINPUT3) may also be routed directly to the output mixer, including when the boost PGA is powered down. If a differential microphone connection is used, then only one of the line inputs is available. For example, if LINPUT1 and LINPUT2 are used as a differential microphone, then LINPUT3 can be used as a line input Note that, in this configuration, the input impedance LINPUT2 (RINPUT2) or LINPUT3 (RINPUT3) changes with the boost gain setting, as described under "Electrical Characteristics". The input impedance can be determined for any gain setting as described above for the Single-Ended microphone configuration, but based upon the boost gain amplification instead of the microphone input PGA. A mono input, AUX, is also provided. This input may be mixed with the Left and Right channel ADC inputs and may also be routed directly to the output mixers. The gain of this input on the ADC input path is described in Table 16. The external connections for this configuration and the required register settings are detailed below:
w
PD, August 2008, Rev 4.0 32
Production Data
WM8900
Figure 14 Line Input Configurations Note that when using LRINPUT2 or LRINPUT3, there is inherent feedback signal to LRINPUT1 as shown in Figure 15.
Figure 15 Input Feedback INPUT PGA / BOOST MIXER ENABLE The input boost mixers are enabled by the MIXINL_ENA and MIXINR_ENA register bits, as described in Table 10. The microphone input PGAs are enabled by the INL_ENA and INR_ENA register bits and can be disabled independently of the boost mixer to save power. The microphone input PGAs cannot be enabled if the associated boost mixer is not enabled.
w
PD, August 2008, Rev 4.0 33
WM8900
Production Data
REGISTER ADDRESS R2 (02h) Power Management 2
BIT 5
LABEL MIXINL_ENA 0
DEFAULT
DESCRIPTION Left channel input boost enable 0 = Boost disabled 1 = Boost enabled Right channel input boost enable 0 = Boost disabled 1 = Boost enabled Left channel input PGA enable 0 = PGA disabled 1 = PGA enabled (if MIXINL_ENA = 1) Right channel input PGA enable 0 = PGA disabled 1 = PGA enabled (if MIXINR_ENA = 1)
4
MIXINR_ENA
0
3
INL_ENA
0
2
INR_ENA
0
Table 10 Input PGA and Boost Mixer Enable Register Settings
INPUT PGA CONFIGURATION The input PGAs are configured by the input signal path control registers, as described in Table 11. The input PGA is connected to the ADC signal path under the control of the ADC signal path input register. REGISTER ADDRESS R26 (1Ah) ADC Signal Path R21 (15h) Input Control BIT 6 LABEL INL_TO_MIXINL DEFAUL T 0 DESCRIPTION Connect Left Input PGA to Left Input Boost mixer 0 = Not connected 1 = Connected Connect LINPUT1 to inverting input of Left Input PGA 0 = LINPUT1 not connected to PGA 1 = LINPUT1 connected to PGA 5 IN2L_ENA 0 Connect LINPUT2 to non-inverting input of Left Input PGA 0 = LINPUT2 not connected to PGA 1 = LINPUT2 connected to PGA Connect LINPUT3 to non-inverting input of Left Input PGA 0 = LINPUT3 not connected to PGA 1 = LINPUT3 connected to PGA R26 (1Ah) ADC Signal Path R21 (15h) Input Control 2 INR_TO_MIXINR 0 Connect Right Input PGA to Right Input Boost mixer 0 = Not connected 1 = Connected Connect RINPUT1 to inverting input of Right Input PGA 0 = RINPUT1 not connected to PGA 1 = RINPUT1 connected to PGA 1 IN2R_ENA 0 Connect RINPUT2 to non-inverting input of Right Input PGA 0 = RINPUT2 not connected to PGA 1 = RINPUT2 connected to PGA Connect RINPUT3 to non-inverting input of Right Input PGA 0 = RINPUT3 not connected to PGA 1 = RINPUT3 connected to PGA Table 11 Input PGA Control
6
IN1L_ENA
1
4
IN3L_ENA
0
2
IN1R_ENA
1
0
IN3R_ENA
0
w
PD, August 2008, Rev 4.0 34
Production Data
WM8900
MICROPHONE BIAS The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones via an external resistor. Refer to the Applications Information section for recommended external components. The MICBIAS can be enabled or disabled using the MICB_ENA control bit and the voltage can be selected using the MICB_LVL register bit as detailed in Table 12. REGISTER ADDRESS R1 (01h) Power Management 1 R21 (15h) Input Control 4 BIT LABEL MICB_ENA DEFAULT 0 DESCRIPTION Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.65 * AVDD
8
MICB_LVL
0
Table 12 Microphone Bias Control Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistance must be large enough to limit the MICBIAS current to 3mA.
REFERENCE VOLTAGES All internal analogue input and output circuitry requires a reference voltage AVDD/2 (VMID). This voltage is generated internally using 5k, 50k or 250k resistors and is buffered as required. These functions are controlled using register bits VMID_MODE and BIAS_ENA. REGISTER ADDRESS R1 (01h) Power Management 1 3 BIT LABEL BIAS_ENA DEFAULT 0 DESCRIPTION VREF (necessary for all analogue functions) 0 = VREF buffer disabled 1 = VREF buffer enabled VMID Divider Enable and Select 00 = VMID disabled (for OFF mode) 01 = 2 x 50k divider (Normal mode) 10 = 2 x 250k divider (Standby mode) 11 = 2 x 5k divider (for fast start-up)
1:0
VMID_MODE [1:0]
00
Table 13 Reference Voltages
INPUT PGA VOLUME CONTROL The input PGAs have a gain range from -12dB to +19dB in 1dB steps. The gain on the inverting and non-inverting inputs to the PGA are always equal and are controlled by the register bits INL_VOL[4:0] and INR_VOL[4:0]. The left and right input PGAs can be independently muted using the INL_MUTE and INR_MUTE register bits. To allow simultaneous volume updates of left and right channels, PGA gains are not altered until a 1 is written to either of the IN_VU bits. To prevent "zipper noise", a zero-cross function is provided, so that when enabled, volume updates will not take place until a zero-crossing is detected. In the event of a long period without zerocrossings, a timeout function is available. When this function is enabled (using the TOCLK_ENA register bit), the volume will update after the timeout period if no earlier zero-cross has occurred. The timeout period is set by TOCLK_RATE. See Table 46 in the "Headphone Jack Detect" section for the definition of these register bits, The Input PGA Volume Control register fields are described in Table 14. Note that these volume/mute settings have no effect on Line inputs routed directly to the boost mixer.
w
PD, August 2008, Rev 4.0 35
WM8900
Production Data
REGISTER ADDRESS R22 (16h) Left Input Volume
BIT 8
LABEL IN_VU 0
DEFAULT
DESCRIPTION Input PGA Volume Update Writing a 1 to this bit will cause left and right Input PGA volume to be updated simultaneously Left Input PGA Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately Left Input PGA Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: IN_VU must be set to un-mute. Left Input PGA Volume Control 11111 = +19dB 11110 = +18dB . . 1dB steps down to 00000 = -12dB Input PGA Volume Update Writing a 1 to this bit will cause left and right Input PGA volume to be updated simultaneously Right Input PGA Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately Right Input PGA Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: IN_VU must be set to un-mute. Right Input PGA Volume Control 11111 = +19dB 11110 = +18dB . . 1dB steps down to 00000 = -12dB
7
INL_ZC
0
6
INL_MUTE
1
4:0
INL_VOL [4:0]
01100 (0dB)
R23 (17h) Right Input Volume
8
IN_VU
0
7
INR_ZC
0
6
INR_MUTE
1
4:0
INR_VOL [4:0]
01100 (0dB)
Table 14 Input PGA Volume Control
See "Volume Updates" for more information on volume update bits, zero cross and timeout operation. See "Headphone Jack Detect" for more information on jack detect / debounce.
INPUT BOOST VOLUME CONTROL The input path to the ADCs is via a boost stage, which mixes the signals from the microphone input PGAs and from the line inputs. The boost stage can apply up to +29dB gain to the microphone input PGA path, providing a total maximum available analogue gain of +48dB from microphone to ADC input. The microphone PGA path to the boost mixer may be muted using INL_MUTE and INR_MUTE as described in Table 14. The Microphone PGA to boost gain settings are shown in Table 15. It is recommended that maximum gain is applied to the input signals at the input PGA stage, with minimal boost gain being applied where necessary. This prevents unnecessary amplification of small DC offsets from the input PGA output.
w
PD, August 2008, Rev 4.0 36
Production Data
WM8900
REGISTER ADDRESS R26 (1Ah) ADC Signal Path
BIT 5:4
LABEL INL_MIXINL_BOOST [1:0]
DEFAULT 00
DESCRIPTION Left Channel PGA Boost Gain 00 = +0dB 01 = +13dB 10 = +20dB 11 = +29dB Right Channel PGA Boost Gain 00 = +0dB 01 = +13dB 10 = +20dB 11 = +29dB
1:0
INR_MIXINR_BOOST [1:0]
00
Table 15 Microphone Input PGA Boost Control The boost stage can apply -12dB to +6dB gain to the line inputs. The line inputs may also be muted via the boost gain settings, as shown in Table 16. REGISTER ADDRESS R24 (18h) Input Boost Mixer 1 BIT 6:4 LABEL IN3L_BOOST [2:0] DEFAULT 100 DESCRIPTION LINPUT3 to Boost Gain 000 = -12dB ...6dB steps up to 011 = +6dB 1XX = Mute LINPUT2 to Boost Gain 000 = -12dB ...6dB steps up to 011 = +6dB 1XX = Mute RINPUT3 to Boost Gain 000 = -12dB ...6dB steps up to 011 = +6dB 1XX = Mute RINPUT2 to Boost Gain 000 = -12dB ...6dB steps up to 011 = +6dB 1XX = Mute AUX input to Boost Gain 000 = -12dB ...6dB steps up to 011 = +6dB 1XX = Mute AUX input to Boost Gain 000 = -12dB ...6dB steps up to 011 = +6dB 1XX = Mute
2:0
IN2L_BOOST [2:0]
100
R25 (19h) Input Boost Mixer 2
6:4
IN3R_BOOST [2:0]
100
2:0
IN2R_BOOST [2:0]
100
R27 (1Bh) Aux Boost
6:4
IN4L_BOOST [2:0]
100
2:0
IN4R_BOOST [2:0]
100
Table 16 Line Input Boost Control
Note that, when all input paths to the boost mixer are disabled, the boost mixer will automatically be muted.
w
PD, August 2008, Rev 4.0 37
WM8900
ANALOGUE TO DIGITAL CONVERTER (ADC)
Production Data
The WM8900 uses stereo 24-bit, 64x oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduce the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1.0Vrms. Any voltage greater than full scale may overload the ADC and cause distortion. The ADCs are enabled by the ADCL_ENA/ADCR_ENA register bit. REGISTER ADDRESS R2 (02h) Power Management 2 BIT 1 LABEL ADCL_ENA DEFAULT 0 DESCRIPTION Enable ADC left channel: 0 = ADC disabled 1 = ADC enabled Enable ADC right channel: 0 = ADC disabled 1 = ADC enabled
0
ADCR_ENA
0
Table 17 ADC Enable Control
ADC DIGITAL VOLUME CONTROL The output of the ADCs can be digitally amplified or attenuated over a range from -71.625dB to +17.625dB in 0.375dB steps. The volume of each channel can be controlled separately. The gain for a given eight-bit code X is given by: 0.375 x (X-192) dB for 1 X 239; MUTE for X = 0 +17.625dB for 239 X 255
The ADC_VU bit controls the loading of digital volume control data. When ADC_VU is set to 0, the ADCL_VOL or ADCR_VOL control data will be loaded into the respective control register, but will not actually change the digital gain setting. Both left and right gain settings are updated when a 1 is written to ADC_VU. This makes it possible to update the gain of both channels simultaneously. REGISTER ADDRESS R15 (0Fh) Left ADC Digital Volume BIT 8 LABEL ADC_VU DEFAULT 0 DESCRIPTION ADC Volume Update Writing a 1 to this bit will cause left and right ADC volume to be updated simultaneously Left ADC Digital Volume (See Table 19 for volume range) ADC Volume Update Writing a 1 to this bit will cause left and right ADC volume to be updated simultaneously Right ADC Digital Volume (See Table 19 for volume range)
7:0 R16 (10h) Right ADC Digital Volume 8
ADCL_VOL [7:0] ADC_VU
1100 0000 (0dB) 0
7:0
ADCR_VOL [7:0]
1100 0000 (0dB)
Table 18 ADC Digital Volume Control
w
PD, August 2008, Rev 4.0 38
Production Data
WM8900
Volume (dB) MUTE -71.625 -71.250 -70.875 -70.500 -70.125 -69.750 -69.375 -69.000 -68.625 -68.250 -67.875 -67.500 -67.125 -66.750 -66.375 -66.000 -65.625 -65.250 -64.875 -64.500 -64.125 -63.750 -63.375 -63.000 -62.625 -62.250 -61.875 -61.500 -61.125 -60.750 -60.375 -60.000 -59.625 -59.250 -58.875 -58.500 -58.125 -57.750 -57.375 -57.000 -56.625 -56.250 -55.875 -55.500 -55.125 -54.750 -54.375 -54.000 -53.625 -53.250 -52.875 -52.500 -52.125 -51.750 -51.375 -51.000 -50.625 -50.250 -49.875 -49.500 -49.125 -48.750 -48.375 ADCL_VOL or ADCR_VOL 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh Volume (dB) -48.000 -47.625 -47.250 -46.875 -46.500 -46.125 -45.750 -45.375 -45.000 -44.625 -44.250 -43.875 -43.500 -43.125 -42.750 -42.375 -42.000 -41.625 -41.250 -40.875 -40.500 -40.125 -39.750 -39.375 -39.000 -38.625 -38.250 -37.875 -37.500 -37.125 -36.750 -36.375 -36.000 -35.625 -35.250 -34.875 -34.500 -34.125 -33.750 -33.375 -33.000 -32.625 -32.250 -31.875 -31.500 -31.125 -30.750 -30.375 -30.000 -29.625 -29.250 -28.875 -28.500 -28.125 -27.750 -27.375 -27.000 -26.625 -26.250 -25.875 -25.500 -25.125 -24.750 -24.375 ADCL_VOL or ADCR_VOL 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh Volume (dB) -24.000 -23.625 -23.250 -22.875 -22.500 -22.125 -21.750 -21.375 -21.000 -20.625 -20.250 -19.875 -19.500 -19.125 -18.750 -18.375 -18.000 -17.625 -17.250 -16.875 -16.500 -16.125 -15.750 -15.375 -15.000 -14.625 -14.250 -13.875 -13.500 -13.125 -12.750 -12.375 -12.000 -11.625 -11.250 -10.875 -10.500 -10.125 -9.750 -9.375 -9.000 -8.625 -8.250 -7.875 -7.500 -7.125 -6.750 -6.375 -6.000 -5.625 -5.250 -4.875 -4.500 -4.125 -3.750 -3.375 -3.000 -2.625 -2.250 -1.875 -1.500 -1.125 -0.750 -0.375 ADCL_VOL or ADCR_VOL C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh Volume (dB) 0.000 0.375 0.750 1.125 1.500 1.875 2.250 2.625 3.000 3.375 3.750 4.125 4.500 4.875 5.250 5.625 6.000 6.375 6.750 7.125 7.500 7.875 8.250 8.625 9.000 9.375 9.750 10.125 10.500 10.875 11.250 11.625 12.000 12.375 12.750 13.125 13.500 13.875 14.250 14.625 15.000 15.375 15.750 16.125 16.500 16.875 17.250 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625
ADCL_VOL or ADCR_VOL 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh
Table 19 ADC Digital Volume Range
w
PD, August 2008, Rev 4.0 39
WM8900
ADC DIGITAL FILTERS
Production Data
The ADC filters perform true 24-bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface.
HIGH PASS FILTER A digital high pass filter is applied by default to the ADC path to remove DC offsets. This filter can also be programmed to remove low frequency noise in voice applications (e.g. wind noise or mechanical vibration). This filter is controlled using the ADC_HPF_ENA and ADC_HPF_CUT register bits. In hi-fi mode the high pass filter is optimised for removing DC offsets without degrading the bass response and has a cut-off frequency of 3.7Hz at fs=44.1kHz. In voice mode the high pass filter is optimised for voice communication and it is recommended to program the cut-off frequency below 300Hz (e.g. ADC_HPF_CUT=11 at fs=8kHz or ADC_HPF_CUT=10 at fs=16kHz). REGISTER ADDRESS R14 (0Eh) ADC Control BIT 8 LABEL ADC_HPF_ENA DEFAULT 1 DESCRIPTION ADC Digital High Pass Filter Enable 0 = disabled 1 = enabled ADC Digital High Pass Filter Cut-Off Frequency (fc) 00 = Hi-fi mode (fc=4Hz at fs=48kHz) 01 = Voice mode 1 (fc=127Hz at fs=16kHz) 10 = Voice mode 2 (fc=130Hz at fs=8kHz) 11 = Voice mode 3 (fc=267Hz at fs=8kHz) (Note: fc scales with sample rate. See Table 21 for cut-off frequencies at all supported sample rates.)
6:5
ADC_HPF_CUT [1:0]
00
Table 20 ADC High Pass Filter Control Registers
Sample Frequency (kHz) 8.000 11.025 16.000 22.050 24.000 32.000 44.100 48.000
CUT-OFF FREQUENCY (HZ) ADC_HPF_CUT = 00 0.7 0.9 1.3 1.9 2.0 2.7 3.7 4.0 ADC_HPF_CUT = 01 64 88 127 175 190 253 348 379 ADC_HPF_CUT = 10 130 178 258 354 386 514 707 770 ADC_HPF_CUT = 11 267 367 532 733 798 1063 1464 1594
Table 21 ADC High Pass Filter Cut-Off Frequencies The high pass filter characteristics are shown in the "Digital Filter Characteristics" section.
w
PD, August 2008, Rev 4.0 40
Production Data
WM8900
DIGITAL MIXING
The ADC and DAC data can be combined in various ways to support a range of different usage modes. Data from either of the two ADCs can be routed to either the left or the right channel of the digital audio interface. In addition, data from either of the digital audio interface channels can be routed to either the left or right DAC. See "Digital Audio Interface" section for more information on the audio interface. DIGITAL MIXING PATHS Figure 16 shows the digital mixing paths available in the WM8900 digital core.
Figure 16 Digital Mixing Paths
The polarity of each ADC output signal can be changed under software control using the ADCL_DATINV and ADCR_DATINV register bits. The AIFADCL_SRC and AIFADCR_SRC register bits may be used to select which ADC is used for the left and right digital audio interface data. These register bits are described in Table 22.
w
PD, August 2008, Rev 4.0 41
WM8900
Production Data
REGISTER ADDRESS R4 (04h) Audio Interface 1
BIT 15
LABEL AIFADCL_SRC
DEFAULT 0
DESCRIPTION Left Digital Audio channel source 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel Right Digital Audio channel source 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel Left ADC Invert 0 = Left ADC output not inverted 1 = Left ADC output inverted Right ADC Invert 0 = Right ADC output not inverted 1 = Right ADC output inverted
14
AIFADCR_SRC
1
R14 (0Eh) ADC Control
1
ADCL_DATINV
0
0
ADCR_DATINV
0
Table 22 ADC Routing and Control
The input data source for each DAC can be changed under software control using register bits DACL_SRC and DACR_SRC. The polarity of each DAC input may also be modified using register bits DACL_DATINV and DAVR_DATINV. These register bits are described in Table 23. REGISTER ADDRESS R5 (05h) Audio Interface 2 BIT 15 LABEL DACL_SRC DEFAULT 0 DESCRIPTION Left DAC Data Source Select 0 = Left DAC outputs left channel data 1 = Left DAC outputs right channel data Right DAC Data Source Select 0 = Right DAC outputs left channel data 1 = Right DAC outputs right channel data Left DAC Invert 0 = Left DAC output not inverted 1 = Left DAC output inverted Right DAC Invert 0 = Right DAC output not inverted 1 = Right DAC output inverted
14
DACR_SRC
1
R10 (0Ah) DAC Control
1
DACL_DATINV
0
0
DACR_DATINV
0
Table 23 DAC Routing and Control
DAC INTERFACE VOLUME BOOST A digital gain function is available at the audio interface to boost the DAC volume when a small signal is received on DACDAT. This is controlled using register bits DAC_BOOST[1:0]. To prevent clipping at the DAC input, this function should not be used when the boosted DAC data is expected to be greater than 0dBFS. REGISTER ADDRESS R5 (05h) Audio Interface 2 BIT 11:10 LABEL DAC_BOOST [1:0] DEFAULT 00 DESCRIPTION DAC Input Volume Boost 00 = 0dB 01 = +6dB (Input data must not exceed -6dBFS) 10 = +12dB (Input data must not exceed -12dBFS) 11 = +18dB (Input data must not exceed -18dBFS)
Table 24 DAC Interface Volume Boost
w
PD, August 2008, Rev 4.0 42
Production Data
WM8900
DIGITAL SIDETONE A digital sidetone is available when ADCs and DACs are operating at the same sample rate. Digital data from either left or right ADC can be mixed with the audio interface data on the left and right DAC channels. Sidetone data is taken from the ADC high pass filter output, to reduce low frequency noise in the sidetone (e.g. wind noise or mechanical vibration). The digital sidetone will not function when ADCs and DACs are operating at different sample rates. When using the digital sidetone it is recommended that the ADCs are enabled before un-muting the DACs to prevent pop noise. The DAC volumes and sidetone volumes should be set to an appropriate level to prevent clipping at the DAC input. The digital sidetone is controlled as shown in Table 25. REGISTER ADDRESS R13 (0Dh) Digital Sidetone BIT 12:9 8:5 3:2 LABEL ADCL_DAC_SVOL [3:0] ADCR_DAC_SVOL [3:0] ADC_TO_DACL [1:0] DEFAULT 0000 0000 00 DESCRIPTION Left Digital Sidetone Volume (See Table 26 for volume range) Right Digital Sidetone Volume (See Table 26 for volume range) Left DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = Reserved Right DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = Reserved
1:0
ADC_TO_DACR [1:0]
00
Table 25 Digital Sidetone Control
ADCL_DAC_SVOL or Sidetone ADCR_DAC_SVOL Volume 0000 -36 0001 -33 0010 -30 0011 -27 0100 -24 0101 -21 0110 -18 0111 -15 1000 -12 1001 -9 1010 -6 1011 -3 1100 0 1101 0 1110 0 1111 0
Table 26 Digital Sidetone Volume
w
PD, August 2008, Rev 4.0 43
WM8900
DIGITAL TO ANALOGUE CONVERTER (DAC)
Production Data
The WM8900 DACs receive digital input data from the DACDAT pin and via the digital sidetone path. The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which convert them to high quality analogue audio signals. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low distortion. The analogue outputs from the DACs can then be mixed with other analogue inputs using the output mixers. This mix is fed to the output drivers for headphone or line outputs. The DACs are enabled by the DACL_ENA and DACR_ENA register bits as defined in Table 27. The DAC output stage bias current can be optimised by the DAC_BIAS register bits. Note that the optimum setting for minimum power consumption is not the power-on default value. REGISTER ADDRESS R3 (03h) Power Management 3 1 BIT LABEL DACL_ENA DEFAULT 0 DESCRIPTION Left DAC Enable 0 = DAC disabled 1 = DAC enabled Right DAC Enable 0 = DAC disabled 1 = DAC enabled Adjusts DAC bias 00 = Full bias 01 = Half bias (recommended) 10 = Reserved 11 = Reserved
0
DACR_ENA
0
R115 (73h) Output Bias Control
2:1
DAC_BIAS [1:0]
00
Table 27 DAC Enable Control
DAC DIGITAL VOLUME CONTROL The output level of each DAC can be controlled digitally over a range from-71.625dB to 0dB in 0.375dB steps. The level of attenuation for an eight-bit code X is given by: 0.375 x (X-192) dB for 1 X 192; MUTE for X = 0 0dB for 192 X 255
The DAC_VU bit controls the loading of digital volume control data. When DAC_VU is set to 0, the DACL_VOL or DACR_VOL control data will be loaded into the respective control register, but will not actually change the digital gain setting. Both left and right gain settings are updated when a 1 is written to DAC_VU. This makes it possible to update the gain of both channels simultaneously. REGISTER ADDRESS R11 (0Bh) Left DAC Digital Volume BIT 8 LABEL DAC_VU DEFAULT 0 DESCRIPTION DAC Volume Update Writing a 1 to this bit will cause left and right DAC volume to be updated simultaneously Left DAC Digital Volume (See Table 29 for volume range) DAC Volume Update Writing a 1 to this bit will cause left and right DAC volume to be updated simultaneously Right DAC Digital Volume (See Table 29 for volume range)
7:0 R12 (0Ch) Right DAC Digital Volume 8
DACL_VOL [7:0] DAC_VU
11000000 (0dB) 0
7:0
DACR_VOL [7:0]
11000000 (0dB)
Table 28 Digital Volume Control
w
PD, August 2008, Rev 4.0 44
Production Data
WM8900
Volume (dB) MUTE -71.625 -71.250 -70.875 -70.500 -70.125 -69.750 -69.375 -69.000 -68.625 -68.250 -67.875 -67.500 -67.125 -66.750 -66.375 -66.000 -65.625 -65.250 -64.875 -64.500 -64.125 -63.750 -63.375 -63.000 -62.625 -62.250 -61.875 -61.500 -61.125 -60.750 -60.375 -60.000 -59.625 -59.250 -58.875 -58.500 -58.125 -57.750 -57.375 -57.000 -56.625 -56.250 -55.875 -55.500 -55.125 -54.750 -54.375 -54.000 -53.625 -53.250 -52.875 -52.500 -52.125 -51.750 -51.375 -51.000 -50.625 -50.250 -49.875 -49.500 -49.125 -48.750 -48.375 DACL_VOL or DACR_VOL 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh Volume (dB) -48.000 -47.625 -47.250 -46.875 -46.500 -46.125 -45.750 -45.375 -45.000 -44.625 -44.250 -43.875 -43.500 -43.125 -42.750 -42.375 -42.000 -41.625 -41.250 -40.875 -40.500 -40.125 -39.750 -39.375 -39.000 -38.625 -38.250 -37.875 -37.500 -37.125 -36.750 -36.375 -36.000 -35.625 -35.250 -34.875 -34.500 -34.125 -33.750 -33.375 -33.000 -32.625 -32.250 -31.875 -31.500 -31.125 -30.750 -30.375 -30.000 -29.625 -29.250 -28.875 -28.500 -28.125 -27.750 -27.375 -27.000 -26.625 -26.250 -25.875 -25.500 -25.125 -24.750 -24.375 DACL_VOL or DACR_VOL 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh Volume (dB) -24.000 -23.625 -23.250 -22.875 -22.500 -22.125 -21.750 -21.375 -21.000 -20.625 -20.250 -19.875 -19.500 -19.125 -18.750 -18.375 -18.000 -17.625 -17.250 -16.875 -16.500 -16.125 -15.750 -15.375 -15.000 -14.625 -14.250 -13.875 -13.500 -13.125 -12.750 -12.375 -12.000 -11.625 -11.250 -10.875 -10.500 -10.125 -9.750 -9.375 -9.000 -8.625 -8.250 -7.875 -7.500 -7.125 -6.750 -6.375 -6.000 -5.625 -5.250 -4.875 -4.500 -4.125 -3.750 -3.375 -3.000 -2.625 -2.250 -1.875 -1.500 -1.125 -0.750 -0.375 DACL_VOL or DACR_VOL C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh Volume (dB) 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000
DACL_VOL or DACR_VOL 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh
Table 29 DAC Digital Volume Range
w
PD, August 2008, Rev 4.0 45
WM8900
DAC SOFT MUTE AND SOFT UN-MUTE
Production Data
The WM8900 has a soft mute and un-mute function, which, when enabled, gradually attenuates or amplifies the volume of the DAC output. When the DAC is un-muted the gain will either gradually ramp back up to the digital gain setting, or return instantly to the digital gain setting, depending on the DAC_MUTEMODE register bit. Conversely, when the DAC is muted the gain will either gradually ramp down to the digital mute level, or drop instantly to the digital mute level, depending on the DAC_MUTEMODE register bit setting. The DAC is muted by default (DAC_MUTE = 1). To play back an audio signal, this function must first be disabled by setting the DAC_MUTE bit to 0. Soft Mute Mode would typically be enabled (DAC_MUTEMODE = 1) when using DAC_MUTE during playback of audio data. When DAC_MUTE is set to logic 0 and the DAC is un-muted, the sudden volume increase will not create pop noise by jumping immediately to the previous volume level (e.g. resuming playback after pausing during a track). Soft Mute Mode would typically be disabled (DAC_MUTEMODE = 0) when un-muting at the start of a music file, in order that the first part of the track is not attenuated (e.g. when starting playback of a new track, or resuming playback after pausing between tracks).
Figure 17 DAC Mute Control The volume ramp rate during soft mute and un-mute is controlled by the DAC_MUTERATE bit. Ramp rates of fs/32 and fs/2 are selectable as shown in Table 30. The ramp rate determines the rate at which the volume will be increased or decreased. The actual ramp time depends on the extent of the difference between the muted and un-muted volume settings.
w
PD, August 2008, Rev 4.0 46
Production Data
WM8900
REGISTER ADDRESS R10 (0Ah) DAC Control
BIT 7
LABEL DAC_MUTERATE
DEFAULT 0
DESCRIPTION DAC Soft Mute Ramp Rate 0 = Fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48k) 1 = Slow ramp (fs/32, maximum ramp time is 171ms at fs=48k) DAC Soft Mute and Un-mute Mode 0 = Disabling soft-mute (DAC_MUTE=0) will cause the DAC volume to change immediately to DACL_VOL and DACR_VOL settings or change to digital mute level immediately 1 = Enabling soft-mute (DAC_MUTE=0) will cause the DAC volume to ramp up gradually to the DACL_VOL and DACR_VOL settings or gradually ramp down to digital mute level DAC Mute Control 0 = DAC Un-mute 1 = DAC Mute
6
DAC_MUTEMODE
0
2
DAC_MUTE
1
Table 30 DAC Soft-Mute Control DAC MONO MIX A DAC digital mono-mix mode can be enabled using the DAC_MONO register bit. This mono mix will be output on the enabled DACs. To prevent clipping, a -6dB attenuation is automatically applied to the mono mix. REGISTER ADDRESS R10 (0Ah) DAC Control BIT 9 LABEL DAC_MONO DEFAULT 0 DESCRIPTION DAC Mono Mix 0 = Stereo 1 = Mono (Mono mix output on enabled DACs)
Table 31 DAC Mono Mix
DAC DE-EMPHASIS Digital de-emphasis can be applied to the DAC playback data (e.g. when the data comes from a CD with pre-emphasis used in the recording). De-emphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz. See "Digital Filter Characteristics" section for details of de-emphasis filter characteristics. REGISTER ADDRESS R10 (0Ah) DAC Control BIT 5:4 LABEL DEEMP [1:0] DEFAULT 00 DESCRIPTION De-Emphasis Control 11 = 48kHz sample rate 10 = 44.1kHz sample rate 01 = 32kHz sample rate 00 = No de-emphasis
Table 32 DAC De-Emphasis Control
DAC SLOPING STOPBAND FILTER Two DAC filter types are available, selected by the register bit DAC_SB_FILT. When operating at lower sample rates (e.g. during voice communication) it is recommended that the sloping stopband filter type is selected (DAC_SB_FILT = 1) to reduce out-of-band noise which can be audible at low
w
PD, August 2008, Rev 4.0 47
WM8900
Production Data
DAC sample rates. See "Digital Filter Characteristics" section for details of DAC filter characteristics. REGISTER ADDRESS R10 (0Ah) DAC Control BIT 8 LABEL DAC_SB_FILT DEFAULT 0 DESCRIPTION Selects DAC filter characteristics 0 = Normal mode 1 = Sloping stopband mode
Table 33 DAC Sloping Stopband Filter
DAC SIGMA-DELTA CLOCK RATE When operating the DAC at lower sample rates (e.g. during voice communication) it is recommended that the DAC sigma-delta modulator clock is enabled by default (DAC_SDMCLK_RATE = 1) to maintain an independent clock rate and reduce idle channel noise. Setting DAC_SDMCLK_RATE to 0 will allow the DAC clock to scale with sample rate and give a minimal power consumption improvement, at the expense of idle channel noise increasing REGISTER ADDRESS R10 (0Ah) DAC Control BIT 12 LABEL DAC_SDMCLK_RATE DEFAULT 1 DESCRIPTION DAC sigma delta modulator clock 0 = DAC clock scales with sample rate 1 = DAC clock independent of sample rate
Table 34 DAC Sigma-delta Modulator Clock Rate
OUTPUT SIGNAL PATH
The WM8900 has two analogue output mixers which allow the ADC bypass, DAC output and LINPUT3 (RINPUT3) and AUX signals to be combined as desired. The flexible configuration of these mixers allows a mono mix to be generated as well as combining audio signals (eg. speech) from the input bypass path. The output mixers are connected to two stereo line outputs; the built-in ground-referenced headphone driver may be connected to one of these line output pairs.
OUTPUT MIXER ENABLE The output mixers are independently enabled by the MIXOUTL_ENA and MIXOUTR_ENA register bits, as described in Table 35. The output mixers bias current can be optimised by the MIXOUT_BIAS register bits. Note that the optimum setting for minimum power consumption is not the power-on default value. REGISTER ADDRESS R3 (03h) Power Management 3 BIT 3 LABEL MIXOUTL_ENA DEFAULT 0 DESCRIPTION Left output mixer enable 0 = Mixer disabled 1 = Mixer enabled Right output mixer enable 0 = Mixer disabled 1 = Mixer enabled Adjusts output mixer bias 00 = Full bias 01 = Half bias (recommended) 10 = Reserved 11 = Reserved
2
MIXOUTR_ENA
0
R115 (R73h) Output Bias Control
8:7
MIXOUT_BIAS
00
Table 35 Output Mixers Enable
w
PD, August 2008, Rev 4.0 48
Production Data
WM8900
OUTPUT MIXER CONFIGURATION The output mixers are configured by the output mixer control registers, as described in Table 36. Each mixer input can be independently enabled/disabled. With the exception of the DAC output, each signal's gain can be controlled in the range -15dB to +6dB, as shown in Figure 18. The DAC volume can be adjusted in the digital domain if required, see Table 28.
Figure 18 Output Mixers Control
w
PD, August 2008, Rev 4.0 49
WM8900
Production Data
REGISTER ADDRESS R44 (2Ch) Left Output Mixer Control 1
BIT 8
LABEL DACL_TO_MIXOUTL
DEFAULT 0
DESCRIPTION Left DAC output to left output mixer 0 = not selected 1 = selected
7
IN3L_TO_MIXOUTL
0
Left input 3 channel to left output mixer path 0 = not selected 1 = selected
6:4
IN3L_MIXOUTL_VOL
101
Left input 3 channel to left output mixer path volume control (-15dB -> +6dB in 3dB steps) 000 = -15dB 101 = 0dB 111 = +6dB
R45 (2Dh) Right Output Mixer Control 1
8
DACR_TO_MIXOUTR
0
Right DAC output to right output mixer 0 = not selected 1 = selected
7
IN3R_TO_MIXOUTR
0
Right input 3 channel to right output mixer path 0 = not selected 1 = selected Right input 3 channel to right output mixer path volume control (-15dB -> +6dB in 3dB steps) 000 = -15dB 101 = 0dB 111 = +6dB
6:4
IN3R_MIXOUTR_VOL
101
R46 (2Eh) Bypass 1
7
MIXINL_TO_MIXOUTL
0
Left bypass path (from the Left channel ADC input) to left output mixer 0 = not selected 1 = selected
6:4
MIXINL_MIXOUTL_VOL
101
Left bypass path to left output mixer path volume control (-15dB -> +6dB in 3dB steps) 000 = -15dB 101 = 0dB 111 = +6dB
3
MIXINL_TO_MIXOUTR
0
Left bypass path (from the Left channel ADC input) to right output mixer 0 = not selected 1 = selected
2:0
MIXINL_MIXOUTR_VOL
101
Left bypass path to right output mixer path volume control (-15dB -> +6dB in 3dB steps) 000 = -15dB 101 = 0dB 111 = +6dB
w
PD, August 2008, Rev 4.0 50
Production Data
WM8900
REGISTER ADDRESS R47 (2Fh) Bypass 2 BIT 7 LABEL MIXINR_TO_MIXOUTR DEFAULT 0 DESCRIPTION Right bypass path (from the Right channel ADC input) to right output mixer 0 = not selected 1 = selected 6:4 MIXINR_MIXOUTR_VOL 101 Right bypass path to right output mixer path volume control (-15dB -> +6dB in 3dB steps) 000 = -15dB 101 = 0dB 111 = +6dB 3 MIXINR_TO_MIXOUTL 0 Right bypass path (from the Right channel ADC input) to left output mixer 0 = not selected 1 = selected 2:0 MIXINR_MIXOUTL_VOL 101 Right bypass path to left output mixer path volume control (-15dB -> +6dB in 3dB steps) 000 = -15dB 101 = 0dB 111 = +6dB AUX input channel to left output mixer path 0 = not selected 1 = selected 6:4 IN4_MIXOUTL_VOL 101 AUX input channel to left output mixer path volume control (-15dB -> +6dB in 3dB steps) 000 = -15dB 101 = 0dB 111 = +6dB AUX input channel to right output mixer path 0 = not selected 1 = selected 2:0 IN4_MIXOUTR_VOL 101 AUX input channel to right output mixer path volume control (-15dB -> +6dB in 3dB steps) 000 = -15dB 101 = 0dB 111 = +6dB Table 36 Output Mixer Control
R48 (30h) AUX to Mixer Output Control
7
IN4_TO_MIXOUTL
0
3
IN4_TO_MIXOUTR
0
w
PD, August 2008, Rev 4.0 51
WM8900
LINE OUTPUT ENABLE
Production Data
Each analogue output driver can be independently enabled via the Power Management register bits, as described in Table 37. Muting and volume control of the outputs is only possible when the correct power management register bits are enabled. When the correct power management bit for an output is not set, some signal leakage to the output pin may occur. REGISTER ADDRESS R2 (02h) Power Management 2 8 BIT LABEL OUT1L_ENA DEFAULT 0 DESCRIPTION Left channel LINEOUT1 enable 0 = LINEOUT_1L disabled 1 = LINEOUT_1L enabled Right channel LINEOUT1 enable 0 = LINEOUT_1R disabled 1 = LINEOUT_1R enabled Left channel LINEOUT2 enable 0 = LINEOUT_2L disabled 1 = LINEOUT_2L enabled Right channel LINEOUT2 enable 0 = LINEOUT_2R disabled 1 = LINEOUT_2R enabled
7
OUT1R_ENA
0
R3 (03h) Power Management 3
6
OUT2L_ENA
0
5
OUT2R_ENA
0
Table 37 Line Output Enable LINEOUT_1L AND LINEOUT_1R OUTPUTS The outputs LINEOUT_1L and LINEOUT_1R are capable of driving a 16 headphone load and are independently controlled by the register bits described in Table 38. The outputs can be independently muted and the volumes controlled in the range -57dB to +6dB. To allow simultaneous volume updates of left and right channels, output gains are not altered until a 1 is written to the OUT1_VU bit. To prevent "zipper noise", a zero-cross function is provided, so that when enabled, volume updates will not take place until a zero-crossing is detected. In the event of a long period without zerocrossings, a timeout function is available. When this function is enabled (using the TOCLK_ENA register bit), the volume will update after the timeout period if no earlier zero-cross has occurred. The timeout period is set by TOCLK_RATE. Note that this timer is the same timer as applied to the Input PGA zero-cross function. LCOM FUNCTION Common ground noise on LINEOUT1L and LINEOUT1R outputs can be eliminated by enabling the OUT1_FB_ENA bit. This allows the connection of the AUX/LCOM pin to the shared LINEOUT ground via a 4.7F capacitor. Note that the AUX/LCOM pin cannot be used as an auxiliary input when used as a common ground connection. It is recommended that the AUX input is not connected to the output mixers (see register R48; IN4_TO_MIXOUTL and IN4_TO_MIXOUTR bits) and that the AUX boost stages are muted (R27; IN4L_BOOST and IN4R_BOOST) when using this configuration. This configuration can be seen below.
w
PD, August 2008, Rev 4.0 52
Production Data
WM8900
4.7uF AGND
1uF 10uF AUX / LCOM DGND DCVDD DBVDD CPVDDHI CPVDDLO CFB1 CFB2 VNEG 10uF VPOS CPGND 10K
-57 to +6dB, 1dB steps, mute -15 to +6dB, 3dB steps
10K
LINPUT3/JD LINPUT2
-12 to +19dB, 1dB steps -12 -> 6dB, 3dB steps, mute -12 -> 6dB, 3dB steps, mute
-15 to +6dB, 3dB steps
LINEOUT1L
-57 to +6dB, 1dB steps, mute
LINEOUT2L 0.47uF
+ vmid -
+
0, 13, 20, 29dB, mute -12 -> 6dB, 3dB steps, mute -12 -> 6dB, 3dB steps, mute
ADC
ADC DIGITAL FILTERS VOLUME DAC DIGITAL FILTERS VOLUME
-15 to +6dB, 3dB steps
+
DAC
-15 to +6dB, 3dB steps
LEFT MIXER
HPVP
HPINL HPL
LINPUT1
RINPUT1
vmid
INPUT PGAs
+
-12 to +19dB, 1dB steps
SYSCLK
-15 to +6dB, 3dB steps
Charge Pump
RIGHT MIXER
HPVN
0, 13, 20, 29dB, mute
HPGND
HPVP
+
-12 -> 6dB, 3dB steps, mute -12 -> 6dB, 3dB steps, mute
ADC
DAC
-15 to +6dB, 3dB steps
+
HPR
HPVN
HPINR 0.47uF LINEOUT2R
RINPUT2
-15 to +6dB, 3dB steps -15 to +6dB, 3dB steps
-57 to +6dB, 1dB steps, mute
RINPUT3/JD
SYSCLK
-57 to +6dB, 1dB steps, mute
LINEOUT1R
MICBIAS
50K 50K
ADCREF DACREF
DIGITAL AUDIO INTERFACE
GPIO
FLL
CONTROL INTERFACE
AGND
VMID
BCLK ADCLRC/GPIO ADCDAT DACLRC DACDAT
Figure 19 LCOM Common Ground Connection for LINEOUT1
SCLK SDIN CSB/GPIO MODE/GPIO
4.7uF
AVDD
MCLK
w
PD, August 2008, Rev 4.0 53
WM8900
Production Data
REGISTER ADDRESS R51 (33h) Left OUT1 Control 8
BIT
LABEL OUT1_VU
DEFAULT 0
DESCRIPTION Left Channel LINEOUT1 Volume Update Writing a 1 to this bit will cause left and right LINEOUT1 volume to be updated simultaneously Left Channel LINEOUT1 Zero Cross enable 0 = Change gain immediately 1 = Change gain on zero cross only
7
OUT1L_ZC
0
6
OUT1L_MUTE
1
Left Channel LINEOUT1 Mute 0 = LINEOUT_1L Unmuted 1 = LINEOUT_1L Mute Left Channel LINEOUT1 Volume Control (-57dB -> +6dB in 1dB steps) 111111 = +6dB 000000 = -57dB Right Channel LINEOUT1 Volume Update Writing a 1 to this bit will cause left and right LINEOUT1 volume to be updated simultaneously Right Channel LINEOUT1 Zero Cross enable 0 = Change gain immediately 1 = Change gain on zero cross only Right Channel LINEOUT1 Mute 0 = LINEOUT_1R Unmuted 1 = LINEOUT_1R Mute Right Channel LINEOUT1 Volume Control (-57dB -> +6dB in 1dB steps) 111111 = +6dB 000000 = -57dB Common mode feedback for Lineout1 0: Disable common mode feedback 1: Enable common mode feedback
5:0
OUT1L_VOL [5:0]
111001
R52 (34h) Right OUT1 Control
8
OUT1_VU
0
7
OUT1R_ZC
0
6
OUT1R_MUTE
1
5:0
OUT1R_VOL [5:0]
111001
R3 (03h) Power Management 3
8
OUT1_FB_ENA
0
Table 38 LINEOUT_1L/ LINEOUT_1R Volume Control
w
PD, August 2008, Rev 4.0 54
Production Data
WM8900
LINEOUT_2L AND LINEOUT_2R OUTPUTS The outputs LINEOUT_2L and LINEOUT_2R are independently controlled by the register bits described in Table 39. The outputs can be independently muted and the volumes controlled in the range -57dB to +6dB. To allow simultaneous volume updates of left and right channels, output gains are not altered until a 1 is written to the OUT2_VU bit. To prevent "zipper noise", a zero-cross function is provided, so that when enabled, volume updates will not take place until a zero-crossing is detected. In the event of a long period without zerocrossings, a timeout function is available. When this function is enabled (using the TOCLK_ENA register bit), the volume will update after the timeout period if no earlier zero-cross has occurred. The timeout period is set by TOCLK_RATE. Note that this timer is the same timer as applied to the Input PGA zero-cross function. With the addition of small capacitors linking the LINEOUT_2L and LINEOUT_2R signals to the Headphone driver, the HP_L and HP_R pins can drive a 16 or 32 headphone. The headphone output is ground referenced and therefore no further capacitors are required and no headphone click noise is produced when muting or un-muting. See "Ultra Low Power Ground-Referenced Headphone Output" for further details. The Line Output 2 Volume Control register fields are described in Table 39. REGISTER ADDRESS R53 (35h) Left OUT2 Control 8 BIT LABEL OUT2_VU DEFAULT 0 DESCRIPTION Left Channel LINEOUT2 Volume Update Writing a 1 to this bit will cause left and right LINEOUT2 volume to be updated simultaneously Left Channel LINEOUT2 Zero Cross enable 0 = Change gain immediately 1 = Change gain on zero cross only 6 OUT2L_MUTE 1 Left Channel LINEOUT2 Mute 0 = LINEOUT_2L Unmuted 1 = LINEOUT_2L Mute Left Channel LINEOUT2 Volume Control (-57dB -> +6dB in 1dB steps) 111111 = +6dB 000000 = -57dB Right Channel LINEOUT2 Volume Update Writing a 1 to this bit will cause left and right LINEOUT2 volume to be updated simultaneously Right Channel LINEOUT2 Zero Cross enable 0 = Change gain immediately 1 = Change gain on zero cross only 6 OUT2R_MUTE 1 Right Channel LINEOUT2 Mute 0 = LINEOUT_2R Unmuted 1 = LINEOUT_2R Mute Right Channel LINEOUT2 Volume Control (-57dB -> +6dB in 1dB steps) 111111 = +6dB 000000 = -57dB
7
OUT2L_ZC
0
5:0
OUT2L_VOL [5:0]
111001
R54 (36h) Right OUT2 Control
8
OUT2_VU
0
7
OUT2R_ZC
0
5:0
OUT2R_VOL [5:0]
111001
Table 39 LINEOUT_2L/ LINEOUT_2R Volume Control See "Volume Updates" for more information on volume update bits, zero cross and timeout operation.
w
PD, August 2008, Rev 4.0 55
WM8900
ULTRA-LOW POWER GROUND-REFERENCED HEADPHONE OUTPUT
Production Data
The WM8900 headphone amplifier architecture offers highly efficient DAC playback at typical listening levels. A level-shifting charge pump enables the headphone output to be ground referenced, eliminating the need for large DC blocking capacitors on the output. Class G operation provides additional benefits to power consumption. Typical power consumption figures are detailed in Table 2, Table 3, Table 4,Table 5 and Table 6. The headphone amplifier configuration is illustrated in Figure 20.
WM8900
LINEOUT2L
0.47uF Headphone Driver HPINL HPL
Headphone Output
HPR HPINR
0.47uF
Charge Pump
LINEOUT2R
HPGND
Figure 20 Ultra-Low Power Ground-Referenced Headphone Output
w
CPVDDLO
CPVDDHI
CFB2
CFB1
The Charge Pump and the Headphone Amplifier are described separately in the following two sections. CHARGE PUMP The level shifting charge pump has two outputs (VPOS and VNEG) and two inputs (CPVDDHI and CPVDDLO). The input voltage selection is automatically determined by the output volume required. For correct functionality, CPVDDHI should be higher than CPVDDLO. The positive output, VPOS, generated by the charge pump will be half the input voltage. The negative output, VNEG, will be a negative voltage of the same magnitude. The Charge Pump is enabled by CP_ENA, as defined in Table 40. The charge pump requires SYSCLK to be present at all times when the headphone amplifier is in use.
VPOS
VNEG
PD, August 2008, Rev 4.0 56
Production Data
WM8900
REGISTER ADDRESS R3 (03h) Power Management 3
BIT 7
LABEL CP_ENA
DEFAULT 0
DESCRIPTION Charge Pump Enable 0 = Disable charge pump 1 = Enable charge pump Must be enabled when the headphone output is used.
Table 40 Charge Pump Control HEADPHONE AMPLIFIER The Headphone amplifier input (HP_INL / HP_INR) must be coupled to the LINEOUT_2L / LINEOUT_2R via a small DC blocking capacitor as illustrated in Figure 20. A high pass filter is formed between this capacitor and the impedance of the headphone amplifier, which is approximately 20k. The choice of capacitor determines the high pass filter cut-off frequency as detailed in Table 41, and can be chosen to fit the desired bass response requirements. CAPACITOR VALUE 0.47 uF 1 uF -3DB CUT-OFF FREQUENCY 17 Hz 8 Hz
Table 41 Headphone AC Coupling Capacitor A zobel network is required to stabilise the amplifier. The zobel network should comprise a 50 ohm (5%) resistor and a 20nF (20%) capacitor, as illustrated in the recommended external components diagram.. The Headphone amplifier can be controlled via the register settings described in Table 42. See also Table 9 for additional control fields that may be used to minimise pops and clicks under certain mode changes. REGISTER ADDRESS R58 (3Ah) Headphone Control 1 BIT 7 LABEL HP_IPSTAGE_ENA DEFAULT 0 DESCRIPTION Headphone input stage Enable 0 = Headphone input stage disabled 1 = Headphone input stage enabled Headphone output stage Enable 0 = Headphone output stage disabled 1 = Headphone output stage enabled
6
HP_OPSTAGE_ENA
0
Table 42 Headphone Amplifier Control If the headphone output is being used in a mono configuration, it is a requirement that the un-used OUT2 volume PGA ( R53 (0x35) or R54 (0x36)) should be set up with minimum volume setting and not muted, i.e. must clear bits 6:0. This ensures that the Class G power saving features of WM8900 will function correctly for the mono output channel.
MASTER BIAS
The overall analogue master bias current can be optimised by the MASTER_BIAS register bits. Note that the optimum setting for minimum power consumption is not the power-on default value. The various power saving options are discussed in Table 45. REGISTER ADDRESS R116 (74h) Master Bias Control Master Bias Control BIT 8:7 LABEL MASTER_BIAS DEFAULT 10 DESCRIPTION Adjusts master bias 00 = Reserved 01 = 0.75 bias 10 = full bias - default 11 = Reserved
Table 43 Master Bias Control
w
PD, August 2008, Rev 4.0 57
WM8900
OPTIMAL PLAYBACK POWER CONSUMPTION
Production Data
During DAC to Headphone playback, reduced bias modes are available to optimise power consumption, giving increased battery life with a slight performance trade-off. These modes are selected using the register bits DAC_BIAS (R115 bits 2:1),MIXOUT_BIAS (R115 bits 8:7), and MASTER_BIAS (R116 bits 8:7). REGISTER ADDRESS R115 (73h) Output Bias Control BIT 8:7 LABEL MIXOUT_BIAS DEFAULT 00 DESCRIPTION Adjusts output mixer bias 00 = Full bias 01 = Half bias (recommended) 10 = Reserved 11 = Reserved Adjusts DAC bias 00 = Full bias 01 = Half bias (recommended) 10 = Reserved 11 = Reserved Adjusts master bias 00 = Reserved 01 = 0.75 bias 10 = full bias - default 11 = Reserved
2:1
DAC_BIAS
00
R116 (74h) Master Bias Control Master Bias Control
8:7
MASTER_BIAS
10
Table 44 Playback Power Management The reduced bias modes are available using the combination of register settings as shown. Default: Reduced Power Mode: Ultra Low Power Mode: DAC_BIAS = 00 (Full bias) DAC_BIAS = 01 (Half bias) DAC_BIAS = 01 (Half bias) MIXOUT_BIAS = 00 (Full bias) MIXOUT_BIAS = 00 (Full bias) MIXOUT_BIAS = 01 (Half bias) MASTER_BIAS = 10 (Full bias) MASTER_BIAS = 10 (Full bias) MASTER_BIAS = 01 (x0.75 bias)
Table 45 Bias Conditions for Default, Reduced and Ultra Low Power Modes The performance and power consumption differences between these modes are detailed in Table 3, Table 4, Table 5, and Table 6 on page 15, and in Table 1.
w
PD, August 2008, Rev 4.0 58
Production Data
WM8900
VOLUME UPDATES
Volume settings will not be applied to input or output PGAs until a '1' is written to one of the update bits. This is to allow left and right channels to be updated at the same time, as shown in Figure 21.
Figure 21 Simultaneous Left and Right Volume Updates
If the volume is adjusted while the signal is a non-zero value, an audible click can occur as shown in Figure 22.
Figure 22 Click Noise During Volume Update
In order to prevent this click noise, a zero cross function is provided. When enabled, this will cause the PGA volume to update only when a zero crossing occurs, minimising click noise as shown in Figure 23.
w
PD, August 2008, Rev 4.0 59
WM8900
Production Data
Figure 23 Volume Update Using Zero Cross Detection
If there is a long period where no zero-crossing occurs, a timeout circuit in the WM8900 will automatically update the volume. The volume updates will occur between one and two timeout periods, depending on when the volume update bit is set as shown in Figure 24. The TOCLK_ENA register bit must be set to enable this timeout function. The timeout period is set by TOCLK_RATE.
Left PGA Input
Left PGA Output Zero crossing causes volume update Right PGA Input No zero crossing
Right PGA Output Timeout Counter
Timeout causes volume update
SYSCLK/221 or SYSCLK/219, depending on TOCLK_RATE Control Interface
Write Left Volume Update bit = 0 Write Right Volume Update bit = 1
Time
Write Left PGA Volume without update
Write Right PGA Volume with update
Figure 24 Volume Update after Timeout
w
PD, August 2008, Rev 4.0 60
Production Data
WM8900
HEADPHONE JACK DETECT
The headphone jack detect feature may be used to automatically control any of the Line outputs and Headphone outputs when a connection is made to a jack socket. Any of the ADCLRC/GPIO, LINPUT3/JD, RINPUT3/JD, MODE/GPIO or CSB/GPIO pins may be selected as headphone jack detect input to control the lineout enables. The most likely usage of this feature would be to disable the Line outputs when a headphone is plugged into a jack socket. The Jack Detect mode is enabled via the JD_ENA register bit. When enabled, the Jack Detect input is selected via the JD_SRC field - this determines which pin of the WM8900 is used to activate the Jack Detect feature. The JD_MODE bit may be used to reverse the polarity of the selected Jack Detect input. The selected Jack Detect input has two states - logic 0 and logic 1. For each of these two states, the desired combination of Line output enables can be set by the user. The JD_EN0 register field controls which outputs are enabled in the logic 0 Jack Detect state. The JD_EN1 field controls which outputs are enabled in the logic 1 Jack Detect state. The Line output and Headphone outputs controlled by the Jack Detect mode are controlled via an AND function with their normal enable signals. Therefore, any output that is enabled via the JD_EN0 or JD_EN1 fields will only be active if its normal enable signal (see Table 37) is also enabled. Any output that is disabled via its normal enable signal will be unaffected by the Jack Detect mode. Any Line or Headphone output that is to be controlled by the Jack Detect mode must have its normal enable signal active. Any Line or Headphone output that is to be unaffected by the Jack Detect mode must set enabled in both the JD_EN0 and JD_EN1 fields. The Jack Detect input must be de-bounced for correct operation. To do this, TOCLK_ENA must be set and TOCLK_RATE set according to the desired fast/slow response time. The de-bounced headphone Jack Detect signal may be output to the GPIO pin (see "General Purpose Input/Output"). This is not possible if the pin is used for any other GPIO function. Note that, when LINPUT3/JD or RINPUT3/JD is used as the Jack Detect input, the logic levels are CMOS levels (0.3 AVDD / 0.7 AVDD). REGISTER ADDRESS R18 (12h) GPIO Control 9 BIT LABEL JD_ENA DEFAULT 0 DESCRIPTION Jack Detect Switch Enable 0 = Jack Detect disabled 1 = Jack Detect enabled Jack Detect Switch Polarity 0 = Jack Detect active high 1 = Jack Detect active low Jack Detect Input Select 000 = ADCLRC/GPIO used for jack detect 001 = CSB/GPIO used for jack detect 010 = LINPUT3/JD used for jack detect 011 = RINPUT3/JD used for jack detect 100 = MODE/GPIO used for jack detect 101 to 111 Reserved Output enables when selected jack detection input is logic 1 JD_EN1[0] =1 enables LINEOUT_1L JD_EN1[1] =1 enables LINEOUT_1R JD_EN1[2] =1 enables LINEOUT_2R JD_EN1[3] =1 enables LINEOUT_2R JD_EN1[4] =1 enables Headphone JD_EN1[5] =1 enables Charge Pump
8
JD_MODE
0
3:1
JD_SRC[2:0]
000
R17 (11h) Jack Detect Control
13:8
JD_EN1[5:0]
000000
w
PD, August 2008, Rev 4.0 61
WM8900
REGISTER ADDRESS BIT 5:0 LABEL JD_EN0[5:0] DEFAULT 000000
Production Data
DESCRIPTION Output enables when selected jack detection input is logic 0 JD_EN0[0] =1 enables LINEOUT_1L JD_EN0[1] =1 enables LINEOUT_1R JD_EN0[2] =1 enables LINEOUT_2R JD_EN0[3] =1 enables LINEOUT_2R JD_EN0[4] =1 enables Headphone JD_EN0[5] =1 enables Charge Pump
R7 (07h) Clocking 2
1
TOCLK_RATE
0
Slow Clock Selection (Used for volume update timeouts and for jack detect debounce) 0 = SYSCLK / 221 (Slower Response) 1 = SYSCLK / 219 (Faster Response)
0
TOCLK_ENA
0
Slow Clock Enable (Must be enabled for jack detect de-bounce) 0 = Slow Clock Disabled 1 = Slow Clock Enabled
Table 46 Jack Detect Control
DISABLED OUTPUTS Whenever an analogue output is disabled, it remains connected to VREF through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance between VREF and each output can be controlled using register bit VROI. If a high impedance is desired for disabled outputs, VROI can then be set to 1, increasing the resistance to about 20k. REGISTER ADDRESS R30 (1Eh) Additional Control 0 BIT LABEL VROI 0 DEFAULT DESCRIPTION VREF to Analogue Output Resistance (Disabled Outputs) 0 = 500 from buffered VMID to output 1 = 20k from buffered VMID to output
Table 47 Disabled Outputs to VREF Resistance
THERMAL SHUTDOWN
The headphone outputs can drive very large currents. To protect the WM8900 from overheating a thermal shutdown circuit is included. If the device temperature reaches approximately 1500C and the thermal shutdown circuit is enabled (TEMP_SD = 1; TEMP_ENA = 1) the headphone amplifiers (HP_L, HP_R) and the Line Outputs (LINEOUT_1L, LINEOUT_1R, LINEOUT_2L and LINEOUT_2R) will be disabled. TEMP_ENA must be set to 1 to enable the temperature sensor when using the TEMP_SD thermal shutdown function. The output of the temperature sensor can also be output to the GPIO pin. REGISTER ADDRESS R30 (1Eh) Additional Control 1 BIT LABEL TEMP_SD 1 DEFAULT DESCRIPTION Thermal Shutdown Enable 0 = Thermal shutdown disabled 1 = Thermal shutdown enabled (TEMP_ENA must be enabled for this function to work) Temperature Sensor Enable 0 = Temperature sensor disabled 1 = Temperature sensor enabled
R18 (12h) GPIO Control
0
TEMP_ENA
1
Table 48 Thermal Shutdown
w
PD, August 2008, Rev 4.0 62
Production Data
WM8900
GENERAL PURPOSE INPUT/OUTPUT
The WM8900 has three dual purpose input/output pins which may be configured according to the selected control mode and according to GPIO register settings. The three pins are as follows: * * * ADCLRC/GPIO - ADC Left/Right frame clock or GPIO pin CSB - Control Interface control or GPIO pin MODE - Control Interface control or GPIO pin
Two analogue inputs may also be configured as headphone jack detect inputs, by use of some of the same GPIO register fields. These two inputs are as listed below. The default configuration for these pins is to be analogue inputs. * * LINPUT3/JD2 - Analogue input or headphone detect input RINPUT3/JD3 - Analogue input or headphone detect input
The ADCLRC/GPIO pin can be configured as a left/right frame clock for the ADC, a headphone jack detect input, or as one of a number of GPIO output functions. The configuration of this pin as ADCLRC or as GPIO is determined by the ADCLRC_FN bit. During power-up, if the MODE pin is low, the serial interface mode of operation is selected as 2 wire, in this case CSB is sampled in order to select the correct device address according to Table 69. Thereafter, the normal CSB function is not required in 2-wire control mode, and the CSB pin is automatically configured as one of the GPIO functions. In 3-wire control mode, the MODE pin may be configured as GPIO by register bit MODE_FN. (See "Control Interface" for further details of this bit.) The GPIO function of the pin (or pins) selected as GPIO is controlled by the ADCLRC_SRC register. It is possible for more than one of the GPIO pins to output the same function simultaneously. The polarity of the GPIO output may be inverted by setting the ADCLRC_INV bit. If headphone jack detect input is selected, then only one of the possible sources may be selected as the jack detect input; the chosen input will be determined by the JD_SRC field. (See "Headphone Jack Detect" for further details of this bit.)
REGISTER ADDRESS R5 (05h) Audio Interface 2 R18 (12h) GPIO Control 6
BIT
LABEL ADCLRC_FN
DEFAULT 0
DESCRIPTION ADCLRC/GPIO Pin Function Select 0 = ADCLRC frame clock for ADC 1 = GPIO pin GPIO Output Polarity Invert 0 = Non inverted 1 = Inverted GPIO Pin Function Select: 000 = Jack detect input 001 = Reserved 010 = Temperature ok 011 = Debounced jack detect output 100 = SYSCLK output 101 = FLL lock 110 = Logic 0 111 = Logic 1
7
ADCLRC_INV
0
6:4
ADCLRC_SRC [2:0]
000
Table 49 GPIO Control The slow clock must be enabled when using the Jack Detect function. This is used to de-bounce the jack detect input. See "Headphone Jack Detect" for further details of the associated controls. The temperature sensor must be enabled for the `Temperature ok' GPIO output to function properly. See "Thermal Shutdown" for further details. The SYSCLK GPIO output is derived from SYSCLK and also set by a programmable divider OPCLK_DIV. See "Clocking and Sample Rates" for further details of this field.
w
PD, August 2008, Rev 4.0 63
WM8900
DIGITAL AUDIO INTERFACE
Production Data
The digital audio interface is used for inputting DAC data into the WM8900 and outputting ADC data from it. It uses five pins: * * * * * ADCDAT: ADC data output ADCLRC: ADC data alignment clock DACDAT: DAC data input DACLRC: DAC data alignment clock BCLK: Bit clock, for synchronisation
The clock signals BCLK, ADCLRC and DACLRC can be outputs when the WM8900 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). ADCLRC can also be configured as a GPIO pin. In this case, the ADC will use DACLRC as a frame clock. The ADCLRC/GPIO pin function should not be modified while the ADC is enabled. Four different audio data formats are supported: * * * * Left justified Right justified I2S DSP mode
All four of these modes are MSB first. They are described in the "Audio Data Formats" section below. Refer to the "Electrical Characteristics" section for timing information. Time division multiplexing (TDM) is available in all four data format modes. The WM8900 can be programmed to send and receive data in one of two time slots.
MASTER AND SLAVE MODE OPERATION The WM8900 can be configured as either a master or slave mode device. As a master device the WM8900 generates BCLK, ADCLRC and DACLRC and thus controls sequencing of the data transfer on ADCDAT and DACDAT. In slave mode, the WM8900 responds with data to clocks it receives over the digital audio interface. The mode can be selected by writing to the BCLK_DIR, ADCLRC_DIR and DACLRC_DIR register bits. Master and slave modes are illustrated below. Note that the WM8900 also supports mixed master and slave modes - see "Audio Interface Control".
BCLK ADCLRC WM8900 CODEC DACLRC ADCDAT DACDAT DSP ENCODER/ DECODER WM8900 CODEC
BCLK ADCLRC DACLRC ADCDAT DACDAT DSP ENCODER/ DECODER
Note: The ADC and DAC can run at different sample rates
Note: The ADC and DAC can run at different sample rates
Figure 25 Master Mode
Figure 26 Slave Mode
OPERATION WITH ADCLRC AS GPIO When the ADCLRC/GPIO pin is configured as a GPIO pin (ADCLRC_FN = 1), the DACLRC pin is used as a frame clock for ADCs and DACs as shown below. The ADCs and DACs must operate at the same sample rate in this mode. See "General Purpose Input/Output" section for details of GPIO pin configuration.
w
PD, August 2008, Rev 4.0 64
Production Data
WM8900
BCLK GPIO
WM8900 CODEC
BCLK ADCLRC
DSP ENCODER/ DECODER
ADCLRC DACLRC
WM8900 CODEC
GPIO ADCDAT DACDAT
DSP ENCODER/ DECODER
DACLRC ADCDAT DACDAT
Note: The ADC and DAC cannot run at different sample rates in this mode
Note: The ADC and DAC cannot run at different sample rates in this mode
Figure 27 Master Mode with ADCLRC as GPIO
Figure 28 Slave Mode with ADCLRC as GPIO
The Audio Interface output control is illustrated above. The left-right clock control bits, ADCLRC_DIR and DACLRC_DIR, determine whether the corresponding clock output is enabled (see "Audio Interface Control" for the definition of these bits). The ADCLRC_FN register bit controls the mode of operation of the ADCLRC/GPIO pin (see "GPIO" for the definition of this bit).
OPERATION WITH TDM The digital audio interface on WM8900 has the facility of tri-stating the ADCDAT pin to allow multiple data sources on the same bus. Time division multiplexing (TDM) is also supported, allowing audio output data to be transferred simultaneously from two different sources. The WM8900 ADCs and DACs support TDM in master and slave modes, on both interfaces, and for all data formats and word lengths. TDM is enabled using register bits AIFADC_TDM and AIFDAC_TDM. The TDM data slot is programmed using register bits AIFADC_TDM_CHAN and AIFDAC_TDM_CHAN. (See "Audio Interface Control" for the definition of these bits.) When operating in TDM mode with another device, the possible connections are as follows:
BCLK ADCLRC WM8900 DACLRC ADCDAT DACDAT Processor WM8900
BCLK ADCLRC DACLRC ADCDAT DACDAT Processor
BCLK ADCLRC WM8900 or similar CODEC DACLRC ADCDAT DACDAT WM8900 Or similar CODEC
BCLK ADCLRC DACLRC ADCDAT DACDAT
Figure 29 TDM with WM8900 as Master
Figure 30 TDM with Other CODEC as Master
w
PD, August 2008, Rev 4.0 65
WM8900
Production Data
BCLK ADCLRC WM8900 DACLRC ADCDAT DACDAT Processor
BCLK ADCLRC WM8900 Or similar CODEC DACLRC ADCDAT DACDAT
Figure 31 TDM with Processor as Master
Note: The WM8900 is a 24-bit device. If the user operates the WM8900 in 32-bit mode then the 8 LSBs will be ignored on the receiving side and not driven on the transmitting side. It is therefore recommended to add a pull-down resistor if necessary to the DACDAT line and the ADCDAT line in TDM mode.
AUDIO DATA FORMATS (NORMAL MODE) In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 32 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
w
PD, August 2008, Rev 4.0 66
Production Data
WM8900
Figure 33 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next.
Figure 34 I2S Justified Audio Interface (assuming n-bit word length)
In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by AIF_LRCLKINV) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In device master mode, the LRC output will resemble the frame pulse shown in Figure 35 and Figure 36. In device slave mode, Figure 37 and Figure 38, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse.
w
PD, August 2008, Rev 4.0 67
WM8900
Production Data
Figure 35 DSP/PCM Mode Audio Interface (mode A, AIF_LRCLKINV=0, Master)
Figure 36 DSP/PCM Mode Audio Interface (mode B, AIF_LRCLKINV =0, Master)
Figure 37 DSP/PCM Mode Audio Interface (mode A, AIF_LRCLKINV =0, Slave)
w
PD, August 2008, Rev 4.0 68
Production Data
WM8900
Figure 38 DSP/PCM Mode Audio Interface (mode B, AIF_LRCLKINV =0, Slave)
AUDIO DATA FORMATS (TDM MODE) TDM is supported in master and slave mode and is enabled by register bits AIF_ADC_TDM and AIF_DAC_TDM. All audio interface data formats support time division multiplexing (TDM) for ADC and DAC data. Two time slots are available (Slot 0 and Slot 1), selected by register bits AIFADC_TDM_CHAN and AIFDAC_TDM_CHAN which control time slots for the ADC data and the DAC data. When TDM is enabled, the ADCDAT pin will be tri-stated immediately before and immediately after data transmission, to allow another ADC device to drive this signal line for the remainder of the sample period. When TDM is enabled, BCLK frequency must be high enough to allow data from both time slots to be transferred. The number of BCLK cycles from the start of Slot 0 to the start of Slot 1 is determined by the selected word length of the applicable interface. The timing of Slot 0 and Slot 1 also depends upon the selected data format as shown in Figure 39 to Figure 43. Timing diagrams for the various interface formats in TDM mode are shown below for the ADC. Similar timings apply to the DACDAT and DACLRC pins.
Figure 39 TDM in Left-Justified Mode
w
PD, August 2008, Rev 4.0 69
WM8900
Production Data
Figure 40 TDM in Right-Justified Mode
Figure 41 TDM in I2S Mode
1/fs 1 BCLK
ADCLRC
BCLK
ADCDAT
SLOT0 L
SLOT0 R
SLOT1 L
SLOT1 R
Figure 42 TDM in DSP/PCM Mode A
w
PD, August 2008, Rev 4.0 70
Production Data
WM8900
1/fs 1 BCLK
ADCLRC
BCLK
ADCDAT
SLOT0 L
SLOT0 R
SLOT1 L
SLOT1 R
Figure 43 TDM in DSP/PCM Mode B
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and the TDM parameters are summarised in Table 50. In Master mode BCLK, ADCLRC and DACLRC are outputs, and the frequency of ADCLRC, DACLRC and BCLK are set by the fields ADCLRC_RATE, DACLRC_RATE and BCLK_DIV (see "Clocking and Sample Rates"). In Slave mode BCLK, ADCLRC and DACLRC are inputs. It is possible to control these clock outputs individually using register bits ADCLRC_DIR, DACLRC_DIR and BCLK_DIR, allowing mixed master and slave modes for the ADCs and DACs. See Table 52 for a definition of these fields. BCLK inverted (AIF_BCLK_INV = 1) is not available in Master Mode (BCLK_DIR = 1). REGISTER ADDRESS R4 (04h) Audio Interface 1 BIT 13 LABEL AIFADC_TDM DEFAULT 0 DESCRIPTION ADC TDM Enable 0 = Normal ADCDAT operation 1 = TDM enabled on ADCDAT ADCDAT TDM Channel Select 0 = ADCDAT outputs data on slot 0 1 = ADCDAT output data on slot 1 BCLK Invert 0 = BCLK not inverted 1 = BCLK inverted (see note 1) Right, left and I2S modes - LRCLK polarity 0 = normal LRCLK polarity 1 = invert LRCLK polarity DSP Mode - mode A/B select 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) 6:5 AIF_WL [1:0] 10 Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits Digital Audio Interface Format 00 = Right justified 01 = Left justified 10 = I2S Format 11 = DSP Mode
12
AIFADC_TDM_CHAN
0
8
AIF_BCLK_INV
0
7
AIF_LRCLK_INV
0
4:3
AIF_FMT [1:0]
10
w
PD, August 2008, Rev 4.0 71
WM8900
REGISTER ADDRESS R5 (05h) Audio Interface 2 BIT 13 LABEL AIFDAC_TDM DEFAULT 0
Production Data
DESCRIPTION DAC TDM Enable 0 = Normal DACDAT operation 1 = TDM enabled on DACDAT DACDAT TDM Channel Select 0 = DACDAT data input on slot 0 1 = DACDAT data input on slot 1
12
AIFDAC_TDM_CHAN
0
Table 50: Audio Data Format Control Notes 1) AIF_BCLK_INV = 1 is not available in Master Mode (BCLK_DIR = 1). AUDIO INTERFACE OUTPUT TRISTATE The audio interface tri-state feature is controlled by register bit AIF_TRI, as described in Table 51. This bit can be used to tri-state the ADCDAT pin and switch ADCLRC, DACLRC and BCLK to inputs. Note that, in Slave mode, ADCLRC, DACLRC and BCLK are already configured as inputs by default and will be unaffected by the tri-state selection. When the ADCLRC/GPIO pin is configured as a GPIO, this pin is not affected by the AIF_TRI register bit. REGISTER ADDRESS R7 (07h) Clocking 2 BIT 12 LABEL AIF_TRI DEFAULT 0 DESCRIPTION Tri-states ADCDAT and switches ADCLRC, DACLRC and BCLK to inputs. 0 = ADCDAT is an output; DACLRC and BCLK may be inputs or outputs; ADCLRC is input, output or GPIO. 1 = ADCDAT is tri-stated; DACLRC and BCLK are inputs; ADCLRC is input or GPIO.
Table 51 Tri-stating the Audio Interface
ADCLRC, DACLRC AND BCLK ENABLE The ADCLRC, DACLRC and BCLK pins may be individually configured as inputs or outputs, allowing mixed master and slave modes for the ADCs and DACs. ADCLRC may be configured as an input or output by setting the ADCLRC_DIR register bit defined in Table 52. If AIF_TRI is set to 1, then ADCLRC will be an input irrespective ADCLRC_DIR. If ADCLRC_FN is set to 1, then ADCLRC will be a GPIO irrespective ADCLRC_DIR or ADCLRC_FN. When ADCLRC is configured as an output, this clock will enabled when one or both ADCs are enabled. as of of be
DACLRC may be configured as an input or output by setting the DACLRC_DIR register bit as defined in Table 52. If AIF_TRI is set to 1, then DACLRC will be an input irrespective of DACLRC_DIR. When DACLRC is configured as an output, this clock will be enabled when one or both DACs are enabled. BCLK may be configured as an input or output by setting the BCLK_DIR register bit as defined in Table 52. If AIF_TRI is set to 1, then BCLK will be an input irrespective of BCLK_DIR. When BCLK is configured as an output, this clock will be enabled when any of the ADCs or DACs is enabled. When ADCLRC is configured as a GPIO (using ADCLRC_FN - see "General Purpose Input/Output"), the DACLRC is used for the ADCs and the DACs and will only be disabled when both ADCs and both DACs are disabled. If one or both DACs are enabled, the DACLRC clock rate will be determined by DACLRC_RATE. If both DACs are disabled, and ADCLRC is configured as a GPIO, then the DACLRC clock rate will be set by ADCLRC_RATE. Table 52 describes how these clock signals are controlled.
w
PD, August 2008, Rev 4.0 72
Production Data
WM8900
See "Clocking and Sample Rates" for the definition of how the clock frequencies are set. REGISTER ADDRESS R6 (06h) Clocking 1 R8 (08h) Audio Interface 3 R9 (09h) Audio Interface 4 0 BIT LABEL BCLK_DIR DEFAULT 0 DESCRIPTION BCLK Direction 0 = BCLK is input 1 = BCLK is output ADCLRC Direction 0 = ADCLRC is input 1 = ADCLRC is output DACLRC Direction 0 = DACLRC is input 1 = DACLRC is output
11
ADCLRC_DIR
0
11
DACLRC_DIR
0
Table 52 Master Clock Controls
COMPANDING The WM8900 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively. REGISTER ADDRESS R5 (05h) Audio Interface 2 4 BIT LABEL DAC_COMP DEFAULT 0 DESCRIPTION DAC Companding enable 0 = off 1 = on DAC Companding mode select: 0 = -law 1 = A-law ADC Companding enable 0 = off 1 = on ADC Companding mode select: 0 = -law 1 = A-law
3
DAC_COMPMODE
0
2
ADC_COMP
0
1
ADC_COMPMODE
0
Table 53 Companding Control
Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: -law (where =255 for the U.S. and Japan): F(x) = ln( 1 + |x|) / ln( 1 + ) A-law (where A=87.6 for Europe): F(x) = A|x| / ( 1 + lnA) F(x) = ( 1 + lnA|x|) / (1 + lnA) } for x 1/A } for 1/A x 1 -1 x 1
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB's of data. Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The input data range is separated into 8 levels, allowing low amplitude signals better precision than that of high amplitude signals. This is to exploit the operation of the human auditory system, where louder sounds do not require as much resolution as quieter sounds. The companded signal is an 8-bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits).
w
PD, August 2008, Rev 4.0 73
WM8900
Production Data
BIT7 SIGN
BIT[6:4] EXPONENT
BIT[3:0] MANTISSA
Table 54 8-bit Companded Word Composition
u-law Companding
1 120 100 Companded Output 80 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output
Figure 44 -Law Companding
A-law Companding
1 120 100 Companded Output 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1 Normalised Input 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output
Figure 45 A-Law Companding LOOPBACK Setting the LOOPBACK register bit enables digital loopback. When this bit is set, the output data from the ADC audio interface is fed directly into the DAC data input interface. REGISTER ADDRESS R5 (05h) Audio Interface 2 0 BIT LABEL LOOPBACK DEFAULT 0 DESCRIPTION Digital Loopback Function 0 = No loopback. 1 = Loopback enabled, ADC data output is fed directly into DAC data input.
Table 55 Loopback Control
w
PD, August 2008, Rev 4.0 74
Production Data
WM8900
Notes: 1. Master Mode: ADC and DAC left/right clocks must be connected together externally, or be of the same frequency and completely synchronised, when using LOOPBACK function (ADCLRC_FN=1) Slave Mode: It is recommended to set ADCLRC_FN = 1 as well, otherwise ADCLRC and DACLRC must be running at the same BCLK rate and in phase. When Loopback is enabled simultaneously to the Digital Sidetone, ADC data will be mixed with DAC data through both signal paths.
2.
3.
CLOCKING AND SAMPLE RATES
Clocks for the ADCs, DACs, DSP core functions, the digital audio interface and the GroundReferenced Headphone output driver are all derived from a common internal clock source, SYSCLK. SYSCLK can either be derived directly from MCLK, or may be generated from an FLL using MCLK or DACLRC as an external reference. The SYSCLK source is selected by MCLK_SRC. Many commonly-used audio sample rates can be derived directly from typical MCLK frequencies; the FLL provides additional flexibility for a wider range of MCLK or DACLRC frequencies. The ADC and DAC sample rates are independently selectable, relative to SYSCLK, using ADC_CLKDIV and DAC_CLKDIV. These fields must be set according to the required sampling frequency and depending upon the selected clocking mode. Two clocking modes are provided Normal mode allows selection of the commonly used sample rates from typical audio system clocking frequencies (eg. 12.288MHz); USB mode allows many of these sample rates to be generated from a 12MHz USB clock. Depending on the available clock sources, the USB mode may be used to save power by supporting 44.1kHz operation without recourse to the FLL. In Normal mode, ADC_SYSCLK = 256 x ADC Sampling Frequency DAC_SYSCLK = 256 x DAC Sampling Frequency In USB mode, ADC_SYSCLK = 272 x ADC Sampling Frequency DAC_SYSCLK = 272 x DAC Sampling Frequency The above equations determine the required values for ADC_CLKDIV and DAC_CLKDIV. The clocking mode is selected via the AIF_LRCLKRATE field. In master mode, BCLK is also derived from SYSCLK via a programmable division set by BCLK_DIV. In the case where the ADCs and DACs are operating at different sample rates, BCLK must be set according to whichever is the faster rate. In Master Mode, internal clock divide and phase control mechanisms ensure that the BCLK, ADCLRC and DACLRC edges will occur in a predictable and repeatable position relative to each other and to the data for a given combination of ADC/DAC sample rates and BCLK settings. In Slave Mode, the host processor must ensure that BCLK, ADCLRC and DACLRC are fully synchronised; if these inputs are not synchronised, unpredictable pops and noise may result. Changing the clocking or sample rates on the WM8900 may result in audible pops and clicks. It is recommended that the amplifier mute control bits are used to enable/disable the analogue outputs whenever a change is made to any of the clocking or sample rates. The mute control bits for specific amplifier stages within the WM8900 are detailed in the applicable sections within this datasheet. Detailed information is available for specific requirements - see "Applications Information". When the ADCLRC/GPIO pin is configured as a GPIO, a clock derived from SYSCLK may be output on this pin to provide clocking for other parts of the system. The frequency of this signal is set by OPCLK_DIV. A slow clock derived from SYSCLK may be used to provide de-bouncing of the headphone detect function, and to set the timeout period for volume updates when zero-cross functions are used. This clock is enabled by TOCLK_ENA and its frequency is set by TOCLK_RATE.
w
PD, August 2008, Rev 4.0 75
WM8900
The overall clocking scheme is illustrated in Figure 46.
Production Data
Figure 46 System Clocking
SYSCLK CONTROL The MCLK_SRC bit is used to select the source for SYSCLK. The source may be either MCLK or the output of the FLL. These fields are described in Table 56. See "FLL" for further details of the Frequency Locked Loop control. When the internal clock source is switched from one value to another using MCLK_SRC, the change of source will only occur following a falling edge of the source signal that was originally selected. In the case where the clock source is switched from FLL to MCLK, a suitable falling edge can be ensured by disabling the FLL after selection of MCLK as the source. The recommended sequence of actions to switch from FLL to MCLK source is as follows: * * * Select MCLK as source (MCLK_SRC = 0) Disable FLL (FLL_ENA = 0) Disable FLL oscillator (FLL_OSC_ENA = 0) (Optional)
Note that, as an alternative to the above sequence, a software reset may be used to re-select MCLK as the default SYSCLK source The recommended sequence of actions to switch from MCLK to FLL source is as follows: * * * * Enable FLL oscillator (FLL_OSC_ENA = 1) Enable FLL (FLL_ENA = 1) Allow for FLL lock time to elapse. Select FLL as source (MCLK_SRC = 1)
w
PD, August 2008, Rev 4.0 76
Production Data
WM8900
REGISTER ADDRESS R6 (06h) Clocking 1 8
BIT
LABEL MCLK_SRC
DEFAULT 0
DESCRIPTION Clock Source selection 0 = SYSCLK derived from MCLK 1 = SYSCLK derived from FLL output
Table 56 SYSCLK Control
ADC / DAC SAMPLE RATES The ADC and DAC sample rates are independently selectable, relative to SYSCLK, by setting the register fields ADC_CLKDIV and DAC_CLKDIV. These fields must be set according to the SYSCLK frequency, and according to the selected mode of operation (Normal or USB). The applicable fields are described in Table 57. Selection of USB mode enables a 12MHz USB clock to be used to generate the required internal clock signals. Table 58 describes the available sample rates using four different common MCLK frequencies. The AIF_LRCLKRATE field must be set as described in Table 57 to ensure correct operation of internal functions according to the SYSCLK / Fs ratio. In Normal mode, the programmable division set by ADC_CLKDIV must ensure that ADC_SYSCLK is 256 * ADC Sampling Frequency. DAC_CLKDIV must ensure that DAC_SYSCLK is 256 * DAC Sampling Frequency. There are constraints on the SYSCLK frequency when using the headphone output. SYSCLK should be maintained according to the electrical characteristics shown in Table 1, to maintain output power. In USB mode, ADC_CLKDIV must ensure that ADC_SYSCLK is 272 * ADC Sampling Frequency. DAC_CLKDIV must ensure that DAC_SYSCLK is 272 * DAC Sampling Frequency. REGISTER ADDRESS R10 (0Ah) DAC Control R7 (07h) Clocking 2 BIT 10 LABEL AIF_LRCLKRATE DEFAULT 0 DESCRIPTION Mode Select 1 = USB mode (272 * Fs) 0 = Normal mode (256 * Fs) ADC Sample rate divider 000 = SYSCLK / 1.0 001 = SYSCLK / 1.5 010 = SYSCLK / 2 011 = SYSCLK / 3 100 = SYSCLK / 4 101 = SYSCLK / 5.5 110 = SYSCLK / 6 111 = Reserved DAC Sample rate divider 000 = SYSCLK / 1.0 001 = SYSCLK / 1.5 010 = SYSCLK / 2 011 = SYSCLK / 3 100 = SYSCLK / 4 101 = SYSCLK / 5.5 110 = SYSCLK / 6 111 = Reserved
7:5
ADC_CLKDIV [2:0]
000
4:2
DAC_CLKDIV [2:0]
000
Table 57 ADC / DAC Sample Rate Control
w
PD, August 2008, Rev 4.0 77
WM8900
Production Data
SYSCLK
ADC / DAC SAMPLE RATE DIVIDER 000 = SYSCLK / 1 001 = SYSCLK / 1.5 010 = SYSCLK / 2 011 = SYSCLK / 3 100 = SYSCLK / 4 101 = SYSCLK / 5.5 110 = SYSCLK / 6 111 = Reserved 000 = SYSCLK / 1 001 = SYSCLK / 1.5 010 = SYSCLK / 2 011 = SYSCLK / 3 100 = SYSCLK / 4 101 = SYSCLK / 5.5 110 = SYSCLK / 6 111 = Reserved 000 = SYSCLK / 1 001 = SYSCLK / 1.5 010 = SYSCLK / 2 011 = SYSCLK / 3 100 = SYSCLK / 4 101 = SYSCLK / 5.5 110 = SYSCLK / 6 111 = Reserved 000 = SYSCLK / 1 001 = SYSCLK / 1.5 010 = SYSCLK / 2 011 = SYSCLK / 3 100 = SYSCLK / 4 101 = SYSCLK / 5.5 110 = SYSCLK / 6 111 = Reserved
CLOCKING MODE
ADC / DAC SAMPLE RATE 48 kHz 32 kHz 24 kHz 16 kHz 12 kHz Not used 8 kHz Reserved 44.1 kHz Not used 22.05 kHz Not used 11.025 kHz 8.018 kHz Not used Reserved 44.118 kHz Not used 22.059 kHz Not used 11.029 kHz 8.021 kHz Not used Reserved 8 kHz Not used Not used Not used Not used Not used Not used Reserved
Normal (256 * Fs)
12.2880 MHz
Normal (256 * Fs)
11.2896 MHz
USB (272 * Fs)
12.0000 MHz
Normal (256 * Fs)
2.0480 MHz
Table 58 Derivation of Sample Rates in Normal / USB Modes
Note that, in USB mode, the ADC / DAC sample rates do not match exactly with the commonly used sample rates (eg. 44.118 kHz instead of 44.100 kHz). At most, the difference is less than 0.5%, which is within normal accepted tolerances. Data recorded at 44.100 kHz sample rate and replayed at 44.118 kHz will experience a slight (sub 0.5%) pitch shift as a result of this difference. Note USB mode cannot be used to generate a 48kHz samples rate from a 12MHz MCLK. The FLL should be used in this case. The user must ensure correct synchronisation of data across the digital interfaces. This is particularly important when different sample rates are used, as described above.
BCLK CONTROL In Master Mode, BCLK is derived from SYSCLK via a programmable division set by BCLK_DIV, as described in Table 59. BCLK_DIV must be set to an appropriate value to ensure that there are sufficient BCLK cycles to transfer the complete data words from the ADCs and to the DACs. Note that, although the ADC and DAC can run at different sample rates, they share the same bit clock BCLK. In the case where different ADC / DAC sample rates are used, the BCLK frequency should be set according to the higher of the ADC / DAC bit rates.
w
PD, August 2008, Rev 4.0 78
Production Data
WM8900
In Slave Mode, BCLK is generated externally and appears as an input to the CODEC. The host device must provide sufficient BCLK cycles to transfer complete data words to the ADCs and DACs. See "Digital Audio Interface" for details of Master/Salve operation. See "Audio Interface Control" for further details of how BCLK is configured as an input or output. BCLK_DIV = 32 (1101) is not available in USB mode (AIF_LRCLKRATE = 1). REGISTER ADDRESS R6 (06h) Clocking 1 BIT 4:1 LABEL BCLK_DIV [3:0] DEFAULT 0000 DESCRIPTION BCLK Frequency (Master Mode) 0000 = SYSCLK 0001 = SYSCLK / 1.5 0010 = SYSCLK / 2 0011 = SYSCLK / 3 0100 = SYSCLK / 4 0101 = SYSCLK / 5.5 0110 = SYSCLK / 6 0111 = SYSCLK / 8 1000 = SYSCLK / 11 1001 = SYSCLK / 12 1010 = SYSCLK / 16 1011 = SYSCLK / 22 1100 = SYSCLK / 24 1101 = SYSCLK / 32 (see note 1) 1110 = SYSCLK / 44 1111 = SYSCLK / 48
Table 59 BCLK Control Notes 1. Not available in USB mode (AIF_LRCLKRATE = 1). Table 60 shows the maximum word lengths supported for a given SYSCLK and BCLK_DIV, assuming that one or both the ADCs and DACs are running at maximum rate. SYSCLK BCLK DIVIDER BCLK_DIV 0000 = SYSCLK / 1 0001 = SYSCLK / 1.5 0010 = SYSCLK / 2 0011 = SYSCLK / 3 0100 = SYSCLK / 4 0101 = SYSCLK / 5.5 0110 = SYSCLK / 6 12.288 MHz 0111 = SYSCLK / 8 1000 = SYSCLK / 11 1001 = SYSCLK / 12 1010 = SYSCLK / 16 1011 = SYSCLK / 22 1100 = SYSCLK / 24 1101 = SYSCLK / 32 1110 = SYSCLK / 32 1111 = SYSCLK / 32 11.2896 MHz 0000 = SYSCLK / 1 0001 = SYSCLK / 1.5 0010 = SYSCLK / 2 0011 = SYSCLK / 3 0100 = SYSCLK / 4 BCLK RATE (MASTER MODE) (MHz) 12.288 8.192 6.144 4.096 3.072 2.2341818 2.048 1.536 1.117091 1.024 0.768 0.558545 0.512 0.384 0.384 0.384 11.2896 7.5264 5.6448 3.7632 2.8224 32 32 32 32 32 20 20 16 8 8 8 N/A N/A N/A N/A N/A 32 32 32 32 32 MAXIMUM WORD LENGTH
w
PD, August 2008, Rev 4.0 79
WM8900
SYSCLK BCLK DIVIDER BCLK_DIV 0101 = SYSCLK / 5.5 0110 = SYSCLK / 6 0111 = SYSCLK / 8 1000 = SYSCLK / 11 1001 = SYSCLK / 12 1010 = SYSCLK / 16 1011 = SYSCLK / 22 1100 = SYSCLK / 24 1101 = SYSCLK / 32 1110 = SYSCLK / 32 1111 = SYSCLK / 32 Table 60 BCLK Divider in Master Mode BCLK RATE (MASTER MODE) (MHz) 2.052655 1.8816 1.4112 1.026327 0.9408 0.7056 0.513164 0.4704 0.3528 0.3528 0.3528
Production Data
MAXIMUM WORD LENGTH
20 20 16 8 8 8 N/A N/A N/A N/A N/A
ADCLRC / DACLRC CONTROL In Master Mode, ADCLRC and DACLRC are derived from BCLK via programmable dividers set by ADCLRC_RATE and DACLRC_RATE. The BCLK frequency is derived from SYSCLK according to BCLK_DIV, as described earlier in Table 59. The definitions of ADCLRC_RATE and DACLRC_RATE are described in Table 61. In Slave Mode, ADCLRC and DACLRC are generated externally and appear as an input to the CODEC. See "Digital Audio Interface" for details of Master/Salve operation. See "Audio Interface Control" for further details of how ADCLRC and DACLRC are configured as input or output. REGISTER ADDRESS R8 (08h) Audio Interface 3 BIT 10:0 LABEL ADCLRC_RATE [10:0] DEFAULT 040h DESCRIPTION ADCLRC Frequency (Master Mode). BCLK is divided by this integer. ADCLRC_RATE is an 11-bit integer (LSB = 1). Valid range is 8 .. 2047 R9 (09h) Audio Interface 4 10:0 DACLRC_RATE [10:0] 040h DACLRC Frequency (Master Mode). BCLK is divided by this integer. DACLRC_RATE is an 11-bit integer (LSB = 1). Valid range is 8 .. 2047 Table 61 ADCLRC / DACLRC Control
OPCLK CONTROL When the ADCLRC/GPIO pin is configured as a GPIO, a clock derived from SYSCLK may be output on this pin to provide clocking for other parts of the system. The frequency of this signal is derived from SYSCLK and determined by OPCLK_DIV, as described in Table 62. This output of this clock is dependent upon the ADCLRC_SRC register settings described under "General Purpose Input/Output".
w
PD, August 2008, Rev 4.0 80
Production Data
WM8900
REGISTER ADDRESS R6 (06h) Clocking 1
BIT 14:12
LABEL OPCLK_DIV [2:0]
DEFAULT 000
DESCRIPTION OPCLK Frequency (GPIO function) 000 = SYSCLK 001 = SYSCLK / 2 010 = SYSCLK / 3 011 = SYSCLK / 4 100 = SYSCLK / 5.5 101 = SYSCLK / 6 110 = Reserved 111 = Reserved
Table 62 OPCLK Control
SLOWCLK CONTROL A slow clock derived from SYSCLK may be generated for de-bouncing of the headphone detect function or to set the timeout period for volume updates when zero-cross functions are used. This clock is enabled by TOCLK_ENA and its frequency is set by TOCLK_RATE, as described in Table 46 in the "Headphone Jack Detect" section.
FLL
The integrated FLL can be used to generate SYSCLK from a wide variety of different reference sources and frequencies. The FLL can uses MCLK as its reference, which may be a high frequency (e.g. 13 MHz) reference. The FLL is tolerant of jitter and may be used to generate a stable SYSCLK from a less stable input signal. The FLL characteristics are summarised in "Electrical Characteristics". The analogue and digital portions of the FLL may be enabled independently via FLL_OSC_ENA and FLL_ENA. When initialising the FLL, the analogue circuit must be enabled first by setting FLL_OSC_ENA. The digital circuit may then be enabled on the next register write or later. When changing FLL settings, it is recommended that the digital circuit be disabled via FLL_ENA and then re-enabled after the other register settings have been updated. When changing the input reference frequency FREF, it is recommended that the FLL be reset by setting FLL_ENA to 0. It is recommended that the analogue circuit should remain enabled throughout any change of FLL settings. The FLL output frequency is directly determined from FLL_FRATIO, FLLCLK_DIV and the real number represented by FLL_N and FLL_K. The field FLL_N is an integer (LSB = 1); FLL_K is the fractional portion of the number (MSB = 0.5). The fractional portion is only valid when enabled by the field FLL_FRACN_ENA. De-selection of fractional mode results in lower power consumption. The FLL frequency is determined according to the following equation: FOUT = (FVCO / FLLCLK_DIV) FVCO = FREF x (N + K) x FLL_FRATIO FVCO must be in the range 90-100 MHz. The value of FLLCLK_DIV should be selected as follows according to the desired output FOUT. OUTPUT FREQUENCY FOUT 2.8125 MHz - 3.125 MHz 5.625 MHz - 6.25 MHz 11.25 MHz - 12.5 MHz Table 63 Choice of FLLCLK_DIV Note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed across the full range of device operating temperatures. FLLCLK_DIV 4h (divide by 32) 3h (divide by 16) 2h (divide by 8)
w
PD, August 2008, Rev 4.0 81
WM8900
Production Data
When setting up the FLL, after the register write to enable the FLL (FLL_ENA = 1), the FLL output clock will be available after the FLL lock time has elapsed. The FLL lock time is the time from last CSB edge of the serial interface write to first clock edge of fOUT from FLL. The FLL lock time is specified in Table 1. The FLL lock status can be monitored using a GPIO pin, see Table 49. The register fields that control the FLL are described in Table 64. Example settings for a variety of reference frequencies and output frequencies are shown in Table 65. REGISTER ADDRESS R1 (01h) Power Management 1 6 BIT LABEL FLL_ENA DEFAULT 0 DESCRIPTION FLL Digital Enable 0 = Power down 1 = Power up FLL_OSC_ENA must be enabled before enabling FLL_ENA. The order is important. R36 (24h) FLL Control 1 8 FLL_OSC_ENA 0 Analogue enable 0 = FLL disabled 1 = FLL enabled FLL_OSC_ENA must be enabled before enabling FLL_ENA. The order is important. 4:0 FLL_FRATIO [4:0] 8h CLK_VCO is divided by this integer, valid from 1 .. 31. Value 1 recommended for Reference clock > 96kHz Value 8 recommended for Reference clock < 96kHz Fractional enable 0 = Integer Mode 1 = Fractional Mode Fractional multiply for CLK_REF (Most Significant Bits) Fractional multiply for CLK_REF (Least Significant Bits) Integer multiply for CLK_REF (Most Significant Bits) FOUT clock divider 000 = FVCO / 2 001 = FVCO / 4 010 = FVCO / 8 (best performance) 011 = FVCO / 16 100 = FVCO / 32 101-111 = Reserved Integer multiply for CLK_REF (Least Significant Bits) Low frequency reference locking 0 = Lock achieved after 509 ref clks (Recommended for Reference clock > 48kHz) 1 = Lock achieved after 49 ref clks (Recommended for Reference clock <= 48kHz) FLL reference clock input selector 0 = MCLK 1 = DACLRC
R37 (25h) FLL Control 2
8
FLL_FRACN_E NA
0
7:0 R38 (26h) FLL Control 3 R39 (27h) FLL Control 4 R40 (28h) FLL Control 5 7:0 4:0 8:6
FLL_K [15:8] FLL_K [7:0] FLL_N [9:5] FLLCLK_DIV [2:0]
0h 0h 0Bh 3h
4:0 R41 (29h) FLL Control 6 8
FLL_N [4:0] FLL_SLOW_L OCK_REF
17h 1
7
LRCLK_REF_E NA
0
Table 64 FLL Register Map
w
PD, August 2008, Rev 4.0 82
Production Data
WM8900
EXAMPLE FLL SETTINGS Table 65 provides example FLL settings for generating common SYSCLK frequencies from a variety of reference inputs.
FREF 12.000 MHz 12.000 MHz 12.288 MHz 13.000 MHz 13.000 MHz 19.200 MHz 19.200 MHz
FOUT 12.288 MHz 11.289597 MHz 11.2896 MHz 12.287990 MHz 11.289606 MHz 12.287988 MHz 11.289588 MHz
FVCO 98.3040 MHz 90.3168 MHz 90.3168 MHz 98.3040 MHz 90.3168 MHz 98.3040 MHz 90.3168 MHz
FLL_N 8 (008h) 7 (007h) 7 (007h) 7 (007h) 6 (006h) 5 (005h) 4 (004h)
FLL_K 0.192 (3127h) 0.526398 (86C2h) 0.35 (599Ah) 0.56184 (8FD5h) 0.94745 (F28Ch) 0.119995 (1EB8h) 0.703995 (B439h) 1 1 1 1 1 1 1
FLL_F RATIO
FLLCLK _DIV 2h (divide by 8) 2h (divide by 8) 2h (divide by 8) 2h (divide by 8) 2h (divide by 8) 2h (divide by 8) 2h (divide by 8) 1 1 1 1 1 1 1
FRACN _ENA
FLL_SLOW _LOCK_REF 0 0 0 0 0 0 0
Table 65 Example FLL Settings
w
PD, August 2008, Rev 4.0 83
WM8900
CONTROL INTERFACE
Production Data
The WM8900 is controlled by writing to registers through a serial control interface. The interface may be either a 2-wire or 3-wire configuration. SELECTION OF CONTROL MODE At power-up, the MODE pin determines which control mode is selected, as described in Table 66. An internal pull-up causes default selection of 3-wire mode. MODE Low High (default) INTERFACE FORMAT 2 wire 3 wire
Table 66 Control Interface Mode Selection In 3-wire mode, the MODE pin can also be used as GPIO. To achieve this, the MODE_FN register bit must be set to 1. This causes the WM8900 to select 3-wire mode regardless of the MODE pin. Note that GPIO is not supported on the MODE pin in 2-wire mode and setting MODE_FN to 1 has no effect in 2-wire mode. Therefore, 3-wire mode must be initially selected as per Table 66 before writing to MODE_FN to select the GPIO function. The MODE pull-up can be enabled / disabled by register bit MODE_PU_ENA. When using the MODE pin as a GPIO output, it may be desirable to disable the pull-up to reduce power consumption. The value of MODE_PU_ENA has no effect on Mode selection when 3-wire mode has been selected by setting MODE_FN to 1. The register bits that determine the 2-wire or 3-wire mode selection are described in Table 67. See "General Purpose Input/Output" for more details on the use of the MODE pin as GPIO. REGISTER ADDRESS R18 (12h) GPIO Control BIT 12 LABEL MODE_PU_ENA DEFAULT 1 DESCRIPTION Enables the MODE Pull-Up resistor 0 = MODE Pull-Up disabled 1 = MODE Pull-Up enabled 11 MODE_FN 0 Selects Interface Control Mode 0 = MODE pin selects 2-wire mode when low and 3-wire mode when high. 1 = Interface operates in 3-wire mode regardless of the MODE pin. MODE can be an input or output under the control of the GPIO control register. Table 67 MODE Pin Function Control 3-WIRE CONTROL MODE 3-wire mode uses the CSB, SCLK and SDIN pins on the WM8900. In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on CSB/GPIO latches in a complete control word consisting of the last 16 bits. In 3-wire mode, the data comprises 24 bits in total. The first bit is the read/write (R/W) bit. This is followed by 7 address bits (A6 to A0), which identify the register to be accessed. The remaining 16 bits (B15 to B0) are data bits, corresponding to the 16 bits in the WM8900 register. The following timing diagram shows the supported read and write implementation in 3 wire mode.
Figure 47 3-Wire Serial Control Timing
w
PD, August 2008, Rev 4.0 84
Production Data
WM8900
The same sequence applies to both Read and Write operations. The only difference is that the data bits are driven by the controlling device in Write mode, and by the WM8900 in Read mode. The R/W bit is set to 0 for Write operations and is set to 1 for Read operations. Register Read operations are only supported from a limited set of registers, as described in Table 68. REGISTER ADDRESS R0 (00h) Reset R1 (01h) Power Management 1 BIT 15:0 15:12 LABEL SW_RESET_ CHIP_ID CHIP_REV [3:0] DEFAULT DESCRIPTION CHIP ID 16 data bits DEVICE_REVISON 4 data bits
Table 68 Readback Registers
2-WIRE SERIAL CONTROL MODE The WM8900 supports software control via a 2-wire serial bus. 2-wire mode uses the SCLK and SDIN pins only. Many devices can be controlled by the same bus, and each device has a unique 7bit device address (this is not the same as the 7-bit address of each register in the WM8900). To allow arbitration of multiple slaves (and/or multiple masters) on the same interface, the WM8900 transmits logic 1 by tri-stating the SDIN pin, rather than by pulling it high. An external pull-up resistor is required to pull the SDIN line high so that the logic 1 can be recognised by the master. The device address of the WM8900 can be one of two values and is determined by the CSB input pin when the device is powered up, as described in Table 69. An internal pull-down causes default selection of the device address. After CSB is sampled on power up, it reverts to a GPIO function and is not used in 2 wire mode. CSB Low (default) High DEVICE ADDRESS 0011010 0011011
Table 69 2-Wire Interface Device Address Selection The WM8900 operates as a slave device only. The controller indicates the START of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the START condition and shift in the next eight bits on SDIN (7-bit address, MSB first + Read/Write bit = 0). Hence the first byte should equal 0x34 or 0x36. If the device address received matches the address of the WM8900 (configured by the CSB pin on power up), then the WM8900 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised, the WM8900 returns to the idle condition and waits for a new start condition and valid device address. During a write, once the WM8900 has acknowledged a correct device address, the controller sends the WM8900 register address (MSB first). The WM8900 then acknowledges the register address byte by pulling SDIN low for one clock pulse. The controller then sends bits 15-8 of register data (MSB first), and the WM8900 acknowledges again by pulling SDIN low for one clock pulse. The controller then sends bits 7-0 of register data (MSB first), and the WM8900 acknowledges again by pulling SDIN low for one clock pulse. Transfers are complete when there is a low to high transition on SDIN while SCLK is high (STOP). After a complete sequence the WM8900 returns to the idle state and waits for another start condition. If a START or STOP condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
Figure 48 2-Wire Serial Control Interface Writes
w
PD, August 2008, Rev 4.0 85
WM8900
Production Data
In 2-wire mode, Auto-Incremental Write operations are supported. In this type of transfer, additional bytes of data (B15-B8 and B7-B0) are transmitted in sequence without the need to re-transmit the device address or register address. The WM8900 automatically increments the register address for each additional set of data bits received. This continues until the controlling device indicates the transfer is complete by a rising edge on SDIN while SCLK is held high. Auto-Incremental Writes are enabled by default; this can be set by the user as described in Table 70. REGISTER ADDRESS R18 (12h) GPIO Control BIT 15 LABEL AUTO_INC DEFAULT 1 DESCRIPTION Auto-Incremental write enable 0 = Auto-Incremental writes disabled 1 = Auto-Incremental writes enabled Enables the CSB Pull-Down resistor 0 = CSB Pull-Down disabled 1 = CSB Pull-Down enabled Table 70 2-Wire Interface Control
13
CSB_PD_ENA
1
READBACK IN 2-WIRE MODE
Readback is supported from the registers listed in Table 68. The controller indicates the START of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2wire bus respond to the START condition and shift in the next eight bits on SDIN (7-bit address, MSB first + Read/Write bit = 0). Hence the first byte should equal 0x34 or 0x36. If the device address received matches the address of the WM8900 (configured by the CSB pin on power up), then the WM8900 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised the WM8900 returns to the idle condition and waits for a new start condition and valid device address. During a read, once the WM8900 has acknowledged a correct device address, the controller sends the WM8900 register address (MSB first). The WM8900 then acknowledges the register address byte by pulling SDIN low for one clock pulse. The controller then issues a repeated START with a high to low transition on SDIN while SCLK remains high. The controller then sends the WM8900 device read address (7-bit address, MSB first + Read/Write bit = 1). Hence this byte should equal 0x35 or 0x37. If the device address received matches the address of the WM8900 (configured by the CSB pin on power up), then the WM8900 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised the WM8900 returns to the idle condition and waits for a new start condition and valid device address. During the next 9 SCLK cycles from the controller, WM8900 clocks out register data (bits 15-8, MSB first) on the first 8 cycles, and on the 9th cycle, the controller responds by pulling SDIN low. During the next 9 SCLK cycles from the controller, WM8900 clocks out register data (bits 7-0, MSB first) on the first 8 cycles, and on the 9th SCLK cycle, the controller responds by pulling SDIN low. Transfers are complete when there is a low to high transition on SDIN while SCLK is high (STOP). After a complete sequence the WM8900 returns to the idle state and waits for another start condition. If a START or STOP condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
Figure 49 2-Wire Serial Control Interface Reads
w
PD, August 2008, Rev 4.0 86
Production Data
WM8900
RESETTING THE CHIP
The WM8900 can be reset by performing a write of any value to the software reset register (address 00h). This will cause all register values to be reset to their default values. In addition to this there is a Power-On Reset (POR) circuit which ensures that the registers are set to default when the device is powered up.
REGISTER ADDRESS R0 (00h) Reset
BIT 15:0
LABEL SW_RESET_ CHIP_ID
DEFAULT
DESCRIPTION Read: CHIP ID (0x8900) Write: Software Reset
Table 71 Software Reset Register
POWER MANAGEMENT
The WM8900 has three control registers that allow users to select which functions are active. For minimum power consumption, unused functions should be disabled and bias currents set to the recommended values. To avoid any pop or click noise, it is important to enable or disable functions in the correct order (see "Applications Information"). VMID_MODE is the enable for the Vmid reference, which defaults to disabled and can be enabled as a 2x50k potential divider or, for low power maintenance of Vref when all other blocks are disabled, as a 2x250k potential divider. REGISTER ADDRESS R1 (01h) Power Management 1 BIT 8 LABEL STARTUP_BIAS_ENA DEFAULT 0 DESCRIPTION Bias Startup control. Normally 0 but can be temporarily set to one during startup to minimise pops and clicks. FLL Digital Enable 0 = Power down 1 = Power up FLL_OSC_ENA must be enabled before enabling FLL_ENA. The order is important. 4 MICB_ENA 0 Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON VREF (necessary for all analogue functions) 0 = Power down 1 = Power up 2 VMID_BUF_ENA 0 Provides VMID to input and output analogue pins when not enabled. Normally 0 but can be temporarily set to one during startup to minimise pops and clicks. VMID Divider Enable and Select 00 = VMID disabled (for OFF mode) 01 = 2 x 50k divider (Normal mode) 10 = 2 x 250k divider (Standby mode) 11 = 2 x 5k divider (for fast start-up) Master Clock Disable 0 = Master clock disabled 1 = Master clock enabled Left LINEOUT1 Output Buffer 0 = Power down 1 = Power up
6
FLL_ENA
0
3
BIAS_ENA
0
1:0
VMID_MODE [1:0]
00
R2 (02h) Power Management 2
15
SYSCLK_ENA
0
8
OUT1L_ENA
0
w
PD, August 2008, Rev 4.0 87
WM8900
REGISTER ADDRESS BIT 7 LABEL OUT1R_ENA DEFAULT 0
Production Data
DESCRIPTION Right LINEOUT1 Output Buffer 0 = Power down 1 = Power up Left channel input boost enable 0 = Boost disabled 1 = Boost enabled Right channel input boost enable 0 = Boost disabled 1 = Boost enabled Left channel input PGA enable 0 = PGA disabled 1 = PGA enabled (if MIXINL_ENA = 1) Right channel input PGA enable 0 = PGA disabled 1 = PGA enabled (if MIXINR_ENA = 1) Enable ADC left channel: 0 = ADC disabled 1 = ADC enabled Enable ADC right channel: 0 = ADC disabled 1 = ADC enabled Charge Pump Enable 0: Disable charge pump 1: Enable charge pump Must be enabled when the headphone output is used. Left LINEOUT2 Output Buffer 0 = Power down 1 = Power up Right LINEOUT2 Output Buffer 0 = Power down 1 = Power up Left output mixer enable 0 = Mixer disabled 1 = Mixer enabled Right output mixer enable 0 = Mixer disabled 1 = Mixer enabled Left DAC Enable 0 = DAC disabled 1 = DAC enabled Right DAC Enable 0 = DAC disabled 1 = DAC enabled
5
MIXINL_ENA
0
4
MIXINR_ENA
0
3
INL_ENA
0
2
INR_ENA
0
1
ADCL_ENA
0
0
ADCR_ENA
0
R3 (03h) Power Management 3
7
CP_ENA
0
6
OUT2L_ENA
0
5
OUT2R_ENA
0
3
MIXOUTL_ENA
0
2
MIXOUTR_ENA
0
1
DACL_ENA
0
0
DACR_ENA
0
Table 72 Power Management
w
PD, August 2008, Rev 4.0 88
Production Data
WM8900
STOPPING THE MASTER CLOCK
In order to minimise power consumed in the digital core of the WM8900, the master clock may be stopped in Standby and OFF modes. If this cannot be done externally at the clock source, the SYSCLK_ENA bit (R2, bit 15) can be set to stop the MCLK signal from propagating into the device core. In Standby mode, setting SYSCLK_ENA will typically provide an additional power saving on DCVDD of 20uA. However, since setting SYSCLK_ENA has no effect on the power consumption of other system components external to the WM8900, it is preferable to disable the master clock at its source wherever possible. Figure 46 on page 76 shows the clock distribution within WM8900. MCLK should not be stopped while the Headphone outputs are enabled, as this would prevent the charge pump from functioning.
REGISTER ADDRESS R2 (02h) Power Management 2
BIT 15
LABEL SYSCLK_ENA 0
DEFAULT
DESCRIPTION Master clock disable 0 = Master clock disabled 1 = Master clock enabled
Table 73 Stopping the Master Clock Note: Before SYSCLK_ENA can be set, the control bits ADCL_ENA, ADCR_ENA, DACL_ENA and DACR_ENA must be set to zero and a waiting time of 1ms must be observed. Any failure to follow this procedure may prevent DACs and ADCs from re-starting correctly.
w
PD, August 2008, Rev 4.0 89
WM8900 REGISTER MAP
REG R0 (0h) R1 (1h) NAME RESET PWR MGMT (1) CHIP_REV[3:0] 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Production Data
0
DEFAULT 8900h
SW_RESET_CHIP_ID[15:0] 0 START UP_BI AS_EN A 0 FLL_E NA 0
MICB_ BIAS_ VMID_ VMID_MODE[1: 2000h ENA ENA BUF_E 0] NA
R2 (2h) R3 (3h) R4 (4h)
PWR MGMT (2) SYSCL K_ENA PWR MGMT (3) 0
1 0
0 0
0 0
0 0
0 0
0 0
OUtT1 OUT1R L_ENA _ENA
0
MIXINL MIXIN INL_E INR_E ADCL_ ADCR_ C000h _ENA R_ENA NA NA ENA ENA 0 MIXOU MIXOU DACL_ DACR_ 0000h TL_EN TR_EN ENA ENA A A 0 0 0 4050h
OUT1_ CP_EN OUT2L OUT2R FB_EN A _ENA _ENA A AIF_B AIF_LR CLK_I CLK_I NV NV 0 0 AIF_WL[1:0]
AUDIO AIFAD AIFAD AIFAD AIFAD INTERFACE (1) CL_SR CR_SR C_TD C_TD C C M M_CH AN
0
0
0
AIF_FMT[1:0]
R5 (5h)
AUDIO DACL_ DACR_ AIFDA AIFDA DAC_BOOST[1: INTERFACE (2) SRC SRC C_TD C_TD 0] M M_CH AN CLOCKING (1) CLOCKING (2) AUDIO INTERFACE (3) AUDIO INTERFACE (4) DAC CTRL 0 0 0 0 0 OPCLK_DIV[2:0] 0 0 0 0 0 0 0 0 AIF_T RI 0 0 DAC_S DMCL K_RAT E 0 0 0 ADCLR C_DIR DACLR C_DIR 0 0 0
0
ADCLR C_FN
0
DAC_C DAC_C ADC_C ADC_C LOOP OMP OMPM OMP OMPM BACK ODE ODE BCLK_DIV[3:0] DAC_CLKDIV[2:0]
4000h
R6 (6h) R7 (7h) R8 (8h) R9 (9h) R10 (Ah)
0 0
MCLK_ SRC 0
0
0
0
BCLK_ 0008h DIR TOCLK TOCLK 0000h _RATE _ENA 0040h 0040h
ADC_CLKDIV[2:0]
ADCLRC_RATE[10:0] DACLRC_RATE[10:0] AIF_LR DAC_ DAC_S DAC_ DAC_ CLKRA MONO B_FILT MUTE MUTE RATE MODE TE 0 0 DAC_V U DAC_V U ADCR_DAC_SVOL[3:0] 0 ADC_H PF_EN A ADC_V U ADC_V U 0 JD_EN JD_MO ADCLR A DE C_INV 0 0 0 0 MICB_ LVL 0 0 ADCLRC_SRC[2:0] 0 ADC_HPF_CUT [1:0] DEEMP[1:0] 0
DAC_ DACL_ DACR_ 1004h MUTE DATIN DATIN V V 00C0h
R11 (Bh) R12 (Ch) R13 (Dh) R14 (Eh) R15 (Fh) R16 (10h)
LEFT DAC DIGITAL VOLUME RIGHT DAC DIGITAL VOLUME DIGITAL SIDE TONE ADC CTRL
0
0
0
0
DACL_VOL[7:0]
0
0
0
0
0
0
0
DACR_VOL[7:0]
00C0h
0 0
0 0
0 0 0
ADCL_DAC_SVOL[3:0] 0 0
0 0
ADC_TO_DACL ADC_TO_DAC [1:0] R[1:0] 0 0
0000h
ADCL_ ADCR_ 0100h DATIN DATIN V V 00C0h
LEFT ADC DIGITAL VOLUME RIGHT ADC DIGITAL VOLUME
0
0
0
0
0
0
0
ADCL_VOL[7:0]
0
0
0
0
0
0
0
ADCR_VOL[7:0]
00C0h
R17 JACK DETECT (11h) CTRL R18 (12h) R21 (15h) R22 (16h) R23 (17h) R24 GPIOCTRL
0 AUTO_ INC 0 0 0 0
0 0
JD_EN1[5:0] CSB_P MODE MODE D_ENA _PU_E _FN NA 0 0 0 0 0 0 0 0 0 0 0 0 0
JD_EN0[5:0] JD_SRC[2:0]
0000h TEMP_ B001h ENA 0044h 004Ch 004Ch 0044h
INPUT CTRL LEFT INPUT VOLUME RIGHT INPUT VOLUME INPUT BOOST
0 0 0 0
0 0 0 0
IN1L_E IN2L_E IN3L_E NA NA NA 0 0
0
IN1R_ IN2R_ IN3R_ ENA ENA ENA INL_VOL[4:0] INR_VOL[4:0]
IN_VU INL_Z INL_M C UTE IN_VU INR_Z INR_M C UTE 0 0
IN3L_BOOST[2:0]
0
IN2L_BOOST[2:0]
w
PD, August 2008, Rev 4.0 90
Production Data
WM8900
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT
REG (18h)
NAME MIXER (1)
R25 INPUT BOOST (19h) MIXER (2) R26 (1Ah) R27 (1Bh) R30 (1Eh) R36 (24h) R37 (25h) R38 (26h) R39 (27h) R40 (28h) R41 (29h) ADC SIGNAL PATH AUX BOOST ADDITIONAL CTRL FLL 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
IN3R_BOOST[2:0] INL_T INL_MIXINL_B O_MIXI OOST[1:0] NL IN4L_BOOST[2:0] 0
0 0
IN2R_BOOST[2:0]
0044h
INR_T INR_MIXINR_B 0000h O_MIXI OOST[1:0] NR IN4R_BOOST[2:0] 0 TEMP_ VROI SD 0044h 0002h
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0
0
0
OUT1_ OUT2_ DIS DIS FLL_O SC_EN A FLL_F RACN_ ENA 0 0
VMID_ BIAS_ VMID_ DISCH SRC SOFTS T 0
0
0
0
0
0
0
0
0
FLL_FRATIO[4:0]
0008h
FLL 2
0
0
0
0
0
0
0
FLL_K[7:0]
0000h
FLL 3 FLL 4 FLL 5 FLL 6
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
FLL_K[7:0] DF_GAIN[3:0] FLL_N[4:0] 0 0 0 0 FLL_N[4:0] 0 0 0
0000h 000Bh 0097h 0100h
FLL_CLKDIV[2:0] FLL_S LRCLK LOW_L _REF_ OCK_ ENA REF 0
R44 (2Ch) R45 (2Dh)
LEFT OUT MIXER CTRL (1) RIGHT OUT MIXER CTRL (1) BYPASS (1)
0
0
0
0
0
0
0
DACL_ IN3L_T IN3L_MIXOUTL_VOL[2: TO_MI O_MIX 0] XOUTL OUTL DACR_ IN3R_ IN3R_MIXOUTR_VOL[2: TO_MI TO_MI 0] XOUT XOUT R R 0
0
0
0
0
0050h
0
0
0
0
0
0
0
0
0
0
0
0050h
R46 (2Eh)
0
0
0
0
0
0
0
MIXINL MIXINL_MIXOUTL_VOL[ MIXINL MIXINL_MIXOUTR_VOL 0055h _TO_M 2:0] _TO_M [2:0] IXOUT IXOUT L R MIXIN MIXINR_MIXOUTR_VOL MIXIN MIXINR_MIXOUTL_VOL 0055h R_TO_ [2:0] R_TO_ [2:0] MIXOU MIXOU TR TL IN4_T IN4_MIXOUTL_VOL[2:0] IN4_T IN4_MIXOUTR_VOL[2:0] 0055h O_MIX O_MIX OUTR OUTL OUT1L_VOL[5:0] OUT1R_VOL[5:0] OUT2L_VOL[5:0] OUT2R_VOL[5:0] 0079h 0079h 0079h 0079h
R47 (2Fh)
BYPASS (2)
0
0
0
0
0
0
0
0
R48 AUX TO MIXER OUT CTRL (30h) R51 (33h) R52 (34h) R53 (35h) R54 (36h) LEFT OUT1 CTRL RIGHT OUT1 CTRL LEFT OUT2 CTRL RIGHT OUT2 CTRL
0
0
0
0
0
0
0
0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
OUT1_ OUT1L OUT1L VU _ZC _MUTE OUT1_ OUT1R OUT1R VU _ZC _MUTE OUT2_ OUT2L OUT2L VU _ZC _MUTE OUT2_ OUT2R OUT2R VU _ZC _MUTE
R58 (3Ah) R115 (73h)
HEADPHONE CTRL 1 OUTPUT BIAS CTRL
0
0
0
0
0
0
0
0
HP_IP HP_OP HP_CL HP_CL HP_SH HP_SH HP_BIAS[1:0] STAGE STAGE AMP_I AMP_ ORT ORT2 _ENA _ENA P OP 0 0 0 0 0 0 0 0 DAC_BIAS[1:0] 0 0 0 0
0000h
0 0
0 0
0 0
0 0
0 0
0 0
0 0
MIXOUT_BIAS[ 1:0] MASTER_BIAS[ 1:0]
0000h 0100h
R116 MASTER BIAS (74h) CTRL
w
PD, August 2008, Rev 4.0 91
WM8900
Production Data
REGISTER ADDRESS R0 (00h) Reset R1 (01h) Power Management 1
BIT 15:0 15:12 8
LABEL SW_RESET_CHIP_ID CHIP_REV [3:0] STARTUP_BIAS_ENA
DEFAULT
DESCRIPTION Read: CHIP ID (0x8900) Write: Software Reset DEVICE_REVISON 4 data bits
0
Bias Startup control. Normally 0 but can be temporarily set to one during startup to minimise pops and clicks. FLL Digital Enable 0 = Power down 1 = Power up FLL_OSC_ENA must be enabled before enabling FLL_ENA. The order is important.
6
FLL_ENA
0
4
MICB_ENA
0
Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON VREF (necessary for all analogue functions) 0 = Power down 1 = Power up Provides VMID to input and output analogue pins when not enabled. Normally 0 but can be temporarily set to one during startup to minimise pops and clicks. VMID Divider Enable and Select 00 = VMID disabled (for OFF mode) 01 = 2 x 50k divider (Normal mode) 10 = 2 x 250k divider (Standby mode) 11 = 2 x 5k divider (for fast start-up) Master Clock Disable 0 = Master clock disabled 1 = Master clock enabled Left channel LINEOUT1 enable 0 = LINEOUT_1L disabled 1 = LINEOUT_1L enabled Right channel LINEOUT1 enable 0 = LINEOUT_1R disabled 1 = LINEOUT_1R enabled Left channel input boost enable 0 = Boost disabled 1 = Boost enabled Right channel input boost enable 0 = Boost disabled 1 = Boost enabled Left channel input PGA enable 0 = PGA disabled 1 = PGA enabled (if MIXINL_ENA = 1) Right channel input PGA enable 0 = PGA disabled 1 = PGA enabled (if MIXINR_ENA = 1) Enable ADC left channel: 0 = ADC disabled 1 = ADC enabled
3
BIAS_ENA
0
2
VMID_BUF_ENA
0
1:0
VMID_MODE [1:0]
00
R2 (02h) Power Management 2
15
SYSCLK_ENA
0
8
OUT1L_ENA
0
7
OUT1R_ENA
0
5
MIXINL_ENA
0
4
MIXINR_ENA
0
3
INL_ENA
0
2
INR_ENA
0
1
ADCL_ENA
0
w
PD, August 2008, Rev 4.0 92
Production Data
WM8900
BIT 0 LABEL ADCR_ENA DEFAULT 0 DESCRIPTION Enable ADC right channel: 0 = ADC disabled 1 = ADC enabled Common mode feedback for Lineout1 0: Disable common mode feedback 1: Enable common mode feedback Charge Pump Enable 0 = Disable charge pump 1 = Enable charge pump Must be enabled when the headphone output is used. Left channel LINEOUT2 enable 0 = LINEOUT_2L disabled 1 = LINEOUT_2L enabled Right channel LINEOUT2 enable 0 = LINEOUT_2R disabled 1 = LINEOUT_2R enabled Left output mixer enable 0 = Mixer disabled 1 = Mixer enabled Right output mixer enable 0 = Mixer disabled 1 = Mixer enabled Left DAC Enable 0 = DAC disabled 1 = DAC enabled Right DAC Enable 0 = DAC disabled 1 = DAC enabled Left Digital Audio channel source 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel Right Digital Audio channel source 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel ADC TDM Enable 0 = Normal ADCDAT operation 1 = TDM enabled on ADCDAT ADCDAT TDM Channel Select 0 = ADCDAT outputs data on slot 0 1 = ADCDAT output data on slot 1 BCLK Invert 0 = BCLK not inverted 1 = BCLK inverted Right, left and I2S modes - LRCLK polarity 0 = normal LRCLK polarity 1 = invert LRCLK polarity DSP Mode - mode A/B select 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B)
REGISTER ADDRESS
R3 (03h) Power Management 3
8
OUT1_FB_ENA
0
7
CP_ENA
0
6
OUT2L_ENA
0
5
OUT2R_ENA
0
3
MIXOUTL_ENA
0
2
MIXOUTR_ENA
0
1
DACL_ENA
0
0
DACR_ENA
0
R4 (04h) Audio Interface 1
15
AIFADCL_SRC
0
14
AIFADCR_SRC
1
13
AIFADC_TDM
0
12
AIFADC_TDM_CHAN
0
8
AIF_BCLK_INV
0
7
AIF_LRCLK_INV
0
w
PD, August 2008, Rev 4.0 93
WM8900
REGISTER ADDRESS BIT 6:5 AIF_WL [1:0] LABEL DEFAULT 10 DESCRIPTION
Production Data
Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits Digital Audio Interface Format 00 = Right justified 01 = Left justified 10 = I2S Format 11 = DSP Mode Left DAC Data Source Select 0 = Left DAC outputs left channel data 1 = Left DAC outputs right channel data Right DAC Data Source Select 0 = Right DAC outputs left channel data 1 = Right DAC outputs right channel data DAC TDM Enable 0 = Normal DACDAT operation 1 = TDM enabled on DACDAT DACDAT TDM Channel Select 0 = DACDAT data input on slot 0 1 = DACDAT data input on slot 1 DAC Input Volume Boost 00 = 0dB 01 = +6dB (Input data must not exceed -6dBFS) 10 = +12dB (Input data must not exceed -12dBFS) 11 = +18dB (Input data must not exceed -18dBFS) ADCLRC/GPIO Pin Function Select 0 = ADCLRC frame clock for ADC 1 = GPIO pin DAC Companding enable 0 = off 1 = on DAC Companding mode select: 0 = -law 1 = A-law ADC Companding enable 0 = off 1 = on ADC Companding mode select: 0 = -law 1 = A-law Digital Loopback Function 0 = No loopback. 1 = Loopback enabled, ADC data output is fed directly into DAC data input.
4:3
AIF_FMT [1:0]
10
R5 (05h) Audio Interface 2
15
DACL_SRC
0
14
DACR_SRC
1
13
AIFDAC_TDM
0
12
AIFDAC_TDM_CHAN
0
11:10
DAC_BOOST [1:0]
00
6
ADCLRC_FN
0
4
DAC_COMP
0
3
DAC_COMPMODE
0
2
ADC_COMP
0
1
ADC_COMPMODE
0
0
LOOPBACK
0
w
PD, August 2008, Rev 4.0 94
Production Data
WM8900
BIT 14:12 LABEL OPCLK_DIV [2:0] DEFAULT 000 DESCRIPTION OPCLK Frequency (GPIO function) 000 = SYSCLK 001 = SYSCLK / 2 010 = SYSCLK / 3 011 = SYSCLK / 4 100 = SYSCLK / 5.5 101 = SYSCLK / 6 110 = Reserved 111 = Reserved Clock Source selection 0 = SYSCLK derived from MCLK 1 = SYSCLK derived from FLL output BCLK Frequency (Master Mode) 0000 = SYSCLK 0001 = SYSCLK / 1.5 0010 = SYSCLK / 2 0011 = SYSCLK / 3 0100 = SYSCLK / 4 0101 = SYSCLK / 5.5 0110 = SYSCLK / 6 0111 = SYSCLK / 8 1000 = SYSCLK / 11 1001 = SYSCLK / 12 1010 = SYSCLK / 16 1011 = SYSCLK / 22 1100 = SYSCLK / 24 1101 = SYSCLK / 32 1110 = SYSCLK / 44 1111 = SYSCLK / 48 BCLK Direction 0 = BCLK is input 1 = BCLK is output Tri-states ADCDAT and switches ADCLRC, DACLRC and BCLK to inputs. 0 = ADCDAT is an output; DACLRC and BCLK may be inputs or outputs; ADCLRC is input, output or GPIO. 1 = ADCDAT is tri-stated; DACLRC and BCLK are inputs; ADCLRC is input or GPIO. ADC Sample rate divider 000 = SYSCLK / 1.0 001 = SYSCLK / 1.5 010 = SYSCLK / 2 011 = SYSCLK / 3 100 = SYSCLK / 4 101 = SYSCLK / 5.5 110 = SYSCLK / 6 111 = Reserved
REGISTER ADDRESS R6 (06h) Clocking 1
8
MCLK_SRC
0
4:1
BCLK_DIV [3:0]
0000
0
BCLK_DIR
0
R7 (07h) Clocking 2
12
AIF_TRI
0
7:5
ADC_CLKDIV [2:0]
000
w
PD, August 2008, Rev 4.0 95
WM8900
REGISTER ADDRESS BIT 4:2 LABEL DAC_CLKDIV [2:0] DEFAULT 000 DESCRIPTION DAC Sample rate divider 000 = SYSCLK / 1.0 001 = SYSCLK / 1.5 010 = SYSCLK / 2 011 = SYSCLK / 3 100 = SYSCLK / 4 101 = SYSCLK / 5.5 110 = SYSCLK / 6 111 = Reserved
Production Data
1
TOCLK_RATE
0
Slow Clock Selection (Used for volume update timeouts and for jack detect debounce) 0 = SYSCLK / 221 (Slower Response) 1 = SYSCLK / 219 (Faster Response)
0
TOCLK_ENA
0
Slow Clock Enable (Must be enabled for jack detect de-bounce) 0 = Slow Clock Disabled 1 = Slow Clock Enabled ADCLRC Direction 0 = ADCLRC is input 1 = ADCLRC is output ADCLRC Frequency (Master Mode). BCLK is divided by this integer. ADCLRC_RATE is an 11-bit integer (LSB = 1). Valid range is 8 .. 2047
R8 (08h) Audio Interface 3
11
ADCLRC_DIR
0
10:0
ADCLRC_RATE [10:0]
040h
R9 (09h) Audio Interface 4
11
DACLRC_DIR
0
DACLRC Direction 0 = DACLRC is input 1 = DACLRC is output DACLRC Frequency (Master Mode). BCLK is divided by this integer. DACLRC_RATE is an 11-bit integer (LSB = 1). Valid range is 8 .. 2047
10:0
DACLRC_RATE [10:0]
040h
R10 (0Ah) DAC Control
12
DAC_SDMCLK_RATE
1
DAC sigma delta modulator clock 0 = DAC clock scales with sample rate 1 = DAC clock independent of sample rate Mode Select 1 = USB mode (272 * Fs) 0 = Normal mode (256 * Fs) DAC Mono Mix 0 = Stereo 1 = Mono (Mono mix output on enabled DACs) Selects DAC filter characteristics 0 = Normal mode 1 = Sloping stopband mode DAC Soft Mute Ramp Rate 0 = Fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48k) 1 = Slow ramp (fs/32, maximum ramp time is 171ms at fs=48k)
10
AIF_LRCLKRATE
0
9
DAC_MONO
0
8
DAC_SB_FILT
0
7
DAC_MUTERATE
0
w
PD, August 2008, Rev 4.0 96
Production Data
WM8900
BIT 6 LABEL DAC_MUTEMODE DEFAULT 0 DESCRIPTION DAC Soft Mute and Un-mute Mode 0 = Disabling soft-mute (DAC_MUTE=0) will cause the DAC volume to change immediately to DACL_VOL and DACR_VOL settings or change to digital mute level immediately 1 = Enabling soft-mute (DAC_MUTE=0) will cause the DAC volume to ramp up gradually to the DACL_VOL and DACR_VOL settings or gradually ramp down to digital mute level De-Emphasis Control 11 = 48kHz sample rate 10 = 44.1kHz sample rate 01 = 32kHz sample rate 00 = No de-emphasis DAC Soft Mute Control 0 = DAC Un-mute 1 = DAC Mute Left DAC Invert 0 = Left DAC output not inverted 1 = Left DAC output inverted Right DAC Invert 0 = Right DAC output not inverted 1 = Right DAC output inverted DAC Volume Update Writing a 1 to this bit will cause left and right DAC volume to be updated simultaneously Left DAC Digital Volume (See Table 29 for volume range) DAC Volume Update Writing a 1 to this bit will cause left and right DAC volume to be updated simultaneously Right DAC Digital Volume (See Table 29 for volume range) Left Digital Sidetone Volume (See Table 26 for volume range) Right Digital Sidetone Volume (See Table 26 for volume range) Left DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = Reserved Right DAC Digital Sidetone Source 00 = No sidetone 01 = Left ADC 10 = Right ADC 11 = Reserved
REGISTER ADDRESS
5:4
DEEMP [1:0]
00
2
DAC_MUTE
1
1
DACL_DATINV
0
0
DACR_DATINV
0
R11 (0Bh) Left DAC Digital Volume
8
DAC_VU
0
7:0 R12 (0Ch) Right DAC Digital Volume 8
DACL_VOL [7:0] DAC_VU
11000000 (0dB) 0
7:0 R13 (0Dh) Digital Sidetone 12:9 8:5 3:2
DACR_VOL [7:0] ADCL_DAC_SVOL [3:0] ADCR_DAC_SVOL [3:0] ADC_TO_DACL [1:0]
11000000 (0dB) 0000 0000 00
1:0
ADC_TO_DACR [1:0]
00
w
PD, August 2008, Rev 4.0 97
WM8900
REGISTER ADDRESS R14 (0Eh) ADC Control BIT 8 LABEL ADC_HPF_ENA DEFAULT 1 DESCRIPTION
Production Data
ADC Digital High Pass Filter Enable 0 = disabled 1 = enabled ADC Digital High Pass Filter Cut-Off Frequency (fc) 00 = Hi-fi mode (fc=4Hz at fs=48kHz) 01 = Voice mode 1 (fc=127Hz at fs=16kHz) 10 = Voice mode 2 (fc=130Hz at fs=8kHz) 11 = Voice mode 3 (fc=267Hz at fs=8kHz) (Note: fc scales with sample rate. See Table 21 for cut-off frequencies at all supported sample rates.)
6:5
ADC_HPF_CUT [1:0]
00
1
ADCL_DATINV
0
Left ADC Invert 0 = Left ADC output not inverted 1 = Left ADC output inverted Right ADC Invert 0 = Right ADC output not inverted 1 = Right ADC output inverted ADC Volume Update Writing a 1 to this bit will cause left and right ADC volume to be updated simultaneously Left ADC Digital Volume (See Table 19 for volume range) ADC Volume Update Writing a 1 to this bit will cause left and right ADC volume to be updated simultaneously Right ADC Digital Volume (See Table 19 for volume range) Output enables when selected jack detection input is logic 1 JD_EN1[0] =1 enables LINEOUT_1L JD_EN1[1] =1 enables LINEOUT_1R JD_EN1[2] =1 enables LINEOUT_2R JD_EN1[3] =1 enables LINEOUT_2R JD_EN1[4] =1 enables Headphone JD_EN1[5] =1 enables Charge Pump
0
ADCR_DATINV
0
R15 (0Fh) Left ADC Digital Volume
8
ADC_VU
0
7:0 R16 (10h) Right ADC Digital Volume 8
ADCL_VOL [7:0] ADC_VU
1100 0000 (0dB) 0
7:0 R17 (11h) Jack Detect Control 13:8
ADCR_VOL [7:0] JD_EN1[5:0]
1100 0000 (0dB) 000000
5:0
JD_EN0[5:0]
000000
Output enables when selected jack detection input is logic 0 JD_EN0[0] =1 enables LINEOUT_1L JD_EN0[1] =1 enables LINEOUT_1R JD_EN0[2] =1 enables LINEOUT_2R JD_EN0[3] =1 enables LINEOUT_2R JD_EN0[4] =1 enables Headphone JD_EN0[5] =1 enables Charge Pump
R18 (12h) GPIO Control
15
AUTO_INC
1
Auto-Incremental write enable 0 = Auto-Incremental writes disabled 1 = Auto-Incremental writes enabled Enables the CSB Pull-Down resistor 0 = CSB Pull-Down disabled 1 = CSB Pull-Down enabled Enables the MODE Pull-Up resistor 0 = MODE Pull-Up disabled 1 = MODE Pull-Up enabled
13
CSB_PD_ENA
1
12
MODE_PU_ENA
1
w
PD, August 2008, Rev 4.0 98
Production Data
WM8900
BIT 11 LABEL MODE_FN DEFAULT 0 DESCRIPTION Selects Interface Control Mode 0 = MODE pin selects 2-wire mode when low and 3-wire mode when high. 1 = Interface operates in 3-wire mode regardless of the MODE pin. MODE can be an input or output under the control of the GPIO control register. 9 JD_ENA 0 Jack Detect Switch Enable 0 = Jack Detect disabled 1 = Jack Detect enabled Jack Detect Switch Polarity 0 = Jack Detect active high 1 = Jack Detect active low GPIO Output Polarity Invert 0 = Non inverted 1 = Inverted GPIO Pin Function Select: 000 = Jack detect input 001 = Reserved 010 = Temperature ok 011 = Debounced jack detect output 100 = SYSCLK output 101 = FLL lock 110 = Logic 0 111 = Logic 1 Jack Detect Input Select 000 = ADCLRC/GPIO used for jack detect 001 = CSB/GPIO used for jack detect 010 = LINPUT3/JD used for jack detect 011 = RINPUT3/JD used for jack detect 100 = MODE/GPIO used for jack detect 101 to 111 Reserved Temperature Sensor Enable 0 = Temperature sensor disabled 1 = Temperature sensor enabled Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.65 * AVDD Connect LINPUT1 to inverting input of Left Input PGA 0 = LINPUT1 not connected to PGA 1 = LINPUT1 connected to PGA 5 IN2L_ENA 0 Connect LINPUT2 to non-inverting input of Left Input PGA 0 = LINPUT2 not connected to PGA 1 = LINPUT2 connected to PGA 4 IN3L_ENA 0 Connect LINPUT3 to non-inverting input of Left Input PGA 0 = LINPUT3 not connected to PGA 1 = LINPUT3 connected to PGA 2 IN1R_ENA 1 Connect RINPUT1 to inverting input of Right Input PGA 0 = RINPUT1 not connected to PGA 1 = RINPUT1 connected to PGA
REGISTER ADDRESS
8
JD_MODE
0
7
ADCLRC_INV
0
6:4
ADCLRC_SRC [2:0]
000
3:1
JD_SRC[2:0]
000
0
TEMP_ENA
1
R21 (15h) Input Control
8
MICB_LVL
0
6
IN1L_ENA
1
w
PD, August 2008, Rev 4.0 99
WM8900
REGISTER ADDRESS BIT 1 LABEL IN2R_ENA DEFAULT 0 DESCRIPTION
Production Data
Connect RINPUT2 to non-inverting input of Right Input PGA 0 = RINPUT2 not connected to PGA 1 = RINPUT2 connected to PGA Connect RINPUT3 to non-inverting input of Right Input PGA 0 = RINPUT3 not connected to PGA 1 = RINPUT3 connected to PGA
0
IN3R_ENA
0
R22 (16h) Left Input Volume
8
IN_VU
0
Input PGA Volume Update Writing a 1 to this bit will cause left and right Input PGA volume to be updated simultaneously Left Input PGA Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately Left Input PGA Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: IN_VU must be set to un-mute. Left Input PGA Volume Control 11111 = +19dB 11110 = +18dB . . 1dB steps down to 00000 = -12dB Input PGA Volume Update Writing a 1 to this bit will cause left and right Input PGA volume to be updated simultaneously Right Input PGA Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately Right Input PGA Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: IN_VU must be set to un-mute. Right Input PGA Volume Control 11111 = +19dB 11110 = +18dB . . 1dB steps down to 00000 = -12dB LINPUT3 to Boost Gain 000 = -12dB ...6dB steps up to 011 = +6dB 1XX = Mute LINPUT2 to Boost Gain 000 = -12dB ...6dB steps up to 011 = +6dB 1XX = Mute
7
INL_ZC
0
6
INL_MUTE
1
4:0
INL_VOL [4:0]
01100 (0dB)
R23 (17h) Right Input Volume
8
IN_VU
0
7
INR_ZC
0
6
INR_MUTE
1
4:0
INR_VOL [4:0]
01100 (0dB)
R24 (18h) Input Boost Mixer 1
6:4
IN3L_BOOST [2:0]
100
2:0
IN2L_BOOST [2:0]
100
w
PD, August 2008, Rev 4.0 100
Production Data
WM8900
BIT 6:4 LABEL IN3R_BOOST [2:0] DEFAULT 100 DESCRIPTION RINPUT3 to Boost Gain 000 = -12dB ...6dB steps up to 011 = +6dB 1XX = Mute RINPUT2 to Boost Gain 000 = -12dB ...6dB steps up to 011 = +6dB 1XX = Mute Connect Left Input PGA to Left Input Boost mixer 0 = Not connected 1 = Connected 5:4 INL_MIXINL_BOOST [1:0] 00 Left Channel PGA Boost Gain 00 = +0dB 01 = +13dB 10 = +20dB 11 = +29dB Connect Right Input PGA to Right Input Boost mixer 0 = Not connected 1 = Connected Right Channel PGA Boost Gain 00 = +0dB 01 = +13dB 10 = +20dB 11 = +29dB AUX input to Boost Gain 000 = -12dB ...6dB steps up to 011 = +6dB 1XX = Mute AUX input to Boost Gain 000 = -12dB ...6dB steps up to 011 = +6dB 1XX = Mute 1 = Clamps LINEOUT_1L and LINEOUT_1R to GND via 8K resistance 0 = 8k resistance not connected to GND 1 = Clamps LINEOUT_2L and LINEOUT_2R to GND via 8K resistance 0 = 8k resistance not connected to GND 5 4 VMID_DISCH BIAS_SRC 0 0 Enables fast discharge of Vmid to GND Vmid bias select. Normally 0 but can be temporarily set to one during startup to select the soft-start Vmid source. Vmid soft-start control. Normally 0 but can be temporarily set to one during startup to ramp Vmid in a controlled manner. Thermal Shutdown Enable 0 = Thermal shutdown disabled 1 = Thermal shutdown enabled (TEMP_ENA must be enabled for this function to work) PD, August 2008, Rev 4.0 101
REGISTER ADDRESS R25 (19h) Input Boost Mixer 2
2:0
IN2R_BOOST [2:0]
100
R26 (1Ah) ADC Signal Path
6
INL_TO_MIXINL
0
2
INR_TO_MIXINR
0
1:0
INR_MIXINR_BOOST [1:0]
00
R27 (1Bh) Aux Boost
6:4
IN4L_BOOST [2:0]
100
2:0
IN4R_BOOST [2:0]
100
R30 (1Eh) Additional Control
8
OUT1_DIS
0
7
OUT2_DIS
0
3
VMID_SOFTST
0
1
TEMP_SD
1
w
WM8900
REGISTER ADDRESS BIT 0 VROI LABEL DEFAULT 0 DESCRIPTION
Production Data
VREF to Analogue Output Resistance (Disabled Outputs) 0 = 500 from buffered VMID to output 1 = 20k from buffered VMID to output Analogue enable 0 = FLL disabled 1 = FLL enabled FLL_OSC_ENA must be enabled before enabling FLL_ENA. The order is important.
R36 (24h) FLL Control 1
8
FLL_OSC_ENA
0
4:0
FLL_FRATIO [4:0]
8h
CLK_VCO is divided by this integer, valid from 1 .. 31. Value 1 recommended for Reference clock > 96kHz Value 8 recommended for Reference clock < 96kHz Fractional enable 0 = Integer Mode 1 = Fractional Mode (Fractional N mode increases digital power consumption of the FLL) Fractional multiply for CLK_REF (Most Significant Bits) Fractional multiply for CLK_REF (Least Significant Bits) Integer multiply for CLK_REF (Most Significant Bits) FOUT clock divider 000 = FVCO / 2 001 = FVCO / 4 010 = FVCO / 8 (best performance) 011 = FVCO / 16 100 = FVCO / 32 101 = Reserved 110 = Reserved 111 = Reserved Integer multiply for CLK_REF (Least Significant Bits) Low frequency reference locking 0 = Lock achieved after 509 ref clks (Recommended for Reference clock > 48kHz) 1 = Lock achieved after 49 ref clks (Recommended for Reference clock <= 48kHz) FLL reference clock input selector 0 = MCLK 1 = DACLRC Left DAC output to left output mixer 0 = not selected 1 = selected Left input 3 channel to left output mixer path 0 = not selected 1 = selected
R37 (25h) FLL Control 2
8
FLL_FRACN_ENA
0
7:0 R38 (26h) FLL Control 3 R39 (27h) FLL Control 4 R40 (28h) FLL Control 5 7:0 4:0 8:6
FLL_K [15:8] FLL_K [7:0] FLL_N [9:5] FLLCLK_DIV [2:0]
0h 0h 0Bh 3h
4:0 R41 (29h) FLL Control 6 8
FLL_N [4:0] FLL_SLOW_LOCK_R EF
17h 1
7
LRCLK_REF_ENA
0
R44 (2Ch) Left Output Mixer Control 1
8
DACL_TO_MIXOUTL
0
7
IN3L_TO_MIXOUTL
0
w
PD, August 2008, Rev 4.0 102
Production Data
WM8900
BIT 6:4 LABEL IN3L_MIXOUTL_VOL DEFAULT 101 DESCRIPTION Left input 3 channel to left output mixer path volume control (-15dB -> +6dB in 3dB steps) 000 = -15dB 101 = 0dB 111 = +6dB DAC Low power control: 0 = DAC low power path disabled 1 = DAC low power path enabled DAC Low power volume control: 0 = 0dB 1 = -12dB Right DAC output to right output mixer 0 = not selected 1 = selected Right input 3 channel to right output mixer path 0 = not selected 1 = selected Right input 3 channel to right output mixer path volume control (-15dB -> +6dB in 3dB steps) 000 = -15dB 101 = 0dB 111 = +6dB
REGISTER ADDRESS
1
DAC_LP
0
0
DAC_LP_VOL
0
R45 (2Dh) Right Output Mixer Control 1
8
DACR_TO_MIXOUTR
0
7
IN3R_TO_MIXOUTR
0
6:4
IN3R_MIXOUTR_VOL
101
R46 (2Eh) Bypass 1
7
MIXINL_TO_MIXOUT L
0
Left bypass path (from the Left channel ADC input) to left output mixer 0 = not selected 1 = selected Left bypass path to left output mixer path volume control (-15dB -> +6dB in 3dB steps) 000 = -15dB 101 = 0dB 111 = +6dB
6:4
MIXINL_MIXOUTL_V OL
101
3
MIXINL_TO_MIXOUT R
0
Left bypass path (from the Left channel ADC input) to right output mixer 0 = not selected 1 = selected Left bypass path to right output mixer path volume control (-15dB -> +6dB in 3dB steps) 000 = -15dB 101 = 0dB 111 = +6dB
2:0
MIXINL_MIXOUTR_V OL
101
R47 (2Fh) Bypass 2
7
MIXINR_TO_MIXOUT R
0
Right bypass path (from the Right channel ADC input) to right output mixer 0 = not selected 1 = selected Right bypass path to right output mixer path volume control (-15dB -> +6dB in 3dB steps) 000 = -15dB 101 = 0dB 111 = +6dB
6:4
MIXINR_MIXOUTR_V OL
101
w
PD, August 2008, Rev 4.0 103
WM8900
REGISTER ADDRESS BIT 3 LABEL MIXINR_TO_MIXOUT L DEFAULT 0 DESCRIPTION
Production Data
Right bypass path (from the Right channel ADC input) to left output mixer 0 = not selected 1 = selected Right bypass path to left output mixer path volume control (-15dB -> +6dB in 3dB steps) 000 = -15dB 101 = 0dB 111 = +6dB
2:0
MIXINR_MIXOUTL_V OL
101
R48 (30h) AUX to Mixer Output Control
7
IN4_TO_MIXOUTL
0
AUX input channel to left output mixer path 0 = not selected 1 = selected AUX input channel to left output mixer path volume control (-15dB -> +6dB in 3dB steps) 000 = -15dB 101 = 0dB 111 = +6dB
6:4
IN4_MIXOUTL_VOL
101
3
IN4_TO_MIXOUTR
0
AUX input channel to right output mixer path 0 = not selected 1 = selected
2:0
IN4_MIXOUTR_VOL
101
AUX input channel to right output mixer path volume control (-15dB -> +6dB in 3dB steps) 000 = -15dB 101 = 0dB 111 = +6dB
R51 (33h) Left OUT1 Control
8
OUT1_VU
0
Left Channel LINEOUT1 Volume Update Writing a 1 to this bit will cause left and right LINEOUT1 volume to be updated simultaneously Left Channel LINEOUT1 Zero Cross enable 0 = Change gain immediately 1 = Change gain on zero cross only Left Channel LINEOUT1 Mute 0 = LINEOUT_1L Unmuted 1 = LINEOUT_1L Mute Left Channel LINEOUT1 Volume Control (-57dB -> +6dB in 1dB steps) 111111 = +6dB 000000 = -57dB Left Channel LINEOUT1 Volume Update Writing a 1 to this bit will cause left and right LINEOUT1 volume to be updated simultaneously Left Channel LINEOUT1 Zero Cross enable 0 = Change gain immediately 1 = Change gain on zero cross only Left Channel LINEOUT1 Mute 0 = LINEOUT_1L Unmuted 1 = LINEOUT_1L Mute Left Channel LINEOUT1 Volume Control (-57dB -> +6dB in 1dB steps) 111111 = +6dB 000000 = -57dB
7
OUT1L_ZC
0
6
OUT1L_MUTE
1
5:0
OUT1L_VOL [5:0]
111001
R52 (34h) Right OUT1 Control
8
OUT1_VU
0
7
OUT1L_ZC
0
6
OUT1L_MUTE
1
5:0
OUT1L_VOL [5:0]
111001
w
PD, August 2008, Rev 4.0 104
Production Data
WM8900
BIT 8 LABEL OUT2_VU DEFAULT 0 DESCRIPTION Left Channel LINEOUT2 Volume Update Writing a 1 to this bit will cause left and right LINEOUT2 volume to be updated simultaneously Left Channel LINEOUT2 Zero Cross enable 0 = Change gain immediately 1 = Change gain on zero cross only Left Channel LINEOUT2 Mute 0 = LINEOUT_1L Unmuted 1 = LINEOUT_1L Mute Left Channel LINEOUT2 Volume Control (-57dB -> +6dB in 1dB steps) 111111 = +6dB 000000 = -57dB Right Channel LINEOUT2 Volume Update Writing a 1 to this bit will cause left and right LINEOUT2 volume to be updated simultaneously Right Channel LINEOUT2 Zero Cross enable 0 = Change gain immediately 1 = Change gain on zero cross only 6 OUT2R_MUTE 1 Right Channel LINEOUT2 Mute 0 = LINEOUT_1R Unmuted 1 = LINEOUT_1R Mute Right Channel LINEOUT2 Volume Control (-57dB -> +6dB in 1dB steps) 111111 = +6dB 000000 = -57dB Headphone input stage Enable 0 = Headphone input stage disabled 1 = Headphone input stage enabled Headphone output stage Enable 0 = Headphone output stage disabled 1 = Headphone output stage enabled Clamps HP_INL and HP_INR to GND Clamps HP_L and HP_R outputs to GND Shorts the inputs to the outputs Shorts the feedback resistor. 0 = Normal operation 1 = Shorts feedback resistor. About 20dB `mute' attenuation Adjusts output mixer bias 00 = Full bias 01 = Half bias (recommended) 10 = Reserved 11 = Reserved Adjusts DAC bias 00 = Full bias 01 = Half bias (recommended) 10 = Reserved 11 = Reserved Adjusts master bias 00 = Reserved 01 = 0.75 bias 10 = full bias - default 11 = Reserved
REGISTER ADDRESS R53 (35h) Left OUT2 Control
7
OUT2L_ZC
0
6
OUT2L_MUTE
1
5:0
OUT2L_VOL [5:0]
111001
R54 (36h) Right OUT2 Control
8
OUT2_VU
0
7
OUT2R_ZC
0
5:0
OUT2R_VOL [5:0]
111001
R58 (3Ah) Headphone Control 1
7
HP_IPSTAGE_ENA
0
6
HP_OPSTAGE_ENA
0
5 4 3 2
HP_CLAMP_IP HP_CLAMP_OP HP_SHORT HP_SHORT2
0 0 0 0
R115 (R73h) Output Bias Control
8:7
MIXOUT_BIAS
00
2:1
DAC_BIAS
00
R116 (R74h) Master Bias Control Master Bias Control
8:7
MASTER_BIAS
10
Table 74 Register Map Summary
w
PD, August 2008, Rev 4.0 105
WM8900 DIGITAL FILTER CHARACTERISTICS
PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation DAC Normal Filter Passband Passband Ripple Stopband Stopband Attenuation DAC Sloping Stopband Filter Passband +/- 0.03dB +/- 1dB -3dB Passband Ripple Stopband 1 Stopband 1 Attenuation Stopband 2 Stopband 2 Attenuation Stopband 3 Stopband 3 Attenuation F > 1.4 fs f > 0.7 fs f > 0.546 fs 0.25 fs 0.546 fs -60 0.7 fs -85 1.4 fs -55 1.4 fs 0 0.25 fs 0.5 fs +/- 0.03 0.7 fs 0.25 fs 0.454 fs F > 0.546 fs +/- 0.03dB -6dB 0.454 fs 0.546 fs -50 0 0.5 fs +/- 0.03 0.454 fs f > 0.546fs 0.546s -60 +/- 0.05dB -3dB 0 0.5fs +/- 0.05 0.454fs TEST CONDITIONS MIN TYP MAX
Production Data
UNIT
dB dB
dB dB
dB dB dB dB
DAC FILTERS Mode Normal Sloping Stopband Group Delay 18 / fs 18 / fs Mode Normal
ADC FILTERS Group Delay 18 / fs
w
PD, August 2008, Rev 4.0 106
Production Data
WM8900
ADC FILTER RESPONSES
10
Magnitude (dB): Passband Ripple
0 0.1 0.2 0.3 0.4 0.51 0.61 0.71 0.81 0.91 1.01 1.11 1.21 1.31 1.42 1.52 1.62 1.72 1.82 1.92 2.02 2.12 2.22 2.33 2.43 2.53 2.63 2.73 2.83 2.93 3.03 3.13 3.24 3.34 3.44 3.54 3.64 3.74 3.84 3.94
-10
0.1 0.08 0.06 0.04
-30
-50 Magnitude (dB)
-70
0.02
-90
-110
0 0.00 -0.02 -0.04 -0.06
0.25
-130
-150 Frequency (fs)
-0.08 -0.1 Frequency
Figure 50 ADC Digital Filter Frequency Response
Figure 51 ADC Digital Filter Ripple
DAC FILTER RESPONSES
MAGNITUDE(dB) 10 -10 0 -30 -50
0.02 0.04 MAGNITUDE(dB)
0.5
1
1.5
2
2.5
3
0.035 0.03 0.025
-70 -90 -110 -130 -150 Frequency (fs)
0.015 0.01 0.005 0 -0.005 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency (fs)
Figure 52 DAC Digital Filter Frequency Response (Normal Mode)
MAGNITUDE(dB) 10 -10 0 -30 -50 -70 -90 -110 -130 -150 Frequency (fs) 0.5 1 1.5 2 2.5 3
Figure 53 DAC Digital Filter Ripple (Normal Mode)
MAGNITUDE(dB) 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 -0.45 -0.5 Frequency (fs) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Figure 54 DAC Digital Filter Frequency Response (Sloping Stopband Mode)
Figure 55 DAC Digital Filter Ripple (Sloping Stopband Mode)
w
PD, August 2008, Rev 4.0 107
WM8900
DE-EMPHASIS FILTER RESPONSES
MAGNITUDE(dB)
0.3 MAGNITUDE(dB)
Production Data
0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 Frequency (Hz) 0 5000 10000 15000 20000
0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 Frequency (Hz) 0 2000 4000 6000 8000 10000 12000 14000 16000 18000
Figure 56 De-Emhpasis Digital Filter Response (32kHz)
MAGNITUDE(dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 Frequency (Hz) 0 5000 10000 15000 20000 25000
Figure 57 De-Emphasis Error (32kHz)
MAGNITUDE(dB) 0.2 0.15 0.1 0.05 0 0 -0.05 -0.1 Frequency (Hz) 5000 10000 15000 20000 25000
Figure 58 De-Emhpasis Digital Filter Response (44.1kHz)
MAGNITUDE(dB) 0 0 -2 -4 -6 -8 -10 -12 Frequency (Hz) 5000 10000 15000 20000 25000 30000
Figure 59 De-Emphasis Error (44.1kHz)
MAGNITUDE(dB) 0.15 0.1 0.05 0 0 -0.05 -0.1 -0.15 Frequency (Hz) 5000 10000 15000 20000 25000 30000
Figure 60 De-Emhpasis Digital Filter Response (48kHz)
Figure 61 De-Emphasis Error (48kHz)
w
PD, August 2008, Rev 4.0 108
Production Data
WM8900
ADC HIGH PASS FILTER RESPONSES
2.1246m
-2.3338m
-1.1717
-8.3373
-2.3455
-16.672
-3.5193
-25.007
-4.6931
-33.342
-5.8669
-41.677
-7.0407
-50.012
-8.2145
-58.347
-9.3883
-66.682
-10.562
-75.017
-11.736 1 2.6923 7.2484 19.515 52.54 141.45 380.83 1.0253k 2.7605k 7.432k 20.009k
-83.352 2 5.0248 12.624 31.716 79.683 200.19 502.96 1.2636k 3.1747k 7.9761k 20.039k
MAGNITUDE(dB)
hpf_response.res MAGNITUDE(dB) hpf_response2.res#1 MAGNITUDE(dB)
hpf_response2.res MAGNITUDE(dB)
ADC Digital High Pass Filter Frequency Response (48kHz, Hi-Fi Mode, ADC_HPF_CUT[1:0]=00)
ADC Digital High Pass Filter Ripple. Fs = 48kHz. ADC_HPF_CUT= 01 [voice mode 1] - black, ADC_HPF_CUT= 10 [Voice mode 2] - red ADC_HPF_CUT= 11 [Voice mode 3] - green
Figure 62 ADD High Pass Filter Characteristics
w
PD, August 2008, Rev 4.0 109
WM8900 APPLICATIONS INFORMATION
RECOMMENDED PATHS
STEREO DAC TO HEADPHONE
Production Data
The following section details the configuration for stereo DAC to headphone output with charge pump enabled. Slave mode, 24-bit I2S digital audio interface. Block Diagram:
AGND
VMID
BCLK ADCLRC/GPIO ADCDAT DACLRC DACDAT
-15 to +6dB, 3dB steps
Figure 63 Stereo DAC to Headphone Device Internal Signal Path Register Settings: REG INDEX 0x3A 0x1E 0x01 0x1E 0x03 0x1E 0x01 DATA VALUE 0x0030 0x0082 0x0100 0x009A 0x0060 0x001A 0x0101 400ms Delay 0x01 0x1E 0x01 0x03 0x0A 0x2C 0x2D 0x0109 0x0002 0x0009 0x00EF 0x0000 0x0150 0x0150 Write Write Write Write Write Write Write READ OR WRITE Write Write Write Write Write Write Write COMMENT
Set CLAMP_IP=1, CLAMP_OP=1 (HP amp) Set OUT2_DIS=1 (Enable), OUT1_DIS=0 (Disable) Set STARTUP_BIAS_ENA=1 Set BIAS_SRC=1, VMID_SOFTST=1 Set OUT2L_ENA=1, OUT2R_ENA=1 Reset OUT2_DIS=0, Leave BIAS_SRC=1, VMID_SOFTST=1 Set VMID_MODE=01 (2x50K Ohm Divider) Delay (400ms) to allow VMID to initially Set BIAS_ENA=1, VMID_MODE remains the same Reset BIAS_SRC=0, VMID_SOFTST=0 (Disable) CHIP_REV=0000, STARTUP_BIAS_ENA=0, FLL_ENA=0, MICB_ENA=0, BIAS_ENA=1, VMID_BUF_ENA=0, VMID_MODE=01 CP_ENA=1, OUT2L_ENA=1, OUT2R_ENA=1, MIXOUTL_ENA=1, MIXOUTR_ENA=1, DACL_ENA=1, DACR_ENA=1 DAC_MUTE=0 DACL_TO_MIXOUTL=1 DACR_TO_MIXOUTR=1
SCLK SDIN CSB/GPIO MODE/GPIO
-15 to +6dB, 3dB steps
4.7uF
AVDD
MCLK
w
PD, August 2008, Rev 4.0 110
Production Data
WM8900
READ OR WRITE Write Write Write Write Write Write COMMENT
REG INDEX 0x35 0x36 0x3A 0x3A 0x3A 0x3A
DATA VALUE 0x0139 0x0139 0x009C 0x00CC 0x00C8 0x00C0
OUT2_VU=1, OUT2L_MUTE=0, OUT2L_VOL=11_1001 OUT2_VU=1, OUT2R_MUTE=0, OUT2R_VOL=11_1001 Set HP_SHORT=1, HP_SHORT2=1, HP_IPSTAGE_ENA=1; Reset CLAMP_IP=0 400ms Delay Set HP_OPSTAGE_ENA = 1, Reset CLAMP_OP=0 Reset HP_SHORT2=0 Reset HP_SHORT=0
Table 75 Stereo DAC to Headphone - Recommended Power up Sequence and Device Register Settings
Note: These sequences are optimised for best audio performance and minimal pops; however a faster power up sequence can be gained by reducing the delay time at the expense of reducing the pop suppression capability of the device STEREO DAC TO LINE OUTPUT The following section details the configuration for stereo DAC to line output (LINEOUT1L/R). Slave mode, 24-bit I2S digital audio interface.
Block Diagram:
Figure 64 Stereo DAC to Line Output 1 Device Internal Signal Path
w
PD, August 2008, Rev 4.0 111
WM8900
Production Data
Register Settings: REG INDEX 0x1E DATA VALUE READ OR WRITE 0x0102 100ms Delay 0x01 0x1E 0x02 0x1E 0x01 0x0100 0x011A 0xC180 0x001A 0x0101 200 ms Delay 0x01 0x1E 0x01 0x03 0x0A 0x0109 0x0002 0x0009 0x008F 0x0000 COMMENT
Set OUT1_DIS=1 (Enable), OUT2_DIS=0 Delay (100ms) to remove any residual charge on LINEOUT_1 Set STARTUP_BIAS_ENA=1, BIAS_ENA=0 Set BIAS_SRC=1, VMID_SOFTST=1 Set OUT1L_ENA=1, OUT1R_ENA=1 Reset OUT1_DIS=0, Leave BIAS_SRC=1, VMID_SOFTST=1 Set VMID_MODE=01 (2x50K Ohm Divider) Delay (200ms) to allow VMID to initially charge Set BIAS_ENA=1, VMID_MODE remains the same Reset BIAS_SRC=0, VMID_SOFTST=0 (Disable) Set BIAS_ENA=0 Set CP_ENA=1, OUT2L_ENA=0, OUT2R_ENA=0, MIXOUTL_ENA=1, MIXOUTR_ENA=1, DACL_ENA=1, DACR_ENA=1 AIF_LRCLKRATE=0, DAC_MONO=0, DAC_SB_FILT=0, DAC_MUTERATE=0, DAC_MUTEMODE=0, DEEMP=00, DAC_MUTE=0, DACL_DATINV=0, DACR_DATINV=0 DACL_TO_MIXOUTL=1, IN3L_TO_MIXOUTL=0, IN3L_MIXOUTL_VOL=101, DAC_LP=0, DAC_LP_VOL=0 DACR_TO_MIXOUTR=1, IN3R_TO_MIXOUTR=0, IN3R_MIXOUTR_VOL=101 OUT1_VU=1, OUT1L_ZC=1, OUT1L_MUTE=0, OUT1L_VOL=0dB OUT1_VU=1, OUT1R_ZC=1, OUT1R_MUTE=0, OUT1R_VOL=0dB
0x2C 0x2D 0x33 0x34
0x0150 0x0150 0x01B9 0x01B9
Table 76 Stereo DAC to Line Output 1 - Recommended Power up Sequence and Device Register Settings Note: These sequences are optimised for best audio performance and minimal pops; however a faster power up sequence can be gained by reducing the delay time at the expense of reducing the pop suppression capability of the device SINGLE ENDED MIC INPUT (L/RINPUT1) TO STEREO ADC The following section details the configuration for single-ended stereo microphone input (L/RINPUT1) to stereo ADC. Slave mode, 24-bit I2S digital audio interface.
w
PD, August 2008, Rev 4.0 112
Production Data
WM8900
Block diagram:
Figure 65 L/RINPUT1 to ADC Internal Signal Path - Recommended Power up Sequence and Device Register Settings
Register Settings: REG INDEX R0 R1 R2 R15 R16 R22 R23 R26 DATA VALUE 0x0000 0x001D 0xC03F 0x01C0 0x01C0 0x010C 0x010C 0x0044 READ OR WRITE Write Write Write Write Write Write Write Write Reset WM8900 Enable VMID, VMID_BUF, BIAS, MIC_BIAS Enable ADC, Input PGA, Input Mixer, Enable Left ADC Volume Update Enable Right ADC Volume Update Disable Left Input PGA MUTE, Set Input PGA Volume Update, 0dB Gain Disable Right Input PGA MUTE, Set Input PGA Volume Update, 0dB Gain Set Input PGAs to Input Mixers COMMENT
Table 77 L/RINPUT1 to ADC Device Register Settings
w
PD, August 2008, Rev 4.0 113
WM8900
LINE INPUT 3 TO HEADPHONE (BYPASS PATH)
Production Data
The following section details the configuration for LINPUT3 and RINPUT3 to stereo headphone mode, Note that SYSCLK is still required to operate the charge pump which powers the headphone amplifiers, even although the digital audio interface is off.
AGND
VMID
BCLK ADCLRC/GPIO ADCDAT DACLRC DACDAT
-15 to +6dB, 3dB steps
Figure 66 LR Input 3 to Headphone Bypass Path REG INDEX 0x3A 0x1E 0x01 0x1E 0x03 0x1E 0x01 DATA VALUE 0x0030 0x0082 0x0100 0x009A 0x0060 0x001A 0x0101 400ms Delay 0x01 0x1E 0x01 0x03 0x0109 0x0002 0x0009 0x00EC Write Write Write Write READ OR WRITE Write Write Write Write Write Write Write COMMENT
HIGHPOW=0, HP_IPSTAGE_ENA=0, HP_OPSTAGE_ENA=0, HP_CLAMP_IP=1, HP_CLAMP_OP=1, HP_SHORT=0, HP_SHORT2=0, HP_BIAS=00 OUT1_DIS=0, OUT2_DIS=1, VMID_DISCH=0, BIAS_SRC=0, VMID_SOFTST=0, TEMP_SD=1, VROI=0 STARTUP_BIAS_ENA=1, FLL_ENA=0, MICB_ENA=0, BIAS_ENA=0, VMID_BUF_ENA=0, VMID_MODE=00 OUT1_DIS=0, OUT2_DIS=1, VMID_DISCH=0, BIAS_SRC=1, VMID_SOFTST=1, TEMP_SD=1, VROI=0 CP_ENA=0, OUT2L_ENA=1, OUT2R_ENA=1, MIXOUTL_ENA=0, MIXOUTR_ENA=0, DACL_ENA=0, DACR_ENA=0 OUT1_DIS=0, OUT2_DIS=0, VMID_DISCH=0, BIAS_SRC=1, VMID_SOFTST=1, TEMP_SD=1, VROI=0 STARTUP_BIAS_ENA=1, FLL_ENA=0, MICB_ENA=0, BIAS_ENA=0, VMID_BUF_ENA=0, VMID_MODE=01 INSERT_DELAY_MS 400 STARTUP_BIAS_ENA=1, FLL_ENA=0, MICB_ENA=0, BIAS_ENA=1, VMID_BUF_ENA=0, VMID_MODE=01 OUT1_DIS=0, OUT2_DIS=0, VMID_DISCH=0, BIAS_SRC=0, VMID_SOFTST=0, TEMP_SD=1, VROI=0 STARTUP_BIAS_ENA=0, FLL_ENA=0, MICB_ENA=0, BIAS_ENA=1, VMID_BUF_ENA=0, VMID_MODE=01 CP_ENA=1, OUT2L_ENA=1, OUT2R_ENA=1, MIXOUTL_ENA=1, MIXOUTR_ENA=1, DACL_ENA=0, DACR_ENA=0
SCLK SDIN CSB/GPIO MODE/GPIO
-15 to +6dB, 3dB steps
4.7uF
AVDD
MCLK
w
PD, August 2008, Rev 4.0 114
Production Data
WM8900
READ OR WRITE Write COMMENT
REG INDEX 0x0A
DATA VALUE 0x1004
DAC_SDMCLK_RATE=1, AIF_LRCLKRATE=0, DAC_MONO=0, DAC_SB_FILT=0, DAC_MUTERATE=0, DAC_MUTEMODE=0, DEEMP=00, DAC_MUTE=1, DACL_DATINV=0, DACR_DATINV=0 DACL_TO_MIXOUTL=0, IN3L_TO_MIXOUTL=1, IN3L_MIXOUTL_VOL=101, DAC_LP=0, DAC_LP_VOL=0 DACR_TO_MIXOUTR=0, IN3R_TO_MIXOUTR=1, IN3R_MIXOUTR_VOL=101 OUT2_VU=1, OUT2L_ZC=0, OUT2L_MUTE=0, OUT2L_VOL=11_1001 OUT2_VU=1, OUT2R_ZC=0, OUT2R_MUTE=0, OUT2R_VOL=11_1001 HIGHPOW=0, HP_IPSTAGE_ENA=1, HP_OPSTAGE_ENA=0, HP_CLAMP_IP=0, HP_CLAMP_OP=1, HP_SHORT=1, HP_SHORT2=1, HP_BIAS=00 INSERT_DELAY_MS 400
0x2C 0x2D 0x35 0x36 0x3A
0x00D0 0x00D0 0x0139 0x0139 0x009C 400ms Delay
Write Write Write Write Write
0x3A 0x3A 0x3A
0x00CC 0x00C8 0x00C0
Write Write Write
HIGHPOW=0, HP_IPSTAGE_ENA=1, HP_OPSTAGE_ENA=1, HP_CLAMP_IP=0, HP_CLAMP_OP=0, HP_SHORT=1, HP_SHORT2=1, HP_BIAS=00 HIGHPOW=0, HP_IPSTAGE_ENA=1, HP_OPSTAGE_ENA=1, HP_CLAMP_IP=0, HP_CLAMP_OP=0, HP_SHORT=1, HP_SHORT2=0, HP_BIAS=00 HIGHPOW=0, HP_IPSTAGE_ENA=1, HP_OPSTAGE_ENA=1, HP_CLAMP_IP=0, HP_CLAMP_OP=0, HP_SHORT=0, HP_SHORT2=0, HP_BIAS=00
Table 78 LR input 3 to Headphone Bypass Path Note:
- Recommended Power Up Sequence and Device Register Settings
These sequences are optimised for best audio performance and minimal pops; however a faster power up sequence can be gained by reducing the delay time at the expense of reducing the pop suppression capability of the device
RECOMMENDED POWER DOWN SEQUENCE
REG INDEX 0x3A 0x3A 0x3A 0x2C 0x2D 0x01 0x1E 0x01 DATA VALUE 0x00C8 0x0088 0x0030 0x0050 0x0050 0x0109 0x001A 0x0100 500ms Delay 0x1E 0x0100 Write READ OR WRITE Write Write Write Write Write Write Write Write Set HP_SHORT=1 Reset HP_OPSTAGE_ENA=0 Set CLAMP_IP=1, CLAMP_OP=1; Reset HP_SHORT=0, HP_IPSTAGE_ENA=0 Reset DACL_TO_MIXOUTL=0 Reset DACR_TO_MIXOUTR=0 Set STARTUP_BIAS_ENA=1 Set BIAS_SRC=1, VMID_SOFTST=1 Reset BIAS_ENA=0, VMIDBUF_ENA=0, VMID_MODE=00, Leave STARTUP_BIAS_ENA=1 INSERT_DELAY_MS [500] Disable Thermal shutdown, Set OUT1_DIS=1 COMMENT
From here, the user can achieve optimal power saving and a predictable mode of operation by writing the default data value to all registers except R30 (0x1E). These default register writes can be carried out in any order. Table 79 Recommended Power Down Sequence Note: These sequences are optimised for best audio performance and minimal pops; however a faster power up sequence can be gained by reducing the delay time at the expense of reducing the pop suppression capability of the device.
w
PD, August 2008, Rev 4.0 115
WM8900 PACKAGE DIMENSIONS
FL: 40 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.55 mm BODY, 0.40 mm LEAD PITCH
D2 B D2/2 31 39 40 L 30 EXPOSED 6 GND PADDLE A 1 2 E2/2 INDEX AREA (D/2 X E/2) SEE DETAIL A
Production Data
DM051.A
TOP VIEW
D
A
E2
E
21
10
SEE DETAIL B aaa C aaa C
18 17 e B b
11 ccc M C A B
2X 2X
DETAIL A
ccc C (A3) 1 A 0.08 C SEATING PLANE 1 e/2 TERMINAL TIP A1 1 bbb M C A B L 40x b PIN #1 IDENTIFICATION CHAMFER R0.300 X 45o
C
DETAIL B
DATUM
e
EXPOSED GND PADDLE
R
1 R
Symbols A A1 A3 b D D2 E E2 e L aaa bbb ccc REF:
Dimensions (mm) NOM MAX 0.55 0.60 0.02 0.05 0.203 REF 0.15 0.20 0.25 5.00 BSC 3.55 3.6 3.65 5.00 BSC 3.55 3.6 3.65 0.4 BSC 0.35 0.4 0.45 Tolerances of Form and Position MIN 0.50 0 0.15 0.10 0.10 JEDEC, MO-220
NOTE
1 2 2
NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC, MO-220. 3. ALL DIMENSIONS ARE IN MILLIMETRES 4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 5. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION.
w
PD, August 2008, Rev 4.0 116
Production Data
WM8900
IMPORTANT NOTICE
Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
w
PD, August 2008, Rev 4.0 117

▲Up To Search▲

Price & Availability of WM8900LGEFKRV

Part #	Manufacturer	Description	Price	BuyNow Qty.
WM8900LGEFK/RV	Wolfson Microelectronics	QFN		1000

	To Download WM8900LGEFKRV Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .