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Freescale Semiconductor Advance Information
Document Number: MC33894 Rev 3.0, 10/2006
Quad High-Side Switch (Quad 35 m)
The 33894 is one in a family of devices designed for low-voltage automotive and industrial lighting and motor control applications. Its four low RDS(ON) MOSFETs (four 35 m) can control the high sides of four separate resistive or inductive loads. Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. Additionally, each output has its own parallel input for pulse-width modulation (PWM) control if desired. The 33894 allows the user to program the fault current trip levels and duration of acceptable lamp inrush or motor stall intervals via the SPI. Such programmability allows tight control of fault currents and can protect wiring harnesses and circuit boards as well as loads. The 33894 is packaged in a power-enhanced 12 x 12 nonleaded Power QFN package with exposed tabs. Features * Quad 35 m High-Side Switches (at 25C) * Operating Voltage Range of 6.0 V to 27 V with Standby Current < 5.0 A * SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time, Output OFF Open Load Detection, Output ON /OFF Control, Watchdog Timeout, Slew Rates, and Fault Status Reporting * SPI Status Reporting of Overcurrent, Open and Shorted Loads, Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe Pin Status, and Program Status * Analog Current Feedback with Selectable Ratio * Enhanced -16 V Reverse Polarity VPWR Protection *
VDD VDD VPWR VDD
33894
QUAD HIGH-SIDE SWITCH 35 m
Bottom View PNA SUFFIX 98ARL10596D 24-PIN PQFN
ORDERING INFORMATION
Device MC33894PNA/R2 Temperature Range (TA) -40C to 125C Package 24 PQFN
VPWR
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VDD WAKE I/O SCLK CS SI MCU I/O SO I/O I/O I/O I/O A/D GND FS SCLK CS SO RST SI IN0 IN1 IN2 IN3 CSNS FSI GND HS3 LOAD 3 HS2 LOAD 2 HS1 LOAD 1 VPWR HS0 LOAD 0
Figure 1. 33894 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2006. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
VPWR
VIC
IUP CS SCLK IDWN SO SI RST WAKE FS IN0 IN1 IN2 IN3
SPI 3.0 MHz
Internal Regulator
Over/Undervoltage Protection
Selectable Slew Rate Gate Drive
Selectable Overcurrent High Detection HS[0:3]: 50 A or 35 A Logic Selectable Overcurrent Low Detection Blanking Time 0.15 ms-155 ms Open Load Detection Overtemperature Detection Selectable Overcurrent Low Detection HS[0:3]: 2.4 A-9.1 A
HS0
HS0
RDWN
IDWN HS1
HS1
Programmable Watchdog 310 ms-2500 ms
VIC
HS2 HS2
FSI HS3 HS3
Selectable Output Current Recopy (Analog MUX) HS[0:3]: 1/6500 or 1/20000
GND
CSNS
Figure 2. 33894 Simplified Internal Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
Transparent Top View of Package
WAKE CSNS 1 24 14 GND 23 FSI GND 22 HS2 SCLK VDD RST IN3 IN2 IN1 3 IN0 2 NC 4 CS FS 7 SI
13 12 11 10 SO GND 16 17
9
8
6
5
HS3
18
15 VPWR
19 HS1
20 NC
21 HS0
Figure 3. 33894 Pin Connections Table 1. 33894 Pin Definitions Functional descriptions of many of these pins can be found in Functional Description on page 16.
Pin Number 1 Pin Name CSNS Formal Name Output Current Monitoring Definition The Current Sense pin sources a current proportional to the designated HS0 : HS3 output. That current is fed into a ground-referenced resistor and its voltage is monitored by an MCU's A/D. The output to be monitored is selected via the SPI. This pin can be tri-stated through SPI. The IN0 : IN3 high-side input pins are used to directly control HS0 : HS3 high-side output pins, respectively. An SPI register determines if each input is activated or if the input logic state is OR ed or AND ed with the SPI instruction. These pins are to be driven with 5.0 V CMOS levels, and they have an active internal pulldown current source. These pins may not be connected. This pin is an open drain configured output requiring an external pullup resistor to VDD for fault reporting. If a device fault condition is detected, this pin is active LOW. Specific device diagnostic faults are reported via the SPI SO pin. This input pin controls the device mode and watchdog timeout feature if enabled. An internal clamp protects this pin from high damaging voltages when the output is current limited with an external resistor. This input has a passive internal pulldown. This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low-current sleep mode. The pin also starts the watchdog timer when transitioning from logic [0] to logic [1]. This pin should not be allowed to be logic [1] until VDD is in regulation. This pin has a passive internal pulldown.
2 3 5 6 4, 20 7
IN0 IN1 IN2 IN3 NC FS
Serial Inputs
No Connect Fault Status (Active Low) Wake
8
WAKE
9
RST
Reset
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PIN CONNECTIONS
Table 1. 33894 Pin Definitions (continued) Functional descriptions of many of these pins can be found in Functional Description on page 16.
Pin Number 10 Pin Name CS Formal Name Chip Select (Active Low) Definition This input pin is connected to a chip select output of a master MCU. The MCU determines which device is addressed (selected) to receive data by pulling the CS pin of the selected device logic LOW, thereby enabling SPI communication with the device. Other unselected devices on the serial link having their CS pins pulled up logic HIGH disregard the SPI communication data sent. This pin has an active internal pullup current source and requires CMOS logic levels. This input pin is connected to the MCU providing the required bit shift clock for SPI communication. It transitions one time per bit transferred at an operating frequency, fSPI, defined by the communication interface. The 50 percent duty cycle CMOS level serial clock signal is idle between command transfers. The signal is used to shift data into and out of the device. This pin has an active internal pulldown current source. This pin is a command data input pin connected to the SPI Serial Data Output of the microcontroller (MCU) or to the SO pin of the previous device of a daisy-chain of devices. The input requires CMOS logic level signals and incorporates an internal active pulldown. Device control is facilitated by the input's receiving the MSB first of a serial 8-bit control command. The MCU ensures data is available upon the falling edge of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit command into the internal command shift register. This pin has an active internal pulldown current source. This pin is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost, an internal supply provides power to a portion of the logic, ensuring limited functionality of the device. These pins are the ground for the logic and analog circuitry of the device. This pin connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the backside surface mount tab of the package. This output pin is connected to the SPI Serial Data Input pin of the MCU or to the SI pin of the next device of a daisy-chain of devices. This output will remain tri-stated (highimpedance OFF condition) so long as the CS pin of the device is logic HIGH. SO is only active when the CS pin of the device is asserted logic LOW. The generated SO output signals are CMOS logic levels. SO output data is available on the falling edge of SCLK and transitions immediately on the rising edge of SCLK. Protected 35 m high-side power output pins to the load.
11
SCLK
Serial Clock
12
SI
Serial Input
13
VDD
Digital Drain Voltage (Power)
14, 17, 23 15
GND VPWR SO
Ground Positive Power Supply
16
Serial Output
18 19 21 22 24
HS3 HS1 HS0 HS2 FSI
High-Side Outputs
Fail-Safe Input
The value of the resistance connected between this pin and ground determines the state of the outputs after a Watchdog timeout occurs. Depending on the resistance value, either all outputs are OFF or the output HSO only is ON. If the FSI pin is left to float up to a logic [1] level, then the outputs HS0 and HS2 will turn ON when in the FailSafe state. When the FSI pin is connected to GND, the Watchdog circuit and Fail-Safe operation are disabled. This pin incorporates an active internal pullup current source.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Operating Voltage Range Steady-State VDD Supply Voltage Input/Output Voltage (1) VDD VIN[0:3], RST, FSI, CSNS, SI, SCLK, CS, FS VSO ICL(WAKE) ICL(CSNS) IHS[0:3] ECL [0:3] VPWR(SS) -16 to 41 0 to 5.5 - 0.3 to 7.0 V V V Symbol Value Unit
SO Output Voltage (1) WAKE Input Clamp Current CSNS Input Clamp Current Output Current
(2)
- 0.3 to VDD + 0.3 2.5 10 11 TBD
V mA mA A J V
Output Clamp Energy (3) ESD Voltage (4) Human Body Model Machine Model THERMAL RATINGS Operating Temperature Ambient Junction Storage Temperature Thermal Resistance Junction to Case Junction to Ambient Peak Pin Reflow Temperature During Solder Mounting (6)
(5)
VESD1 VESD2
2000 200
C
TA TJ TSTG RJC RJA TSOLDER - 40 to 125 - 40 to 150 - 55 to 150
C C/ W
<1.0 TBD 240
C
Notes 1. Exceeding voltage limits on IN[0:3], RST, FSI, CSNS, SI, SO, SCLK, CS, or FS pins may cause a malfunction or permanent damage to the device. 2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 3. Active clamp energy using single-pulse method (L = 16 mH, RL = 0 , VPWR = 12 V, TJ = 150C). 4. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ) and in accordance with the system module specification with a capacitor > 0.01 F connected from high-side outputs to GND. Device mounted on a 2s2p test board per JEDEC JESD51-2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.
5. 6.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER INPUT Battery Supply Voltage Range Fully Operational VPWR Operating Supply Current Outputs ON, HS[0 : 3] Open VPWR Supply Current Outputs OFF, Open Load Detection Disabled, WAKE > 0.7 VDD, RST = VLOGIC HIGH Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V) TJ = 25C TJ = 85C VDD Supply Voltage VDD Supply Current No SPI Communication 3.0 MHz SPI Communication VDD Sleep State Current Overvoltage Shutdown Threshold Overvoltage Shutdown Hysteresis Undervoltage Shutdown Threshold Undervoltage Hysteresis (8) Undervoltage Power-ON Reset
(7)
Symbol
Min
Typ
Max
Unit
VPWR 6.0 IPWR(ON) - IPWR(SBY) - IPWR(SLEEP) - - VDD(ON) IDD(ON) - - IDD(SLEEP) VPWR(OV) VPWR(OVHYS) VPWR(UV) VPWR(UVHYS) VPWR(UVPOR) - 28 0.2 4.75 - - - - - 32 0.8 5.25 0.25 - 1.0 5.0 5.0 36 1.5 5.75 - 5.0 4.5 - - 5.0 10 50 5.5 - 5.0 - 20 - 27
V
mA
mA
A
V mA
A V V V V V
Notes 7. Output will automatically recover to instructed state when VPWR voltage is restored to normal so long as the VPWR degradation level did not go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the external VDD supply is within specification. 8. This applies when the undervoltage fault is not latched (IN[0 : 3] = 0).
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic OUTPUTS HS0:HS3 Output Drain-to-Source ON Resistance (IHS[0 : 3] = 5.0 A, TJ = 25C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V Output Drain-to-Source ON Resistance (IHS[0 : 3] = 5.0 A, TJ = 150C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V Output Source-to-Drain ON Resistance (9) IHS[0 : 3] = 5.0 A, TJ = 25C, VPWR = -12 V Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V) SOCH = 0 SOCH = 1 Overcurrent Low Detection Levels (SOCL[2:0], 9.0 V < VPWR < 16 V) 000 001 010 011 100 101 110 111 Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) DICR D2 = 0 DICR D2 = 1 Current Sense Ratio (CSR0) Accuracy Output Current 2.0 A 5.0 A 10 A 12.5 A 15 A 20 A - 20 -14 -13 -12 -13 -13 - - - - - - 20 14 13 12 13 13 CSR0 CSR1 CSR0_ACC - - 1/6500 1/20000 - - % IOCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 7.2 6.5 5.7 5.0 4.2 3.4 2.6 1.9 9.1 8.15 7.2 6.25 5.25 4.3 3.35 2.4 11 9.8 8.7 7.5 6.3 5.2 4.1 2.9 - IOCH0 IOCH1 40 28 50 35 62 43 A RDS(ON) - - 70 A RDS(ON) - - - - - - 94 60 60 m RDS(ON) - - - - - - 55 35 35 m m Symbol Min Typ Max Unit
Notes 9. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic OUTPUTS HS0:HS3 (continued) Current Sense Ratio (CSR1) Accuracy Output Current 5.0 A 10 A 12.5 A 15 A 20 A 25 A Current Sense Clamp Voltage CSNS Open; IHS[0:3] = 11 A Open Load Detection Current (10) Output Fault Detection Threshold Output Programmed OFF Output Negative Clamp Voltage 0.5 A < IHS[0:3] < 2.0 A, Output OFF Overtemperature Shutdown (11) Overtemperature Shutdown Hysteresis (11) TSD TSD(HYS) VCL - 20 155 5.0 - 175 - - 190 20 IOLDC VOFD(THRES) 2.0 3.0 4.0 V VCL(CSNS) 4.5 30 6.0 - 7.0 100 A V - 25 -19 -18 -17 -18 -18 - - - - - - 25 19 18 17 18 18 V CSR1_ACC % Symbol Min Typ Max Unit
C C
Notes 10. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 11. Guaranteed by process monitoring. Not production tested.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic CONTROL INTERFACE Input Logic High Voltage (12) Input Logic Low Voltage (12) Input Logic Voltage Hysteresis (12) Input Logic Pulldown Current (SCLK, SI, IN[0:3])
RST Input Voltage Range
Symbol
Min
Typ
Max
Unit
VIH VIL VIN(HYS) IDWN VRST CSO RDWN CIN VCL(WAKE)
0.7 VDD - 100 5.0 4.5 - 100 -
- - 350 - 5.0 - 200 4.0
- 0.2 VDD 750 20 5.5 20 400 12
V V mV A V pF k pF V
SO, FS Tri-State Capacitance (13) Input Logic Pulldown Resistor (RST) and WAKE Input Capacitance
(14)
Wake Input Clamp Voltage (15) ICL(WAKE) < 2.5 mA Wake Input Forward Voltage ICL(WAKE) = -2.5 mA SO High-State Output Voltage IOH = 1.0 mA
FS, SO Low-State Output Voltage
7.0 VF(WAKE) - 2.0 VSOH 0.8 VDD VSOL - ISO(LEAK) - 5.0 IUP 5.0 RFS RFSDIS RFSOFFOFF RFSONOFF RFSONON - 6.0 15 40
-
14 V
-
-0.3 V
-
- V
IOL = -1.6 mA SO Tri-State Leakage Current
CS > 0.7 VDD
0.2
0.4 A
0
5.0 A
Input Logic Pullup Current (16)
CS, VIN > 0.7 VDD
-
20 k
FSI Input pin External Pulldown Resistance (17) FSI Disabled, HS[0:3] Indeterminate FSI Enabled, HS[0:3] OFF FSI Enabled, HS0 ON, HS[1:3] OFF FSI Enabled, HS0 and HS2 ON, HS1 and HS3 OFF
0 6.5 17 Infinite
1.0 7.0 19 -
Notes 12. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3], and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage referenced to VPWR. 13. 14. 15. 16. 17. Parameter is guaranteed by process monitoring but is not production tested. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested. The current must be limited by a series resistance when using voltages > 7.0 V. Pullup current is with CS OPEN. CS has an active internal pullup to VDD. The selection of the RFS must take into consideration the tolerance, temperature coefficient and lifetime duration to assure that the resistance value will always be within the desired (specified) range.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER OUTPUT TIMING HS0:HC3 Output Rising Slow Slew Rate A (DICR D3 = 0) (18) 9.0 V < VPWR < 16 V Output Rising Slow Slew Rate B (DICR D3 = 0) (19) 9.0 V < VPWR < 16 V Output Rising Fast Slew Rate A (DICR D3 = 1) (18) 9.0 V < VPWR < 16 V Output Rising Fast Slew Rate B (DICR D3 = 1) (19) 9.0 V < VPWR < 16 V Output Falling Slow Slew Rate A (DICR D3 = 0) (18) 9.0 V < VPWR < 16 V Output Falling Slow Slew Rate B (DICR D3 = 0) (19) 9.0 V < VPWR < 16 V Output Falling Fast Slew Rate A (DICR D3 = 1) (18) 9.0 V < VPWR < 16 V Output Falling Fast Slew Rate B (DICR D3 = 1) (19) 9.0 V < VPWR < 16 V Output Turn-ON Delay Time in Fast/Slow Slew Rate (20) DICR = 0, DICR = 1 Output Turn-OFF Delay Time in Slow Slew Rate Mode (21) DICR = 0 Output Turn-OFF Delay Time in Fast Slew Rate Mode (21) DICR = 1 Overcurrent Low Detection Blanking Time (OCLT[1:0]) 00 01 (22) 10 11 SRFB_FAST 0.05 0.175 0.6 s 2.0 30 200 s 40 460 1000 s 20 120 400 ms SRFA_FAST 0.4 1.0 2.0 V/s SRFB_SLOW 0.015 0.05 0.15 V/s SRFA_SLOW 0.1 0.3 0.5 V/s SRRB_FAST 0.015 0.05 0.5 V/s SRRA_FAST 0.2 0.5 1.5 V/s SRRB_SLOW 0.015 0.05 0.15 V/s SRRA_SLOW 0.1 0.3 0.5 V/s V/s Symbol Min Typ Max Unit
t DLY(ON) t DLY_SLOW(O
FF)
t DLY_FAST(O
FF)
t OCL0 t OCL1 t OCL2 t OCL3
108 - 55 0.08
155 - 75 0.15
202 - 95 0.25
Notes 18. Rise and Fall Slew Rates A measured across a 5.0 resistive load at high-side output = 0.5 V to VPWR - 3.5 V (see Figure 4, page 13). These parameters are guaranteed by process monitoring. 19. Rise and Fall Slew Rates B measured across a 5.0 resistive load at high-side output = 0.5 V to VPWR - 3.5 V (see Figure 4). These parameters are guaranteed by process monitoring. 20. Turn-ON delay time measured from rising edge of any signal (IN[0 : 3], SCLK, CS) that would turn the output ON to VHS[0 : 3] = 0.5 V with RL = 5.0 resistive load. 21. 22. Turn-OFF delay time measured from falling edge of any signal (IN[0 : 3], SCLK, CS) that would turn the output OFF to VHS[0 : 3] = VPWR 0.5 V with RL = 5.0 resistive load. This logical bit is not defined. Do not use.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER OUTPUT TIMING HS0:HC3 (CONTINUED) Overcurrent High Detection Blanking Time
CS to CSNS Valid Time (23)
Symbol
Min
Typ
Max
Unit
t OCH t CNSVAL t WDTO0 t WDTO1 t WDTO2 t WDTO3
1.0 -
10 -
20 10
s s ms
Watchdog Timeout (WD[1:0]) (24) 00 01 10 11
496 248 2000 1000
620 310 2500 1250
806 403 3250 1625
Notes 23. Time necessary for the CSNS to be with 5% of the targeted value. 24. Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of t WDTO is consistent for all configured watchdog timeouts.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic SPI INTERFACE CHARACTERISTICS Maximum Frequency of SPI Operation Required Low State Duration for RST (25) Rising Edge of CS to Falling Edge of CS (Required Setup Time) (26) Rising Edge of RST to Falling Edge of CS (Required Setup Time) (26) Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (26) Required High State Duration of SCLK (Required Setup Time) (26) Required Low State Duration of SCLK (Required Setup Time) (26) Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (26) SI to Falling Edge of SCLK (Required Setup Time) (27) Falling Edge of SCLK to SI (Required Setup Time) (27) SO Rise Time CL = 200 pF SO Fall Time CL = 200 pF SI, CS, SCLK, Incoming Signal Rise Time (27) SI, CS, SCLK, Incoming Signal Fall Time (27) Time from Falling Edge of CS to SO Low Impedance (28) Time from Rising Edge of CS to SO High Impedance (29) Time from Rising Edge of SCLK to SO Data Valid (30) 0.2 VDD SO 0.8 VDD, CL = 200 pF Notes 25. 26. 27. 28. 29. 30. Symbol Min Typ Max Unit
f SPI t WRST t CS t ENBL t LEAD t WSCLKH t WSCLKL t LAG t SI (SU) t SI (HOLD) t RSO
- - - - - - - - - -
- 50 - - 50 - - 50 25 25
3.0 350 300 5.0 167 167 167 167 83 83
MHz ns ns s ns ns ns ns ns ns ns
-
25
50 ns
t FSO
- 25 - - - 65 50 50 50 145 145
t RSI t FSI t SO(EN) t SO(DIS) t VALID
- - - -
ns ns ns ns ns
-
65
105
RST low duration measured with outputs enabled and going to OFF or disabled condition. Maximum setup time required for the 33894 is the minimum guaranteed time needed from the microcontroller. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at SO. 1.0 k on pullup on CS. Time required for output status data to be terminated at SO. 1.0 k on pullup on CS. Time required to obtain valid data out from SO following the rise of SCLK.
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
CS
VPWR VPWR VPWR - 0.5V VPWR -0.5 V VPWR - 3V VPWR -3.5 V
SRRB SRrB
SRFB SRfB SRFA SRfA
SRRA SRrA
0.5V 0.5
V t DLY(OFF) Tdly(off)
t DLY(ON) Tdly(on)
Figure 4. Output Slew Rate and Time Delays
Figure 5. Overcurrent Shutdown
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
IOCH0 IOCH1 IOCL0
IOCL1
Load Current
IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7
Time
t OCH t OCL3 t OCL2 t OCL0
Figure 6. Overcurrent Low and High Detection
VIH VIH
RSTB RST
0.2 VDD 0.2 VDD tWRST
TwRSTB tENBL TENBL TCSB t CS
VIL VIL
0.7 VDD 0.7VDD CS CSB 0.7 VDD 0.7VDD
VIH VIH VIL VIL
tTlead LEAD
tWSCLKH TwSCLKh
tRSI
TrSI
tLAG Tlag
VIH VIH VIL VIL
SCLK SCLK
0.7 VDD 0.7VDD 0.2 VDD
0.2VDD
tSI(SU) TSIsu
tWSCLKL TwSCLKl tSI(HOLD) TSI(hold)
tTfSI FSI
Valid Don't Care VIH VIH
SI SI
Don't Care
0.7 VDD 0.7 VDD 0.2VDD 0.2 VDD
Valid
Don't Care
VIH VIL
Figure 7. Input timing Switching Characteristics
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
t RSI
TrSI TfSI
t FSI
3.5 3.5V V
VOH VOH 50% 1.0V 1.0 V VOL VOL
SCLK SCLK
t SO(EN)
TdlyLH
SO SO
0.7 VDD VDD
VOH VOH VOL VOL
0.2 VDD 0.2 VDD TrSO t RSO TVALID tVALID
Low-to-High Low to High
SO
SO
0.7 VDD High to Low High-to-Low 0.7 VDD
TfSO t FSO
VOH VOH
TdlyHL
t SO(DIS)
0.2VDD 0.2 VDD
VOL VOL
Figure 8. SCLK Waveform and Valid SO Data Delay Time
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33894 is one in a family of devices designed for lowvoltage automotive and industrial lighting and motor control applications. Its four low RDS(ON) MOSFETs (four 35 m) can control the high sides of four separate resistive or inductive loads. Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. Additionally, each output has its own parallel input for PWM control if desired. The 33894 allows the user to program via the SPI the fault current trip levels and duration of acceptable lamp inrush or motor stall intervals. Such programmability allows tight control of fault currents and can protect wiring harnesses and circuit boards as well as loads. The 33894 is packaged in a power-enhanced 12 x 12 nonleaded PQFN package with exposed tabs.
FUNCTIONAL PIN DESCRIPTION
SPI PROTOCOL DESCRIPTION
The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK), and Chip Select (CS). The SI/SO pins of the 33894 follow a first-in first-out (D15 to D0) protocol, with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0 V CMOS logic levels. The SPI lines perform the following functions:
SCLK. Fault and input status descriptions are provided in Table 15, page 23.
SERIAL CLOCK (SCLK)
The SCLK pin clocks the internal shift registers of the 33894 device. The serial input (SI) pin accepts data into the input shift register on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important the SCLK pin be in a logic low state whenever CS makes any transition. For this reason, it is recommended the SCLK pin be in logic [0] whenever the device is not accessed (CS logic [1] state). SCLK has an active internal pulldown. When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high impedance) (see Figure 9, page 19).
SERIAL INPUT (SI)
This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI pin, starting with D15 to D0. The internal registers of the 33894 are configured and controlled using a 5-bit addressing scheme described in Table 7, page 19. Register addressing and configuration are described in Table 8, page 20. The SI input has an active internal pulldown, IDWN.
CHIP SELECT (CS)
The CS pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the MCU. The 33894 latches in data from the input shift registers to the addressed registers on the rising edge of CS. The device transfers status information from the power output to the Shift register on the falling edge of CS. The SO output driver is enabled when CS is logic [0]. CS should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CS has an active internal pullup, IUP.
SERIAL OUTPUT (SO)
The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until the CS pin is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, and the state of the key inputs. The SO pin changes state on the rising edge of SCLK and reads out on the falling edge of
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The 33894 has four operating modes: Sleep, Normal, Fault, and Fail-Safe. Table 5 summarizes details contained in succeeding paragraphs. Table 5. Fail-Safe Operation and Transitions to Other 33894 Modes
Mode Sleep Normal FS x 1 0 Fault 0 0 1 1 1 FailSafe WAK RST WDTO E 0 x 1 1 x 0 1 1 0 1 1 0 1 1 1 0 Yes Watchdog has timed out and the device is in FailSafe mode. The outputs are as configured with the RFS resistor connected to FSI. RST and WAKE must be transitioned to logic [0] simultaneously to bring the device out of the Fail-safe mode or momentarily tied the FSI pin to ground. No x No Comments Device is in Sleep mode. All outputs are OFF Normal mode. Watchdog is active if enabled. Device is currently in Fault mode. The faulted output(s) is (are) OFF.
FAIL-SAFE MODE
Fail-Safe Mode and Watchdog If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or the RST input pin transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance limiting the internal clamp current according to the specification. The Watchdog timeout is a multiple of an internal oscillator and is specified in the Table 14, page 22. As long as the WD bit (D15) of an incoming SPI message is toggled within the minimum watchdog timeout period (WDTO), based on the programmed value of the WDR, the device will operate normally. If an internal watchdog timeout occurs before the WD bit, the device will revert to a Fail-Safe mode until the device is reinitialized. During the Fail-Safe mode, the outputs will be ON or OFF depending upon the resistor RFS connected to the FSI pin, regardless of the state of the various direct inputs and modes (Table 6). Table 6. Output State During Fail-Safe Mode
RFS (k) 0 6.0 15 High-Side State Fail-Safe Mode Disabled All HS OFF HS0 ON HS1 : HS3 OFF HS0 and HS2 ON HS1 and HS3 OFF
x = Don't care.
SLEEP MODE
The default mode of the 33894 is the Sleep mode. This is the state of the device after first applying battery voltage (VPWR) prior to any I/O transitions. This is also the state of the device when the WAKE and RST are both logic [0]. In the Sleep mode, the output and all unused internal circuitry, such as the internal 5.0 V regulator, are OFF to minimize current draw. In addition, all SPI-configurable features of the device are as if set to logic [0]. The 33894 will transition to the Normal or Fail-Safe operating modes based on the WAKE and RST inputs as defined in Table 5.
30
NORMAL MODE
The 33894 is in Normal mode when: * VPWR is within the normal voltage range. * RST pin is logic [1]. * No fault has occurred.
In the Fail-Safe mode, the SPI register content is retained except for overcurrent high and low detection levels and timing, which are reset to their default value (SOCL, SOCH, and OCTL). Then the watchdog, overvoltage, overtemperature, and overcurrent circuitry (with default value) are fully operational. The Fail-Safe mode can be detected by monitoring the WDTO bit D2 of the WD register. This bit is logic [1] when the device is in Fail-Safe mode. The device can be brought out of the Fail-Safe mode by transitioning the WAKE and RST pins from logic [1] to logic [0] or forcing the FSI pin to logic [0]. Table 5 summarizes the various methods for resetting the device from the latched Fail-Safe mode. If the FSI pin is tied to GND, the Watchdog fail-safe operation is disabled.
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Loss of VDD If the external 5.0 V supply is not within specification, or even disconnected, all register content is reset. The outputs can still be driven by the direct inputs IN0 : IN3. The 33894 uses the battery input to power the output MOSFET-related current sense circuitry and any other internal logic, providing fail-safe device operation with no VDD supplied. In this state, the watchdog, overvoltage, overtemperature, and overcurrent circuitry are fully operational with default values.
device will be sustained. This ensures that when the battery level then returns above 5.75 V, the 33894 can be returned to the state that it was in prior to the low VPWR excursion. Once the output latches OFF, the outputs must be turned OFF and ON again to re-enable them. In the case IN1 : IN0 = 0, this fault is non-latched. The undervoltage protection can be disabled through SPI (bit UV_DIS). When disabled, the returned SO bit OD14 still reflects any undervoltage condition (undervoltage warning). Open Load Fault (Non-Latching) The 33894 incorporates open load detection circuitry on the output. Output open load fault (OLF) is detected and reported as a fault condition when the output is disabled (OFF). The open load fault is detected and latched into the Status register after the internal gate voltage is pulled low enough to turn OFF the output. The OLF fault bit is set in the Status register. If the open load fault is removed, the Status register will be cleared after reading the register. The open load protection can be disabled trough SPI (bit OL_DIS). Overcurrent Fault (Latching) The 33894 has eight programmable overcurrent low detection levels (IOCL) and two programmable overcurrent high detection levels (IOCH) for maximum device protection. The two selectable, simultaneously active overcurrent detection levels, defined by IOCH and IOCL, are illustrated in Figure 6, page 14. The eight different overcurrent low detect levels (IOCL0 : IOCL7) are illustrated in Figure 6. If the load current level ever reaches the selected overcurrent low detection level and the overcurrent condition exceeds the programmed overcurrent time period (tOCx), the device will latch the output OFF. If at any time the current reaches the selected IOCH level, then the device will immediately latch the fault and turn OFF the output, regardless of the selected tOCLx driver. For both cases, the device output will stay off indefinitely until the device is commanded OFF and then ON again.
FAULT MODE
This 33894 indicates the faults below as they occur by driving the FS pin to logic [0]: * Overtemperature fault * Overvoltage and undervoltage fault * Open load fault * Overcurrent fault (high and low) The FS pin automatically returns to logic [1] when the fault condition is removed, except for overcurrent and in some cases undervoltage faults. Fault information is retained in the Fault register and is available (and reset) via the SO pin during the first valid SPI communication (refer to Table 16, page 23). Overtemperature Fault (Non-Latching) The 33894 incorporates overtemperature detection and shutdown circuitry in the output structure. Overtemperature detection is enabled when the output is in the ON state. For the output, an overtemperature fault (OTF) condition results in the faulted output turning OFF until the temperature falls below the TSD(HYS). This cycle will continue indefinitely until action is taken by the MCU to shut OFF the output, or until the offending load is removed. When experiencing this fault, the OTF fault bit will be set in the Status register and cleared after either a valid SPI read or a power reset of the device. Overvoltage Fault (Non-Latching) The 33894 shuts down the output during an overvoltage fault (OVF) condition on the VPWR pin. The output remains in the OFF state until the overvoltage condition is removed. When experiencing this fault, the OVF fault bit is set in the bit D1 and cleared after either a valid SPI read or a power reset of the device. The overvoltage protection can be disabled through SPI (bit OV_DIS). When disabled, the returned SO bit OD13 still reflects any overvoltage condition (overvoltage warning). Undervoltage Shutdown (Latching or Non-Latching) The output latches OFF at some battery voltage between 4.75 V and 5.75 V. As long as the VDD level stays within the normal specified range, the internal logic states within the
REVERSE BATTERY
The output survives the application of reverse voltage as low as -16 V. Under these conditions, the output's gate is enhanced to keep the junction temperature less than 150C. The ON resistance of the output is fairly similar to that in the Normal mode. No additional passive components are required.
GROUND DISCONNECT PROTECTION
In the event the 33894 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless of the state of the output at the time of disconnection.
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SOLDERING INFORMATION
The 33894 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board. The 33894 was qualified in accordance with JEDEC standards JESD22-A113-B and J-STD-020A. The recommended reflow conditions are as follows:
* Convection: 235C +5 .0 / -0C * Vapor Phase Reflow (VPR): 235C +5 .0 / -0C * Infrared (IR) / Convection: 235C +5 .0 / -0C The maximum peak temperature during the soldering process should not exceed 240C. The time at maximum temperature should range from 10 s to 40 s maximum.
LOGIC COMMANDS AND REGISTERS
CSB CS
CS
SCLK
SI
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SO
OD15 OD14 OD13 OD12 OD11 OD10 OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1 OD0
NOTES: 1. 2. 3.
Notes 1. RST is a logic [1] state during the above operation. RSTB is in a 2. D15:D0 logic H state during the aboveordered entry of data into the device. relate to the most recent operation. device. DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC 3. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the device. device. OD0, OD1, OD2, ..., and OD15 relate to the first 16 bits of ordered fault and status data out of the LUX IC
Figure 9. Single 16-Bit Word SPI Communication
SERIAL INPUT COMMUNICATION
SPI communication is accomplished using 16-bit messages. A message is transmitted by the MCU starting with the MSB D15 and ending with the LSB, D0 (Table 7). Each incoming command message on the SI pin can be interpreted using the following bit assignments: the MSB, D15, is the watchdog bit. In some cases, output selection is done with bits D12 : D11. The next three bits, D10 : D8, are used to select the command register. The remaining five bits, D4 : D0, are used to configure and control the outputs and their protection features. Multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is not 16 bits will be ignored. The 33894 has defined registers, which are used to configure the device and to control the state of the outputs. Table 8, page 20, summarizes the SI registers.
Table 7. SI Message Bit Assignment
Bit Sig MSB SI Msg Bit D15 D14 : D15 D12 : D11 D10 : D8 D7 : D5 D4 : D1 Message Bit Description Watchdog in: toggled to satisfy watchdog requirements. Not used. Register address bits used in some cases for output selection. Register address bits. Not used. Used to configure the inputs, outputs, and the device protection features and SO status content. Used to configure the inputs, outputs, and the device protection features and SO status content.
LSB
D0
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Table 8. Serial Input Address and Configuration Bit Map
SI Data SI Register D15 STATR OCR0 OCR1 SOCHLR_s CDTOLR_s DICR_s UOVR WDR NAR TEST WDIN WDIN WDIN WDIN WDIN WDIN WDIN WDIN WDIN WDIN D14 D13 D12 D11 D10 D9 x x x x x x x x x x x x x x x x x x x x x x x A1 A1 A1 x x x x x 0 1 A0 A0 A0 0 1 x x 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 0 1 1 D8 0 1 1 0 1 0 1 1 0 1 D7 x x x x x x x x x x D6 x x x x x x x x x x D5 x x x x x x x x x x D4 SOA4 x x x x x x x x x D3 SOA3 IN3_SPI CSNS3 EN SOCH_s OL_DIS_s D2 SOA2 IN2_SPI CSNS2 EN SOCL2_s OCL_DIS_s D1 SOA1 IN1_SPI D0 SOA0 IN0_SPI
CSNS1 EN CSNS0 EN SOCL1_s OCLT1_s SOCL0_s OCLT0_s A/O_s OV_DIS WD0
FAST_SR_s CSNS_high_ DIR_DIS_s s x x x x UV_DIS WD1
No Action (Allow Toggling of D15-WDIN) Freescale Internal Use (Test)
x = Don't care. s = Output selection with the bits A1A0 as defined in Table 9.
DEVICE REGISTER ADDRESSING
The following section describes the possible register addresses and their impact on device operation.
summed. In the event that bits D3 : D0 are all logic [0], the output CSNS will be tri-stated. This is useful when several CSNS pins of several devices share the same A /D converter.
ADDRESS XX000 -- STATUS REGISTER (STATR)
The STATR register is used to read the device status and the various configuration register contents without disrupting the device operation or the register contents. The register bits D4 : D0 determine the content of the first sixteen bits of SO data. In addition to the device status, this feature provides the ability to read the content of the OCR0, OCR1, SOCHLR, CDTOLR, DICR, UOVR, WDR, and NAR registers. (Refer to the section entitled Serial Output Communication (Device Status Return Data) beginning on page 22.)
ADDRESS A1A0010 -- SELECT OVERCURRENT HIGH AND LOW REGISTER (SOCHLR_S)
The SOCHLR_s register allows the MCU to configure the output overcurrent low and high detection levels, respectively. Each output "s" is independently selected for configuration based on the state of the D12 : D11 bits (Table 9). Table 9. Output Selection
A1 (D12) A0 (D11) 0 1 0 1 HS_s HS0 HS1 HS2 HS3
ADDRESS X0001-- OUTPUT CONTROL REGISTER (OCR0)
The OCR0 register allows the MCU to control the ON/OFF state of four outputs through the SPI. Incoming message bit D3 : D0 reflects the desired states of the four high-side outputs (INx_SPI), respectively. A logic [1] enables the corresponding output switch and a logic [0] turns it OFF.
0 0 1 1
ADDRESS X1001-- OUTPUT CONTROL REGISTER (OCR1)
Incoming message bits D3 : D0 reflect the desired output that will be mirrored on the Current Sense (CSNS) pin. A logic [1] on message bits D3 : D0 enables the CSNS pin for outputs HS3 : HS0, respectively. In the event the current sense is enabled for multiple outputs, the current will be
Each output can be configured to different levels. In addition to protecting the device, this slow blow fuse emulation feature can be used to optimize the load requirements matching system characteristics. Bits D2 : D0 set the overcurrent low detection level to one of eight possible levels, as shown in Table 10, page 21. Bit D3 sets the overcurrent high detection level to one of two levels, as outlined in Table 11, page 21.
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Table 10. Overcurrent Low Detection Levels
SOCL2_s* SOCL1_s* SOCL0_s* (D2) (D1) (D0) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Overcurrent Low Detection (Amperes) HS0 : HS3 9.1 8.15 7.2 6.25 5.25 4.3 3.35 2.4
A logic [1] on bit D2 (OCL_DIS_s) disables the overcurrent low detection feature. When disabled, there is no timeout for the selected output and the overcurrent low detection feature is disabled. A logic [1] on bit D3 (OL_DIS_s) disables the open load (OL) detection feature for the output corresponding to the state of bits D12 : D11.
ADDRESS A1A0100 -- DIRECT INPUT CONTROL REGISTER (DICR)
The DICR register is used by the MCU to enable, disable, or configure the direct IN pin control of each output. Each output is independently selected for configuration based on the state bits D12 : D11 (refer to Table 9, page 20). For the selected output, a logic [0] on bit D1 (DIR_DIS_s) will enable the output for direct control. A logic [1] on bit D1 will disable the output from direct control. While addressing this register, if the Input was enabled for direct control, a logic [1] for the D0 (A/O_s) bit will result in a Boolean AND of the IN pin with its corresponding IN_SPI D4 : D0 message bit when addressing OCR0. Similarly, a logic [0] on the D0 pin results in a Boolean OR of the IN pin to the corresponding message bits when addressing the OCR0. This register is especially useful if several loads are required to be independently PWM controlled. For example, the IN pins of several devices can be configured to operate all of the outputs with one PWM output from the MCU. If each output is then configured to be Boolean ANDed to its respective IN pin, each output can be individually turned OFF by SPI while controlling all of the outputs, commanded on with the single PWM output. A logic [1] on bit D2 (CSNS_high_s) is used to select the high ratio on the CSNS pin for the selected output. The default value [0] is used to select the low ratio (Table 13). Table 13. Current Sense Ratio
Current Sense Ratio CSNS_high_s* (D2) HS0 : HS3 0 1 1/6500 1/20000
* "_s" refers to the output, which is selected through bits D12 : D11;
refer to Table 9, page 20.
Table 11. Overcurrent High Detection Levels
Overcurrent High Detection (Amperes) SOCH_s* (D3) HS0 : HS3 0 1 50 35
* "_s" refers to the output, which is selected through bits D12 : D11;
refer to Table 9, page 20.
ADDRESS A1A0011 -- CURRENT DETECTION TIME AND OPEN LOAD REGISTER (CDTOLR)
The CDTOLR register is used by the MCU to determine the amount of time the device will allow an overcurrent low condition before an output latches OFF. Each output is independently selected for configuration based on A1A0 , which are the state of the D12 : D11 bits (refer to Table 9, page 20). Bits D1 : D0 (OCLT1_s : OCLT0_s) allow the MCU to select one of three overcurrent fault blanking times defined in Table 12. Note that these timeouts apply only to the overcurrent low detection levels. If the selected overcurrent high level is reached, the device will latch off within 20 s. Table 12. Overcurrent Low Detection Blanking Time
OCLT[1:0]_s* 00 01 10 11 refer to Table 9, page 20. Timing 155 ms Do not use 75 ms 150 s
* "_s" refers to the output, which is selected through bits D12 : D11;
refer to Table 9, page 20.
A logic [1] on bit D3 (FAST_SR_s) is used to select the high speed slew rate for the selected output, the default value [0] corresponds to the low speed slew rate.
ADDRESS X0101 -- UNDERVOLTAGE/ OVERVOLTAGE REGISTER (UOVR)
The UOVR register disables the undervoltage (D1) and/or overvoltage (D0) protection. When these two bits are logic [0], the undervoltage and overvoltage are active (default value).
* "_s" refers to the output, which is selected through bits D12 : D11;
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ADDRESS X1101 -- WATCHDOG REGISTER (WDR)
The WDR register is used by the MCU to configure the Watchdog timeout. The Watchdog timeout is configured using bits D1 and D0. When D1 and D0 bits are programmed for the desired watchdog timeout period (Table 14), the WDSPI bit should be toggled as well, ensuring the new timeout period is programmed at the beginning of a new count sequence. Table 14. Watchdog Timeout
WD[1 : 0] (D1 : D0) 00 01 10 11 Timing (ms) 620 310 2500 1250
SO data will represent information ranging from fault status to register contents, user selected by writing to the STATR bits OD4, OD3, OD2, OD1, and OD0. The value of the previous bits SOA4 and SOA3 will determine which output the SO information applies to for the registers which are output specific; viz., Fault, SOCHLR, CDTOLR, and DICR registers. Note that the SO data will continue to reflect the information for each output (depending on the previous OD4, OD3 state) that was selected during the most recent STATR write until changed with an updated STATR write. The output status register correctly reflects the status of the STATR-selected register data at the time that the CS is pulled to a logic [0] during SPI communication, and/or for the period of time since the last valid SPI communication, with the following exceptions: *The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred. *Battery transients below 6.0 V resulting in an undervoltage shutdown of the outputs may result in incorrect data loaded into the Status register. The SO data transmitted to the MCU during the first SPI communication following an undervoltage VPWR condition should be ignored. *The RST pin transition from a logic [0] to logic [1] while the WAKE pin is at logic [0] may result in incorrect data loaded into the Status register. The SO data transmitted to the MCU during the first SPI communication following this condition should be ignored.
ADDRESS XX110 -- NO ACTION REGISTER (NAR)
The NAR register can be used to no-operation fill SPI data packets in a daisy-chain SPI configuration. This would allow devices to be unaffected by commands being clocked over a daisy-chained SPI configuration. By toggling the WD bit (D15) the watchdog circuitry would continue to be reset while no programming or data read back functions are being requested from the device.
ADDRESS XX111 -- TEST
The TEST register is reserved for test and is not accessible with SPI during normal operation.
SERIAL OUTPUT BIT ASSIGNMENT
The 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 15, page 23, summarizes SO returned data for bits OD15 : OD0. *Bit OD15 is the MSB; it reflects the state of the Watchdog bit from the previously clocked-in message. *Bit OD14 remains logic [0] except when an undervoltage condition occurred. *Bit OD13 remains logic [0] except when an overvoltage condition occurred. *Bits OD12 : OD8 reflect the state of the bits SOA4 : SOA0 from the previously clocked in message. *Bits OD7 : OD4 give the fault status flag of the outputs HS3 : HS0, respectively. *The contents of bits OD3 : OD0 depend on bits D4 : D0 from the most recent STATR command SOA4 : SOA0 as explained in the paragraphs following Table 15.
SERIAL OUTPUT COMMUNICATION (DEVICE STATUS RETURN DATA)
When the CS pin is pulled low, the output register is loaded. Meanwhile, the data is clocked out MSB- (OD15-) first as the new message data is clocked into the SI pin. The first 16 bits of data clocking out of the SO, and following a CS transition, is dependent upon the previously written SPI word. Any bits clocked out of the SO pin after the first 16 bits will be representative of the initial message bits clocked into the SI pin since the CS pin first transitioned to logic [0]. This feature is useful for daisy chaining devices as well as message verification. A valid message length is determined following a CS transition of logic [0] to logic [1]. If there is a valid message length, the data is latched into the appropriate registers. A valid message length is a multiple of 16 bits. At this time, the SO pin is tri-stated and the fault status register is now able to accept new fault status information.
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Table 15. Serial Output Bit Map Description
Previous STATR
SO SO SO SO SO A4 A3 A2 A1 A0 A1 A0 x x 0 1 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 0 1 1 0 1 1 0 1 0 1 1 0 0 OD 15
WDIN WDIN WDIN WDIN WDIN WDIN WDIN WDIN WDIN WDIN
SO Returned Data
OD 14
UVF UVF UVF UVF UVF UVF UVF UVF UVF UVF
OD 13
OVF OVF OVF OVF OVF OVF OVF OVF OVF OVF
OD 12
OD 11
OD 10
OD9
OD8
OD7
ST3 ST3 ST3 ST3 ST3 ST3 ST3 ST3 ST3 ST3
OD6
ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2 ST2
OD5
ST1 ST1 ST1 ST1 ST1 ST1 ST1 ST1 ST1 ST1
OD4
ST0 ST0 ST0 ST0 ST0 ST0 ST0 ST0 ST0 ST0
OD3 OTF_s IN3_SPI CSNS3 EN SOCH_s OL_DIS_s Fast_SR_s - - HS2_failsaf IN3
OD2 OCHF_s IN2_SPI CSNS2 EN SOCL2_s OCL_DIS_s CSNS_high_s - WDTO HS0_failsaf IN2
OD1 OCLF_s IN1_SPI CSNS1 EN SOCL1_s OCLT1_s DIR_DIS_s UV_DIS WD1 WD_en IN1
OD0 OLF_s IN0_SPI CSNS0 EN SOCL0_s OCLT0_s A/O_s OV_DIS WD0 WAKE IN0
SOA4 SOA3 SOA2 SOA1 SOA0 SOA4 SOA3 SOA2 SOA1 SOA0 SOA4 SOA3 SOA2 SOA1 SOA0 SOA4 SOA3 SOA2 SOA1 SOA0 SOA4 SOA3 SOA2 SOA1 SOA0 SOA4 SOA3 SOA2 SOA1 SOA0 SOA4 SOA3 SOA2 SOA1 SOA0 SOA4 SOA3 SOA2 SOA1 SOA0 SOA4 SOA3 SOA2 SOA1 SOA0 SOA4 SOA3 SOA2 SOA1 SOA0
A1 A0 A1 A0 A1 A0 x x x x 0 1 0 1
x = Don't care. s = Output selection with the bits A1A0 as defined in Table 9, page 20.
PREVIOUS ADDRESS SOA4 : SOA0 = A1A0000
Bits OD3 : OD0 reflect the current state of the Fault register (FLTR) corresponding to the output previously selected with the bits A1A0 (Table 16). Table 16. Output-Specific Fault Register
OD3 OTF_s OD2 OCHF_s OD1 OCLF_s OD0 OLF_s
PREVIOUS ADDRESS SOA4 : SOA0 = A1A0011
The returned data contains the programmed values in the CDTOLR register for the output selected with A1A0.
PREVIOUS ADDRESS SOA4 : SOA0 = A1A0100
The returned data contains the programmed values in the DICR register for the output selected with A1A0.
PREVIOUS ADDRESS SOA4 : SOA0 = X0101
The returned data contains the programmed values in the UOVR register.
s = Selection of the output.
Note The FS pin reports all faults. For latched faults, this pin is reset by a new Switch ON command (via SPI or direct input IN).
PREVIOUS ADDRESS SOA4 : SOA0 = X1101
The returned data contains the programmed values in the WDR register. Bit OD2 (WDTO) reflects the status of the watchdog circuitry. If WDTO bit is logic [1], the watchdog has timed out and the device is in Fail-Safe mode. IF WDTO is logic [0], the device is in Normal mode (assuming the device is powered and not in the Sleep mode), with the watchdog either enabled or disabled.
PREVIOUS ADDRESS SOA4 : SOA0 = X0001
Data in bits OD3 : OD0 contains IN3_SPI : IN0_SPI programmed bits for outputs HS3 : HS0, respectively.
PREVIOUS ADDRESS SOA4 : SOA0 = X1001
Data in bits OD3 : OD0 contains the programmed CSNS3 EN : CSNS0 EN bits for outputs HS3 : HS0, respectively.
PREVIOUS ADDRESS SOA4 : SOA0 = X0110
The returned data OD3 and OD2 contain the state of the outputs HS2 and HS0, respectively, in case of Fail-Safe state. This information is stated with the external resistance placed at the FSI pin. OD1 indicates if the watchdog is enabled or not. OD0 returns the state of the WAKE pin.
PREVIOUS ADDRESS SOA4 : SOA0 = A1A0010
Data returned in bits OD3 : OD0 are programmed current values for the overcurrent high detection level (refer to Table 11, page 21) and the overcurrent low detection level (refer to Table 10, page 21), corresponding to the output previously selected with A1A0.
PREVIOUS ADDRESS SOA4 : SOA0 = X1110
The returned data OD3 : OD0 reflects the state of the direct pins IN3 : IN0, respectively.
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PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current revision of the package, visit www.freescale.com and perform a keyword search using the "98A" drawing number listed below.
PNA SUFFIX 24-PIN PQFN NON-LEADED PACKAGE 98ARL10596D ISSUE C
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING
PNA SUFFIX 24-PIN PQFN NON-LEADED PACKAGE 98ARL10596D ISSUE C
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Analog Integrated Circuit Device Data Freescale Semiconductor
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PACKAGING
PNA SUFFIX 24-PIN PQFN NON-LEADED PACKAGE 98ARL10596D ISSUE C
33894
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Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION 3.0
DATE 10/2006
DESCRIPTION OF CHANGES * * * Implemented Revision History page Converted to Freescale format and updated with the prevailing form and style Updated to the current package drawing 98ARL10596D, REV C
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MC33894 Rev 3.0 10/2006

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