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H5GQ1H24AFR
1Gb (32Mx32) GDDR5 SGRAM H5GQ1H24AFR
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 1
H5GQ1H24AFR Revision History
Revision No. 0.1 0.2 0.3 0.4 0.5 0.6 Defined target spec. Updated tRTPS / tRTW / tFAW / t32AW / Thermal Characteristics Updated tCKE / Pin Cap / CRCWL / CRCRL/ IDD / PLL Value Updated tRRDL / Revision ID/ Density ID Removed tFLK / tSTDBYLK Updated tCKE / tCKSRE / tCKSRX (@ 6Gbps only) Updated Updated Updated Updated Updated Updated CRCWL / VREFD Selection Coding Auto VREFD Training tCKE & tPD Leakage Current x16 Mode IDD Value & 1.35V Timing Parameters Ordering Information History Draft Date Dec. 2008 Mar. 2009 April. 2009 May. 2009 May. 2009 July. 2009 Remark Preliminary Preliminary Preliminary Preliminary Preliminary Preliminary
0.7 1.0
VREFD Options Figure31 change Revision 1.0 Release
Sep. 2009 Nov. 2009
Preliminary
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TABLE OF CONTENTS
FEATURES........................................................................................................................................................5 FEATURES..............................................................................................................................................5 FUNCTIONAL DESCRIPTION....................................................................................................................5 DEFINITION OF SINGLE STATE TERMINOLOGY....................................................................................................7 CLOCKING..........................................................................................................................................................8 INITIALIZATION................................................................................................................................................10 POWER UP SEQUENCE...........................................................................................................................10 INITIALIZATION WITH STABLE POWER..................................................................................................11 VENDOR ID...........................................................................................................................................13 ADDRESS.........................................................................................................................................................15 ADDRESSING.........................................................................................................................................15 ADDRESS BUS INVERSION(ABI)..............................................................................................................16 BAND GROUP........................................................................................................................................18 TRAINING........................................................................................................................................................21 INTERFACE TRAINING SEQUENCE..........................................................................................................21 ADDRESS TRAINING..............................................................................................................................22 WCK2CK TRAINING...............................................................................................................................25 READ TRAINING...................................................................................................................................32 WRITE TRAINING.................................................................................................................................38 MODE REGISTER..............................................................................................................................................41 Mode REGISTER 0(MR0).......................................................................................................................42 Mode REGISTER 1(MR1).......................................................................................................................45 Mode REGISTER 2(MR2).......................................................................................................................48 Mode REGISTER 3(MR3).......................................................................................................................50 Mode REGISTER 4(MR4).......................................................................................................................52 Mode REGISTER 5(MR5).......................................................................................................................55 Mode REGISTER 6(MR6).......................................................................................................................57 Mode REGISTER 7(MR7).......................................................................................................................60 Mode REGISTER 15(MR15)....................................................................................................................62 OPERATION......................................................................................................................................................63 COMMAND.............................................................................................................................................63 DESELECT.............................................................................................................................................65 NO OPERATION.....................................................................................................................................65 MODE REGISTER SET.............................................................................................................................65 ACTIVATION..........................................................................................................................................66 BANK RESTRITIONS...............................................................................................................................68 WRITE (WOM).......................................................................................................................................70 WRITE DATA MAS(DM)...........................................................................................................................89
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READ....................................................................................................................................................86 DQ PREAMBLE .....................................................................................................................................95 READ AND WRITE DATA BUS INVERSION (DBI).......................................................................................97 ERROR DETECTION CODE.....................................................................................................................99 PRECHARGE........................................................................................................................................103 AUTO PRECHARGE...............................................................................................................................104 REFRESH.............................................................................................................................................104 SELF REFRESH....................................................................................................................................106 POWER-DOWN....................................................................................................................................109 COMMAND TRUTH TABLE.....................................................................................................................110 RDQS MODE........................................................................................................................................114 CLOCK FREQUENCY CHANGE SEQUENCE..............................................................................................116 DYNAMIC VOLTAGE SWITCHING(DVS).................................................................................................117 TEMPERATURE SENSOR.......................................................................................................................119 DUTY CYCLE CORRECTOR....................................................................................................................120 OPERATING CONDITIONS................................................................................................................................122 Absolute Maximum Ratings...................................................................................................................122 AC & DC Characteristics........................................................................................................................124 CLOCK TO DATA TIMING SENSITIVITY..................................................................................................148 PACKAGE SPECIFICATION................................................................................................................................151 BALL-OUT...............................................................................................................................................151 SIGNALS.................................................................................................................................................153 ON DIE TERMINATION(ODT)....................................................................................................................156 PACKAGE DIMENSIONS...........................................................................................................................157 MIRROR FUNCTION(MF) ENABLE AND X16 MODE ENABLE.................................................................................158 BOUNDARY SCAN............................................................................................................................................163
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 4
H5GQ1H24AFR
FEATURES
FUNCTIONAL DESCRIPTION
* Singleendedinterfacefordata,addressandcommand The GDDR5 SGRAM is a high speed dynamic * QuarterdataratedifferentialclockinputsCK/CK#for randomaccess memory designed for applications ADR/CMD requiring high bandwidth. GDDR5 devices contain * TwohalfdataratedifferentialclockinputsWCK/ WCK#,eachassociatedwithtwodatabytes(DQ,DBI#, thefollowingnumberofbits: EDC) * DoubleDataRate(DDR)data(WCK) 1Gbhas1,073,741,824bitsandsixteenbanks * SingleDataRate(SDR)command(CK) * DoubleDataRate(DDR)addressing(CK) * 16internalbanks The GDDR5 SGRAM uses a 8n prefetch * 4bankgroupsfortCCDL=3tCK * 8nprefetcharchitecture:256bitperarrayreadorwrite architecture and DDR interface to achieve high access speed operation. The device can be configured to * Burstlength:8only operate in x32 mode or x16 (clamshell) mode. The * ProgrammableCASlatency:5to20tCK mode is detected during device initialization. The * ProgrammableWRITElatency:1to7tCK GDDR5 interface transfers two 32 bit wide data * WRITEDatamaskfunctionviaaddressbus(single/ doublebytemask) words per WCK clock cycle to/from the I/O pins. * Databusinversion(DBI)&addressbusinversion Corresponding to the 8nprefetch a single write or (ABI) readaccessconsistsofa256bitwide,twoCKclock * Input/outputPLLon/offmode cycledatatransferattheinternalmemorycoreand * Addresstraining:addressinputmonitoringbyDQ pins eightcorresponding32bitwideonehalfWCKclock * WCK2CKclocktrainingwithphaseinformationby cycledatatransfersattheI/Opins. EDCpins The GDDR5 SGRAM operates from a differential * DatareadandwritetrainingviaREADFIFO clock CK and CK#. Commands are registered at * READFIFOpatternpreloadbyLDFFcommand everyrisingedgeofCK.Addressesareregisteredat * DirectwritedataloadtoREADFIFObyWRTR command every rising edge of CK and every rising edge of * ConsecutivereadofREADFIFObyRDTRcommand CK#. * Read/Writedatatransmissionintegritysecuredby GDDR5 replaces the pulsed strobes (WDQS & cyclicredundancycheck(CRC8) RDQS) used in previous DRAMs such as GDDR4 * READ/WRITEEDCon/offmode * ProgrammableEDCholdpatternforCDR with a free running differential forwarded clock * ProgrammableCRCREADlatency=0to3tCK (WCK/WCK#) with both input and output data * ProgrammableCRCWRITElatency=7to14tCK registered and driven respectively at both edges of * LowPowermodes theforwardedWCK. * RDQSmodeonEDCpin * Optionalonchiptemperaturesensorwithreadout ReadandwriteaccessestotheGDDR5SGRAMare * Auto&selfrefreshmodes burstoriented;anaccessstartsataselectedlocation * Autoprechargeoptionforeachburstaccess andconsistsofatotalofeightdatawords.Accesses * 32ms,autorefresh(8kcycles) beginwiththeregistrationofanACTIVEcommand, * Temperaturesensorcontrolledselfrefreshrate * Ondietermination(ODT);nominalvaluesof60ohm which is then followed by a READ or WRITE and120ohm command. The address bits registered coincident * Pseudoopendrain(POD15)compatibleoutputs(40 withtheACTIVEcommandandthenextrisingCK# ohmpulldown,60ohmpullup) * ODTandoutputdrivestrengthautocalibrationwith edge are used to select the bank and the row to be accessed. The address bits registered coincident externalresistorZQpin(120ohm) * Programmableterminationanddriverstrengthoffsets with the READ or WRITE command and the next * SelectableexternalorinternalVREFfordatainputs; risingCK#edgeareusedtoselectthebankandthe programmableoffsetsforinternalVREF columnlocationfortheburstaccess. * SeparateexternalVREFforaddress/commandinputs * VendorID,FIFOdepthandDensityinfofieldsfor identification * x32/x16modeconfigurationsetatpowerupwithEDC pin * MirrorfunctionwithMFpin * BoundaryscanfunctionwithSENpin * 1.6V/1.5V+/0.045Vsupplyfordeviceoperation (VDD) * 1.6V/1.5V+/0.045VsupplyforI/Ointerface(VDDQ) * 170ballBGApackage
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H5GQ1H24AFR
ORDERING INFORMATION
PartNo H5GQ1H24AFR-R0C H5GQ1H24AFR-T3C H5GQ1H24AFR-T2L (Note1) H5GQ1H24AFR-T2C H5GQ1H24AFR-T1C H5GQ1H24AFR-T0C VDD/VDDQ=1.5V PowerSupply VDD/VDDQ=1.6V CKFrequency WCKFrequency MaxDataRate 1.50GHz 1.375GHz 1.25GHz 1.25GHz 1.125GHz 1.00GHz 3.00GHz 2.75GHz 2.50GHz 2.50GHz 2.25GHz 2.00GHz 6.0Gbps/pin 5.5Gbps/pin 5.0Gbps/pin 5.0Gbps/pin 4.5Gbps/pin 4.0Gbps/pin POD_15 Interface
Above Hynix P/N's are Leead-free, RoHS Compliant and Halogen-free. Note.1)It supports not only 5Gbps @ 1.5V, but also 3.2Gbps @ 1.35V.
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0.1.DEFINITIONOFSIGNALSTATETERMINOLOGY
GDDR5SGRAMwillbeoperatedinbothODTEnable(terminated)andODTDisable(unterminated) modes.ForhighestdataratesitisrecommendedtooperateintheODTEnablemode.ODTDisablemode isdesignedtoreducepowerandmayoperateatreduceddatarates.ThereexistsituationswhereODT Enablemodecannotbeguaranteedforashortperiodoftime,i.e.duringpowerup. Followingarefourterminologiesdefinedforthestateofadevice(GDDR5SGRAMorcontroller)pindur ingoperation.Thestateofthebuswillbedeterminedbythecombinationofthedevicepinsconnectedto thebusinthesystem.ForexampleinGDDR5itispossiblefortheSGRAMpintobetristatedwhilethe controllerpinisHighorODT.InbothcasesthebuswouldbeHighiftheODTisenabled.Fordetailson theGDDR5SGRAMpinsandtheirfunctionsee"PACKAGESPECIFICATION"onpage 156and"SIG NALS"onpage 158inthesectionentitled"PACKAGESPECIFICATION"onpage 156.
Devicepinsignallevel:
* High:AdevicepinisdrivingtheLogic"1"state. * Low:AdevicepinisdrivingtheLogic"0"state. * HiZ:Adevicepinistristate. * ODT:AdevicepinterminateswithODTsetting,whichcouldbeterminatingortristatedependingonMode Registersetting.
Bussignallevel:
* High:OnedeviceonbusisHighandallotherdevicesonbusareeitherODTorHiZ.Thevoltagelevelonthebus wouldbenominallyVDDQ * Low:OnedeviceonbusisLowandallotherdevicesonbusareeitherODTorHiZ.Thevoltagelevelonthebus wouldbenominallyVOL(DC)ifODTwasenabled,orVSSQifHiZ. * HiZ:AlldevicesonbusareHiZ.Thevoltagelevelonbusisundefinedasthebusisfloating. * ODT:AtleastonedeviceonbusisODTandallothersareHiZ.Thevoltagelevelonthebuswouldbenominally VDDQ.
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0.2.CLOCKING
TheGDDR5SGRAMoperatesfromadifferentialclockCKandCK#.Commandsareregisteredatevery risingedgeofCK.AddressesareregisteredateveryrisingedgeofCKandeveryrisingedgeofCK#. GDDR5usesaDDRdatainterfaceandan8nprefetcharchitecture.Thedatainterfaceusestwodifferen tialforwardedclocks(WCK/WCK#).DDRmeansthatthedataisregisteredateveryrisingedgeofWCK andrisingedgeofWCK#.WCKandWCK#arecontinuouslyrunningandoperateattwicethefrequency ofthecommand/addressclock(CK/CK#).
CK# CK
COMMAND
ADDRESS
WCK# WCK DQ*1
Figure 1:GDDR5ClockingandInterfaceRelationship
Note:Figure.1showstherelationshipbetweenthedatarateofthebusesandtheclocksandisnotatimingdiagram.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 8
H5GQ1H24AFR
.
Controller
ADD/CMDcenteredwithCK/CK# CMD/ADD
D Q
GDDR5SGRAM
CMDsampledbyCK/CK#asSDR ADDsampledbyCK/CK#asDDR
D Q QB
CMD/ADD
DRAM core
CK/CK# (1GHz) Oscillator PLL
WCK2CK Alignment
DataTx/Rx
D
Q
PLL
/2
WCK/WCK# (2GHz) ToEDCpin WCKint (1GHz) early/late ClockPhase Controller Phasedetector/ Phaseaccumulator corelogic early/latefrom calibrationdata DQ[0][7] (4Gbps)
Q
D
Q
D
Receiver clock ClockPhase Controller
DQ
D D Q
Q
DRAM core
For8databits
Figure 2:BlockDiagramofanexampleclocksystem
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 9
H5GQ1H24AFR 1.INITIALIZATION
1.1.POWERUPSEQUENCE
GDDR5 SGRAMs must be powered up and initialized in a predefined manner as shown in Figure . Operational procedures other than those specified may result in undefined operation. The Mode Registers do not have RESET default values, except for ABI#, ADR/CMD termination, and the EDC hold pattern. If the mode registers are not set during the initialization sequence, it may lead to unspecified operation.
Step 1 2 3 4 5 6 7 ApplypowertoVDD ApplypowertoVDDQatsametimeorafterpowerisappliedtoVDD ApplyVREFCandVREFDatsametimeorafterpowerisappliedtoVDDQ Afterpowerisstable,providestableclocksignalsCK/CK# AssertandholdRESET#lowtoensurealldriversareinHiZandallactiveterminationsareoff.AssertandholdNOPcommand. Waitaminimumof200s. Ifboundaryscanmodeisnecessary,SENcanbeassertedHIGHtoenterboundaryscanmode.Boundaryscanmodemustbe entereddirectlyafterpowerupwhileRESET#islow.Onceboundaryscanisexecuted,powerupsequenceshouldbefollowed. SetCKE#forthedesiredADR/CMDODTsettings,thenbringRESET#HightolatchinthelogicstateofCKE#,tATSandtATHmust bemetduringthisprocedure.SeeTable1forthevaluesandlogicstatesforCKE#.TherisingedgeofRESET#willdetermine x32modeorx16modedependingonthestateofEDC1(EDC2whenMF=1).Innormalx32mode,EDC1hastobesustainedHIGH untilRESET#isHIGH.SeeTableforthevaluesandlogicstatesforEDC1(EDC2whenMF=1). BringCKE#LowaftertATHissatisfied Waitatleast200sreferencedfromthebeginningoftATS Issueatleast2NOPcommands IssueaPRECHARGEALLcommandfollowedbyNOPcommandsuntiltRPissatisfied IssueMRScommandtoMR15.SetGDDR5SGRAMintoaddresstrainingmode(optional) Completeaddresstraining(optional) IssueMRScommandtoreadtheVendorID IssueMRScommandtosetWCK01/WCK01#andWCK23/WCK23#terminationvalues ProvidestableclocksignalsWCK01/WCK01#andWCK23/WCK23# IssueMRScommandstousePLLornotandselectthepositionofaWCK/CKphasedetector.TheuseofPLLandthepositionofa phasedetectorshouldbeissuedbeforeWCK2CKtraining.IssueMRScommandsincludingPLLresettothemoderegistersinany order.tMRDmustbemetduringthisprocedure.WLmrs,CLmrs,CRCWLandCRCRLmustbeprogrammedbeforeWCK2CK training. IssuetwoREFRESHcommandsfollowedbyNOPuntiltRFCissatisfied AfteranynecessaryGDDR5trainingsequencessuchasWCK2CKtraining,READtraining(LDFF,RDTR)andWRITEtraining (WRTR,RDTR),thedeviceisreadyforoperation.
8
9 10 11 12 13 14 15 16 17
18
19 20
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 10
H5GQ1H24AFR
Table 1AddressandCommandTermination
VALUE(OHMS) ZQ/2 ZQ CKE#atRESET#hightransition Low High
VDD VDDQ VREFD/C
(( ))
(( )) (( ))
(( ))
(( ))
(( ))
(( ))
(( ))
(( ))
tATS tATH
(( ))
RESET#
(( ))
(( ))
CKE# CK# CK CMD
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
(( ))
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
(( ))
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
(( ))
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
(( ))
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( ))
NOP
NOP( (
NOP
NOP
PRE
NOP
TRAIN/MRS ((
)) (( ))
A.C.
A.C.
ADR DQ<31:0>, DBI#<3:0> EDC<3,0>
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
TRAIN/MRS ((
)) (( ))
ADR
ADR ADR ADR (( ((
)) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
TRAIN/MRS ((
)) (( )) ))
TRAIN/MRS ((
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
EDC<2,1> WCK# WCK
x32 x16
(( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( ))
TRAIN/MRS ((
)) (( )) (( ))
AllBanks Precharge min.200s Voltagesand CKstable Note:A.C.=AnyCommand min.200s tRP
Executionofsteps 1321inPowerup sequence
Figure 3:GDDR5SGRAMPowerupInitialization
1.2.Initialization with Stable Power Thefollowingsequenceisrequiredforresetsubsequenttopowerupinitialization.Thisrequiresthatthe powerhasbeenstablewithinthespecifiedVDDandVDDQrangessincepowerupinitialization(See
Figure 4)
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H5GQ1H24AFR
1)AssertRESET#Lowanytimewhenresetisneeded. 2)HoldRESET#Lowforminimum100ns.AssertandholdNOPcommand. 3)SetCKE#forthedesiredADR/CMDODTsettings,thenbringRESET#Hightolatchinthelogicstateof CKE#;tATSandtATHmustbemetduringthisprocedure.KeepEDC1(MF=0)/EDC2(MF=1)atthesame logiclevelasduringpowerupinitializationasdevicefunctionalityisnotguaranteediftheI/Owidthhas changed. 4)Continuewithstep9ofthepowerupinitializationsequence.
VDD,VDDQ VREFD/C
(( ))
(( ))
(( ))
(( ))
(( ))
(( ))
tATS tATH
(( ))
RESET#
(( ))
(( ))
CKE# CK# CK CMD
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
(( ))
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( (( )) )) (( )) (( )) (( ))
(( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( ))
NOP
NOP( (
NOP
NOP
PRE
NOP
TRAIN/MRS ((
)) (( ))
A.C.
A.C.
ADR DQ<31:0>, DBI#<3:0> EDC<3:0> WCK# WCK
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
TRAIN/MRS ((
)) (( ))
ADR
ADR ADR ADR (( ((
)) (( )) (( )) (( )) (( )) (( )) (( )) )) (( )) (( )) (( )) (( )) (( )) (( ))
TRAIN/MRS ((
)) (( )) )) (( )) (( ))
TRAIN/MRS ((
AllBanks Precharge min.100ns min.200s tRP
Executionofsteps 1321inPowerup sequence
Notes:1.A.C.=AnyCommand 2.Devicefunctionalityisnotguaranteedifx32/x16modeisnotthesameasduringpowerupinitialization.
Figure 4:InitializationwithStablePower
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H5GQ1H24AFR
1.2.VENDORID
GDDR5SGRAMsarerequiredtoincludeaVendorIDfeaturethatallowsthecontrollertoreceiveinforma tionfromtheGDDR5SGRAMtodifferentiatebetweendifferentvendorsanddifferentdevicesusinga softwarealgorithm. WhentheVendorIDfunctionisenabledtheGDDR5SGRAMwillprovideitsManufacturersVendorCode onbits[3:0]asshowninTable2;RevisionIdentificationonbits[7:4];Densityonbits[9:8];FIFODepthon bits[11:10]asshowninTable3&Table4.Bits[15:12]areRFU. VendorIDispartoftheINFOfieldofModeRegister3(MR3)andisselectedbyissuingaMODEREGIS TERSETcommandwithMR3bitA6setto1,andbitA7setto0.MR3bitsA0A5andA8A11aresettothe desiredvalues. TheVendorIDwillbedrivenontotheDQbusaftertheMRScommandthatsetsbitsA6to1andA7to0. TheDQbuswillbecontinuouslydrivenuntilanMRScommandsetsMR3A6andA7backto0todisable theINFOfieldortoanothervalidstatefortheINFOfieldiftheINFOfieldincludessupportforadditional vendorspecificinformation.TheDQbuswillbeinODTstateaftertWRIDOFF(max).Thecodecanbesam pledbythecontrollerafterwaitingtWRIDON(max)andbeforetWRIDOFF(min).DBIisnotenabledor ignoredduringallVendorIDoperations.Table4showsthemappingoftheVendorIDinfotothephysical DQs.The16bitsofVendorIDaresentonByte0and2whenMF=0.WhenMF=1the16bitsaresenton Byte1and3.Optionallythevendormayreplicatethedataontheother2byteswheninx32mode.Byte0 wouldbereplicatedonByte1andByte2wouldbereplicatedonByte3whenMF=0.WhenMF=1,Byte1 wouldbereplicatedonByte0andByte3wouldbereplicatedonByte2. TABLE2.ManufacturersVendorCode
ManufacturersID 0 1 2 3 4 5 6 7 8 9 A B C D E F Bit3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 NameofCompany Reserved Samsung Qimonda Elpida Etron Nanya Hynix ProMOS Winbond ESMT Reserved Reserved Reserved Reserved Reserved Micron
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H5GQ1H24AFR
Table 3RevisionID&Density&FIFODepth
RevisionID Bit7 0 Bit6 0 Bit6 0 Bit4 1 Bit9 0 Density Bit8 1 Bit11 1 FIFO Bit10 0
Table 4VendorIDtoDQmapping
Bit MF=0 MF=1 Feature Bit MF=0 MF=1 Feature 15 DQ23 DQ15 7 DQ7 DQ31 6 DQ6 DQ30 5 DQ5 DQ29 4 DQ4 DQ28 3 DQ3 DQ27 2 DQ2 DQ26 1 DQ1 DQ25 0 DQ0 DQ24
RevisionIdentification 14 DQ22 DQ14 RFU 13 DQ21 DQ13 12 DQ20 DQ12 11 DQ19 DQ11
ManufacturersVendorCode 10 DQ18 DQ10 9 DQ17 DQ9 Density 8 DQ16 DQ8
FIFODepth
CK# CK CMD BA0BA3 A2A5 A8 A7 A11 A6 A9,A10 A0,A1 NOP MRS
MRA Code
NOP
NOP
NOP
NOP
MRS
MRA Code
NOP
NOP
NOP
NOP
Code
Code
Code
Code
Code Code
Code Code
tWRIDON(max) DQ VendorID+RevCode
tWRIDOFF(min)
MRA=ModeRegisterAddress;Code=Opcodetobeloaded
DontCare
Figure 5:VendorIDTimingDiagram
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H5GQ1H24AFR 2.ADDRESS
2.1.ADDRESSING
GDDR5SGRAMsuseadoubledatarateaddressschemetoreducepinsrequiredontheGDDR5SGRAM asshowninTable5.TheaddressesshouldbeprovidedtotheGDDR5SGRAMintwoparts;thefirsthalfis latchedontherisingedgeofCKalongwiththecommandpinssuchasRAS#,CAS#andWE#;thesecond halfislatchedonthenextrisingedgeofCK#. TheuseofDDRaddressingallowsalladdressvaluestobelatchedinatthesamerateastheSDRcom mands.Alladdressesrelatedtocommandaccesshavebeenpositionedforlatchingontheinitialrising edgeforfasterdecoding.
Table 5AddressPairs
Clock RisingCK RisingCK# BA3 A3 BA2 A4 BA1 A5 BA0 A2 (A12) (RFU) A11 A6 A10 A0 A9 A1 A8 A7
Note:AddresspinA12isrequiredonlyfor2Gdensity.
GDDR5addressingincludessupportfor1Gdensity.Foralldensitiestwomodesaresupported(x32mode orx16mode).x32andx16modesdifferonlyinthenumberofvalidcolumnaddresses,asshowninTable6.
Table 6AddressingScheme
1G x32mode Rowaddress Columnaddress Bankaddress Autoprecharge PageSize Refresh Refreshperiod A0~A11 A0~A5 BA0~BA3 A8 2K 8K/32ms 3.9us x16mode A0~A11 A0~A6 BA0~BA3 A8 2K 8K/32ms 3.9us
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H5GQ1H24AFR
2.2.ADDRESSBUSINVERSION(ABI)
AddressBusInversion(ABI)reducesthepowerrequirementsonaddresspins,astheno.ofaddresslines drivingalowlevelcanbelimitedto4(incaseA12/RFUisnotwired)or5(incaseA12/RFUiswired). TheAddressBusInversionfunctionisassociatedwiththeelectricalsignallingontheaddresslines betweenacontrollerandtheGDDR5SGRAM,regardlessofwhethertheinformationconveyedonthe addresslinesisaroworcolumnaddress,amoderegisteropcode,adatamask,oranyotherpattern. TheABI#inputisanactiveLowdoubledatarate(DDR)signalandsampledbytheGDDR5SGRAMatthe risingedgeofCKandtherisingedgeofCK#alongwiththeaddressinputs. OnceenabledbythecorrespondingABIModeRegisterbit,theGDDR5SGRAMwillinvertthepattern receivedontheaddressinputsincaseABI#wassampledLow,orleavethepatternnoninvertedincase ABI#wassampledHigh,asshowninFigure6.
Address Pins ABI# 8(9) 8(9) to DRAM core
fromModeRegister: 0=enabled 1=disabled
Note:buswidthis8whenA12/RFUpinisnotpresent,and9whenA12/RFUpinispresent
Figure 6:ExampleofAddressBusInversionLogic
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H5GQ1H24AFR
TheflowdiagraminFigure7illustratestheABIoperation.Thecontrollerdecideswhethertoinvertornot invertthedataconveyedontheaddresslines.TheGDDR5SGRAMhastoperformthereverseoperation basedontheleveloftheABI#pin.AddressinputtimingparametersareonlyvalidwithABIbeingenabled andamaximumof4addressinputsdrivenLow.
Controller
Datatobesent onaddresslines Determine'0' count
No
'0'count >4?
Yes
ABI#='H' Don'tinvert
ABI#='L' Invert
ABI#='H' Don'tinvert
ABI#='L' Invert
GDDR5 SGRAM
Datareceived onaddresslines
Figure 7:AddressBusInversion(ABI)FlowDiagram
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2.3.BANKGROUPS
ForGDDR5SGRAMdevicesoperatingatfrequenciesaboveacertainthreshold,theactivitywithinabank groupmustberestrictedtoensureproperoperationofthedevice.The8or16banksinGDDR5SGRAMs aredividedintofourbankgroups.ThebankgroupsfeatureiscontrolledbybitsA10andA11inMode Register3(MR3).TheassignmentofthebankstothebankgroupsisshowninTable7.
Table 7BankGroups
Bank 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Addressing BA3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BA2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BA1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BA0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GroupD GroupC GroupB GroupA 1G 16banks
Thesebankgroupsallowthespecificationofdifferentcommanddelayparametersdependingonwhether backtobackaccessesaretobankswithinonebankgrouporacrossbankgroupsasshowninTable8.
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Table 8CommandSequencesAffectedbyBankGroups
CorrespondingACTimingParameter CommandSequence BankGroups Disabled tRRDS tCCDS tCCDS tWTRS tRTPS BankGroupsEnabled Accessestodifferentbank Accesseswithinthesame groups bankgroup tRRDS tCCDS tCCDS tWTRS 1tck tRRDL tCCDL tCCDL tWTRL tRTPL 1 Notes
ACTIVEtoACTIVE WRITEtoWRITE READtoREAD InternalWRITEtoREAD READtoPRECHARGE
Note.1:ParameterstRTPSandtRTPLapplyonlywhenREADandPRECHARGEgotothesamebank;usetRTPSwhenBGare disabled,andtRTPLwhenBGareenabled.
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Back-to-back column accesses based on tCCDL and tCCDS parameters.
Example1(BankGroupsdisabled):tCCDS=2*tCK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
CLK
CAS A0 DQ A0
A1 A1
B0 B0
B1 B1
C0 C0
C1 C1
D0 D0
Example2:(BankGroupsenabled):tCCDL=4*tCK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
CLK
CAS A0 DQ A0
A1 A1
A2 A2
A3 A3
Example3:(BankGroupsenabled):tCCDS=2*tCK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
CLK
CAS A0 DQ A0
B0 B0
A1 A1
B1 B1
C0 C0
D0 D0
C1 C1
Notes: 1)Columnaccessesaretoopenbanks,andtRCDhasbeenmet. 2)CL=0assumed 3)Ax,Bx,Cx,Dx:accessestobankgroupsA,B,CorD,respectively 4)Withbankgroupsenabled,tCCDLis3tCK,asprogrammedinMR3.
Rev. 1.0 /Nov. 2009 20
H5GQ1H24AFR 3.TRAINING
3.1.INTERFACETRAININGSEQUENCE
DuetothehighdataratesofGDDR5,itisrecommendedthattheinterfacesbetrainedtooperatewiththe optimaltimings.GDDR5SGRAMhasfeaturesdefinedwhichallowforcompleteandefficienttrainingof theI/OinterfacewithouttheuseoftheGDDR5SGRAMarray.Theinterfacetrainingsarerequiredfornor malDRAMfunctionalityunlessrunninginlowerfrequencymodesasdescribedinthelowfrequencysec tion.Interfacetimingswillonlybeguaranteedafterallrequiredtrainingshavebeenexecuted. Arecommendedorderoftrainingsequenceshasbeenchosenbasedonthefollowingcriteria: TheaddresstrainingmustbedonefirsttoallowfullaccesstotheModeRegisters.(MRSforaddresstrain ingisaspecialsingledataratemoderegistersetguaranteedtoworkwithouttraining).Addressinputtim ingshallfunctionwithouttrainingaslongastAS/HaremetattheGDDR5SGRAM. WCK2CKtrainingshouldbedonebeforereadtrainingbecauseashiftinWCKrelativeCKwillcausea shiftinallREADtimingsrelativetoCK. READtrainingshouldbedonebeforeWRITEtrainingbecauseoptimalWRITEtrainingdependsoncor rectREADdata.
Initialization
AddressTraining(optional)
WCK2CKAlignmentTraining
READTraining
WRITETraining
StartNormalOperation
Figure 8:InterfaceTrainingSequence
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3.2.ADDRESSTRAINING
TheGDDR5SGRAMprovidesmeansforaddressbusinterfacetraining.Thecontrollermayusethe addresstrainingmodetoimprovethetimingmarginsontheaddressbus. AddresstrainingmodeisenteredandexitedviatheADTbitinModeRegister15(MR15).ModeRegister 15supportsthesamesetupandholdtimesontheaddresspinsasforcommandstoallowasafeentryinto addresstrainingmode. AddresstrainingmodeusesaninternalbridgebetweentheGDDR5SGRAM'saddressinputsandDQ/ DBI#outputs.ItalsousesaspecialREADcommandforaddresscapturethatisencodedusingtheSDR commandpinsonly(CS#,RAS#,CAS#,WE#=L,H,L,H).Theaddressvaluesnormallyusedtoencodethe commandswillnotbeinterpreted.Oncetheaddresstrainingmodehasbeenentered,theaddressvalues registeredcoincidentwiththisspecialREADcommandwillbetransmittedtothecontrollerontheDQ/ DBI#pins.Thecontrolleristhenexpectedtocomparetheaddresspatternreceivedtotheexpectedvalue andtoadjusttheaddresstransmittimingaccordingly.Theproceduremayberepeatedusingdifferent addresspatternandinterfacetimings. NoWCKclockisrequiredforthisspecialREADcommandoperationduringaddresstrainingmode.The latchedaddressesaredrivenoutasynchronously. TheonlycommandsallowedduringaddresstrainingmodearethisspecialREAD,MRS(e.g.toexit addresstrainingmode)andNOP/DESELECT. WhenenabledbytheABIbitinModeRegister1,addressbusinversion(ABI)iseffectiveduringaddress trainingmode.ItissuggestedtotraintheABI#pin'sinterfacetimingtogetherwiththeotheraddresslines. ThetimingdiagraminFigure9illustratesthetypicalcommandsequenceinaddresstrainingmode.The DQ/DBI#outputdriversareenabledaslongastheADTbitisset.Theminimumspacingbetweenconsec utivespecialREADcommandsis2tCK.
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H5GQ1H24AFR
CK# CK CMD MRS NOP READ(*) NOP READ(*) NOP READ(*) NOP MRS NOP NOP NOP NOP
ADDR
MR15 A10=1
ADRx ADRx R# R
ADRy ADRy R R#
ADRz ADRz R R#
MR15 A10=0
tMRD tADR Even DQ Odd DQ
tADR tADR
tADZ
ADRx R ADRx R#
ADRy R ADRy R#
ADRz R ADRz R#
Notes: 1)READcommandencoding:CS#=L,RAS#=H,CAS#=L,WE#=H 2)ADRxR=1sthalfofaddressx,sampledonrisingedgeofCK; ADRxR#=2ndhalfofaddressx,sampledonrisingedgeofCK# 3)AddressessampledonrisingedgeofCKarereturnedonevenDQaftertADR; addressessampledonrisingedgeofCK#arereturnedonoddDQsimultaneouslywithevenDQ 4)DQsareenabledwhenADTbitinModeRegister15setto1(EnterAddressTrainingMode) DQsaredisabledaftertADZwhenADTbitinModeRegister15setto0(ExitAddressTrainingMode)
DontCare
Figure 9:AddressTrainingTiming Table 9ACtimingsinAddressTrainingMode
Parameter READcommandtodataoutdelay ADTofftoDQ/DBI#inODTstatedelay Symbol tADR tADZ Min 0.5*tCK+0 Max 0.5*tCK+10 0.5*tCK+10 Unit ns ns
Table10definesthecorrespondencebetweenaddressbitsandDQ/DBI#.Devicesconfiguredtox16mode reflecttheaddressonthetwobytesbeingenabledinthatmode,whicharebytes0and2forMF=0and bytes1and3forMF=1configurations.Devicesconfiguredtox32modereflecttheaddressonthesameDQ asinx16mode;inadditiontheyareallowedbutnotrequiredtoreflecttheaddressonthosebytesthatare disabledinx16mode,thusreflectingeachaddresstwice. DevicesnotsupportinganA12/RFUpinshalldrivealogicHighontheDBI#pins.
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Table 10AddresstoDQMappinginAddressTrainingMode
Output DQ AddressbitsregisteredatrisingedgeofCK A12 DBI0# DBI1# A8 DQ22 DQ30 A11 DQ20 DQ28 BA1 DQ18 DQ26 BA2 DQ16 DQ24 BA3 DQ6 DQ14 BA0 DQ4 DQ12 A9 DQ2 DQ10 A10 DQ0 DQ8
Output DQ
AddressbitsregisteredatrisingedgeofCK# RFU DBI2# DBI3# A7 DQ23 DQ31 A6 DQ21 DQ29 A5 DQ19 DQ27 A4 DQ17 DQ25 A3 DQ7 DQ15 A2 DQ5 DQ13 A1 DQ3 DQ11 A0 DQ1 DQ9
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H5GQ1H24AFR
3.3.WCK2CKTRAINING
ThepurposeofWCK2CKtrainingistoalignthedataWCKclockwiththecommandCKclocktoaidinthe GDDR5SGRAM'sinternaldatasynchronizationbetweenthelogicclockedbyCK/CK#andWCK/WCK#. ThiswillhelptodefinebothReadandWritelatenciesbetweentheGDDR5SGRAMandmemorycontrol ler.WCK2CKtrainingmodeiscontrolledviaMRS.
BeforestartingWCK2CKtraining,thefollowingconditionsmustbemet:
* CK/CK#clockisstableandtoggling * Thetimingofalladdressandcommandpinsmustbeguaranteed * PLLon/off(MR1bitA7)andPLLdelaycompensationenable(MR7bitA2)aresettodesiredmodebeforeWCKto CKtrainingisstarted * ThedesiredWCK2CKalignmentpoint(MR6,bitA0)isselected * TheEDCholdpattern(MR4,bitsA0A3)mustbeprogrammedto`1111' * 2ModeRegisterbitsforinternalWCK01andWCK23inversion(MR3,bitsA2A3)mustbesettoaknownstate * Allbanksareidleandnoothercommandexecutionisinprogress
WCK2CKtrainingmustbedoneafteranyofthefollowingconditions:
* Deviceinitialization * AnyCLmrs,WLmrs,CRCRLorCRCWLlatencychange * CKandWCKfrequencychanges * PLLon/off(MR1bitA7)andPLLdelaycompensationmode(MR7bitA2)changes * ChangeoftheWCK2CKalignmentpoint(MR6,bitA0) * WCKstatechangefromofftotoggling,includingselfrefreshexitorexitfrompowerdownwhenbitA1(LP2)in MR5isset
Figure10andFigure11showexampleWCK2CKtrainingsequences.WCK2CKtrainingisenteredvia MRSbysettingbitA4inMR3.ThiswillinitiatetheWCKdivideby2circuitsassociatedwithWCK01and WCK23clocksintheGDDR5SGRAM.Incasethedivideby2circuitsareatoppositeoutputphases, whichisindicatedbyopposite"early/late"phasesontheEDCpinsassociatedwithWCK01andWCK23 (seebelow),theymaybeputinphasebyusingtheWCK01andWCK23inversionbits.Alternatively,the WCKclocksmaybeputintoastableinactivestateforthisinitializationeventtoaidinresettingalldivid erstothesameoutputphaseasshowninFigure11.Thechallengeofthismethodistorestartthe WCKclocksinawaythateventheirfirstclockedgesmeettheWCKclockinputspecification.Otherwise, divideby2circuitsforbothWCK01andWCK23mightagainhaveoppositephasealignment. Figure12illustrateshowtheWCKphaseinformationisderived.Thephasedetectors(PD)samplethe internallydividedby2WCKclocks.Onlyonesamplepointisshowninthefigureforclarity.Inreality, whenWCK2CKtrainingmodeisenabled,asamplewilloccureverytCKandwillbetranslatedtotheEDC pinsaccordingly.Ifthedividedby2WCKclockarrivesearly,thentheEDCpinoutputstheEDChold patternduringthetimeintervalspecifiedinFigure12.Ifthedividedby2WCKclockarriveslate,thenthe EDCpinoutputstheinvertedEDCholdpatternduringthetimeintervalspecifiedinFigure12.Thisis showninTable11.
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CK CK# CMD WCK WCK# tLK EnterWCK2CKTraining StartWCK2CK PhaseSearch PLLReset (PLLononly) tMRD ExitWCK2CKTraining (setsdatasynchronizers, restsFIFOpointers) NOP NOP MRS NOP NOP NOP NOP MRS MRS A.C.
Figure 10:ExampleWCK2CKTrainingSequence
CK# CK CMD WCK WCK# tWCK2MRS tMRSTWCK tWCK2TR tLK tMRD NOP MRS NOP NOP NOP NOP NOP NOP MRS MRS Valid
EnterWCK2CK TrainingbyMRS (resetsWCKdivide by2circuits)
WCK Restart
StartWCK2CK PhaseSearch
PLLReset (PLLononly)
ExitWCK2CK TrainingbyMRS (Setdatasynchronizers, resetsFIFOpointers)
Figure 11:ExampleWCK2CKTrainingSequencewithWCKStopping
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H5GQ1H24AFR
CK 1 WCK01/2 WCK23/2 (internal) 1 Early EDC0 EDC2
tWCK2CK
WCKEarly
x
x
x
x
x
x
x
~ ~
x
1111 tWCKTPH
x
x
x
x
x
x
x
WCK01/2 WCK23/2 (internal) 2 Late EDC0 EDC2
0 +tWCK2CK WCKLate
x
x
x
x
x
x
x
~ ~
x
0000 tWCKTPH
x
x
x
x
x
x
x
WCK01/2 WCK23/2 (internal) 3 Aligned EDC0 EDC2
x
x
x
x
x
x
x
~ ~
x
x
x
x
x
x
x
x
x
x
x
x
tWCKTPH
Figure 12:EDCpinBehaviourforWCK2CKTraining(assumes`1111'asEDCHoldPattern)
Table 11PhaseDetectorandEDCPinbehavior
WCK/2valuesampledbyCK `1' `0' WCK2CKPhase `Early' `Late' DataonEDCPin EDChold(`1111') InvertedEDCHold(`0000') Action IncreaseDelayonWCK DecreaseDelayonWCK
Theidealalignmentisindicatedbythephasedetectoroutputtransitioningfrom"early"to"late"when thedelayoftheWCKphaseiscontinuouslyincreased.TheWCKphaserangeforidealalignmentisspeci fiedbytheparametertWCK2CKPIN;thevalue(s)varywiththePLLmode(onoroff)andtheselectedalign mentpoint. Ifenabled,thePLLshallnotinterfereinthebehavioroftheWCK2CKtraining.Significantlymovingthe phaseand/orstoppingtheWCKduringtrainingmaydisturbthePLL.ItisrequiredtoperformaPLLreset aftertheWCK2CKtraininghasdeterminedandselectedtheproperalignmentbetweenWCKandCK clocks.ThePLLlocktimetLKmustbemetbeforeexitingWCK2CKtrainingtoguaranteethatthePLLisin locksuchthattheGDDR5SGRAMdatasynchronizersaresetuponWCK2CKtrainingexit. WCK2CKtrainingisexitedviaMRSbyresettingbitA4inMR3.Forproperresetofthedatasynchronizers itisrequiredthattheWCKandCKclocksarealignedwithintWCK2CKSYNCatthetimeoftheWCK2CK trainingexit.
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AfterexitingWCK2CKtrainingmode,theWCKphaseisallowedtofurtherdriftfromtheidealalignment pointbyamaximumoftWCK2CK(e.g.duetovoltageandtemperaturevariation).OncethisWCKphase driftexceedstWCK2CK(min)ortWCK2CK(max),itisrequiredtorepeattheWCK2CKtrainingandrealign theclocks.
WCK2CKalignmentatPINMode TheWCKandCKphasealignmentpointcanbechangedviaMRSbysettingbitA0inMR6.Innormal mode,whenMR6A0issetto`0',thephasesofCKandWCKarealignedatCKpinsandtheendofWCK treeasshowninFigure13.Ontheotherhand,whenMR6A0issetto`1',thephasesofCKandWCKare alignedatthepinasshowninFigure14.PINmodeissupporteduptothemaxCKclockfrequencyof fCKPIN,andisanoptiontoreducethetimeofWCK2CKtrainingatlowfrequency.
WCK WCK# CK CK# EDC
D CK
Q InternalWCK/2
Phase Detector
InternalCK
Figure 13:NormalMode
WCK WCK# CK CK# EDC
D CK
Q InternalWCK/2
Phase Detector
InternalCK
Figure 14:PinMode
WCK2CKAutoSynchronization GDDR5SGRAMssupportaWCK2CKautomaticsynchronizationmodethateliminatestheneedfor WCK2CKtraininguponpowerdownexit.Thismodeiscontrolledbytheautosyncbit(MR7,bitA4),and iseffectivewhentheLP2bit(MR5,bitA1)issetandtheWCKclocksarestoppedduringpowerdown.
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H5GQ1H24AFR
Also,thismodeworksforbothnormalandPINmode.WhenWCK2CKautomaticsynchronizationmode isenabled,afullWCK2CKtrainingincludingPhasesearchisnotrequiredafterpowerdownexit, althoughWCK2CKMRSmustbeissuedmomentarilyforsettingthedatasynchronizers.However,WCK andCKclocksmustmeetthetWCK2CKSYNCspecificationuponpowerdownexit.Anyallowedcommand maybeissuedaftertXPNoraftertLKincasethePLLhadbeenenableduponpowerdownentry.ThePLL sequenceisnotaffectedbythismode.TheuseofWCK2CKautomaticsynchronizationmodeisrestricted toloweroperatingfrequenciesuptofCKAUTOSYNCasdescribedinthedatasheets. Table12describesWCK2CKtrainingmethodsfordifferentfrequencyranges.EachFrequencyrangeis vendorspecific.NormalandPINmodeofWCK2CKtrainingaredescribedinTable12.Eachfrequency rangeisDRAMvendorspecific.DividerinitializationcanbedonebytrainingwithWCK2CKinversion, WCK2CKstopping,orWCK2CKautosync.IftheuserwantstouseWCK2CKstopfordividerinitializa tioninsteadofWCK2CKautosync,theusermustnotsettheWCK2CKautosync.Lowfrequency,the combineduseofPINandWCK2CKautosyncmodescanminimizeWCK2CKtrainingtime.
Table 12WCK2CKtrainingsimplifiedforNormalmodeandPINmode
HighFrequency Frequency WCK2CKalignmentmode
PhaseSearch
LowFrequency 2Gbps
2Gbps Normal
Required
PIN
Required
Normal
No*
PIN
No*
*Note:ThedividedWCK/WCK#shouldbealignedCK/CK#byWCK2CKAutoSynchronizationorWCKstopmode
ThefollowingexamplesdescribetheWCK2CKtraininginmoredetail. Example1:outlineofabasicWCK2CKtrainingsequencewithoutWCKclockstop: 1) EnabletrainingmodeviaMRSandwaittMRD 2) SweepandobservethephaseindependentlyforWCK01onEDC0andWCK23onEDC2;incase theinternaldivideby2circuitsareatoppositephaseuseeithertheWCK01orWCK23inversion bit tofliponeoftheWCKdivideby2circuits 3) AdjusttheWCKphaseindependentlyforWCK01andWCK23totheoptimalpoint("ideal alignment") 4) IssueaPLLresetandwaitfortLK(PLLonmodeonly) 5) WhileallWCKandCKarealigned,exitWCK2CKtrainingmodeviaMRS 6) WaittMRDfortheresetofdatasynchronizers
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Example2:outlineofabasicWCK2CKtrainingsequencewithoptionalWCKclockstop: 1) StopWCKclockswithWCK01/WCK23LOWandWCK01#/WCK23#HIGH 2) WaittWCK2MRSforinternalWCKclockstosettle 3) EnabletrainingmodeviaMRSandwaittMRDfordivideby2circuitstoreset 4) StartWCKclockswithoutglitches(bothdivideby2circuitsremaininsync) 5) WaittWCK2TRforinternalWCKclockstostabilize 6) SweepandobservethephaseindependentlyforWCK01onEDC0andWCK23onEDC2;adjust the WCKphasetotheoptimalpoint("idealalignment") 7) IssueaPLLresetandwaittLK(PLLonmodeonly) 8) WhileallWCKandCKarealigned,exitWCK2CKtrainingmodeviaMRS 9) WaittMRDfortheresetofdatasynchronizers
READandWRITElatencytimingsaredefinedrelativetoCK.AnyoffsetinWCKandCKatthepinsand/ orthephasedetectorwillbereflectedinthelatencytimings.Theparametersusedtodefinetherelation shipbetweenWCKandCKareshowninFigure6.FormoredetailsontheimpactonREADandWRITE timingsseetheOPERATIONSsection.
tCK CK# CK
tCH
tCL
Case1:NegativetWCK2CKPIN;tWCK2CK=0(idealWCK2CKalignment) tWCKH tWCKL tWCK tWCK2CKPIN WCK# WCK Case2:NegativetWCK2CKPIN;negativetWCK2CK WCK# WCK Case3:PositivetWCK2CKPIN;tWCK2CK=0(idealWCK2CKalignment) WCK# WCK Case4:PositivetWCK2CKPIN;positivetWCK2CK WCK WCK#
Note: tWCK2CKPINandtWCK2CKparametervaluescouldbenegativeorpositivenumbers,dependingontheselected WCK2CKalignmentpoint,PLLonorPLLoffmodeoperationanddesignimplementation.Theyalsovaryacross PVT.WCK2CKtrainingisrequiredtodeterminethecorrectWCKtoCKphaseforstabledeviceoperation.
tWCK2CKPIN+tWCK2CK
tWCK2CKPIN
tWCK2CKPIN+tWCK2CK
Figure 15:WCK2CKTimings
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GDDR5WCK2CKTraininginx16mode ForconfigurationswithWCKclocksnotsharedbetweentwoGDDR5SGRAMsitissuggestedtosetthe WCKphasetotheidealalignmentpoint.However,forconfigurationswheretwoGDDR5SGRAMs(x16) sharetheirWCKclocksasinax16clamshell,anoffsetgivenbythemidpointofbothDRAM'sidealWCK positionsmayberequired.Themaximumallowedoffsetinthiscaseisspecifiedbyparameter tWCK2CKSYNC:itdefinestheWCKoffsetrangefromtheidealalignmentwhichstillguaranteesaGDDR5 SGRAMdevicetointernallysynchronizeitsWCKandCKclocksupontrainingexit. Example:outlineoftrainingsequenceforx32andx16configurationswith2GDDR5SGRAMssharing theirWCKclocks(e.g.clamshell): 1) EnabletrainingmodeforbothDRAMsviaMRSandwaittMRD 2) ForbothDRAMssweepandobservethephaseindependentlyforWCK01onEDC0andWCK23 on EDC2;incasetheinternaldivideby2circuitsareatoppositephasesuseeithertheWCK01or WCK23inversionbittofliponeoftheWCKdivideby2circuits;incaseofsharedCS#signalsuse MREMF0andMREMF1bitsinMR15toexplicitlydirecttheMRScommandforthisphaseflipping toeitherDRAM1orDRAM2("softchipselect"); 3) SweepandobservethephaseonDRAM1independentlyforWCK01onEDC0andWCK23on EDC2;storethesettingfortheoptimalWCKphase 4) SweepandobservethephaseonDRAM2independentlyforWCK01onEDC0andWCK23on EDC2;storethesettingfortheoptimalWCKphase 5) SweepWCK01andWCK23phasetomidpointofDRAM1andDRAM2optimalsettings 6) IssueaPLLresetandwaitfortLK(PLLonmodeonly) 7) WhileallWCKandCKarealigned,exitWCK2CKtrainingmodeviaMRS 8) WaittMRDfortheresetofdatasynchronizers
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3.4.READTRAINING
Readtrainingallowsthememorycontrollertofindthedataeyecenter(symboltraining)andburstframe location(frametraining)foreachhighspeedoutputoftheGDDR5SGRAM.Eachpin(DQ0DQ31,DBI0# DBI3#,EDC0EDC3)canbeindividuallytrainedduringthissequence. ForReadTrainingthefollowingconditionsmustbetrue:
* atleastonebankisactive,oranautorefreshmustbeinprogressandbitA2inModeRegister5(MR5)issetto0to allowtrainingduringautorefresh(todisablethisspecialREFenablingoftheWCKclocktreeanACTcommand mustbeissued,orthedevicemustbesetintopowerdownorselfrefreshmode) * WCK2CKtrainingmustbecomplete * thePLLmustbelocked,ifenabled * RDBIandWDBImustbeenabledpriortoandduringReadTrainingifthetrainingshallincludetheDBI#pins. RDCRCandWRCRCmustbeenabledpriortoandduringReadTrainingifthetrainingshallincludetheEDC pins.
ThefollowingcommandsareassociatedwithReadTraining:
* LDFFtopreloadtheReadFIFO; * RDTRtoreadaburstofdatadirectlyoutoftheReadFIFO.
NeitherLDFFnorRDTRaccessthememorycore.NoMRSisrequiredtoenterReadTraining. Figure16showsanexampleoftheinternaldatapathsusedwithLDFFandRDTR.Table13listsACtiming parametersassociatedwithReadTraining.
Table 13LDFFandRDTRTIMINGS
VALUES PARAMETER ACTIVEtoLDFFcommanddelay ACTIVEtoRDTRcommanddelay REFRESHtoRDTRorWRTRcommanddelay RDTRtoRDTRcommanddelay LDFFtoLDFFcommandcycletime LDFF(111)toLDFFcommandcycletime LDFF(111)toRDTRcommanddelay READorRDTRtoLDFFcommanddelay
a. Themin.valuedoesnotexceed8tCK.
SYMBOL MIN tRCDLTR tRCDRTR tREFTR tCCDS tLTLTR tLTL7TR tLTRTR tRDTLT 10 10 10 2 4 4 4 4 MAX - - - - - - - -
UNIT NOTES ns ns ns tCK tCK tCK tCK tCK
a
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SerialtoParallel Converter RX
e.g.500Mbps
9
8:1
72
DQ
72
Reverse DBI
64
WRTRstrobe (CKdomain)
WRTR
FIFO6 x72=432 bitsperbyte
DQ0DQ7 DBI0#
e.g.4Gbps
M U X
CRC8
DRAM Core
0 8 ParalleltoSerial Converter TX
1 9
2
3
4
5
6
7 M U X
72 72
DBI
10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
64
9
8:1
72
32 33 34 35 36 37 38 39 WRTR LDFF
72
e.g. 40 41 42 43 44 45 46 47 500Mbps 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 RDTRstrobe 01234 output pointer 012345 input pointer
(WCK)
CRCFIFO6 x 8=48 bitsper byte
ParalleltoSerial Converter
M U X
WRTRstrobe LDFFstrobe(burst7) M U X
8 8
0 1 2 3 4 5 6 7 012345 input pointer
8 8
DEMUX BA0BA2 CRCstrobe LDFFstrobe(burst7)
EDC0
TX
8:1
LDFF M U X
RDTRstrobe (WCK)
01234 output pointer
10
Address Path
ADDR
RX
8
DatapathusedwithLDFF DatapathusedwithWRTR DatapathusedwithLDFF/WRTR DatapathusedwithRDTR
Notes: 1)FIFOdepthof5shown;supportedFIFOdepths:4,5or6 2)datapathsshownfor1of4bytes(byte0)
Figure 16:DataPathsusedforReadandWriteTraining
LDFFCommand TheLDFFcommand(Figure17)isusedtosecurelyloaddatatotheGDDR5SGRAMReadFIFOsviathe addressbus.DependingontheGDDR5SGRAMREADFIFOdepthnFIFO6,anybitpatternoflength32 48canbeloadeduniquelytoeveryDQ,DBI#andEDCpinwithinabyte.TheFIFOdepthisfixedby designandcanbereadviatheVendorIDfunction. EightLDFFcommandsarerequiredtofilloneFIFOstage;eachLDFFcommandloadsoneburstposition, andthebankaddressesBA0BA2selecttheburstpositionfrom0to7. ThedatapatternisconveyedonaddresspinsA0A7forDQ0DQ7,A9forDBI0#,andBA3forEDC0;the dataareinternallyreplicatedtoall4bytes,asshowninFigure18.
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LDFFloadstheDBIFIFOregardlessoftheWDBIandRDBIModeRegisterbits.ItalsoloadstheEDCFIFO regardlessoftheWRCRCandRDCRCModeRegisterbits,andnoCRCiscalculated;however,RDBIand RDCRCmustbeenabledtoreadtheDBIandEDCbits,respectively,withtheRDTRcommand.
LDFF
CK# CK CKE# CS# LOW
RAS# CAS# WE#
A9,BA3 A1,A3 A8,A10,A11 A0,A7,A6 BA0BA2 A2,A4,A5
DATA
DATA
0,0,1
DATA
BP BP=BurstPosition DATA=FIFOdata
DATA
Figure 17:LDFFCommand
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LDFFCommand CK# CK L A10 A9 BA0 BA3 BA2 BA1 H A11 L A8 A0 A1 A2 A3 A4 A5 A6 A7 A0 A1 A2 A3 A4 A5 A6 A7 A9 BA3 1FIFOSTAGE=1BURST 0 1 2 3 4 5 6 7
AddresstoDQMapping Byte0 Byte1 Byte2 Byte3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ16 DQ24 DQ17 DQ25
DQ10 DQ18 DQ26 DQ11 DQ19 DQ27 DQ12 DQ20 DQ28 DQ13 DQ21 DQ29 DQ14 DQ22 DQ30 DQ15 DQ23 DQ31
DBI0# DBI1# DBI2# DBI3# EDC0 EDC1 EDC2 EDC3 BurstPosition 2 3 4 0 0 1 1 1 0 0 1 0
BA2 BA1 BA0
0 0 0 0
1 0 0 1
5 1 0 1
6 1 1 0
7 1 1 1
LDFFFIFOLoadPulse
Figure 18:LDFFCommandAddresstoDQ/DBI#/EDCMapping
Allburstaddresses0to7mustbeloaded;LDFFcommandstoburstaddress0to6maybeissuedinran domorder;theLDFFcommandtoburstaddress7(LDFF7)mustbethelastof8consecutiveLDFFcom mands,asiteffectivelyloadsthedataintotheFIFOandresultsinaFIFOpointerincrement.Consecutive LDFFcommandshavetobespacedbyatleasttLTLTR,andatleasttLTL7TRcyclesarerequiredaftereach LDFFcommandtoburstaddress7. LDFFpatternmayefficientlybereplicatedtothenextFIFOstagesbyissuingconsecutiveLDFFcommands toburstaddress7(withidenticaldatapattern).ThedatapatterninthescratchmemoryforLDFFwillbe availableuntilthefirstRDTRcommand. TheDQ/DBI#outputbuffersremaininODTstateduringLDFF. AnamountofLDFFcommandstoburstaddress7greaterthantheFIFOdepthisallowedandshallresult inaloopingoftheFIFO'sdatainput. ThetotalnumberofLDFFcommandstoburstaddress7moduloFIFOdepthmustequalthetotalnumber ofRDTRcommandsmoduloFIFOdepthwhenusedinconjunctionwithRDTR.NoREADorWRITEcom mandsareallowedbetweenLDFFandRDTR. TheEDCholdpatternisdrivenontheEDCpinsduringLDFF(providedRDQSmodeisnotenabled).
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RDTRCommand ARDTRburstisinitiatedwithaRDTRcommandasshowninFigure19.Nobankorcolumnaddressesare usedasthedataisreadfromtheinternalREADFIFO,notthearray.Thelengthoftheburstinitiatedwith aRDTRcommandiseight.ThereisnointerruptionnortruncationofRDTRbursts.
RDTR
CK# CK CKE# CS# LOW
RAS# CAS# WE#
A9(A12) A1 A8,A10,A11 A7,A0,A6 BA0BA3 A2A5
0,1,1
Figure 19:RDTRCommand
ARDTRcommandmayonlybeissuedwhenabankisopenorarefreshisinprogressandbitA2inMR5 issetto0toallowtrainingduringrefresh. RDBIandRDCRCmustbeenabledtoreadtheDBIandEDCbits,respectively,withtheRDTRcommand. Ifnotset,theDBI#pinswillremaininODTstate,andtheEDCpinswilldrivetheEDCholdpattern. IncaseoftheRDQSmode,theEDCpinfunctionslikewithanormalREADinthismode.TheDBI#pin behaveslikeaDQ,andnoencodingwithDBIisperformed. AnamountofRDTRcommandsgreaterthantheFIFOdepthisallowedandshallresultinaloopingofthe FIFO'sdataoutput.TheFIFOdepthfromwhichtheRDTRdataisreadmustbeanumberbetween46and mustbespecifiedbytheDRAMvendor.TheFIFOdepthisreadviatheVendorIDfunction. DuringRDTRbursts,thefirstvaliddataoutelementwillbeavailableaftertheCASlatency(CL).The latencyisthesameasforREAD.ThedataontheEDCpinscomeswithadditionalCRClatency(tCRCRD) aftertheCL. Uponcompletionofaburst,assumingnootherRDTRcommandhasbeeninitiated,allDQandDBI#pins willdriveavalueof1andtheODTwillbeenabledatamaximumof1tCKlater.Thedrivevalueandter minationvaluemaybedifferentduetoseparatelydefinedcalibrationoffsets.IftheODTisdisabled,the pinswilldriveHiZ.
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DatafromanyRDTRburstmaybeconcatenatedwithdatafromasubsequentRDTRcommand.Acontin uousflowofdatacanbemaintained.Thefirstdataelementfromthenewburstfollowsthelastelementof acompletedburst.ThenewRDTRcommandshouldbeissuedafterthefirstRDTRcommandaccordingto thetCCDStiming. AWRTRcanbeissuedanytimeafteraRDTRcommandaslongasthebusturnaroundtimetRTWismet. ThetotalnumberofRDTRcommandsmoduloFIFOdepthmustbeequaltototalnumberofWRTRcom mandsmoduloFIFOdepthwhenusedinconjunctionwithWRTR.NoREADorWRITEcommandsare allowedbetweenWRTRandRDTR. ThetotalnumberofRDTRcommandsmoduloFIFOdepthmustbeequaltothetotalnumberofLDFF commandstoburstposition7moduloFIFOdepthwhenusedinconjunctionwithLDFF.NoREADor WRITEcommandsareallowedbetweenLDFFandRDTR.
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3.5.WRITETRAINING
Writetrainingallowsthememorycontrollertofindthedataeyecenter(symboltraining)andburstframe location(frametraining)foreachhighspeedinputoftheGDDR5SGRAM.Eachpin(DQ0DQ31,DBI0# DBI3#)canbeindividuallytrainedduringthissequence. ForWriteTrainingthefollowingconditionsmustbetrue:
* atleastonebankisactive,oranautorefreshmustbeinprogressandbitA2inModeRegister5(MR5)issetto0to allowtrainingduringautorefresh(todisablethisspecialREFenablingoftheWCKclocktreeanACTcommand mustbeissued,orthedevicemustbesetintopowerdownorselfrefreshmode) * thePLLmustbelocked,ifenabled. * WCK2CKtrainingshouldbecomplete * Readtrainingshouldbecomplete * RDBIandWDBImustbeenabledpriortoandduringWriteTrainingifthetrainingshallincludetheDBI#pins. RDCRCandWRCRCmustbeenabledpriortoandduringWriteTrainingifthetrainingshallincludetheEDC pins.
ThefollowingcommandsareassociatedwithWriteTraining:
* WRTRtowriteaburstofdatadirectlyintotheReadFIFO; * RDTRtoreadaburstofdatadirectlyoutoftheReadFIFO.
NeitherWRTRnorRDTRaccessthememorycore.NoMRSisrequiredtoenterWriteTraining. Figure16showsanexampleoftheinternaldatapathsusedwithWRTRandRDTR.Figure21showsatyp icalWritetrainingcommandsequenceusingWRTRandRDTR.Table14listsACtimingparametersasso ciatedwithWRITETraining.
Table 14WRTRandRDTRTimings
VALUES PARAMETER ACTIVEtoWRTRcommanddelay ACTIVEtoRDTRcommanddelay REFRESHtoRDTRorWRTRcommanddelay RD/WRbankAtoRD/WRbankBcommanddelay differentbankgroups WRTRtoRDTRcommanddelay WRITEtoWRTRcommanddelay READorRDTRtoWRITEorWRTRcommanddelay SYMBOL MIN tRCDWTR tRCDRTR tREFTR tCCDS tWTRTR tWRWTR tRTW 10 10 10 2 WLtWLmin WL+CRCWL+2 1 MAX - - - - - - - ns ns ns tCK tCK tCK ns
b a
UNIT
NOTES
a. tCCDSiseitherforgaplessconsecutiveREADorRDTR(anycombination),gaplessconsecutiveWRITE,orgaplessconsecutive WRTRcommands. b. tRTWisnotadevicelimitbutdeterminedbythesystembusturnaroundtime.ThedifferencebetweentWCK2DQOandtWCK2DQI shallbeconsideredinthecalculationofthebusturnaroundtime.
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WRTRCommand AWRTRburstisinitiatedwithaWRTRcommandasshowninFigure20.Nobankorcolumnaddresses areusedasthedataiswrittentotheinternalREADFIFO,notthearray.Thelengthoftheburstinitiated withaWRTRcommandiseight.ThereisnointerruptionnortruncationofWRTRbursts.
WRTR
CK# CK CKE# CS# LOW
RAS# CAS# WE#
A9(A12) A1 A8,A10,A11 A7,A0,A6 BA0BA3 A2A5
0,1,1
Figure 20:WRTRCommand
AWRTRcommandmayonlybeissuedwhenabankisopenorarefreshisinprogressandbitA2inMR5 issetto0toallowtrainingduringrefresh. WDBIandWRCRCmustbeenabledtowritetheDBIandEDCbits,respectively,withtheWRTRcom mand.IfWDBIisnotset,a`1'willbewrittentotheDBIFIFO,anda`1'willbeassumedfortheDBI#input intheCRCcalculation.IncontrasttoanormalWRITE,noCRCisreturnedbytheWRTRcommandand theEDCpinswilldrivetheEDCholdpattern. IncaseoftheRDQSmode,theEDCpinfunctionslikewithanormalREADinthismode.Pleasenotethat RDCRCmustbeenabledtoreadthecalculatedCRCdatawiththeRDTRcommand. AnamountofWRTRcommandsequaltotheFIFOdepthisrequiredtofullyloadtheFIFO;anynumberof WRTRcommandsgreaterthantheFIFOdepthisallowedandshallresultinaloopingoftheFIFO'sdata input.TheFIFOdepthtowhichtheWRTRdataiswrittenmustbe6.TheFIFOdepthisreadviatheVen dorIDfunction. DuringWRTRbursts,thefirstvaliddatainelementmustbeavailableattheinputlatchaftertheWrite Latency(WL).TheWriteLatencyisthesameasforWRITE. Uponcompletionofaburst,assumingnootherWRTRdataisexpectedonthebustheGDDR5SGRAM DQandDBI#pinswillbedrivenaccordingtotheODTstate.Anyadditionalinputdatawillbeignored.
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DatafromanyWRTRburstmaybeconcatenatedwithdatafromasubsequentWRTRcommand.Acontin uousflowofdatacanbemaintained.Thefirstdataelementfromthenewburstfollowsthelastelementof acompletedburst.ThenewWRTRcommandshouldbeissuedafterthepreviousWRTRcommand accordingtothetCCDStiming. ARDTRcanbeissuedanytimeafteraWRTRcommandaslongastheinternalbusturnaroundtime tRTWTRismet. ThetotalnumberofWRTRcommandsmoduloFIFOdepthmustequalthetotalnumberofRDTRcom mandsmoduloFIFOdepthwhenusedinconjunctionwithRDTR.NoREADorWRITEcommandsare allowedbetweenWRTRandRDTR.
T0 CK# CK CMD ADDR WLmrs WCK WCK# WRTR
T1
T2
T3
T4
T5
Ta
Ta+1
Ta+2
Ta+3
Ta+4
NOP
WRTR
NOP
NOP
NOP
RDTR
NOP
RDTR
NOP
NOP
WLmrs
tWTRTR
CLmrs
CRCRL
CLmrs
CRCRL
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
DQ
EDC
EDCHold EDCHold EDCHold EDCHold EDCHold EDCHold EDCHold EDCHold
1.WLmrs,CLmrsandCRCRLsetto1foreaseofillustration;checkModeRegisterdefinitionforsupportedsettings 2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
Figure 21:WriteTrainingusingWRTRandRDTRCommands
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D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 DontCare
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5
H5GQ1H24AFR 4.MODEREGISTERS
GDDR5 specifies 10 Mode Registers to define the specific mode of operation. MR0 to MR7 and MR15 are defined as shown in the overview in Figure 22. MR8 to MR13 are not defined and may be used by DRAM vendors for vendor specific features. Reprogramming the Mode Registers will not alter the contents of the memory array. All Mode Registers are programmed via the MODE REGISTER SET (MRS) command and will retain the stored information until they are reprogrammed or the device loses power. Mode Registers must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation. No default states are defined for Mode Registers except when otherwise noted. Users therefore must fully initialize all Mode Registers to the desired values e.g. upon power-up. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. RFU bits are reserved for future use and must be programmed to 0. Bit A12 is not used for any mode register programming as this address input is not defined for 1G density.
BA3 BA2 BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MR0 MR1 MR2 MR3
0
0
0
0
0
WriteRecovery(WR)
TM
CASLatency(CLmrs)
WriteLatency (WLmrs) Driver Strength
0
0
0
1
0
PLL WDBI RDBI PLL Reset ABI
Cal ADR/CMD Data Upd Termination Termination OCDPullup DriverOffset
0
0
1
0
0
ADR/CMD DataandWCK TerminationOffset TerminationOffset Bank Groups WCK Termination Info
OCDPulldown DriverOffset
0
0
1
1
0
RDQS WCK WCK WCK Mode 2CK 23Inv 01Inv SelfRefresh
MR4
0
1
0
0
0
EDC WR RD 13Inv CRC CRC
CRCRead CRCWriteLatency Latency (CRCWL) (CRCRL)
EDCHoldPattern
MR5 MR6 MR7 MR14 MR15
0
1
0
1
0
RFU VREFDOffset Upper2bytes
PLLBandwidth (PLLBW) VREFDOffset Lower2bytes VREFD
LP3
LP2
RFU
0
1
1
0
0
Auto VREFD WCK VREFD Merge PIN RFU
0
1
1
1
0
DCC
RFU
Half Temp DQ Auto LF VREFD Sense PreA Sync Mode
RFU MRE MRE RFU ADT MF1 MF0
1
1
1
1
0
X
X
X
X
X
X
X
X
Figure 22. Mode Registers Overview
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4.1.MODEREGISTER0(MR0)
ModeRegister0controlsoperatingmodessuchasWriteLatency,CASlatency,WriteRecoveryandTest ModeasshowninFigure23. TheregisterisprogrammedviatheMODEREGISTERSET(MRS)commandwithBA0=0,BA1=0,BA2=0 andBA3=0.
BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0
0
WriteRecovery(WR)
TM
CASLatency(CLmrs)
WriteLatency (WLmrs)
A11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
WriteRecovery (WR) 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
A7 0 1
TestMode Normal TestMode
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
WriteLatency (WLmrs) RFU 1 2 3 4 5 6 7
A6 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CASLatency(CLmrs) 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Figure 23. Mode Register 0 (MR0) Definition
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WRITELatency(WLmrs) TheWRITElatency(WLmrs)isthedelayinclockcyclesusedinthecalculationofthetotalWRITElatency (WL)betweentheregistrationofaWRITEcommandandtheavailabilityofthefirstpieceofinputdata. DRAMvendorspecificationsshouldbecheckedforvalue(s)ofWLmrssupported.ThefullWRITElatency definitioncanbefoundinthesectionentitledOPERATION. WhentheWRITElatenciesaresettosmallvalues(i.e.1,2,...clocks),theinputreceiversneverturnoff,in turn,raisingtheoperatingpower.WhentheWRITElatencyissettohighervalues(i.e...6,7clocks)theinput receivers turn on when the WRITE command is registered. Refer to vendor datasheets for value(s) of WLmrswheretheinputreceiversarealwaysonoronlyturnonwhentheWRITEcommandisregistered
Speed 6.0Gbps 5.5Gbps 5.0Gbps 4.5Gbps 4.0Gbps AllowableOperatingFrequency(Gbps) WL7 WL6 WL5 WL4 WL3 WL2 WL1
CASLatency(CLmrs) TheCASlatency(CLmrs)isthedelayinclockcyclesusedinthecalculationofthetotalREADlatency (CL)betweentheregistrationofaREADcommandandtheavailabilityofthefirstpieceofoutputdata. BydefaultCLmrsisspecifiedbybitsA3A6,definingaCLmrsrangeof5to20tCK. DRAMvendorspecificationsshouldbecheckedforvalue(s)ofCLmrssupported.ThefullREADlatency definitioncanbefoundinthesectionentitledOPERATION
Speed
RDBI ON/OFF OFF ON OFF ON OFF ON OFF ON OFF ON
AllowableOperatingFrequency(Gbps) CL20 CL19 CL18 CL17 CL16 CL15 CL14 CL13 CL12
6.0Gbps
5.5Gbps
5.0Gbps
4.5Gbps
4.0Gbps
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WRITERecovery(WR) TheprogrammedWRvalueisusedfortheautoprechargefeaturealongwithtRPtodeterminetDAL.The WR register bits are not a required function and may be implemented at the discretion of the DRAM manufacturer. WRmustbeprogrammedwithavaluegreaterthanorequaltoRU{tWR/tCK},whereRUstandsforround up,tWRistheanalogvaluefromthevendordatasheetandtCKistheoperatingclockcycletime. BydefaultWRisspecifiedbybitsA8A11,definingaWRrangeof4to19tCK. TestMode ThenormaloperatingmodeisselectedbyissuingaMODEREGISTERSETcommandwithbitA7setto '0',andbitsA0A6andA8A11settothedesiredvalues.ProgrammingbitA7to`1'placesthedeviceintoa testmodethatisonlytobeusedbytheDRAMmanufacturer.Nofunctionaloperationisspecifiedwithtest modeenabled.
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4.2.MODEREGISTER1(MR1)
ModeRegister1controlsfunctionslikedrivestrength,datatermination,address/commandtermination, ReadDBI,WriteDBI,ABI,controlofcalibrationupdatesandPLLasshowninFigure24. TheregisterisprogrammedviatheMODEREGISTERSET(MRS)commandwithBA0=1,BA1=0,BA2=0 andBA3=0.BitsA0A1,A4A6andA10ofthisregisterareinitializedwith'0's.
BA3 BA2 BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
1
0
PLL ABI WDBI RDBI PLL Reset
Cal ADR/CMD Data Upd Termination Termination
Driver Strength
A1 0 A11 0 1 PLLReset No Yes
A0 0 1 0 1
DriverStrength
AutoCalibrationOn
A7 0 1
PLL Off On
0 1 1
RFU Nominal(60/40) RFU
A10 0 1
ABI On Off
A6 0 1
CalibrationUpdate On Off
A3 0 0 1 1
A2 0 1 0 1
DataTermination Disabled ZQ/2 ZQ RFU
A9 0 1
WriteDBI On Off
A8 0 1
ReadDBI On Off A5 0 0 1 1 A4 0 1 0 1 ADD/CMDTermination CKE#valueatReset ZQ/2 ZQ Disabled
Figure 24. Mode Register 1 (MR1) Definition
ImpedanceAutocalibrationofOutputBufferandActiveTerminator GDDR5SGRAMsofferautocalibratingimpedanceoutputbuffersandondieterminations.Thisenablesa usertomatchthedriverimpedanceandterminationstothesystemwithinagivenrange.Toadjustthe impedance,anexternalprecisionresistorisconnectedbetweentheZQpinandVSSQ.Anominalresistor
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H5GQ1H24AFR
valueof120Ohmsisequivalenttothe40OhmsPulldownand60OhmsPullupnominalimpedancesof GDDR5SGRAMs.RESET#,CKandCK#arenotinternallyterminated.CKandCK#shallbeterminatedon thesystemusingexternal1%resistorstoVDDQ. TheoutputdriverandondieterminationimpedancesareupdatedduringallREFRESHcommandsto compensateforvariationsinsupplyvoltageandtemperature.Theimpedanceupdatesaretransparentto thesystem. DriverStrength Bits A0 and A1 define the driver strength. The Auto Calibration setting enables the AutoCalibration functionalityforthePulldown,PullupandTerminationoverprocess,temperatureandvoltagechanges. Thedesigntargetforthefactorysettingis40OhmPulldown,60OhmPullupdriverstrengthwithnominal process,voltageandtemperatureconditions. ThenominaloptionenablesthefactorysettingforthePulldown,Pullupdriverstrengthandtermination. With thisoptionenabled, driver strength andterminationareexpected tochangewithprocess,voltage andtemperature.ACtimingsareonlyguaranteedwithAutoCalibration. DataTermination BitsA2andA3definethedataterminationvaluefortheondietermination(ODT)fortheDQandDBI# pinsincombinationwiththedriverstrengthsetting. TheterminationcanbesettoavalueofZQ/2whichisintendedforasingleloadedsystem,orZQwhich is intended for a weaker termination used in a lower power or frequency applications. The data terminationmayalsobeturnedoff. ADR/CMDTermination Bits A4 and A5 define the address/command termination. The default setting ('00') provides that the address/commandterminationisdeterminedbylatchingCKE#ontherisingedgeofRESET#. The address/command termination can also be set to a value of ZQ/2 which is intended for a single loaded system, or ZQ which is intended for double loaded configurations with two devices sharing a commonaddress/commandbus.Theaddress/commandterminationmayalsobeturnedoff.
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CalibrationUpdate The Calibration Update setting enables the calibration value to be updated automatically by the auto calibrationengine.Thefunctionisenableduponpoweruptoreduceupdateinducedjitter.Theusermay decidetosuppressupdatesfromtheautocalibrationenginebydisablingCalibrationUpdate(A6=1). ThecalibrationupdatescanoccurwithanyREFRESHcommand.Theupdateisnotcompleteforatime tKO after the latching of the REFRESH command. During this tKO time, only NOP or DESELECT commandsmaybeissued PLLandPLLReset IfaPLListobeused,itmustbeenabledfornormaloperationbysettingbitA7to'1'. APLLresetisdonebyturningthePLLoffthenon,orbyuseofthePLLResetbitA11.ThePLLResetbit isselfclearingmeaningthatitreturnsbacktothevalue`0'afterthePLLresetfunctionhasbeenissued. RDBIandWDBI BitA8controlsDataBusInversion(DBI)forREADs(RDBI),andbitA9controlsDataBusInversionfor WRITEs(WDBI).FormoredetailsonDBIseeREADandWRITEDataBusInversion(DBI)inthesection entitledOPERATION. ABI AddressBusInversion(ABI)isselectedindependentlyfromDBIusingbitA10.Whenenabledanydata sentovertheaddressbus(whetheropcode,addresses,LDFFdataorDM)isinvertedornotinvertedbased onthestateofABI#signal.FormoredetailsonABIseeAddressBusInversion(ABI)inthesectionentitled OPERATION.
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4.3.MODEREGISTER2(MR2)
ModeRegister2definestheoutputdriver(OCD)andterminationoffsetsasshowninFigure25. Mode Register 2 is programmed via the MODE REGISTER SET (MRS) command with BA0=0, BA1=1, BA2=0andBA3=0.
BA3 BA2 BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
1
0
0
ADR/CMD DataandWCK TerminationOffset TerminationOffset
OCDPullup DriverOffset
OCDPulldown DriverOffset
A8 0 0 0 0 1 1 1 1
A7 0 0 1 1 0 0 1 1
A6 0 1 0 1 0 1 0 1
DataandWCK TerminationOffset 0 +1 +2 +3 4 3 2 1
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
OCDPulldown DriverOffset 0 +1 +2 +3 4 3 2 1
A11 0 0 0 0 1 1 1 1
A10 0 0 1 1 0 0 1 1
A9 0 1 0 1 0 1 0 1
ADR/CMD TerminationOffset 0 +1 +2 +3 4 3 2 1
A5 0 0 0 0 1 1 1 1
A4 0 0 1 1 0 0 1 1
A3 0 1 0 1 0 1 0 1
OCDPullup DriverOffset 0 +1 +2 +3 4 3 2 1
Figure 25. Mode Register 2 (MR2) Definition
ImpedanceOffsets ThedriverandterminationimpedancesmaybeoffsetindividuallyforPDdriver,PUdriver,DQ/DBI#/ WCK termination and address/command termination. The offset impedance step values may be non linearandwillvaryacrossPVT.WithnegativeoffsetstepsthedrivestrengthswillbedecreasedandRon
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will be increased. With positive offset steps the drive strengths will be increased and Ron will be decreased.Withnegativeoffsetstepstheterminationvaluewillbeincreased.Withpositiveoffsetsteps theterminationvaluewillbedecreased. IVcurvesandACtimingsareonlyguaranteedwithzerooffset.
Offset PUDriver Autocalibrated Impedance Offset PDDriver Auto/Fixed nominal(60/40) FixedImpedance Offset ADD/CMDTermination
Pullup Impedance
ZQ 120 Ohms
Calibration Engine
Pulldown Impedance
VSSQ
ADD/CMD Termination Impedance
Note:sumofoffset+auto calibratedimpedancecannot exceedmaximumminimum / availableimpedancesteps
Offset DQ/DBI#/WCKTermination DQ/DBI#/WCK Termination Impedance
Figure 26. Impedance Offsets
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4.4.MODEREGISTER3(MR3)
ModeRegister3controlsfunctionsincludingBankGroups,WCKtermination,selfrefresh,RDQSmode, DRAMInfoandWCK2CKtrainingasshowninFigure27. Mode Register 3 is programmed via the MODE REGISTER SET (MRS) command with BA0=1, BA1=1, BA2=0andBA3=0.
BA3 BA2 BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
1
1
0
Bank Groups
WCK Termination
Info
RDQS WCK WCK WCK Mode 2CK 23Inv 01Inv SelfRefresh
A11 0 1
A10 X X
BankGroups off/tCCDL=2tCK on/tCCDL=3tCK
A1
0 0 1 1
A0
0 1 0 1
SelfRefresh
32ms 16ms
8ms RFU
A9 0 0 1 1
A8 0 1 0 1
WCKTermination Disabled ZQ/2 ZQ RFU A3 0 WCK23Invert Off On A5 0 1 RDQS Mode Off On A2 0 1 WCK01Invert Off On
A7 0 0 1 1
A6 0 1 0 1
DRAMInfo off VendorID TemperatureReadout RFU A4 0 1
1
WCK2CKTraining Off On
Figure 27. Mode Register 3 (MR3) Definition
SelfRefresh Therefreshintervalinselfrefreshmodemaybesetto32ms,16msand8ms.
WCK2CK
Bit A4 (WCK2CK) enables and disables the WCK2CK alignment training. For details on this training sequence,seethesectiononTRAINING.
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WCK01/WCK23Inversion BitsA2andA3controlwhethertheinternalphaseoftheWCK01andWCK23clockinputsafterinternal divideby2shallbeinverted,correspondingtoa2U.I.phaseshift.Thebitsareusedinconjunctionwith WCK2CKtrainingmode. RDQSMode BitA5enablestheRDQSmodeoftheGDDR5SGRAM.InthismodetheEDCpinswillactasaREAD strobe (RDQS). No CRC is supported in RDQS mode, and all related bits in MR4 will be ignored. A detaileddescriptionoftheRDQSmodecanbefoundinthesectionentitledOPERATION. DRAMInfo BitsA6andA7enabletheDRAMInfomodewhichisprovidedtooutputtheVendorID,orthecurrent junctiontemperature. The Vendor ID identifies the manufacturer of the GDDR5 SGRAM, and provides the die revision, memorydensityandFIFOdepth. TheTemperatureReadoutprovidestheSGRAM'sjunctiontemperature.Theonchiptemperaturesensor isenabledinadvancebybitA6inMR7. WCKTermination BitsA8andA9definetheterminationvaluefortheondietermination(ODT)fortheWCK01,WCK01#, WCK23andWCK23#pinsincombinationwiththedriverstrengthsetting. TheterminationcanbesettoavalueofZQ/2whichisintendedforasingleloadedsystem,orZQwhich is intended for double load configurations with two devices sharing the WCK clocks. The WCK terminationmayalsobeturnedoff. BankGroups Bit A11 enables the bank groups feature. With A11 set to `1', the bank groups feature is enabled and tCCDLis3tCK.
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4.5.MODEREGISTER4(MR4)
Mode Register 4 defines the Error Detection Code (EDC) features of GDDR5 SGRAMs as shown in Figure28. TheregisterisprogrammedviatheMODEREGISTERSET(MRS)commandwithBA0=0,BA1=0,BA2=1 andBA3=0.BitsA0A3(EDCHoldPattern)ofthisregisterareinitializedwith'1111'.
BA3 BA2 BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
0
0
0
EDC WR RD 13Inv CRC CRC
CRCRead Latency CRCWriteLatency (CRCWL) (CRCRL)
EDCHoldPattern
A11 0 1
EDCHoldPatternInvert forEDC1+EDC3 EDCholdpatternnot inverted EDCholdpatterninverted
A3 0
A2 0
A1 0
A0 0
EDCHoldPattern Pattern ...
1
1
1
1
Pattern
Burst Burst Burst Burst Pos3 Pos2 Pos1 Pos0
A10 0 1
WRCRC On Off
A9 0 1
RDCRC On Off A6 0 0 0 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CRCWriteLatency(CRCWL) N/A 8 9 10 11 12 13 14
A8 0 0 1 1
A7 0 1 0 1
CRCReadLatency(CRCRL) 0 1 2 3
0 1 1 1 1
Figure 28. Mode Register 4 (MR4) Definition
EDCHoldpattern/EDC13Invert The4bitEDCholdpatternisconsideredabackgroundpatterntransmittedontheEDCpins.Theregister isinitializedwithall'1's.Thepatternisshiftedfromrighttoleftandrepeatedwitheveryclockcycle.The outputtimingisthesameasofaREADburst. CRC bursts calculated from WRITEs or READs will replace the EDC hold pattern for the duration of thosebursts,providedCRCisenabledforthosebursts. With each MRS command to MR4 that changes bits A0A3 or A9A11, the EDC hold pattern will be undefinedfortMRD.
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TheEDCholdpatternwillnotbetransmittedwhenthedeviceisinaddresstrainingmode,inWCK2CK trainingmode,inRDQSmode,inselfrefreshmode,inresetstate,inpowerdownstatewiththeLP2bit set,orinscanmode. WithregisterbitA11setHigh,EDC1andEDC3willtransmittheinvertedEDCholdpattern,resultingin apseudodifferentialpattern.Pleasenotethatthisfunctionisnotavailableinx16configuration.BitA11is ignoredforREAD,WRITEandRDTRCRCburstsandtheclockphaseinformationinWCK2CKtraining mode.
CRCWriteLatency(CRCWL) The value of the CRC write latency is loaded into register bits A4A6. If the DRAM vendor does not supporttheModeRegisterdefinitionofCRCWL,theModeRegistersettingswillbeignored.Inthatcase the valid fixed latency is given with the DRAM vendor's specification. The user must set the CRCWL ModeRegisterbits.
AllowableOperatingFrequency(Gbps) CRCWL14 CRCWL13 CRCWL12 CRCWL11 CRCWL10 CRCWL9 CRCWL8
Speed 6.0Gbps 5.5Gbps 5.0Gbps 4.5Gbps 4.0Gbps
CRCReadLatency(CRCRL) ThevalueoftheCRCreadlatencyisloadedintoregisterbitsA7A8.IftheDRAMvendordoesnotsupport theModeRegisterdefinitionofCRCRL,theModeRegistersettingswillbeignored.Inthatcasethevalid fixedlatencyisgivenwiththeDRAMvendor'sspecification.TheusermustsettheCRCRLModeRegister bits.
Speed RDBI ON/OFF OFF ON OFF ON OFF ON OFF ON OFF ON AllowableOperatingFrequency(Gbps) CRCRL3 CRCRL2 CRCRL1 CRCRL0
6.0Gbps
5.5Gbps
5.0Gbps
4.5Gbps
4.0Gbps
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ReadCRC BitA9controlstheCRCcalculationforREADbursts.Whenenabled,thecalculatedCRCpatternwillbe transmitted on the EDC pins with the latency as programmed in the CRCRL field of this register. With Read CRC being off, no CRC will be calculated for READ bursts, and the EDC hold pattern will be transmittedinstead. WriteCRC BitA10controlstheCRCcalculationforWRITEbursts.Whenenabled,thecalculatedCRCpatternwillbe transmittedontheEDCpinswiththelatencyasprogrammedintheCRCWLfieldofthisregister.With WriteCRCbeingoff,noCRCwillbecalculatedforWRITEbursts,andtheEDCholdpatternwillbetrans mittedinstead.
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4.6.MODEREGISTER5(MR5)
ModeRegister5definesdigitalRAS,PLLbandwidthandlowpowermodesasshowninFigure29. TheregisterisprogrammedviatheMODEREGISTERSET(MRS)commandwithBA0=1,BA1=0,BA2=1 andBA3=0.
BA3 BA2 BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
0
1
0
RFU
PLLBandwidth
LP3
LP2
RFU
A1 A5 0 0 0 0 1 1 1 1 A4 0 0 1 1 0 0 1 1 A3 0 1 0 1 0 1 0 1 3dB[MHz] BW3dBLL 13 18 22 28 36 44 54 69 Peak[MHz] BWPKLL 2 4 5 7 10 13 15 20 Peak[dB] PKLL 1.2 1.1 1.1 1.2 1.2 1.2 1.7 1.5 A2 0 1 LP3 Off On 0 1
LP2 Off On
Note 1) PLL BW characteristics is extracted at 4Gbps Note 2) PLL BW is linearly proportional to the data rate
Figure 29. Mode Register 5 (MR5) Definition
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LowPowerModes(LP2,LP3) BitsA1A2controlseverallowpowermodesoftheGDDR5SGRAM.Themodesareindependentofeach other. WhenbitA1(LP2)isset,theWCKreceiversmaybeturnedoffduringpowerdown. WhenbitA2(LP3)isset,RDTR,WRTRandLDFFcommandsarenotallowedwhileaREFcommandis beingexecuted.
PLL Bandwidth
ThePLLbandwidthmayoptionallybeconfiguredtomatchsystemcharacteristics.Eachsettingdefinesa uniquecombinationof3dBcornerfrequency,peakingfrequencyandpeakingmagnitude.
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4.7.MODEREGISTER6(MR6)
Mode Register 6 controls the WCK2CK alignment point and defines VREFD related features such as source,level,offsets,VREFDMergeandVREFDAutoCalibrationmode,asshowninFigure30. TheregisterisprogrammedviatheMODEREGISTERSET(MRS)commandwithBA0=0,BA1=1,BA2=1 andBA3=0.
BA3 BA2 BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
1
0
0
VREFDOffset BytesinrowsAF
VREFDOffset BytesinrowsMU
Auto VREFD WCK VREFD VREFD Merge PIN
A11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
VREFD Offset 0/ default +1 +2 +3 +4 +5 +6 +7 0/Auto (opt.) 7 6 5 4 3 2 1
A7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
VREFD Offset 0/ default +1 +2 +3 +4 +5 +6 +7 0/Auto (opt.) 7 6 5 4 3 2 1 A3 0 1 A1 0 1
A0 0 1
WCK2CK AlignmentPt. PDinside DRAM PDatpins
VREFDMerge Off On
VREFD externalVREFDpins internallygenerated
Figure 30. Mode Register 6 (MR6) Definition
WCK2CKAlignmentPoint(WCKPIN) BitA0definesthepositionofthealignmentpointbetweenCKandWCK.Whensetto`0`,thealignment pointwillbeatthephasedetectorinsidetheGDDR5SGRAM.Whensetto`1`,thealignmentpointwillbe attheCKandWCKpins. InputReferenceVoltageforDQandDBI#Pins GDDR5SGRAMsoffermultipleoptionsfortheinputreferencevoltage(Vref)fortheDQandDBI#pins, asshowninFigure31.
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SeparateVrefcircuitsareassociatedwiththebytesinrowsAtoFandthebytesinrowsMtoU,with separateVREFDpinsfortherequiredexternalVref. The only mandatory mode is that Vref will be supplied externally at the VREFD pins. This mode is configuredwithbitsA1A3andbitA7inMR7allsetto'0'.
VREFDOffsets
0.7*VDDQ(opt.)
0.5*VDDQ(opt.)
+
VREFD
VREFD Merge (opt.)
+
Receiver
DQ/DBI#
+
Figure 31. VREFD Options
VREFDMerge The VREFD Merge mode is enabled when bit A1 is set to'1'. The externally supplied VFRED and the internally generated Vref will be merged, resulting in the average value of both. DRAM vendor specificationsshouldbecheckedforvaluesofexternalresistorsthatmaybeconnectedtoVREFDpinsin thisVREFMergemode. AutoVREFDTraining When Auto is set for VREFD offsets, the internal Vref generator must be trained. Bit A2 enables this training; the bit is selfclearing, meaning that it returns back to the value `0' after the training has completed. Once the training mode is enabled, the GDDR5 SGRAM drives the EDC pins Low to indicate to the controllerthatthetraininghasstarted.ThecontrollerisnowexpectedtosendthespecifiedPRBSpattern totheGDDR5SGRAM.Uponcompletionofthetraining,theGDDR5SGRAMstopsdrivingtheEDCpins Low,andtheEDCpinswillresumetransmittingtheEDCholdpattern. But,itisnotsupported. VREFD Bit A3selects between external and internalVref. Thebit is "Don't Care"when VREF Merge modeis selected. VREFDOffsetsandVREFDAutoMode ItsupportsthecapabilitytooffsetVrefindependentlyfortheupper2bytesandthelower2bytes.The offsetstepvaluesmaybenonlinearandwillvaryacrossPVT.
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ThevendorsmayoptionallysupporttheoffsetcapabilitytobeappliedtotheexternalVref(notshownin Figure31). TheoptionalAutosettingforVREFDenablestheGDDR5SGRAMtosearchforitsownoptimalinternal Vref.Thereisnooffsetfromthisinternallydeterminedvalue(seealsoAutoVREFDTraining).
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4.8.MODEREGISTER7(MR7)
Mode Register 7 controls features like PLL Standby, PLL FastLock, PLL Delay Compensation, Low Frequency mode, Auto Synchronization, Data Preamble, Temperature Sensor operation, Half VREFD, VDDRangeandDCCasshowninFigure32. TheregisterisprogrammedviatheMODEREGISTERSET(MRS)commandwithBA0=1,BA1=1,BA2=1 andBA3=0.
BA3 BA2 BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
1
1
0
DCC
RFU
Half Temp DQ Auto LF VREFD Sense PreA Sync Mode
RFU
A11 0 0 1 1
A10 0 1 0 1
DCC noDCC/ DCCofforhold/opt. DCCstart DCCresetl RFU A4 0 1 WCK2CKAutoSync Off On
A5 0 1
DataPreamble Off On
A3 0 1
LowFrequencyMode Off On
A7 0 1
HalfVFRED 0.7*VDDQ 0.5*VDDQ
A6 0 1
TemperatureSensor Off On
Figure 32. Mode Register 7 (MR7) Definition
LowFrequencyMode When Low FrequencyMode is enabledby bitA3,the power consumption of input receivers andclock treesisreduced.Themaximumoperatingfrequencyforthislowfrequencymodeisgiveninthevendor`s datasheet. WCK2CKAutoSynchronization GDDR5 SGRAMs support a WCK2CK automatic synchronization mode that eliminates the need for WCK2CKtraininguponpowerdownexitorforreducingWCK2CKtrainingtimeatlowfrequency.This modeiscontrolledbybitA4.ForadetaileddescriptionseeWCK2CKAutoSynchronizationinthesection entitledWCK2CKTraining.
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DataPreamble WhenenabledbybitA5,nongaplessREADburstswillbeprecededbyafixeddatapreambleontheDQ and DBI# pins of 4 U.I. duration. The programmed READ latency does not change when the Data Preambleisenabled.ThepatternisnotencodedwithRDBI,however,ifRDBIisdisabled,theDBI#pins willnottoggleanddriveaHIGH. TemperatureSensor TheonchiptemperaturesensorisenabledbybitA6. AdetaileddescriptionoftheTemperatureSensorcanbefoundintheVENDORID,TEMPSENSORand SCANsection. HalfVREFD This mode allows users to adjust the Vref level in case the GDDR5 SGRAM is operated without termination:whenbitA7issetto'1',aVreflevelofnominally0.5*VDDQisexpectedattheVREFDpinor beinggeneratedinternally(seeFigure31). DutyCycleCorrection(DCC) BitsA10andA11controltheoperationofthedutycyclecorrector(DCC).TheDCCcanbeusedtocancel outastaticdutycycleerrorontheWCKclocks.FormoredetailsseeDutyCycleCorrection(DCC)inthe sectionentitledOPERATION. VREFDSelectionOptionsSummary ThefollowingtablesummarizesthecompletesetofVREFDselectionoptions.
Table 15VREFDSelectionOptions
MR6 A3 InternalVREFD 0 0 1 1 MR7 A7 HalfVREFD 0 1 0 1 External External Internal0.7*VDDQ Internal0.5*VDDQ Description
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4.9.MODEREGISTER15(MR15)
ModeRegister15controlsaddresstrainingmode(ADT)andaccesstoModeRegisters0to14(MRE)as showninFigure33. TheregisterisprogrammedviatheMODEREGISTERSET(MRS)commandwithBA0=1,BA1=1,BA2=1 andBA3=1. ModeRegister15 is a special registerthat operatesin SDR addressing mode. Increasedsetup and hold timesasforcommandinputsareassumedtoensuretheMRScommandtothisregisterissuccessfulwhile addresstraining(ADT)hasnottakenplaceandtheintegrityofDDRaddressesmaynotbeguaranteed. ThisisindicatedbysettingbitsA0A7toDon'tCare("X")whicharepairedwiththeusablebits(A8A11) andtheModeRegisteraddress(BA0BA3).
BA3 BA2 BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
1
1
1
0
RFU ADT
MRE MRE MF1 MF0
X
X
X
X
X
X
X
X
A10 AddressTraining(ADT) 0 1 Off On
A9 0 1
MR014EnableMF=1 Enabled Disabled
A8 0 1
MR014EnableMF=0 Enabled Disabled
Figure 33. Mode Register 15 (MR15) Definition
AddressTraining(ADT) AddresstrainingmodeisenabledanddisabledwithbitA10. ModeRegister014Enable WhendisabledbybitA8(forSGRAMsconfiguredtoMF=0)orbitA9(forSGRAMsconfiguredtoMF=1), the GDDR5 SGRAM will ignore any MODE REGISTER SET command to Mode Registers 0 to 14. If enabled, MODE REGISTER SET commands function as normal. MODE REGISTER SET commands to ModeRegister15(thisregister)arenotaffectedandwillalwaysbeexecuted. ThisfunctionalallowsforindividualconfigurationoftwoGDDR5SGRAMSonacommonaddressbus withouttheuseofaCS#pin.
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H5GQ1H24AFR 5.OPERATION
5.1.COMMANDS Table 16TruthTableCommands
Operation
Symbol
Previous Current cycle cycle DESELECT(NOP) NOOPERATION(NOP) MODEREGISTERSET ACTIVE(Selectbank& activaterow) READ(Selectbankand column,&startburst) READwithAutoprecharge LoadFIFO READTraining WRITEwithoutMask (Selectbankandcolumn,& startburst) WRITEwithoutMaskwith Autoprecharge WRITEwithsinglebyte mask WRITEwithsinglebyte maskwithAutoprecharge WRITEwithdoublebyte mask(WDM) WRITEwithdoublebyte maskwithAutoprecharge WRITETraining PRECHARGE(Deactivate rowinbankorbanks) PRECHARGEALL REFRESH POWERDOWNENTRY POWERDOWNEXIT SELFREFRESHENTRY SELFREFRESHEXIT DES NOP MRS ACT RD RDA LDFF RDTR WOM L L L L L L L L L X X L L L L L L L
CKE# CS#
H L L L L L L L L
RAS# CAS# WE#
X H L L H H H H H X H L H L L L L L X H L H H H H H L
BA
X X MRA BA BA BA X X BA
A11
X X
A10
X X
A8
X X Opcode RA
A6, A7, A9, (A12)
X X
A0 A5 (A6)
X X
Notes
1,2,8 1,2,8 1,2,3 1,2,4
L L H H L
L L L H L
L H L L L
X X X X X
CA CA X X CA
1,2,5, 9 1,2,5 1,2,7 1,2 1,2,5
WOMA WSM WSMA WDM WDMA WRTR PRE PREALL REF PDE PDX SRE SRX
L L L L L L L L L L H L H
L L L L L L L L L H L H L
L L L L L L L L L H L H L L H L
H H H H H H L L L X H X H L X H
L L L L L L H H L X H X H L X H
L L L L L L L L H X H X H H X H
BA BA BA BA BA X BA X X X X X X X
L L L H H H X X X X X X X X
L H H L L H X X X X X X X X
H L H L H L L H X X X X X X
X X X X X X X X X X X X X X
CA CA CA CA CA X X X X X X X X X
1,2,5 1,2,5 1,2,5 1,2,5 1,2,5 1,2 1,2 1,2 1,6 1 1 1 1,6 1
Notes: 1)H=LogicHighLevel;L=LogicLowLevel;X=Don'tcare:signalmaybeHorL,butnotfloating 2)Addressesshownarelogicaladdresses;physicaladdressesareinvertedwhenaddressbusinversion(ABI)isactivatedandABI#=L 3)BA0BA3providetheModeRegisteraddress(MRA),A0A11theopcodetobeloaded 4)BA0BA3providethebankaddress(BA),A0A11(A12)providetherowaddress(RA). 5)BA0BA3providethebankaddress,A0A5(A6)providethecolumnaddress(CA);nosubwordaddressingwithinaburstof8. 6)ThecommandisRefreshwhenCKE#(n)=LandSelfRefreshEntrywhenCKE#(n)=H. 7)BA0BA3andCAareusedtoselectburstlocationanddatarespectively 8)DESELECTandNOParefunctionallyinterchangeable 9)InaddresstrainingmodeREADisdecodedfromthecommandspinsonlywithRAS#=H,CAS#=L,WE#=H
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Figure34andFigure35illustratethetimingsassociatedwiththeCommandandAddressinputaswellas Datainput.
tCK CK# CK
tCH
tCL
tCMDPW COMMAND tAPW ADDRESS tAPW tAS tAH
tCMDS tCMDH
tAS tAH
DontCare
Figure 34. Command and Address Input Timings
WCK# WCK tWCK2DQI
tWCK2DQI
tDIPW tDIVW DQ/DBI# (1Pin)
tDIPW tDIVW
Figure 35. Data Input Timings
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5.2.DESELECT(NOP)
TheDESELECTfunction(CS#HIGH)preventsnewcommandsfrombeingexecutedbytheGDDR5 SGRAM.TheGDDR5SGRAMiseffectivelydeselected.Operationsalreadyinprogressarenotaffected.
5.3.NOOPERATION(NOP)
TheNOOPERATION(NOP)commandisusedtoinstructtheselectedGDDR5SGRAMtoperformaNOP (CS#LOW).Thispreventsunwantedcommandsfrombeingregisteredduringidleorwaitstates.Opera tionsalreadyinprogressarenotaffected.
5.4.MODEREGISTERSET
TheMODEREGISTERSETcommandisusedtoloadtheModeRegistersoftheGDDR5SGRAM.Thebank addressinputsBA0BA3selecttheModeRegister,andaddressputsA0A11(A12)determinetheopcode tobeloaded.SeeMODEREGISTERforaregisterdefinition.TheMODEREGISTERSETcommandcan onlybeissuedwhenallbanksareidleandnoburstsareinprogress,andasubsequentexecutablecom mandcannotbeissueduntiltMRDismet.
ModeRegisterSet
CK# CK CKE# LOW
CS#
RAS#
CAS# WE#
A8A11(A12) A0,A1,A6,A7 BA0BA3 A2A5
CO A8,9,10,11,(12)
CO A0,1,6,7
BA BA0,1,2,3
CO A2,3,4,5
RA=RowAddress DONTCARE CO=Opcode BA=BankAddress ENAP=EnableAutoPrecharge DISAP=DisableAut oPrecharge
Figure 36. MRS Command
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CK# CK CMD NOP PRE ALL NOP tRP OldSetting MRS NOP tMRD UpdatingSetting NewSetting A.C. NOP
A.C.=anycommandallowedinbankidlestate
Figure 37. Mode Register Set Timings 5.5.ACTIVATION
BeforeanyREADorWRITEcommandscanbeissuedtoabankintheGDDR5SGRAM,arowinthatbank mustbe"opened".ThisisaccomplishedbytheACTIVEcommand(seeFigure38):BA0BA3selectthe bank,andA0A11(A12)selecttherowtobeactivated.Oncearowisopen,aREADorWRITEcommand couldbeissuedtothatrow,subjecttothetRCDspecification. AsubsequentACTIVEcommandtoanotherrowinthesamebankcanonlybeissuedaftertheprevious rowhasbeenclosed(precharged).TheminimumtimeintervalbetweentwosuccessiveACTIVEcom mandsonthesamebankisdefinedbytRC.Aminimumtime,tRAS,musthaveelapsedbetweenopening andclosingarow. AsubsequentACTIVEcommandtoanotherbankcanbeissuedwhilethefirstbankisbeingaccessed, whichresultsinareductionoftotalrowaccessoverhead.Theminimumtimeintervalbetweentwosuc cessiveACTIVEcommandsondifferentbankstodifferentbankgroupsisdefinedbytRRDS.Withbank groupsenabled,theminimumtimeintervalbetweentwosuccessiveACTIVEcommandstodifferent banksinthesamebankgroupisdefinedbytRRDL.InallothercasestheintervalisdefinedbytRRDS. FigureshowsthetRCDandtRRDdefinition.
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TherowremainsactiveuntilaPRECHARGEcommand(orREADorWRITEcommandwithAutoPre charge)isissuedtothebank.
RowActivation
CK# CK CKE# LOW
CS#
RAS#
CAS# WE#
A8A11(A12) A0,A1,A6,A7 BA0BA3 A2A5
RA
A8,9,10,11,(12)
RA
A0,1,6,7
BA
BA0,1,2,3
RA
A2,3,4,5
RA=RowAddress CA=ColumnAddress BA=BankAddress
DONTCARE
Figure 38. Active Command
T0 CK# CK CMD ADDR NOP
T1
T2
Ta0
Ta1
Tb0
Tb1
Tc0
Tc1
ACT BA RA RA
NOP
RD/WR
NOP
PRE* BA
NOP
ACT BA RA RA
NOP
BA CA tRCD tRAS
tRP tRC
(*)=couldalsobePREALL
BA=bankaddress;RA=rowaddress;CA=columnaddress tRCD=tRCDRD,tRCDWR,tRCDRTR,tRCDWTRortRCDLTR,dependingoncommand
DontCare
Figure 39. Bank Activation Command Cycle
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5.6.BANKRESTRICTIONS
Theremaybeaneedtolimitthenumberofactivatesinarollingwindowtoensurethattheinstantaneous currentsupplyingcapabilityofthedevicesisnotexceeded.Toreflecttheshorttermcapabilityofthe GDDR5SGRAMcurrentsupply,theparametertFAW(fouractivatewindow)isdefined.Nomorethan4 banksmaybeactivatedinarollingtFAWwindow.ConvertingtoclocksisdonebydividingtFAW(ns)by tCK(ns)androundinguptonextintegervalue.Asanexampleoftherollingwindow,if(tFAW/tCK)rounds upto10clocks,andanactivatecommandisissuedatclockN,nomorethanthreefurtheractivatecom mandsmaybeissuedatclocksN+1throughN+9asillustratedinFigure40. ToreflectalongertermGDDR5SGRAMcurrentsupplycapability,theparametert32AW(thirtytwoacti vatewindow)isdefined.Nomorethan32banksmaybeactivatedinarollingt32AWwindow.Converting toclocksisdonebydividingt32AW(ns)bytCK(ns)androundinguptonextintegervalue.Theuseofa shorterandlongerrollingactivationwindowallowstheGDDR5SGRAMdesigntobeoptimizedtohandle higherinstantaneouscurrentswithinashorterwindowwhilestilllimitingthecurrentstrainoveralonger periodoftime.Thismeansthatingeneralt32AWwillbegreaterthanorequalto8*tFAWasshownin Figure41. ItispreferablethatGDDR5SGRAMshavenorollingactivationwindowrestrictions(tFAW=4*tRRD).
CK# CK CMD ACT
tRRD
ACT
ACT
ACT
ACT
ACT
ACT
ACT
tRRD
tRRD tFAW tFAW + 3 * t RRD
tRRD
tRRD
tRRD
tRRD=tRRDLortRRDSdependingonBankGroupson/offsettingandaccessedbanks
Figure 40. tRRD and tFAW
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A.)t32AW>8*tFAW
tFAW
tFAW
tFAW
tFAW
tFAW
tFAW
tFAW
tFAW
tFAW
t32AW
B.)t32AW=8*tFAW
tFAW
tFAW
tFAW
tFAW t32AW
tFAW
tFAW
tFAW
tFAW
tFAW
Figure 41. t32AW
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5.7.WRITE(WOM)
WRITEburstsareinitiatedwithaWRITEcommandasshowninFigure42.Thebankandcolumn addressesareprovidedwiththeWRITEcommandandautoprechargeiseitherenabledordisabledfor thataccesswiththeA8pin.Ifautoprechargeisenabled,therowbeingaccessedisprechargedatthecom pletionoftheburstaftertRAS(min)hasbeenmet.ThelengthoftheburstinitiatedwithaWRITEcommand iseightandthecolumnaddressisuniqueforthisburstofeight.Thereisnointerruptionnortruncationof WRITEbursts.
WRITE
CK# CK CKE# CS# RAS# CAS# WE# A10,A11 A0,A6 A9(A12) A1 A8 A7 BA0BA3 A2A5
ENAP DISAP
LOW
0,0
CA CA
BA
CA
BA=BankAddress;CA=ColumnAddress ENAP=EnableAutoPrecharge;DISAP=DisableAutoPrecharge
Figure 42. WRITE Command
DuringWRITEbursts,thefirstvaliddatainelementmustbeavailableattheinputlatchaftertheWrite Latency(WL).TheWriteLatencyisdefinedasWLmrs*tCK+tWCK2CKPIN+tWCK2CK+tWCK2DQI,where WLmrsisthenumberofclockcyclesprogramedinMR0,tWCK2CKPINisthephaseoffsetbetweenWCK andCKatthepinswhenphasealignedatphasedetector,tWCK2CKisthealignmenterrorbetweenWCK andCKattheGDDR5SGRAMphasedetector,andtWCK2DQIistheWCKtoDQ/DBI#offsetasmeasured attheDRAMpinstoensureconcurrentarrivalatthelatch.Thetotaldelayisrelativetothedataeyecenter averagedoveronedoublebyte.ThemaximumskewwithinadoublebyteisdefinedbytDQDQI. Thedatainputvalidwindow,tDIVW,definesthetimeregionwheninputdatamustbevalidforreliable datacaptureatthereceiverforanyoneworstcasechannel.Itaccountsforjitterbetweendataandclockat thelatchingpointintroducedinthepathbetweentheDRAMpadsandthelatchingpoint.Anyadditional jitterintroducedintothesourcesignals(i.e.withinthesystembeforetheDRAMpad)mustbeaccounted forinthefinaltimingbudgettogetherwiththechosenPLLmodeandbandwidth.tDIVWismeasuredat thepins.tDIVWisdefinedforthePLLoffandonmodeseparately.InthecaseofPLLon,tDIVWmustbe specifiedforeachsupportedbandwidth.IngeneraltDIVWissmallerthantDIPW.
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Thedatainputpulsewidth,tDIPW,definestheminimumpositiveornegativeinputpulsewidthforany oneworstcasechannelrequiredforproperpropagationofanexternalsignaltothereceiver.tDIPWismea suredatthepins.tDIPWisindependentofthePLLmode.IngeneraltDIPWislargerthantDIVW. Uponcompletionofaburst,assumingnootherWRITEdataisexpectedonthebustheGDDR5SGRAM DQandDBI#pinswillbedrivenaccordingtotheODTstate.Anyadditionalinputdatawillbeignored. DataforanyWRITEburstmaynotbetruncatedwithasubsequentWRITEcommand. DatafromanyWRITEburstmaybeconcatenatedwithdatafromasubsequentWRITEcommand.Acon tinuousflowofdatacanbemaintained.Thefirstdataelementfromthenewburstfollowsthelastelement ofacompletedburst.ThenewWRITEcommandshouldbeissuedafterthepreviousWRITEcommand accordingtothetCCDtiming.IfthatWRITEcommandistoanotherbankthenanACTIVEcommandmust precedetheWRITEcommandandtRCDWRalsomustbemet. AREADcanbeissuedanytimeafteraWRITEcommandaslongastheinternalturnaroundtimetWTRis met.IfthatREADcommandistoanotherbank,thenanACTIVEcommandmustprecedetheREADcom mandandtRCDRDalsomustbemet. APRECHARGEcanalsobeissuedtotheGDDR5SGRAMwiththesametimingrestrictionasthenew WRITEcommandiftRASismet.AfterthePRECHARGEcommand,asubsequentcommandtothesame bankcannotbeissueduntiltRPismet. ThedatainversionflagisreceivedontheDBI#pintoidentifywhethertostorethetrueorinverteddata.If DBI#isLOW,thedatawillbestoredafterinversioninsidetheGDDR5SGRAMandnotinvertedifDBI#is HIGH.WRITEDataInversioncanbeenabled(A9=0)ordisabled(A9=1)usingWDBIinMR1. WhenenabledbytheWRCRCflaginMR4,EDCdataarereturnedtothecontrollerwithalatencyof (WLmrs+CRCWL)*tCK+tWCK2CKPIN+tWCK2CK+tWCK2DQO,whereCRCWListheCRCWritelatency programmedinMR4andtWCK2DQOistheWCKtoDQ/DBI#/EDCphaseoffsetattheDRAMpins.
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WLmrs CK# CK
tCH
tCL
tCK
tWCK2CKPIN+tWCK2CK WCK WCK# Case1:NegativetWCK2DQI tWCK2DQI DQ/DBI# (mean) DQ/DBI# (firstbit) DQ/DBI# (lastbit) D0 D1 D2 D3 D4 D5 D6 D7 tDQDQI(min) D0 D1 D2 D3 D4 D5 D6 D7 tDQDQI(max) D0 D1 D2 D3 D4 D5 D6 D7
Case2:PositivetWCK2DQI DQ/DBI# (mean) DQ/DBI# (firstbit) DQ/DBI# (lastbit)
tWCK2DQI D0 D1 D2 D3 D4 D5 D6 D7 tDQDQI(min) D0 D1 D2 D3 D4 D5 D6 D7 tDQDQI(max) D0 D1 D2 D3 D4 D5 D6 D7 DontCare
1) WLmrsistheWRITElatencyprogrammedinModeRegisterMR0. 2) TimingsareshownwithpositivetWCK2CKPINandtWCK2CKvalues.SeeWCK2CKtimingsfor tWCK2CKPINandtWCK2CKranges. 3) tWCK2DQIparametervaluescouldbenegativeorpositivenumbers,dependingonPLLonorPLLoffmode operationanddesignimplementation.TheyalsovaryacrossPVT.Datatrainingisrequiredtodetermine theactualtWCK2DQIvalueforstableWRITEoperation. 4) tDQDQIdefinestheminimumtomaximumvariationoftWCK2DQIwithinadoublebyte(x32mode)or asinglebyte(x16mode). 5) DataReadtimingsareusedforCRCreturntimingfromWRITEcommandswithCRCenabled.
Figure 43. WRITE Timings
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T0 T1 T2 T3 T3n T4 T4n T5 T6 T7 T8
CK# CK
COMMAND
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ADDRESS
Banka, Coln
Coln
WL=WLmrs=3 WCK
WCK# DQ
DO n DO n+7
DBI#
DBI n
DBI n+7
EDC
EDCHoldPattern
DONTCARE
TRANSITIONINGDATA
Notes: 1.WLmrs=3isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections. 2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK. 3.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins. 4.BeforetheWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDWRmustbemet. 5.tWCK2DQI=0isshownforillustrationpurposes.
Figure 44. Single WRITE without EDC
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T0
CK# CK
T1
T2
T3
T3n
T4
T4n
T5
(( )) (( ))
T11
T12
T13
COMMAND
WRITE
NOP
NOP
NOP
NOP
NOP
(( )) ( ( NOP )) (( )) (( ))
NOP
NOP
ADDRESS
Banka, Coln
Coln
WL=WLmrs=3 WCK
WCK# DQ
DO n DO n+7
(( )) (( )) (( ))
DBI#
DBI n
DBI n+7
(( ))
EDC
EDCHoldPattern
(( )) (( ))
EDC n
EDC n+7
EDCHold Pattern
CRCWL=8
DONTCARE
TRANSITIONINGDATA
Notes: 1.WLmrs=3andCRCWL=8isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections. 2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK. 3.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins. 4.BeforetheWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDWRmustbemet. 5.tWCK2DQI,tWCKDQO=0isshownforillustrationpurposes.
Figure 45. Single WRITE with EDC
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T0
CK# CK
T1
T2
(( )) (( ))
T5
T5n
T6
T6n
T7
(( )) (( )) (( )) (( )) (( )) (( ))
T10
T10n
T11
T11n
T12
COMMAND
WRITE
NOP
ACT
(( )) WRITE (( )) (( ) ) Bankb, ( ( Coln )) tRCDWR
NOP
NOP
NOP
NOP
NOP
ADDRESS
Banka, Colm
Colm
Bankb, Row
Row
Coln
WL=WLmrs=5 WCK
WCK# DQ
WL=WLmrs=5
(( )) (( ))
(( )) (( )) (( ))
DO m DO m+7
(( ))
DO n
DO n+7
DBI#
(( ))
DBI m
DBI m+7
(( ))
DBI n
DBI n+7
DONTCARE
TRANSITIONINGDATA
Notes: 1.WLmrs=5andtRCDWR=3isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections. 2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK. 3.EDCmaybeonoroff.SeeFigure4forEDCTiming. 4.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins. 5.BeforetheWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDWRmustbemet. 6.tWCK2DQI=0isshownforillustrationpurposes.
Figure 46. Non-Gapless WRITEs
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T0
CK# CK
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
T7
T8
COMMAND
WRITE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
tCCD
ADDRESS
Banka, Colm Colm Banka, Coln Coln
WL=WLmrs=2 WCK
WCK# DQ
WL=WLmrs=2
DO m
DO m+7
DO n
DO n+7
DBI#
DBI m
DBI m+7
DBI n
DBI n+7
DONTCARE
TRANSITIONINGDATA
Notes: 1.WLmrs=2isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections. 2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK. 3.EDCmaybeonoroff.SeeFigure4forEDCTiming. 4.tCCD=tCCDSwhenbankgroupsisdisabledorthesecondWRITEistoadifferentbankgroup,otherwisetCCD=tCCDL. 5.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins. 6.BeforetheWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDWRmustbemet. 7.tWCK2DQI=0isshownforillustrationpurposes.
Figure 47. Gapless WRITEs
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T0
CK# CK
WRITE NOP
T1
(( )) (( )) (( )) (( )) (( )) (( ))
T3
T3n
T4
T4n
T5
(( )) (( )) (( )) (( )) (( )) (( ))
Ta0
(( )) (( ))
Ta6
Ta6n
Ta7
Ta8
COMMAND
NOP
NOP
NOP
READ
(( )) NOP (( )) (( )) (( ))
NOP
NOP
ADDRESS
Banka, Colm
Colm
Bankb, Coln
Coln
WL=WLmrs=3 WCK
WCK# DQ
(( )) (( )) (( ))
DO m DO m+7
tWTR
CL=CLmrs=6
(( )) (( )) (( )) (( )) (( )) (( ))
DO n DO n+7
DBI#
(( ))
DBI m
DBI m+7
(( ))
(( ))
DBI n
DBI n+7
DONTCARE
TRANSITIONINGDATA
Notes: 1.WLmrs=3andCLmrs=6isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections. 2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK. 3.EDCmaybeonoroff.SeeFigure4forEDCTiming. 4.tWTR=tWTRLwhenbankgroupsisenabledandbothWRITEandREADaccessbanksinthesamebankgroup,otherwisetWTR=tWTRS. 5.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins. 6.BeforetheREADandWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDortRCDWR respectivelymustbemet. 7.tWCK2DQI,tWCKDQO=0isshownforillustrationpurposes.
Figure 48. WRITE to READ
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T0
CK# CK
T1
T2
T3
T3n
T4
T4n
T5
T6
(( )) (( )) (( )) (( )) (( )) (( ))
Ta0
Ta1
COMMAND
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
PRE
NOP
tWR
ADDRESS
Banka, Coln Coln
tRP
Banka, orall
WL=WLmrs=3 WCK
WCK# DQ
DO n DO n+7
(( )) (( )) (( ))
DBI#
DBI n
DBI n+7
(( ))
DONTCARE
TRANSITIONINGDATA
Notes: 1.WLmrs=3isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections. 2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK. 3.EDCmaybeonoroff.SeeFigure4forEDCTiming. 4.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins. 5.BeforetheWRITEcommand,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDWRmustbemet. 6.tWCK2DQI=0isshownforillustrationpurposes.
Figure 49. WRITE to PRECHARGE
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5.8.WRITEDATAMASK(DM)
ThetraditionalmethodofusingaDMpinforWRITEdatamaskmustbeabandonedforanewmethod. DuetothehighdatarateofGDDR5SGRAMs,biterrorsareexpectedontheinterfaceandarenotrecover ablewhentheyoccuronthetraditionalDMpin. InGDDR5theDMissenttotheSGRAMovertheaddressfollowingthebank/columnaddresscycleassoci atedwiththecommand,duringtheNOP/DESELECTcommandsbetweentheWRITEcommandandthe nextcommand.TheDMisusedtomaskthecorrespondingdataaccordingtothefollowingtable.
Table17:DMState
FUNCTION WriteEnable WriteInhibit DM Value 0 1 DQ Valid X
TwoadditionalWRITEcommandsthataugmentthetraditionalWRITEWithoutMask(WOM)are requiredforproperDMsupport:
* WDM:WRITEWithDoublebyteMask:
2cyclecommandwherethe1stcyclecarriesaddressinformationandthe2ndcyclecarriesdatamask information(2bytegranularity);
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WDM
CK# CK CKE# CS# LOW
RAS# CAS# WE#
A9(A12) A1 A10,A11 A0,A6 A8 A7 BA0BA3 A2A5
CA
DM
DM
0,1
CA
DM
DM
ENAP DISAP
DM
DM
BA
CA
DM
DM
BA=BankAddress;CA=ColumnAddress;DM=DataMask ENAP=EnableAutoPrecharge;DISAP=DisableAutoPrecharge
Note:NOPshownasanexampleonly
Figure 50. WRITE-With-Doublebyte-Mask Command
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T0
CK# CK
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
T7
T8
COMMAND
WDM
NOP
WDM
NOP
NOP
NOP
NOP
NOP
NOP
tCCD
ADDRESS
Banka, Colm Colm DMm DMm Banka, Coln Coln DMn DMn
WL=WLmrs=2 WCK
WCK# DQ
WL=WLmrs=2
DO m
DO m+7
DO n
DO n+7
DBI#
DBI m
DBI m+7
DBI n
DBI n+7
DONTCARE
TRANSITIONINGDATA
Notes: 1.WLmrs=2isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections. 2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK. 3.EDCmaybeonoroff.SeeFigure4forEDCTiming. 4.tCCD=tCCDSwhenbankgroupsisdisabledorthesecondWRITEistoadifferentbankgroup,otherwisetCCD=tCCDL. 5.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins. 6.BeforetheWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDWRmustbemet. 7.tWCK2DQI=0isshownforillustrationpurposes.
Figure 51. WDM Timing
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* WSM:WRITEWithSinglebyteMask:
3cyclecommandwherethe1stcyclecarriesaddressinformation,the2ndand3rdcyclecarrydatamask information
WSM
CK# CK CKE# CS# LOW
RAS# CAS# WE#
A9(A12) A1 A10,A11 A0,A6 A8 A7 BA0BA3 A2A5
CA
DM
DM
DM
DM
0,1
CA
DM
DM
DM
DM
ENAP DISAP
DM
DM
DM
DM
BA
CA
DM
DM
DM
DM
BA=BankAddress;CA=ColumnAddress;DM=DataMask ENAP=EnableAutoPrecharge;DISAP=DisableAutoPrecharge
Note:NOPshownasanexampleonly
Figure 52. WRITE-With-Singlebyte-Mask Command
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T0
CK# CK
T1
T2
(( )) (( ))
T5
T5n
T6
T6n
T7
(( )) (( ))
T10
T10n
T11
T11n
T12
COMMAND
WSM
NOP
NOP
(( )) WSM (( )) (( ) ) Bankb, ( ( Coln ))
NOP
NOP
(( )) NOP (( )) ((
NOP
NOP
ADDRESS
Banka, Colm
Colm
DMm
DMm
DMm
DMm
Coln
DMn
DMn
DMn
DMn ) )
(( ))
WL=WLmrs=5 WCK
WCK# DQ
(( )) (( )) (( ))
DO m
WL=WLmrs=5
(( )) (( ))
DO m+7
(( ) ) DO
n
DO n+7
DBI#
(( ))
DBI m
DBI m+7
(( ) ) DBI
n
DBI n+7
DONTCARE
TRANSITIONINGDATA
Notes: 1.WLmrs=5andtRCDWR=3isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections. 2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK. 3.EDCmaybeonoroff.SeeFigure4forEDCTiming. 4.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins. 5.BeforetheWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDWRmustbemet. 6.tWCK2DQI=0isshownforillustrationpurposes.
Figure 53. WSM Timing
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Table 18WDMMappingformirrored&nonmirroredx32Mode ByteandBurstPositionMaskedduringWDM
ADR A10 A9 BA0 BA3 BA2 BA1 A11 A8 ADRCKRisingEdge Byte DQ[15:0] DQ[15:0] DQ[15:0] DQ[15:0] DQ[31:16] DQ[31:16] DQ[31:16] DQ[31:16] Burst
0 1 2 3 0 1 2 3
ADR A0 A1 A2 A3 A4 A5 A6 A7
ADRCK#RisingEdge Byte DQ[15:0] DQ[15:0] DQ[15:0] DQ[15:0] DQ[31:16] DQ[31:16] DQ[31:16] DQ[31:16] Burst
4 5 6 7 4 5 6 7
Table 19WDMMappingfornonmirroredx16Mode ByteandBurstPositionMaskedduringWDM
ADRCKRisingEdge ADR A10 A9 BA0 BA3 BA2 BA1 A11 A8 Byte DQ[7:0] DQ[7:0] DQ[7:0] DQ[7:0] DQ[23:16] DQ[23:16] DQ[23:16] DQ[23:16] Burst
0 1 2 3 0 1 2 3
ADR A0 A1 A2 A3 A4 A5 A6 A7
ADRCK#RisingEdge Byte DQ[7:0] DQ[7:0] DQ[7:0] DQ[7:0] DQ[23:16] DQ[23:16] DQ[23:16] DQ[23:16] Burst
4 5 6 7 4 5 6 7
Table 20WDMMappingformirroredx16Mode ByteandBurstPositionMaskedduringWDM
ADRCKRisingEdge ADR A10 A9 BA0 BA3 BA2 BA1 A11 A8 Byte DQ[15:8] DQ[15:8] DQ[15:8] DQ[15:8] DQ[31:24] DQ[31:24] DQ[31:24] DQ[31:24] Burst
0 1 2 3 0 1 2 3
ADR A0 A1 A2 A3 A4 A5 A6 A7
ADRCK#RisingEdge Byte DQ[15:8] DQ[15:8] DQ[15:8] DQ[15:8] DQ[31:24] DQ[31:24] DQ[31:24] DQ[31:24] Burst
4 5 6 7 4 5 6 7
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Table 21WSMMappingformirroredandnonmirroredx32Mode ByteandBurstPositionMaskedDuringWSM
ADRCK1strisingEdge
ADR A10 A9 BA0 BA3 BA2 BA1 A11 A8 Byte DQ[7:0] DQ[7:0] DQ[7:0] DQ[7:0] DQ[23:16] DQ[23:16] DQ[23:16] DQ[23:16] Burst
0 1 2 3 0 1 2 3
ADRCK#1strisingEdge
ADR A0 A1 A2 A3 A4 A5 A6 A7 Byte DQ[7:0] DQ[7:0] DQ[7:0] DQ[7:0] DQ[23:16] DQ[23:16] DQ[23:16] DQ[23:16] Burst
4 5 6 7 4 5 6 7
ADRCK2ndrisingEdge
ADR A10 A9 BA0 BA3 BA2 BA1 A11 A8 Byte DQ[15:8] DQ[15:8] DQ[15:8] DQ[15:8] DQ[31:24] DQ[31:24] DQ[31:24] DQ[31:24] Burst
0 1 2 3 0 1 2 3
ADRCK#2ndrisingEdge
ADR A0 A1 A2 A3 A4 A5 A6 A7 Byte DQ[15:8] DQ[15:8] DQ[15:8] DQ[15:8] DQ[31:24] DQ[31:24] DQ[31:24] DQ[31:24] Burst
4 5 6 7 4 5 6 7
Table 22WSMMappingfornonmirroredx16Mode ByteandBurstPositionMaskedDuringWSM
ADRCK1strisingEdge
ADR A10 A9 BA0 BA3 BA2 BA1 A11 A8 Byte DQ[7:0] DQ[7:0] DQ[7:0] DQ[7:0] DQ[23:16] DQ[23:16] DQ[23:16] DQ[23:16] Burst
0 1 2 3 0 1 2 3
ADRCK#1strisingEdge
ADR A0 A1 A2 A3 A4 A5 A6 A7 Byte DQ[7:0] DQ[7:0] DQ[7:0] DQ[7:0] DQ[23:16] DQ[23:16] DQ[23:16] DQ[23:16] Burst
4 5 6 7 4 5 6 7
ADRCK2ndrisingEdge
Byte Burst
0 1 2 3 0 1 2 3
ADRCK#2ndrisingEdge
Byte Burst
4 5 6 7 4 5 6 7
Table 23WSMMappingformirroredx16Mode ByteandBurstPositionMaskedDuringWSM
ADRCK1strisingEdge Byte Burst
0 1 2 3 0 1 2 3
ADRCK#1strisingEdge Byte Burst
4 5 6 7 4 5 6 7
ADRCK2ndrisingEdge ADR A10 A9 BA0 BA3 BA2 BA1 A11 A8 Byte DQ[15:8] DQ[15:8] DQ[15:8] DQ[15:8] DQ[31:24] DQ[31:24] DQ[31:24] DQ[31:24] Burst
0 1 2 3 0 1 2 3
ADRCK#2ndrisingEdge ADR A0 A1 A2 A3 A4 A5 A6 A7 Byte DQ[15:8] DQ[15:8] DQ[15:8] DQ[15:8] DQ[31:24] DQ[31:24] DQ[31:24] DQ[31:24] Burst
4 5 6 7 4 5 6 7
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5.9.READ
AREADburstisinitiatedwithaREADcommandasshowninFigure54.Thebankandcolumnaddresses areprovidedwiththeREADcommandandautoprechargeiseitherenabledordisabledforthataccess withtheA8address.Ifautoprechargeisenabled,therowbeingaccessedisprechargedatthecompletion oftheburstaftertRAS(min)hasbeenmet.ThelengthoftheburstinitiatedwithaREADcommandiseight andthecolumnaddressisuniqueforthisburstofeight.ThereisnointerruptionnortruncationofREAD bursts.
READ
CK# CK CKE# CS# RAS# CAS# WE# A10,A11 A0,A6 A9(A12) A1 A8 A7 BA0BA3 A2A5
ENAP DISAP
LOW
0,0
CA CA
BA
CA
BA=BankAddress;CA=ColumnAddress ENAP=EnableAutoPrecharge;DISAP=DisableAutoPrecharge
Figure 54. READ Command
DuringREADbursts,thefirstvaliddataoutelementwillbeavailableaftertheCASlatency(CL).TheCAS LatencyisdefinedasCLmrs*tCK+tWCK2CKPIN+tWCK2CK+tWCK2DQO,whereCLmrsisthenumberof clockcyclesprogramedinMR0,tWCK2CKPINisthephaseoffsetbetweenWCKandCKatthepinswhen phasealignedatphasedetector,tWCK2CKisthealignmenterrorbetweenWCKandCKattheGDDR5 SGRAMphasedetector,andtWCK2DQOistheWCKtoDQ/DBI#/EDCoffsetasmeasuredattheDRAM pins.Thetotaldelayisrelativetothedataeyeinitialedgeaveragedoveronedoublebyte.Themaximum skewwithinadoublebyteisdefinedbytDQDQO. Uponcompletionofaburst,assumingnootherREADcommandhasbeeninitiated,allDQandDBI#pins willdriveavalueof1andtheODTwillbeenabledatamaximumof1tCKlater.Thedrivevalueandter minationvaluemaybedifferentduetoseparatelydefinedcalibrationoffsets.IftheODTisdisabled,the pinswilldriveHiZ. DatafromanyREADburstmaybeconcatenatedwithdatafromasubsequentREADcommand.Acontin uousflowofdatacanbemaintained.Thefirstdataelementfromthenewburstfollowsthelastelementof acompletedburst.ThenewREADcommandshouldbeissuedafterthepreviousREADcommandaccord ingtothetCCDtiming.IfthatREADcommandistoanotherbankthenanACTIVEcommandmustpre cedetheREADcommandandtRCDRDalsomustbemet.
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AWRITEcanbeissuedanytimeafteraREADcommandaslongasthebusturnaroundtimetRTWismet. IfthatWRITEcommandistoanotherbank,thenanACTIVEcommandmustprecedethesecondWRITE commandandtRCDWRalsomustbemet. APRECHARGEcanalsobeissuedtotheGDDR5SGRAMwiththesametimingrestrictionasthenew READcommandiftRASismet.AfterthePRECHARGEcommand,asubsequentcommandtothesame bankcannotbeissueduntiltRPismet. ThedatainversionflagisdrivenontheDBI#pintoidentifywhetherthedataistrueorinverteddata.If DBI#isHIGH,thedataisnotinverted,andifLOWitisinverted.READDataInversioncanbeenabled (A8=0)ordisabled(A8=1)usingRDBIinMR1.
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WhenenabledbytheRDCRCflaginMR4,EDCdataisreturnedtothecontrollerwithalatencyof(CLmrs +CRCRL)*tCK+tWCK2CKPIN+tWCK2CK+tWCK2DQO,whereCRCRListheCRCReadlatencypro grammedinMR4.
CLmrs CK# CK tWCK2CKPIN+tWCK2CK WCK WCK# Case1:NegativetWCK2DQO tWCK2DQO DQ/DBI#/EDC (mean) DQ/DBI#/EDC (firstbit) DQ/DBI#/EDC (lastbit) D0 D1 D2 D3 D4 D5 D6 D7 tDQDQO(min) D0 D1 D2 D3 D4 D5 D6 D7 tDQDQO(max) D0 D1 D2 D3 D4 D5 D6 D7 tCH tCL tCK
Case2:PositivetWCK2DQO DQ/DBI#/EDC (mean) DQ/DBI#/EDC (firstbit) DQ/DBI#/EDC (lastbit)
tWCK2DQO D0 D1 D2 D3 D4 D5 D6 D7 tDQDQO(min) D0 D1 D2 D3 D4 D5 D6 D7 tDQDQO(max) D0 D1 D2 D3 D4 D5 D6 D7 DontCare
1) CLmrsistheCASlatencyprogrammedinModeRegisterMR0. 2) TimingsareshownwithpositivetWCK2CKPINandtWCK2CKvalues.SeeWCK2CKtimingsfor tWCK2CKPINandtWCK2CKranges. 3) tWCK2DQOparametervaluescouldbenegativeorpositivenumbers,dependingonPLLonorPLLoffmode operationanddesignimplementation.TheyalsovaryacrossPVT.Datatrainingisrequiredtodetermine theactualtWCK2DQOvalueforstableREADoperation. 4) tDQDQOdefinestheminimumtomaximumvariationoftWCK2DQOwithinadoublebyte(x32mode)or asinglebyte(x16mode). 5) tDQDQOalsoappliesforCRCdatafromWRITEandREADcommandswithCRCenabled,theEDChold pattern,andthedatastrobeinRDQSmode.
Figure 55. READ Word Lane Timing
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T0
CK# CK COMMAND
READ NOP NOP
T1
T2
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
T5
T6
T6n
T7
T7n
T8
T9
T10
NOP
NOP
NOP
NOP
NOP
NOP
ADDRESS
Banka, Coln
Coln
CL=CLmrs=6
WCK WCK# DQ
DO n
DO n+7
DBI#
DBI n
DBI n+7
ODT
ODTEnabled
(( )) (( )) (( )) (( ))
ODTDisabled
ODTEnabled
EDC
EDCHoldPattern
DONTCARE
TRANSITIONINGDATA
Notes: 1.CLmrs=6isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections. 2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK. 3.BeforetheREADcommand,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDmustbemet. 4.tWCK2DQO=0isshownforillustrationpurposes.
Figure 56. Single READ without EDC
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T0
CK# CK
T1
(( )) (( )) (( )) (( )) (( )) (( ))
T6
T6n
T7
T7n
T8
T9
T10
T10n
T11
T11n
T12
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ADDRESS
Banka, Coln
Coln
CL=CLmrs=6
WCK WCK# DQ
(( )) (( )) (( ))
DO n
DO n+7
DBI#
(( ))
DBI n
DBI n+7
EDC
(( )) (( ))
EDCHoldPattern
EDC n
EDC n+7
EDCHold Pattern
CRCRL=4
DONTCARE
TRANSITIONINGDATA
Notes: 1.CLmrs=6andCRCRL=4areshownasexamples.ActualsupportedvalueswillbefoundintheMRandACtimingssections. 2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK. 3.BeforetheREADcommand,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDmustbemet. 4.tWCK2DQO=0isshownforillustrationpurposes.
Figure 57. Single READ with EDC
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T0
CK# CK
NOP
T1
(( )) (( )) (( )) (( )) (( )) (( ))
T3
(( )) (( ))
T6
T6n
T7
T7n
T8
T9
T9n
T10
T10n
T11
COMMAND
READ
READ
tCCD
ADDRESS
Banka, Colm Colm
(( )) NOP (( )) (( )) (( ))
NOP
NOP
NOP
NOP
NOP
Bankb, Coln
Coln
CL=CLmrs=6 WCK
WCK# DQ
CL=CLmrs=6
(( )) (( )) (( )) (( )) (( )) (( ))
DO m DO m+7 DO n DO n+7
DBI#
(( ))
(( ))
DBI m
DBI m+7
DBI n
DBI n+7
DONTCARE
TRANSITIONINGDATA
Notes: 1.CLmrs=6isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections. 2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK. 3.EDCmaybeonoroff.SeeFigure4forEDCTiming. 4.tCCD=tCCDLwhenbankgroupsareenabledandbothREADsaccessbanksinthesamebankgroup;otherwisetCCD=tCCDS. 5.BeforetheREADcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDmustbemet. 6.tWCK2DQI=0isshownforillustrationpurposes.
Figure 58. Non-Gapless READs
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T0
CK# CK
READ NOP READ NOP
T1
T2
T3
(( )) (( )) (( )) (( )) (( )) (( ))
T6
T6n
T7
T7n
T8
T8n
T9
T9n
T10
COMMAND
NOP
NOP
NOP
NOP
NOP
tCCD
ADDRESS
Banka, Colm Colm Bankb, Coln Coln
CL=CLmrs=6 WCK
WCK# DQ
(( )) (( )) (( ))
DO m DO m+7 DO n DO n+7
DBI#
(( ))
DBI m
DBI m+7
DBI n
DBI n+7
DONTCARE
TRANSITIONINGDATA
Notes: 1.CLmrs=6isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections. 2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK. 3.EDCmaybeonoroff.SeeFigure4forEDCTiming. 4.tCCD=tCCDSwhenbankgroupsaredisabledorthesecondREADistoadifferentbankgroup;otherwisetCCD=tCCDL. 5.BeforetheREADcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDmustbemet. 6.tWCK2DQI=0isshownforillustrationpurposes.
Figure 59. Gapless READs
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T0
CK# CK
T1
(( )) (( )) (( )) (( )) (( )) (( ))
T6
T6n
T7
T7n
T8
T9
T10
T10n
T11
T11n
T12
COMMAND
READ
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
tRTW
ADDRESS
Banka, Colm Colm
Bankb, Coln
Coln
CL=CLmrs=6 WCK
WCK# DQ
(( )) (( )) (( ))
DO m
WL=WLmrs=3
DO m+7
DO n
DO n+7
DBI#
(( ))
DBI m
DBI m+7
DBI n
DBI n+7
DONTCARE
TRANSITIONINGDATA
Notes: 1.WLmrs=3andCLmrs=6isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections. 2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK. 3.EDCmaybeonoroff.SeeFigure4forEDCTiming. 4.tWTR=tWTRLwhenbankgroupsisenabledandbothWRITEandREADaccessbanksinthesamebankgroup,otherwisetWTR=tWTRS. 5.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins. 6.BeforetheREADandWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDortRCDWR respectivelymustbemet. 7.tWCK2DQI,tWCKDQO=0isshownforillustrationpurposes.
Figure 60. READ to WRITE
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T0
CK# CK
T1
T2
T3
T4
T5
T6
T6n
T7
T7n
T8
COMMAND
READ
NOP
PRE
NOP
NOP
NOP
NOP
NOP
NOP
tRTP
ADDRESS
Banka, Coln Coln Banka, orall
tRP
CL=CLmrs=6 WCK
WCK# DQ
DO n DO n+7
DBI#
DBI n
DBI n+7
DONTCARE
TRANSITIONINGDATA
Notes: 1.CLmrs=6isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections. 2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK. 3.EDCmaybeonoroff.SeeFigure4forEDCTiming. 4.tRTP=tRTPLwhenbankgroupsareenabledandthePRECHARGEcommandaccessesthesamebank;otherwisetRTP=tRTPS. 5.BeforetheREADcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDmustbemet. 6.tWCK2DQO=0isshownforillustrationpurposes.
Figure 61. READ to PRECHARGE
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5.10.DQPREAMBLE
DQpreambleisafeatureforGDDR5SGRAMsthatisusedforREADdata.DQpreambleconditionsthe DQsforbettersignalintegrityontheinitialdataofaburst. Onceenabledbybit5inMR7,theDQpreamblewillprecedeallREADbursts,includingnonconsecutive READburstswithaminimumgapof1tCK,asshowninFigure58.Whenenabled,theDQpreamblepat ternappliestoallDQandDBI#pinsinabyte,andthesamepatternisusedforallbytesasshownin Figure62.DQpreambleisenabledordisabledforallbytes.TheEDCpinineachbyteisnotincludedinthe DQpreamble.IfODTisenabled,theODTisdisabled1tCKbeforethestartofthepreamblepatternas showninFigure63. ThepreamblepatternontheDBI#pinisonlyenablediftheMRforRDBIisenabled(MR1A8bit).During thepreambletheDBI#pinistreatedasanotherDQpinandthepreamblepatternontheDQsisnot encodedwithRDBI.IfRDBIisdisabled,thentheDBI#pindrivesODT.
Byte0
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 DBI0#
Byte1
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DBI1#
Byte2
DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DBI2#
Byte3
DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DBI3# Max0's 1 1 1 1 1 1 1 1 1 0
Idle
1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1 0 1 0 5
Preamble
1 0 1 0 1 0 1 0 1 4 0 1 0 1 0 1 0 1 0 5 1 0 1 0 1 0 1 0 1 4 x x x x x x x x x 4 x x x x x x x x x 4 x x x x x x x x x 4
Burst
x x x x x x x x x 4 x x x x x x x x x 4 x x x x x x x x x 4 x x x x x x x x x 4 x x x x x x x x x 4
Time
Notes: 1)ThenumberofMax0'sintheburstis4onlyifRDBIisenabled.Max0`sisonaperbytebasisanddoesnotincludetheEDCpin. 2)x=ValidData
Figure 62. DQ Preamble Pattern
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T0
CK# CK COMMAND
READ NOP
T1
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
T4
T5
T5n
T6
T6n
T7
T7n
T8
T9
T10
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ADDRESS
Banka, Coln
Coln
CL=CLmrs=6
WCK WCK# DQ6
DO n
DO n+7
DQ7
DO n
DO n+7
DBI#
DBI n
DBI n+7
ODT
ODTEnabled
(( )) (( ))
ODTDisabled
ODTEnabled
DONTCARE
TRANSITIONINGDATA
Notes: 1.CLmrs=6isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections. 2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK. 3.EDCmaybeonoroff.SeeFigure4forEDCTiming. 4.DQ6,DQ7andtheDBI#pinareshowntoillustratetheDQpreamblepattern.RDBIisEnabled(MR1A8=0). 5.BeforetheREADcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDmustbemet. 6.tWCK2DQO=0isshownforillustrationpurposes.
Figure 63. Preamble Timing Diagram
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5.11.READandWRITEDATABUSINVERSION(DBI)
TheGDDR5SGRAMDataBusInversion(DBIdc)reducestheDCpowerconsumptionondatapins,asthe numberofDQlinesdrivingalowlevelcanbelimitedto4withinabyte.DBIdcisevaluatedperbyte. ThereisoneDBI#pinperbyte:DBI0#isassociatedwithDQ0DQ7,DBI1#withDQ8DQ15,DBI2#with DQ16DQ23andDBI3#withDQ24DQ31. TheDBI#pinsarebidirectionalactiveLowdoubledatarate(DDR)signals.ForWrites,theyaresampled bytheGDDR5SGRAMalongwiththeDQofthesamebyte.ForReads,theyaredrivenbytheGDDR5 SGRAMalongwiththeDQofthesamebyte. OnceenabledbythecorrespondingRDBIModeRegisterbit,theGDDR5SGRAMinvertsreaddataand setsDBI#Low,whenthenumberof'0'databitswithinabyteisgreaterthan4;otherwisetheGDDR5 SGRAMdoesnotinvertthereaddataandsetsDBI#High,asshowninFigure64. OnceenabledbythecorrespondingWDBIModeRegisterbit,theGDDR5SGRAMinvertswritedata receivedontheDQinputsincaseDBI#wassampledLow,orleavesthedatanoninvertedincaseDBI# wassampledHigh,asshowninFigure65.
from DRAM core 8 8 DQ
'0' count >4
fromModeRegister: 0=enabled 1=disabled
DBI#
Figure 64. Example of Data Bus Inversion Logic for READs
8 DQ DBI# 8
to DRAM core
fromModeRegister: 0=enabled 1=disabled
Figure 65. Example of Data Bus Inversion Logic for WRITEs
TheflowdiagraminFigure66illustratestheDBIdcoperation.Inanycase,thetransmitter(thecontroller forWRITEs,theGDDR5SGRAMforREADs)decideswhethertoinvertornotinvertthedataconveyedon theDQs.Thereceiver(theGDDR5SGRAMforWRITEs,thecontrollerforREADs)hastoperformthe reverseoperationbasedonthelevelontheDBI#pin.Datainputandoutputtimingparametersareonly validwithDBIbeingenabledandamaximumof4datalinesperbytedrivenLow.
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Transmitter
Logical outputdata Determine'0'count indatabyte
No DBI#='H' Don'tinvert databyte
'0'count >4?
Yes DBI#='L' Invert databyte
DBI#='H' Don'tinvert databyte
DBI#='L' Invert databyte
Receiver
Logical inputdata
Figure 66. DBI Flow Diagram
DBI#PinSpecialFunctionOverview TheDBI#pinhasspecialbehaviorcomparedtoDQpinsbecauseoftheabilitytoenableanddisableitvia MRS.ForeitherWRITEorREADDBI#pintraining,bothDBIREADandDBIWRITEinMRSmustbe enabled.ThebehavioroftheDBI#pininvariousmoderegistersettingsissummarizedbelow: IfbothDBIREADandDBIWRITEareenabled:
* PindrivesDBIFIFOdatawithRDTRcommand * DBI#pinFIFOacceptsWRTRdatawiththeWRTRcommand
IfonlyDBIREADisenabled:
* DBI#pindrivesODTwhennotREADorRDTR
IfonlyDBIWRITEisenabled:
* PinalwaysdrivesODT(unlessRESET)
IfbothDBIREADandDBIWRITEaredisabled:
* DBI#pindrivesODT(unlessRESET)
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5.12.ERRORDETECTIONCODE(EDC)
TheGDDR5SGRAMprovideserrordetectiononthedatabustoimprovesystemreliability.Thedevice generatesachecksumperbytelaneforbothREADandWRITEdataandreturnsthechecksumtothecon troller.Basedonthechecksum,thecontrollercandecideifthedata(orthereturnedCRC)wastransmitted inerrorandretrytheREADorWRITEcommand.TheGDDR5SGRAMitselfdoesnotperformanyerror correction.ThefeaturesoftheEDCare:
* 8bitchecksumon72bits(9channelsx8bitburst) * dedicatedEDCtransferpinper9channels(4xperGDDR5SGRAM) * asymmetricallatenciesonEDCtransferforReadsandWrites
TheCRCpolynomialusedbytheGDDR5SGRAMisanATM8HEC,X^8+X^2+X^1+1.Thestartingseed valueissetinhardwareat"zero".Table24showstheerrortypesthataredetectableandthedetectionrate.
Table 24ErrorCorrectionDetails
ErrorType RandomSingleBit RandomDoubleBit RandomOddCount Burst<=8 DetectionRate 100% 100% 100% 100%
ThebitorderingcalculationfortheCRCerrordetectionisoptimizedforerrorsinthetimeburstdirection. Figure67showsthebitorientationonabytelanebasis.
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CRCDataInput DQ/DBI#bitordering
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DBI0#
T0 0 0 8 16 24 32 40 48 56 64
Burst8Ordering(2tCK) 1 1 9 17 25 33 41 49 57 65 2 2 10 18 26 34 42 50 58 66 3 3 11 19 27 35 43 51 59 67 4 4 12 20 28 36 44 52 60 68 5 5 13 21 29 37 45 53 61 69 6 6 14 22 30 38 46 54 62 70 7 7 15 23 31 39 47 55 63 71
T0+8U.I.
CRCPolynomial
X8+X2+X+1=0x83=(X+1)(X7+X6+X5+X4+X3+X2+1)
CRCDataOutput EDCbitordering
T0
Burst8Ordering(2tCK) X0 X1 X2 X3 X4 X5 X6 X7
T0+8U.I.
Figure 67. EDC Calculation matrix
TheCRCcalculationisembeddedintotheWRITEandREADdatastreamasshowninFigure16:
* forWRITEs,theCRCchecksumiscalculatedontheDQandDBI#inputdatabeforedecodingwithDBI * forREADs,theCRCchecksumiscalculatedontheDQandDBI#outputdataafterencodingwithDBI
Thebitorderingisoptimizedforerrorsinthetimeburstdirection.Figure67showsthebitorientationona bytelanebasis.All1sareassumedinthecalculationfortheDBI#inburstincaseDBIisdisabledfor WRITEsorREADsintheModeRegister. TheCRCcalculationisalsonotaffectedbyanydatamasksentalongwithWDM,WDMA,WSMorWSMA commands. TheEDClatencyisbasedontheCASlatencyforREADdataandtheWRITElatencyforWRITEdata. Table25showsthe2timingparametersassociatedwiththeEDCscheme. ModeRegister4isusedtodeterminethefunctionalityoftheEDCpin.RegisterbitsA9andA10controlthe GDDR5SGRAM'sCRCcalculationindependentlyforREADsandWRITEs.WithEDCoff,thecalculated CRCpatternwillbereplacedbytheEDCholdpatterndefinedinModeRegisterbitsA0A3.See"Mode Registersonpage39"sectionformoredetails.
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Table 25EDCTiming
Description EDCREADLatency EDCWRITELatency Parameter tEDCRL tEDCWL Value CL+CRCRL WL+CRCWL Units tCK tCK
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EDCPinSpecialFunctionOverview TheEDCpinisusedformanydifferentfunctions.ThebehavioroftheEDCpininvariousmodesissum marizedinTable26.
Table 26EDCPinBehavior
DeviceStatus Condition RESET#=LOW DevicePowerup RESET#=HIGH;noWCKclocks RESET#=HIGH;stableWCKclocks WCK2CKTraining WCKissampledHigh WCKissampledLow EDC13invMR4A11=0 Idle EDC13invMR4A11=1 WRCRCon WRCRCoff RDCRCon RDCRCoff WRCRC+RDCRCbothonorbothoff WCKenabled(MR5A1=0) PowerDown SelfRefresh ReadBurstinRDQSMode WCKdisabledduringPowerDown usingMR5A1=1 MR3A5=1 HiZ High EDCholdpattern(default='1111') EDCholdpattern('1111') InvertedEDCholdpattern('0000') EDCholdpattern EDC0,EDC2:EDCholdpattern EDC1,EDC3:invertedEDCholdpattern CRCdata EDCholdpattern CRCdata EDCholdpattern EDCholdpattern EDCholdpattern EDCholdpattern High High Fixed'1010'strobepatternwith4U.I. preamble EDC0,EDC2:Fixed'1010'strobepattern with4U.I.preamble EDC1,EDC3:Fixed'0101'strobepattern with4U.I.preamble EDC0EDC3PinStatus
WRITEBurst
READorRDTRburst LDFF WRTRburst
READburstinRDQSModewith MR3A5=1;EDC13invMR4A11=1 RDQSpseudodifferential
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5.13.PRECHARGE
ThePRECHARGEcommand(seeFigure68)isusedtodeactivatetheopenrowinaparticularbank(PRE) ortheopenrowinallbanks(PREALL).Thebank(s)willbeavailableforasubsequentrowaccessaspeci fiedtime(tRP)afterthePRECHARGEcommandisissuedasillustratedinFigure39. InputA8determineswhetheroneorallbanksaretobeprecharged.Incasewhereonlyonebankistobe precharged,inputsBA0BA3selectthebank.OtherwiseBA0BA3aretreatedas"Don'tCare". Onceabankhasbeenprecharged,itisintheidlestateandmustbeactivatedpriortoanyREADorWRITE commandbeingissued.APRECHARGEcommandwillbetreatedasaNOPifthereisnoopenrowinthat bank,orifthepreviouslyopenrowisalreadyintheprocessofprecharging.SequencesofPRECHARGE commandsmustbespacedbyatleasttPPDasshowninFigure69.
Precharge
CK# CK CKE# CS# LOW
RAS# CAS# WE#
A9A11(A12) A0,A1,A6,A7 A8 A7 BA0BA3 A2A5
PREALL
PRE
BA
BA=BankAddress(ifA8isLOW; otherwiseDontCare)
Figure 68. PRECHARGE command
T0 CK# CK CMD ADDR tRAS
BAx,y=bankaddressx,y
T1
T2
T3
T4
NOP
PRE BAx
NOP
PRE BAy
NOP
tPPD
tRP DontCare
Figure 69. Precharge to Precharge Timings
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5.14.AUTOPRECHARGE
AutoPrechargeisafeaturewhichperformsthesameindividualbankprechargefunctionasdescribed above,butwithoutrequiringanexplicitcommand.ThisisaccomplishedbyusingA8(A8=High),to enableAutoPrechargeinconjunctionwithaspecificREADorWRITEcommand.Aprechargeofthebank /rowthatisaddressedwiththeREADorWRITEcommandisautomaticallyperformeduponcompletion ofthereadorwriteburst.AutoPrechargeisnonpersistentinthatitiseitherenabledordisabledforeach individualREADorWRITEcommand. AutoPrechargeensuresthataprechargeisinitiatedattheearliestvalidstagewithinaburst.Theuser mustnotissueanothercommandtothesamebankuntiltheprechargetime(tRP)iscompleted.Thisis determinedasifanexplicitPRECHARGEcommandwasissuedattheearliestpossibletime,asdescribed foreachbursttypeintheOPERATIONsectionofthisspecification.
5.15.REFRESH
TheREFRESHcommandisusedduringnormaloperationoftheGDDR5SGRAM.Thecommandisnon persistent,soitmustbeissuedeachtimearefreshisrequired.AminimumtimetRFCisrequiredbetween twoREFRESHcommands.Thesameruleappliestoanyaccesscommandaftertherefreshoperation.All banksmustbeprechargedpriortotheREFRESHcommand. Therefreshaddressingisgeneratedbytheinternalrefreshcontroller.ThismakestheaddressbitsDont CareduringaREFRESHcommand.TheGDDR5SGRAMrequiresREFRESHcyclesatanaverageperi odicintervaloftREFI(max).ThevaluesoftREFIfordifferentdensitiesarelistedinTable6.Toallowfor improvedefficiencyinschedulingandswitchingbetweentasks,someflexibilityintheabsoluterefresh intervalisprovided.AmaximumofeightREFRESHcommandscanbepostedtotheGDDR5SGRAM,and themaximumabsoluteintervalbetweenanyREFRESHcommandandthenextREFRESHcommandis9* tREFI. DuringREFRESH,andwhenbitA2inMR5issetto0,WRTR,RDTR,andLDFFcommandsareallowedat timetREFTRaftertheREFRESHcommand,whichenable(incremental)datatrainingtooccurinparallel withtheinternalrefreshoperationandthuswithoutlossofperformanceontheinterface.SeeREADTrain ingandWRITETrainingfordetails. AsimpedanceupdatesfromtheautocalibrationenginemayoccurwithanyREFRESHcommand,itissafe toonlyissueNOPcommandsduringtKOperiodtopreventfalsecommand,addressordatalatching resultingfromimpedanceupdates.
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Refresh
CK# CK CKE# CS# LOW
RAS# CAS#
WE#
A9A11(A12) A0,A1,A6 A8 A7 BA0BA3 A2A5
Figure 70. REFRESH command
T0 CK# CK CMD PRE ALL
T1
Ta0
Ta1
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Tc0
NOP tRP
REF
NOP tREFTR
WRTR
NOP
NOP tRFC
NOP
NOP
NOP
ACT
ADDR tKO WCK WCK# DQ
D0 D1 D2 D3 D4 D5 D6 D7
BA RA WL=3
BA=bankaddress;RA=rowaddress WRTRandRDTRcommandsareallowedduringrefreshunlessdisabledintheModeRegister
DontCare
WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdetermines theneededoffsetbetweenWCKandCK.
Figure 71. Refresh Timings
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5.16.SELFREFRESH
SelfRefreshcanbeusedtoretaindataintheGDDR5SGRAM,eveniftherestofthesystemispowered down.WhenintheSelfRefreshmode,theGDDR5SGRAMretainsdatawithoutexternalclocking.The SELFREFRESHENTRYcommand(seeFigure72)isinitiatedlikeaREFRESHcommandexceptthatCKE# ispulledHIGH.SELFREFRESHENTRYisonlyallowedwhenallbanksareprechargedwithtRPsatisfied, andwhenthelastdataelementorCRCdataelementfromaprecedingREADorWRITEcommandhave beenpushedout(tRDSRE).NOPcommandsarerequireduntiltCKSREismetaftertheenteringSelfRefresh. ThePLLisautomaticallydisableduponenteringSelfRefreshandisautomaticallyenabledandresetupon exitingSelfRefresh.IftheGDDR5SGRAMentersSelfRefreshwiththePLLdisabled,itwillexitSelf RefreshwiththePLLdisabled. OncetheSELFREFRESHENTRYcommandisregistered,CKE#mustbeheldHIGHtokeepthedevicein SelfRefreshmode.WhenthedevicehasenteredtheSelfRefreshmode,allexternalcontrolsignals,except CKE#andRESET#are"Don'tcare".ForproperSelfRefreshoperation,allpowersupplyandreference pins(VDD,VDDQ,VSS,VSSQ,VREFC,VREFD)mustbeatvalidlevels.TheGDDR5SGRAMinitiatesa minimumofoneinternalrefreshwithintCKEperiodonceitentersSelfRefreshmode.Theaddress,com mand,dataandWCKpinsareinODTstate,andtheEDCpinsdriveaHIGH. TheclockisinternallydisabledduringSelfRefreshoperationtosavepower.Theminimumtimethatthe GDDR5SGRAMmustremaininSelfRefreshmodeistCKE.Theusermaychangetheexternalclockfre quencyorhalttheexternalCKandWCKclockstCKSREafterSelfRefreshentryisregistered.However,the clocksmustberestartedandstabletCKSRXbeforethedevicecanexitSelfRefreshoperation. TheprocedureforexitingSelfRefreshrequiresasequenceofevents.First,theCKandWCKclocksmust bestablepriortoCKE#goingbackLOW.AdelayofatleasttXSNRWmustbesatisfiedbeforeavalidcom mandnotrequiringalockedPLLcanbeissuedtothedevicetoallowforcompletionofanyinternal refreshinprogress.BeforeacommandrequiringalockedPLLcanbeapplied,adelayofatleasttXSRW mustbesatisfied. DuringSelfRefreshtheondietermination(ODT)anddriverwillnotbeautocalibrated.Therefore,itis recommendedthattheODTanddriverberecalibratedbythecontrolleruponexitingSelfRefresh.Alter natively,ifchangesinvoltageandtemperaturearetrackedorknowntobeboundedthentheprovided VoltageandTemperatureVariationtablesmaybeconsultedtodetermineifrecalibrationisnecessary. UponexitfromSelfRefresh,theGDDR5SGRAMcanbeputbackintoSelfRefreshmodeafterwaitingat leasttXSNRWperiodandissuingoneextraREFRESHcommand.
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SelfRefresh
CK# CK HIGH CKE# CS#
RAS# CAS# WE#
A9A11(A12) A0,A1,A6 A8 A7 BA0BA3 A2A5
Figure 72. SELF REFRESH Entry Command
T0 CK# CK CKE#
T1
T2
Ta0
Tb0
Tb1
Tb2
Tc0
Td0
tCKSRE tRDSREortWRSRE tRP
tCKSRX
tCMDS tXSRW tXSNRW
tCPDED NOP NOP NOP
CMD ADDR DQ
NOP
SRE
SRX
PREA
Valid
EnterSelfRefreshMode
ExitSelfRefreshMode
DontCare
SelfrefreshexitrequiresWCK2CKtrainingpriortoanyWRITEorREADoperation AtleastoneREFRESHcommandshallbeissuedaftertXSNRWforoutputdriverandterminationimpedanceupdates.
Figure 73. Self Refresh Entry and Exit
Note: 1.Clock(CKandCK#)mustbestablebeforeexitingselfrefreshmode. 2.Devicemustbeintheallbanksidlestatepriortoenteringselfrefreshmode. 3.tXSNRWisrequiredbeforeanynonREADorWRITEcommandcanbeapplied,andtXSRWisrequiredbeforeaREADorWRITEcommandcanbe applied. 4.REF=REFRESHcommand.
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Table 27PinStatesDuringSelfRefresh
Pin EDC DQ/DBI# ADR/CMD CKE# WCK/WCK# State High ODT ODT ODT(DrivenHighbyController) ODT
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5.17.POWERDOWN
GDDR5SGRAMsrequiresCKE#tobeLOWatalltimesanaccessisinprogress:fromtheissuingofa READorWRITEcommanduntilcompletionoftheburst.ForREADs,aburstcompletionisdefinedas whenthelastdataelementincludingCRChasbeentransmittedontheDQoutputs,forWRITEs,aburst completionisdefinedaswhenthelastdataelementhasbeenwrittentothememoryarrayandCRCdata hasbeenreturnedtothecontroller. POWERDOWNisenteredwhenCKE#isregisteredHIGH.IfPOWERDOWNoccurswhenallbanksare idle,thismodeisreferredtoasprechargePOWERDOWN;ifPOWERDOWNoccurswhenthereisarow activeinanybank,thismodeisreferredtoasactivePOWERDOWN.EnteringPOWERDOWNdeacti vatestheinputandoutputbuffers,excludingCK,CK#,WCK,WCK#,EDCpinsandCKE#. Formaximumpowersavings,theuserhastheoptionofdisablingthePLLpriortoenteringPOWER DOWN.Inthatcase,onexitingPOWERDOWN,WCK2CKtrainingisrequiredtosettheinternalsynchro nizerswhichwillincludetheenablingofthePLL,PLLreset,andtLKclockcyclesmustoccurbeforeany READorWRITEcommandcanbeissued. Whileinpowerdown,CKE#HIGHandstableCKandWCKsignalsmustbemaintainedatthedevice inputs.TheEDCpinscontinuouslydrivetheEDCholdpattern;ifthecontrollerdoesnotrequireCDR, usersmayprogramtheEDCholdpatternto'1111'priortoenteringpowerdownmode.POWERDOWN durationislimitedbytherefreshrequirementsofthedevice. ThePOWERDOWNstateissynchronouslyexitedwhenCKE#isregisteredLOW(inconjunctionwitha NOPorDESELECTcommand).AvalidexecutablecommandmaybeappliedtXPNcycleslater.Themin. powerdowndurationisspecifiedbytPD.
T0 CK# CK CKE#
T1
T2
T3
T4
Ta0
Ta1
Ta2
Tb0
tRDSREortWRSRE
tCPDED tPD NOP NOP NOP PDX tXPN Valid
CMD WCK WCK#
NOP
PDE
EnterPowerDownMode
ExitPowerDownMode
DontCare
Figure 74. Power-Down Entry and Exit
Note: 1.MinimumCKE#pulsewidthmustsatisfytCKE. 2.AfterissuingPowerDowncommand,twomoreNOPsshouldbeissued.
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Table 28PinStatesDuringPowerDown
Pin EDC DQ/DBI# ADR/CMD CKE# WCK/WCK# LP2 WCK noWCK x x x x State `Hold' High ODT ODT ODT(DrivenHighbyController) ODT
5.18.COMMANDTRUTHTABLES Table 29TruthTable-CKE#
CKE#n1
H H H H L L L L
CKE#n
H H L L H H H L
CURRENT STATE
PowerDown SelfRefresh PowerDown SelfRefresh AllBanksIdle Bank(s)Active AllBanksIdle X X
COMMANDn
ACTIONn
MaintainPowerDown MaintainSelfRefresh ExitPowerDown ExitSelfRefresh PrechargePowerDownEntry ActivePowerDownEntry SelfRefreshEntry
NOTES
DESELECTorNOP DESELECTorNOP DESELECTorNOP DESELECTorNOP REFRESH SeeTable30and Table31
5
1,2,3
Notes: 1.CKE#nisthelogicstateofCKE#atclockedgen;CKE#n1wasthestateofCKE#atthepreviousclockedge. 2.CurrentstateisthestateoftheGDDR5SGRAMimmediatelypriortoclockedgen. 3.COMMANDnisthecommandregisteredatclockedgen,andACTIONnisaresultofCOMMANDn. 4.Allstatesandsequencesnotshownareillegalorreserved. 5.DESELECTorNOPcommandsshouldbeissuedonanyclockedgesoccurringduringthetXSRWperiod.AminimumoftLKis neededforthePLLtolockbeforeapplyingaREADorWRITEcommandifthePLLwasdisabled.
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Table 30TruthTable-CurrentStateBankn-CommandToBankn
CURRENT STATE
Any
CS#
H L L L L L
RAS# CAS#
X H L L L H H L H H L H H L X H H L L L L H L L H L L H
WE#
X H H H L H L L H L L H L L
COMMAND/ACTION
DESELECT(NOP/continuepreviousoperation) NOOPERATION(NOP/continuepreviousoperation) ACTIVE(selectandactivaterow) REFRESH MODEREGISTERSET READ(selectcolumnandstartREADburst) WRITE(selectcolumnandstartWRITEburst) (WOM,WSMorWDM) PRECHARGE(deactivaterowinbankorbanks) READ(selectcolumnandstartnewREADburst) WRITE(selectcolumnandstartWRITEburst) (WOM,WSMorWDM) PRECHARGE(onlyaftertheREADburstiscomplete READ(selectcolumnandstartREADburst) WRITE(selectcolumnandstartnewWRITEburst) (WOM,WSMorWDM) PRECHARGE(onlyaftertheWRITEburstiscomplete)
NOTES
Idle
4 4 6 6 5 6 6,8 5 6,7 6 5,7
RowActive
L L
Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) (WOM,WSM orWDM)
L L L L L L
Notes 1.ThistableapplieswhenCKE#n1wasLOWandCKE#nisLOW(seeTable29)andaftertXSNRhasbeenmet(iftheprevious statewasselfrefresh). 2.Thistableisbankspecific,exceptwherenoted(i.e.,thecurrentstateisforaspecificbankandthecommandsshownarethose allowedtobeissuedtothatbankwheninthatstate).Exceptionsarecoveredinthenotesbelow. 3.Currentstatedefinitions: Idle:Thebankhasbeenprecharged,andtRPhasbeenmet. RowActive:Arowinthebankhasbeenactivated,andtRCDhasbeenmet.Nodatabursts/accessesandnoregisteraccessesare inprogress. Read:AREADbursthasbeeninitiated,withautoprechargedisabled. Write:AWRITEbursthasbeeninitiated,withautoprechargedisabled. 4.Thefollowingstatesmustnotbeinterruptedbyacommandissuedtothesamebank.DESELECTorNOPcommands,orallowable commandstotheotherbankshouldbeissuedonanyclockedgeoccurringduringthesestates.Allowablecommandstotheother bankaredeterminedbyitscurrentstateandTable30,andaccordingtoTable31. Precharging:StartswithregistrationofaPRECHARGEcommandandendswhentRPismet.OncetRPismet,thebankwillbein theidlestate. RowActivating:StartswithregistrationofanACTIVEcommandandendswhentRCDismet.OncetRCDismet,thebankwillbe inthe"rowactive"state. Readw/AutoPrechargeEnabled:StartswithregistrationofaREADcommandwithautoprechargeenabledandendswhentRP hasbeenmet.OncetRPismet,thebankwillbeintheidlestate. Writew/AutoPrechargeEnabled:StartswithregistrationofaWRITEcommandwithautoprechargeenabledandendswhentRP hasbeenmet.OncetRPismet,thebankwillbeintheidlestate. 5.Thefollowingstatesmustnotbeinterruptedbyanyexecutablecommand;DESELECTorNOPcommandsmustbeappliedoneach positiveclockedgeduringthesestates. Refreshing:StartswithregistrationofaREFRESHcommandandendswhentRCismet.OncetRCismet,theGDDR5SGRAMwill beintheallbanksidlestate. AccessingModeRegister:StartswithregistrationofaMODEREGISTERSETcommandandendswhentMRDhasbeenmet.Once tMRDismet,theGDDR5SGRAMwillbeintheallbanksidlestate. PrechargingAll:StartswithregistrationofaPRECHARGEALLcommandandendswhentRPismet.OncetRPismet,allbanks willbeintheidlestate. READorWRITE:StartswiththeregistrationoftheACTIVEcommandandendsthelastvaliddatanibble. 6.Allstatesandsequencesnotshownareillegalorreserved. 7.Notbankspecific;requiresthatallbanksareidle,andburstsarenotinprogress. 8.Mayormaynotbebankspecific;ifmultiplebanksaretobeprecharged,eachmustbeinavalidstateforprecharging.
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9.ReadsorWriteslistedintheCommand/ActioncolumnincludeReadsorWriteswithautoprechargeenabledandReadsorWrites withautoprechargedisabled. 10.AWRITEcommandmaybeappliedafterthecompletionoftheREADburst
Table 31TruthTable-CurrentStateBankn-CommandToBankm
CURRENT STATE
Any Idle RowActivating, Active,or Precharging
CS#
H L X L L L L
RAS#
X H X L H H L L H H L L H H L L H H L L H H L
CAS#
X H X H L L H H L L H H L L H H L L H H L L H
WE#
X H X H H L L H H L L H H L L H H L L H H L L
COMMAND/ACTION
DESELECT(NOP/continuepreviousoperation) NOOPERATION(NOP/continuepreviousoperation) AnyCommandOtherwiseAllowedtoBankm ACTIVE(selectandactivaterow) READ(selectcolumnandstartREADburst) WRITE(selectcolumnandstartWRITEburst) (WOM,WSMorWDM) PRECHARGE ACTIVE(selectandactivaterow) READ(selectcolumnandstartnewREADburst) WRITE(selectcolumnandstartWRITEburst) (WOM,WSMorWDM) PRECHARGE ACTIVE(selectandactivaterow) READ(selectcolumnandstartREADburst) WRITE(selectcolumnandstartnewWRITEburst) (WOM,WSMorWDM) PRECHARGE ACTIVE(selectandactivaterow) READ(selectcolumnandstartnewREADburst) WRITE(selectcolumnandstartWRITEburst) (WOM,WSMorWDM) PRECHARGE ACTIVE(selectandactivaterow) READ(selectcolumnandstartREADburst) WRITE(selectcolumnandstartnewWRITEburst) (WOM,WSMorWDM) PRECHARGE
NOTES
6 6
Read (AutoPrecharge Disabled)
L L L L
6 6
Write (AutoPrecharge Disabled)
L L L L
6,7 6
Read (WithAuto Precharge)
L L L L
6 6
Write (WithAuto Precharge)
L L L L
6 6
Notes 1.ThistableapplieswhenCKE#n1wasLOWandCKE#nisLOW(seeTable30)andaftertXSNRhasbeenmet(iftheprevious statewasselfrefresh). 2.WRITEinthistablereferstobothWOM/WOMA,WSM/WSMAandWDM/WDMAcommands 3.Thistabledescribesalternatebankoperation,exceptwherenoted(i.e.,thecurrentstateisforbanknandthecommandsshownare thoseallowedtobeissuedtobankm,assumingthatbankmisinsuchastatethatthegivencommandisallowable).Exceptions arecoveredinthenotesbelow. 4.Currentstatedefinitions: Idle:Thebankhasbeenprecharged,andtRPhasbeenmet. RowActive:Arowinthebankhasbeenactivated,andtRCDhasbeenmet.Nodatabursts/accessesandnoregisteraccessesare inprogress. Read:AREADbursthasbeeninitiated,withautoprechargedisabled. Write:AWRITEbursthasbeeninitiated,withautoprechargedisabled. ReadwithAutoPrechargeEnabled:Seefollowingtext WritewithAutoPrechargeEnabled:Seefollowingtext 4a.Thereadwithautoprechargeenabledorwritewithautoprechargeenabledstatescaneachbebrokenintotwoparts:theaccess periodandtheprechargeperiod.Forreadwithautoprecharge,theprechargeperiodisdefinedasifthesameburstwas This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 112
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executedwithautoprechargedisabledandthenfollowedwiththeearliestpossiblePRECHARGEcommandthatstillaccesses allofthedataintheburst.Forwritewithautoprecharge,theprechargeperiodbeginswhentWRends,withtWRmeasuredasif autoprechargewasdisabled.Theaccessperiodstartswithregistrationofthecommandandendswheretheprechargeperiod (ortRP)begins.Duringtheprechargeperiodofthereadwithautoprechargeenabledorwritewithautoprechargeenabled states,ACTIVE,PRECHARGE,READandWRITEcommandstotheotherbankmaybeapplied.Ineithercase,allotherrelated limitationsapply(e.g.,contentionbetweenreaddataandwritedatamustbeavoided). 4b.TheminimumdelayfromaREADorWRITEcommandwithautoprechargeenabled,toacommandtoadifferentbankis summarizedbelow. 5.REFRESHandMODEREGISTERSETcommandsmayonlybeissuedwhenallbanksareidle. 6.Allstatesandsequencesnotshownareillegalorreserved. 7.READsorWRITEslistedintheCommand/ActioncolumnincludeREADsorWRITEswithautoprechargeenabledandREADsor WRITEswithautoprechargedisabled.
Table 32MinimumDelayBetweenCommandstoDifferentBankswithAutoPrechargeEnabled
FromCommand ToCommand READorREADwithAUTOPRECHARGE WRITE withAUTO PRECHARGE (WOMA) WRITEorWRITEwithAUTOPRECHARGE (WOM/WOMA,WSM/WSMAorWDM/WDMA) PRECHARGE ACTIVE READorREADwithAUTOPRECHARGE WRITE withAUTO PRECHARGE (WDMA) WRITEorWRITEwithAUTOPRECHARGE (WOM/WOMA,WSM/WSMAorWDM/WDMA) PRECHARGE ACTIVE READorREADwithAUTOPRECHARGE WRITE withAUTO PRECHARGE (WSMA) WRITEorWRITEwithAUTOPRECHARGE (WOM/WOMA,WSM/WSMAorWDM/WDMA) PRECHARGE ACTIVE READorREADwithAUTOPRECHARGE READ withAUTO PRECHARGE WRITEorWRITEwithAUTOPRECHARGE (WOM/WOMA,WSM/WSMAorWDM/WDMA) PRECHARGE ACTIVE Minimumdelay (withconcurrentautoprecharge) [WLmrs+(BL/4)]tCK+tWTRL*** 2*tCK 1tCK 1tCK [WL+(BL/4)]tCK+tWTR*** 2*tCK 2tCK 2tCK [WL+(BL/4)]tCK+tWTR*** 3*tCK 3tCK 3tCK 2*tCK [CLmrs+(BL/4)+2WL]*tCK*** 1tCK 1tCK
*** CL=CASlatency(CL)
BL=Burstlength WL=WRITElatency tWTR=tWTRLifBankGroupsenabledandaccesstothesamebankotherwisetWTR=tWTRS
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5.19.RDQSMODE
FordeviceoperationatlowerclockfrequenciestheGDDR5SGRAMmaybesetintoRDQSmodeinwhich aREADDATASTROBE(RDQS)inthestyleofGDDR4willbesentontheEDCpinsalongwiththeREAD data.ThecontrollerwillusetheRDQStolatchtheREADdata. RDQSmodeisenteredbysettingtheRDQSModebitA5inModeRegister3(MR3).Whenthebitisset,the GDDR5SGRAMwillasynchronouslyterminateanyEDCholdpatternanddrivealogicHIGHaftertMRD atthelatest.AllfeaturescontrolledbyMR4areignoredbyRDQSmode. READcommandsareexecutedasinnormalmoderegardingcommandtodataoutdelayandpro grammedREADlatencies.AfixedclocklikepatternasshowninFigure75isdrivenonEDCpinsinphase (edgealigned)withtheDQ.Priortothefirstvaliddataelement,thisfixedclocklikepatternorREADpre ambleisdrivenfor2tWCK. NoCRCiscalculatedinRDQSmode,neitherforREADsnorforWRITEs.TheCRCengineiseffectively disabled,andthecorrespondingWRCRCandRDCRCModeRegisterbitsareignored.ThePLLmaybeon oroffwithRDQSmode,dependingonsystemconsiderationsandthePLL'sminimumclockfrequency. ThereisnoequivalentWDQSmode;WRITEcommandstotheGDDR5SGRAMarenotaffectedbyRDQS mode. RDQSmodeisexitedbyresettingtheRDQSModebit.InthiscasetheGDDR5SGRAMwillasynchro nouslystartdrivingtheEDCholdpatternaftertMRD.
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TheWCK2CKtrainingshouldbeperformedpriortoenteringRDQSmode.NoWCK2CKtrainingcanbe donewhentheRDQSmodeisactive.
T0 CK# CK CMD ADDR MRS NOP READ BA CA CLmrs NOP NOP NOP NOP NOP MRS NOP NOP T1 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tc0
MRAMRA
MRAMRA
tMRD WCK WCK# DQ EDC EDC Hold EnterRDQSMode
tMRD
D0 D1 D2 D3 D4 D5 D6 D7
EDC Hold ExitRDQSMode DontCare
1.MRA=ModeRegisteraddressandopcode;BA=bankaddress;CA=columnaddress 2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK. 3.BeforetheREADcommand,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDmustbemet. 4.tWCK2DQO=0isshownforillustrationpurposes.
Figure 75. RDQS Mode Timings
EDC1andEDC3canbetreatedaspseudodifferentialtoEDC0andEDC2respectively,bysettingthe EDC13Invfield,bitA11inMR4,asshowninTable34.
Table 33EDCpinbehaviorinRDQSmodeincludingpseudodifferentialRDQS
NOP MRSSet READ/RDTR
(except
RD/RDTR/ PDN/SRF) EDC0123 Output 1111 1111
POWER DOWN/SELF REFRESH EDC0123 Output High High
RDQSMode
WCK2CK Training
EDC13Invert Off
EDC02 Output RDQS RDQS
EDC13 Output RDQS Inverted RDQS
On
Off On
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5.20.CLOCKFREQUENCYCHANGESEQUENCE
Step1)Waituntilallcommandshavefinished,allbanksareidle. Step2)SendNOPorDESELECT(mustmeetsetup/holdrelativetoclockwhileclockischanging)to GDDR5SGRAMfortheentiresequenceunlessstatedtodootherwise.Theusermusttakecareofrefresh requirements. Step3)IfthenewdesiredclockfrequencyisbelowtheminfrequencysupportedbyPLLonmode,turnthe PLLoffviaanMRScommand. Step4)Changetheclockfrequencyandwaituntilclockisstabilized. Step5)IfthenewclockfrequencyiswithinthePLLonrangeandthePLLonstateisdesired,enablethe PLLviaanMRSCommandifitisnotalreadyenabled. Step6)Performaddresstrainingifrequired. Step7)PerformWCK2CKtraining.AsdefinedintheWCK2CKtrainingprocess,ifthePLLisenabled, thencompletesteps7aand7b: 7a)ResetthePLLbywritingtotheMRSregister. 7b)WaittLKclockcyclesbeforeissuinganycommandstotheGDDR5SGRAM. Step8)ExitWCK2CKtraining. Step9)PerformREADandWRITEtraining,ifrequired. Step10)GDDR5SGRAMisreadyfornormaloperationafteranynecessaryinterfacetraining.
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5.21.DYNAMICVOLTAGESWITCHING(DVS)
GDDR5SGRAM'sallowthesupplyvoltagetobechangedduringthecourseofnormaloperationusingthe GDDR5DynamicVoltageSwitching(DVS)feature.ByusingDVStheGDDR5SGRAM'spowerconsump tioncanbereducedwheneveronlyafractionofthemaximumavailablebandwidthisrequiredbythecur rentworkload. DVSrequirestheGDDR5SGRAMtobeproperlyplacedintoselfrefreshbeforethevoltageischanged fromtheexisingstablevoltage,VoriginaltothenewdesiredvoltageVnew.TheDVSproceduremayalso requirechangestotheVDDRangemoderegisterusingMR7bitsA8andA9,dependingonwhetherthe featureissupported.ThedatasheetshallbeconsultedregardingthesupportedsupplyvoltagesforDVS, andanydependenciesofACtimingparametersontheselectedsupplyvoltage. Clockfrequencychangescanalsotakeplacebeforeorafterenteringselfrefreshmodeusingthestandard ClockFrequencyChangeprocedure.AclockfrequencychangeinconjunctionwithDVSisrequirediftCK islessthantCKminsupportedbyVnew.Inthiscasenormaldeviceoperationincludingselfrefreshexitis notguaranteedwithoutafrequencychange.Changingthefrequencywhileinselfrefreshisthemostsafe procedure. Onceselfrefreshisentered,tCKSREmustbemetbeforethesupplyvoltageisallowedtotransitionfrom VoriginaltoVnew.AfterVDDandVDDQarestableatVnew,tVSmustbemettoallowforinternalvoltages intheGDDR5SGRAMtostabilizebeforeselfrefreshmodemaybeexited.Duringthevoltagetransition thevoltagemustnotgobelowVminofthelowervoltageofeitherVoriginalorVnewinordertopreventfalse chipreset.VministheminimumvoltageallowedbyVDDorVDDQintheDCoperatingconditionstable. VREFshallcontinuetotrackVDDQ.
DVSProcedure
Step1)Completealloperationsandprechargeallbanks. Step2)IssueanMRScommandtosetVDDRangetopropervaluesforVnew.ThisstepisonlyrequiredwhentheVDD RangemoderegisterfieldissupportedbytheGDDR5SGRAM. Step3)Enterselfrefreshmode.Selfrefreshentryproceduremustbemet. Step4)WaitrequiredtimetCKSREbeforechangingvoltagetoVnew. Step5)ChangeVDDandVDDQtoVnew. Step6)WaitrequiredtimetVSforvoltagestabilization. Step7)Exitselfrefresh.Theselfrefreshexitproceduremustbemet. Step8)IssueMRScommandstoadjustmoderegistersettingsasdesired(e.g.latencies,PLLon/off,CRCon/off,RDQS modeon/off). Step9)Performanyinterfacetrainingasrequired. Step10)Continuenormaloperation.
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T0 VDD, VDDQ VSS,VSSQ
T1
T2
Ta0
Voriginal
Vnew
Tb0
Tb1
Tb2
Tc0
Td0
Voltageramp
tVS
CK# CK CKE# tRDSREortWRSRE tRP CMD NOP SRE tCKSRE tCKSRX tXSRW tXSNRW NOP NOP SRX PREA Valid
tCPDED NOP
EnterSelfRefreshMode
ExitSelfRefreshMode
DontCare
SelfrefreshexitrequiresWCK2CKtrainingpriortoanyWRITEorREADoperation AtleastoneREFRESHcommandshallbeissuedaftertXSNRWforoutputdriverandterminationimpedanceupdates Voriginal>Vnewshownasanexampleofavoltagechange
Figure 76. DVS Sequence
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5.22.TEMPERATURESENSOR
GDDR5SGRAMsincorporateatemperaturesensorwithdigitaltemperaturereadoutfunction.Thisfunc tionallowsthecontrollertomonitortheGDDR5SGRAMdie'sjunctiontemperatureandusethisinforma tiontomakesurethedeviceisoperatedwithinthespecifiedtemperaturerangeortoadjustinterface timingsrelativetotemperaturechangesovertime. ThetemperaturesensorisenabledbybitA6inModeRegister7(MR7).Inthiscasethetemperatureread outisvalidaftertTSEN.Hynixapplies10ustotTSEN. ThetemperaturereadoutusestheDRAMInfomodefeature.Thedigitalvalueisdrivenasynchronously ontheDQbusfollowingtheMRScommandtoModeRegister3(MR3)thatsetsbitA7to1andbitA6to0. ThetemperaturereadoutwillbecontinuouslydrivenuntilanMRScommandsetsbothbitsto0. TheGDDR5SGRAM'sjunctiontemperatureislinearlyencodedasshowninTable35.Hynixhastheread outtoasubsetofsixdigitalcodesoutofTable35,correspondingtosixtemperaturethresholds.
Table 34TemperatureSensorReadoutPattern
BinaryTemperatureReadout Temperature[C] 45 55 65 75 85 95 95 MF=0: DQ[5:0] MF=1: DQ[31:26] 000000 000001 000011 000111 001111 011111 111111
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5.23.DUTYCYCLECORRECTOR(DCC)
AsGDDR5SGRAMscanoperatewiththePLLoffduringnormaloperation,theuseofaDutyCycleCor rector(DCC)cancorrectforthedutycycleoftheWCK.DCCcanbeusedatanytime,however,risingand fallingedgesofWCKcanbeshiftedaccordingtotheDCCtype.TheDCCshouldbeenabledbeforeWCK trainingandshouldberunfortDCCinordertoeffectivelycorrectanyerror.
Table 35DCCTimings
Parameter Requiredtimefordutycyclecorrector Symbol tDCC Min 150 Max Unit tCK
DCCcancorrectthedutycycleerrorwithintherangeof 100ps.
WCK# WCK CK# CK CMD
NOP NOP MRS NOP NOP NOP NOP MRS MRS A.C.
tWCKTMRS
tMRD
tWCKTTR
tDCC
tLK
tMRD
DCCreset
EnterWCK2CK Training(resetWCK dividebycircuits)
StartWCK2CKPhase Training
PLLReset
EnterWCK2CK Training(setsdata synchronizers,resets FIFOpointers)
DCCstart DCCstopornot
Figure 77. Timing Diagram of DCC Control Signals
DCCcontrolsignals
* DCCreset:TheDCCresetisusedtoinitializetheDCCcodeandshouldbeissuedanytimebeforetheWCK enables(MRS7A11:1,A10:0) * DCCstart:TheDCCstartisusedtoupdatetheDCCcodeandshouldbeissuedanytimeaftertheWCKisstable (MRS7A11:0,A10:1) * DCCstop:TheDCCstopisusedtomakeitstoptoupdatetheDCCcodewhiletheDCCcodeisheld.Thisshould beissuedafterenoughtimefromDCCstartifneeds(MRS7A11:0,A10:0)
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Table 36DCCControlSignals
A11 0 0 1 1 A10 0 1 0 1 DCC noDCC&DCCstop DCCstart DCCreset RFU
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6.1.ABSOLUTEMAXIMUMRATINGS
VoltageonVddSupply RelativetoVss...................................................0.5Vto+2.0V VoltageonVddQSupply RelativetoVss..................................................0.5Vto+2.0V VoltageonVrefandInputs RelativetoVss..................................................0.5Vto+2.0V VoltageonI/OPins RelativetoVss..................................................0.5VtoVddQ+0.5V StorageTemperature(plastic)............................55Cto+150C ShortCircuitOutputCurrent.............................50mA
*Stressesgreaterthanthoselistedmaycausepermanentdamagetothedevice.Thisisastressratingonly,andfunctionaloperationof thedeviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionsofthisspecificationisnotimplied. Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectreliability.
Table 37Capacitance
PARAMETER DeltaInput/OutputCapacitance:DQs,DBI#,EDC, WCK,WCK# DeltaInputCapacitance:CommandandAddress DeltaInputCapacitance:CK,CK# Input/OutputCapacitance:DQs,DBI#,EDC,WCK, WCK# InputCapacitance:CommandandAddress InputCapacitance:CK,CK#,WCK,WCK# InputCapacitance:CKE# SYMBOL DCio DCi1 DCi2 Cio Ci1 Ci2 Ci3 MIN 0 0 0 1.2 0.9 0.9 0.9 MAX 0.5 0.5 0.3 1.9 1.6 1.6 1.6 UNITS pF pF pF pF pF pF pF NOTES
Table 38ThermalCharacteristics
Parameter Description Value 45
1s Theta_JA 2s2p Theta_JB Theta_JC
o
Units C/W 1,2,4,5
Notes
Thermalresistancejunctiontoambient
33 30
oC/W oC/W o
1,4,5(atTc115oC) 1,2,4,5 1,3 1,6
Thermalresistancejunctiontoboard Thermalresistancejunctiontocase
12 3
C/W
oC/W
Notes: 1.MeasurementproceduresforeachparametermustfollowstandardproceduresdefinedinthecurrentJEDECJESD51standard. 2.Theta_JAmeasuredwiththelowandhighthermalconductivitytestboarddefinedinJESD519 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 122
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3.Theta_JBmeasuredwiththespecialboundaryconditiondefinedinJESD518 4.Theta_JAshouldonlybeusedforcomparingthethermalperformanceofsinglepackageandnotforsystemrelatedjunction. 5.Theta_JAisthenaturalconvectionjunctiontoambientairthermalresistancemeasuredinonecubicfootsealedenclosure asdecribedinJESD512. Theenvironmentissometimesreferedtoas"stillair"althoughnaturalconvectioncausestheairtomove. 6.Theta_JCcasesurfaceisdefinedasthe"outsidesurfaceofthepackage(case)closesttothechipmountingareawhenthat samesurfaceisproperlyhearsunk"soastominimizetemperaturevariationacrossthatsurface.
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6.2.AC&DCCHARACTERISTICS
AllGDDR5SGRAMsaredesignedfor1.5Vtypicalvoltagesupplies.TheinterfaceofGDDR5with1.5V VDDQwillfollowthePOD15specification.AllACandDCvaluesaremeasuredattheball.
Table 39DCOperatingConditions
Parameter
DeviceSupplyVoltage OutputSupplyVoltage DeviceSupplyVoltage OutputSupplyVoltage ReferenceVoltageforDQandDBI#pins ReferenceVoltageforDQandDBI#pins ExternalReferenceVoltageforaddressand command DCInputLogicHIGHVoltageforaddressand command DCInputLogicLOWVoltageforaddressand command DCInputLogicHIGHVoltageforDQandDBI# pinswithVREFD DCInputLogicLOWVoltageforDQandDBI# pinswithVREFD DCInputLogicHIGHVoltageforDQandDBI# pinswithVREFD2 DCInputLogicLOWVoltageforDQandDBI# pinswithVREFD2 InputLogicHIGHVoltageforRESET#,SEN,MF InputLogicLOWVoltageforRESET#,SEN,MF InputlogicHIGHvoltagefor EDC1/2(x16modedetect) InputlogicLOWvoltagefor EDC1/2(x16modedetect) InputLeakageCurrent AnyInput0V<=VIN<=VDDQ (Allotherpinsnotundertest=0V) OutputLeakageCurrent (DQsaredisabled;0V<=Vout<=VDDQ) OutputLogicLOWVoltage
Symbol
VDD VDDQ VDD VDDQ VREFD VREFD2 VREFC VIHA(DC) VILA(DC) VIHD(DC) VILD(DC) VIHD2 (DC) VILD2(DC) VIHR VILR VIHX VILX Il Ioz VOL(DC)
Min
1.452 1.452 1.455 1.455 0.69*VDDQ 0.49*VDDQ 0.69*VDDQ VREFC+0.15
Typ
1.6 1.6 1.5 1.5
Max
1.648 1.648 1.545 1.545 0.71*VDDQ 0.51*VDDQ 0.71*VDDQ
Unit
V V V V V V V V
Note
1 1 2 2 3,4 3,4,5 6
VREFC0.15 VREFD+0.10 VREFD0.10 VREFD2+0.30 VREFD20.30 VDDQ0.50 0.30 VDDQ0.3 0.30 10 10 0.62
V V V V V V V V V A A V 9 9
Notes: 1.VDD/VDDQ1.6Visfor6Gbps 2.GDDR5SGRAMsaredesignedtotoleratePCBdesignswithseparateVDDandVDDQpowerregulators. 3.ACnoiseinthesystemisestimatedat50mVpkpkforthepurposeofDRAMdesign. 4.SourceofReferenceVoltageandcontrolofReferenceVoltageforDQandDBI#pinsisdeterminedbyVREFD,HalfVREFD,Auto VREFD,VREFDMERGEandVREFDOffsetsmoderegisters. 5.VREFDOffsetsarenotsupportedwithVREFD2. 6.ExternalVREFCistobeprovidedbythecontrollerasthereisnootheralternativesupply. 7.DQ/DBI#inputslewratemustbegreaterthanorequalto3V/ns.TheslewrateismeasuredbetweenVREFDcrossingandVIHD(AC) orVILD(AC)orVREFD2crossingandVIHD2(AC)orVILD2(AC). 8.ADR/CMDinputslewratemustbegreaterthanorequalto3V/ns.TheslewrateismeasuredbetweenVREFCcrossingand VIHA(AC)orVILA(AC). 9.VIHXandVILXdefinethevoltagelevelsforthereceiverthatdetectsx32orx16modewithRESET#goingHigh.
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Table 40ACOperatingConditions
POD15 Parameter
ACInputLogicHIGHVoltagefor addressandcommand ACInputLogicLOWVoltagefor addressandcommand ACInputLogicHIGHVoltagefor DQandDBI#pinswithVREFD ACInputLogicLOWVoltagefor DQandDBI#pinswithVREFD ACInputLogicHIGHVoltagefor DQandDBI#pinswithVREFD2 ACInputLogicLOWVoltagefor DQandDBI#pinswithVREFD2
Symbol
VIHA(AC) VILA(AC) VIHD(AC) VILD(AC) VIHD2(AC) VILD2(AC)
Min
VREFC+0.20
Typ
Max
Unit
V
Note
VREFC0.20 VREFD+0.15 VREFD0.15 VREFD2+0.40 VREFD20.40
V V V V V
VDDQ
VOH SystemNoiseMargin(Power/Ground, Crosstalk,SignalIntegrityAttenuation) VIH(AC)
VIH(DC)
VREF+ACNoise VREF+DCNoise VREFDCNoise VREFACNoise
VIL(DC)
VIL(AC) VIN(AC)Providesmargin betweenVOL(MAX)and VIL(AC) VOL(MAX)
Note:VREF,VIH,VILreferto whicheverVREFxx(VREFD, VREFD2,orVREFC)isbeingused.
Output
Input
Figure 78. Voltage Waveform
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Table 41ClockInputOperatingConditions
POD15 Parameter
ClockInputMidPointVoltage;CKandCK# ClockInputDifferentialVoltage;CKandCK# ClockInputDifferentialVoltage;CKandCK# ClockInputDifferentialVoltage;WCKandWCK# ClockInputDifferentialVoltage;WCKandWCK# ClockInputVoltageLevel;CK,CK#,WCKandWCK# singleended CK/CK#Singleendedslewrate WCK/WCK#Singleendedslewrate ClockInputCrossingPointVoltage;CKandCK# ClockInputCrossingPointVoltage;WCKandWCK# AllowedtimebeforeringbackofCK/WCKbelow VIDCK/WCK(AC)
Symbol
VMP(DC) VIDCK(DC) VIDCK(AC) VIDWCK(DC) VIDWCK(AC) VIN CKslew WCKslew VIXCK(AC) VIXWCK(AC) tDVAC
Min
VREFC0.10 0.22 0.40 0.20 0.30 0.30 3 3 VREFC0.12 VREFD0.10
Max
VREFC+0.10
Unit
V V V V
Note
1,6 4,6 2,4,6 5,7 2,5,7
VDDQ+0.30 V/ns V/ns VREFC+0.12 VREFD+0.10 V V ps 9 10 2,3,6 2,3,7, 8 11,12, 13
Notes: 1.Thisprovidesaminimumof0.9Vtoamaximumof1.2V,andisnominally70%ofVDDQwithPOD15.DRAMtimingsrelativeto CKcannotbeguaranteediftheselimitsareexceeded. 2.ForACoperations,allDCclockrequirementsmustbesatisfiedaswell. 3.ThevalueofVIXCKandVIXWCKisexpectedtoequal70%VDDQforthetransmittingdeviceandmusttrackvariationsintheDC levelofthesame. 4.VIDCKisthemagnitudeofthedifferencebetweentheinputlevelinCKandtheinputlevelonCK#.Theinputreferencelevelfor signalsotherthanCKandCK#isVREFC. 5.VIDWCKisthemagnitudeofthedifferencebetweentheinputlevelinWCKandtheinputlevelonWCK#.Theinputreferencelevel forsignalsotherthanWCKandWCK#iseitherVREFD,VREFD2ortheinternalVREFD. 6.TheCKandCK#inputreferencelevel(fortimingreferencedtoCKandCK#)isthepointatwhichCKandCK#cross.Pleaserefer totheapplicabletimingsintheACtimingstable(Table44). 7.TheWCKandWCK#inputreferencelevel(fortimingreferencedtoWCKandWCK#)isthepointatwhichWCKandWCK#cross. PleaserefertotheapplicabletimingsintheACTimingstable(Table44). 8.VREFDiseitherVREFD,VREFD2ortheinternalVREFD. 9.TheslewrateismeasuredbetweenVREFCcrossingandVIXCK(AC). 10.TheslewrateismeasuredbetweenVREFDcrossingandVIXWCK(AC). 11.Figure illustratestheexactrelationshipbetween(CKCK#)or(WCKWCK#)andVID(AC),VID(DC)andtDVAC 12.RingbackbelowVID(DC)isnotallowed. 13.tDVACisnotmeasuredinandofitselfasacompliancespecification,butisrelieduponinmeasurementofclockoperating conditionsandclockrelatedparameters.
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MaximumClockLevel CK
VMP(DC)
VIX(AC)
VID(DC) VID(AC)
CK# MinimumClockLevel
Figure 79. Clock Waveform
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tDVAC
DifferentialInputVoltage(i.e.WCKWCK#,CKCK#) VID(AC)MIN
VID(DC)MIN
0 halfcycle (VID(DC)MIN)
(VID(AC)MIN)
tDVAC
time
Figure 80. Definition of differential ac-swing and "time above ac-level" tDVAC
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Table 42IDDSpecificationsandTestConditions
PARAMETER/CONDITION
OneBankActivatePrechargeCurrent:tCK=tCK(min);tWCK=tWCK(min);tRC=tRC(min);CKE#= LOW;DQ,DBI#areHIGH;randombankandrowaddresses(4addressinputssetLOW)withACT command OneBankActivateReadPrechargeCurrent:tCK=tCK(min);tWCK=tWCK(min); tRC=tRC(min);CKE#=LOW;onebankactivated;singlereadburstwith50%datatoggleoneachdata transfer,with4outputsperdatabytedrivenLOW;otherwiseDQ,DBI#areHIGH;randombank,row andcolumnaddresses(4addressinputssetLOW)withACTandREADcommands;IOUT=0mA PrechargePowerdownCurrent:tCK=tCK(min);tWCK=tWCK(min);allbanksidle; CKE#=HIGH;allotherinputsareHIGH;PLLsareoff PrechargeStandbyCurrent:tCK=tCK(min);tWCK=tWCK(min);allbanksidle; CKE#=LOW;allotherinputsareHIGH ActivePowerdownCurrent:tCK=tCK(min);tWCK=tWCK(min);onebankactive; CKE#=HIGH;allotherinputsareHIGH ActiveStandbyCurrent:tCK=tCK(min);tWCK=tWCK(min);onebankactive; CKE#=LOW;allotherinputsareHIGH ReadBurstCurrent:tCK=tCK(min);tWCK=tWCK(min);CKE#=LOW;onebankineachofthe4bank groupsactivated;continuousreadburstacrossbankgroupswith50%datatoggleoneachdata transfer,with4outputsperdatabytedrivenLOW;randombankandcolumnaddresses(4address inputssetLOW)withREADcommand;IOUT=0mA WriteBurstCurrent:tCK=tCK(min);tWCK=tWCK(min);CKE#=LOW;onebankineachofthe4bank groupsactivated;continuouswriteburstacrossbankgroupswith50%datatoggleoneachdata transfer,with4inputsperdatabytesetLOW;randombankandcolumnaddresses(4addressinputs setLOW)withWRITEcommand;nodatamask RefreshCurrent:tCK=tCK(min);tWCK=tWCK(min);tRFC=tRFC(min);CKE#=LOW; DQ,DBI#areHIGH;addressinputsareHIGH SelfRefreshCurrent:CKE#=HIGH;allotherinputsareHIGH FourBankInterleaveReadCurrent:tCK=tCK(min);tWCK=tWCK(min);CKE#=LOW; onebankineachofthe4bankgroupsactivatedandprechargedattRC(min);continuousreadburst acrossbankgroupswith50%datatoggleoneachdatatransfer,with4outputsperdatabytedriven LOW;randombank,rowandcolumnaddresses(4addressinputssetLOW)withACTandREAD/ READAcommands;IOUT=0mA
SYMBOL
IDD0
NOTES
1
IDD1
1
IDD2P IDD2N IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD6
1
IDD7
NOTE: MintRCortRFCforIDDmeasurementsisthesmallestmultipleoftCKthatmeetstheminimumoftheabsolutevalueforthe respectiveparameter.
CommonTestconditions:
1) 2) 3) 4) 5) 6) 7) 8) 9) Deviceisconfiguredtox32mode ABIandDBIareenabled AllODTsareenabledwithZQ/2 PLLsareenabledunlessotherwisenoted CRCisenabledforREADsandWRITEs,andtheEDCholdpatternisprogrammedto'1010' BankgroupsareenabledifrequiredfordeviceoperationattCK(min) AddressinputsincludeABI#pin EachdatabyteconsistsofeightDQsandoneDBI#pin DESELECTconditionduringidlecommandcycles
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 129
H5GQ1H24AFR
Table 43. IDD SPECIFICATIONS AND CONDITIONS
1. x 32 Mode IDD
Symbol IDD0 IDD1 IDD2P IDD2N IDD3P IDD3N IDD4W IDD4R IDD5 IDD6 IDD7 4.0Gbps 550 590 240 260 385 540 1300 1370 545 60 900 4.5Gbps 590 630 260 280 405 580 1430 1500 580 60 1000 5.0Gbps 630 670 280 300 425 620 1560 1630 615 60 1100 5.5Gbps 670 710 300 320 445 660 1690 1760 650 60 1200 6.0Gbps 710 750 320 340 465 700 1820 1890 685 60 1300 Units mA mA mA mA mA mA mA mA mA mA mA
2. x 16 Mode IDD
Symbol IDD0 IDD1 IDD2P IDD2N IDD3P IDD3N IDD4W IDD4R IDD5 IDD6 IDD7 4.0Gbps 370 390 170 190 250 350 830 850 350 60 660 4.5Gbps 400 420 175 200 260 370 910 930 370 60 710 5.0Gbps 420 450 185 210 275 390 990 1010 390 60 770 5.5Gbps 450 480 195 230 290 420 1070 1090 420 60 840 6.0Gbps 490 520 210 250 310 450 1160 1080 450 60 910 Units mA mA mA mA mA mA mA mA mA mA mA
Rev. 1.0 /Nov. 2009
130
H5GQ1H24AFR
Table 44. AC Timings (@1.5V)
6.0Gbps PARAMETER a, b SYMBOL MIN CK and WCK Timings
PLL on CK Clock cycle time PLL off CK Clock high-level width CK Clock low-level width Min CK Clock half period Max CK Clock frequency with bank groups disabled Max CK Clock frequency with bank groups enabled and tCCDL=3tCK Max CK Clock frequency with WCK2CK alignment at pins Max CK Clock frequency in RDQS Mode Max CK Clock frequency for device operation with VREFD2 Max CK Clock frequency for WCK-to-CK auto synchronization in WCK2CK training mode Max CK Clock frequency for device operation with Low Frequency Mode enabled PLL on WCK Clock cycle time PLL off WCK Clock high-level width WCK Clock low-level width Min WCK Clock half period tWCKH tWCKL tWCKHP tWCK 0.333 0.470 0.470 0.470 10 0.530 0.530 0.364 0.470 0.470 0.470 10 0.530 0.530 tWCK tWCK tWCK k,l k,l tCH tCL tHP fCKBG fCKBG4 tCK 0.667 0.470 0.470 0.470 20 0.530 0.530 1500 1500 0.727 0.470 0.470 0.470 20 0.530 0.530 1375 1375 tCK tCK tCK MHz MHz d d C C 0.667 2 0.727 2 ns
5.5Gbps UNIT NOTES MIN MAX
MAX
fCKPIN fCKRDQS fCKVREFD2
-
1500 TBD TBD
-
1375 TBD TBD
MHz MHz MHz
e f g
fCKAUTOSYNC
-
1500
-
1375
MHz
h
fCKLF
0.333
900 1
0.364
900 1
MHz
i
ns
j
Command and Address Input Timings
Command input setup time Command input hold time Command input pulse width Address input setup time Address input hold time Address input pulse width tCMDS tCMDH tCMDPW tAS tAH tAPW 0.25 0.25 0.60 0.1 0.1 0.3 0.25 0.25 0.65 0.1 0.1 0.32 ns ns ns ns ns ns m,n m,n m,n,o m,n,p m,n,p m,n,o,p
Rev. 1.0 /Nov. 2009
131
H5GQ1H24AFR
Table 44. AC Timings (@1.5V)
6.0Gbps PARAMETER a, b SYMBOL MIN WCK2CK Timings
WCK stop to MRS delay for entering WCK2CK training MRS to WCK restart delay after entering WCK2CK training WCK start to WCK phase movement delay WCK phase change to phase detector out delay WCK Clock high-level width during WCK2CK training WCK Clock low-level width during WCK2CK training PLL on;MR6A0=0 (at phase detector) WCK2CK offset when zero offset at phase detector or at pins PLL on;MR6A0=1 (at pins) tWCK2CKPIN PLL off;MR6A0=0 (at phase detector) PLL off;MR6A0=1 (at pins) MR6A0=0 (at phase detector) tWCK2CKSYNC MR6A0=1 (at pins) MR6A0=0 (at phase detector) WCK2CK phase offset MR6A0=1 (at pins) tWCK2CK -0.4 0.4 -0.4 0.4 ns -0.25 0.25 -0.25 0.25 ns -0.2 0.2 -0.2 0.2 tWCK2MRS 3 3 ns
5.5Gbps UNIT NOTES MIN MAX
MAX
tMRSTWCK tWCK2TR tWCK2PH tWCKHTR
10 10 5 0.42
0.58
10 10 5 0.42
0.58
ns tCK ns tWCK
q
k,l,r
tWCKLTR
0.42
0.58
0.42
0.58
tWCK
k,l,r
-0.2
0.2
-0.2
0.2
-0.2
0.2
-0.2
0.2 ns s
-0.2
0.2
-0.2
0.2
-0.25
0.25
-0.25
0.25
tCK t
WCK2CK phase offset upon WCK2CK training exit
-0.4
0.4
-0.4
0.4
tCK u
PLL Input and Output Timings
WCK to DQ/DBI# offset for input data WCK to DQ/DBI#/EDC/ offset for output data DQ/DBI# input pulse width PLL on tWCK2DQI PLL off PLL on tWCK2DQO PLL off tDIPW 1.1 0.15 2.2 1.1 0.164 2.2 ns y,z,aa 0.7 1.1 1.7 2.2 0.7 1.1 1.7 2.2 ns w,x 0.7 1.7 0.7 1.7 ns v
Rev. 1.0 /Nov. 2009
132
H5GQ1H24AFR
Table 44. AC Timings (@1.5V)
6.0Gbps PARAMETER a, b
PLL on tDIVW PLL off tDQDQI tDQDQO 0.1 -0.1 -0.125 0.1 0.125 0.11 -0.1 -0.125 0.1 0.125 ns ns ac ad
5.5Gbps UNIT NOTES MIN
0.11
SYMBOL MIN MAX
-
MAX
ns y,z,ab
DQ/DBI# data input valid window
0.1
DQ/DBI# input skew within double byte DQ/DBI#/EDC output skew within double byte
Row Access Timings
Active to Active command period Active to PRECHARGE command period Active to READ command delay Active to WRITE command delay Active to RDTR command delay Active to WRTR command delay Active to LDFF command delay REFRESH to RDTR or WRTR command delay Active bank A to Active bank B command delay same bank group Active bank A to Active bank B command delay different bank groups Four bank activate window Thirty two bank activate window READ to PRECHARGE command delay same bank with bank groups enabled READ to PRECHARGE command delay same bank with bank groups disabled PRECHARGE to PRECHARGE command delay PRECHARGE command period WRITE recovery time Auto precharge write recovery + precharge time tRC tRAS tRCDRD tRCDWR tRCDRTR tRCDWTR tRCDLTR tREFTR tRRDL 40 28 12 10 10 10 10 10 5.5 9*tREFI 40 28 12 10 10 10 10 10 5.5 9*tREFI ns ns ns ns ns ns ns ns ns af ae
tRRDS tFAW t32AW tRTPL
5.5 23 184 2
-
5.5 23 184 2
-
ns ns ns tCK
ag ah ai aj
tRTPS tPPD tRP tWR tDAL
2 1 12 12 24
-
2 1 12 12 24
-
tCK ns ns ns tCK
ak
al
Column Access Timings
RD/WR bank A to RD/WR bank B command delay same bank group RD/WR bank A to RD/WR bank B command delay different bank groups Rev. 1.0 /Nov. 2009 tCCDL 3 3 tCK af,am
tCCDS
2
-
2
-
tCK
ag,an 133
H5GQ1H24AFR
Table 44. AC Timings (@1.5V)
6.0Gbps PARAMETER a, b
LDFF to LDFF command cycle time LDFF(111) to LDFF command cycle time LDFF(111) to RDTR command cycle delay READ or RDTR to LDFF command delay WRITE to LDFF command delay WRTR to RDTR command delay
5.5Gbps UNIT NOTES MIN
4 4 4 4 WL+5 WLtWLmin WL+tCR CWL+2 5
SYMBOL MIN
tLTLTR tLTL7TR tLTRTR tRDTLT tWRTLT tWTRTR 4 4 4 4 WL+5 WLtWLmin WL+tCR CWL+2 5
MAX
-
MAX
tCK tCK tCK tCK tCK tCK ao
WRITE to WRTR command delay Internal WRITE to READ command delay same bank group Internal WRITE to READ command delay different bank groups READ or RDTR to WRITE or WRTR command delay Write Latency
tWRWTR
-
-
tCK
tWTRL
-
-
ns
af
tWTRS
5
[CLmrs+(BL /4)+2WLmrs]*tC K
-
5
[CLmrs+(BL /4)+2WLmrs]*tC K
-
ns
ag
tRTW
-
-
tCK
ap
tWL
4
7
4
7
tCK
aq
Power-Down and Refresh Timings
CKE# min high and low pulse width Valid CK Clock required after self refresh entry Valid CK Clock required before self refresh exit READ to SELF REFRESH ENTRY or POWER DOWN ENTRY command delay WRITE to SELF REFRESH ENTRY or POWER DOWN ENTRY command delay REFRESH command period Exit self refresh to non-READ/WRITE command delay Exit self refresh to READ/WRITE command delay Refresh period Average periodic refresh interval Min Power down entry to exit time Rev. 1.0 /Nov. 2009 8k rows tREFI 16k rows tPD 16 1.9 14 1.9 tCK 134 tCKE tCKSRE tCKSRX tRDSRE 16 16 16 CL+2tCK 14 14 14 CL+2tCK tCK tCK tCK tCK ar
tWRSRE tRFC tXSNRW
TBD 65 tRFC tRFC+ tRCD -
-
TBD 65 tRFC tRFC+ tRCD -
-
tCK ns ns
as
tXSRW tREF
32 3.9
32 3.9
tCK ms us
at
au
H5GQ1H24AFR
Table 44. AC Timings (@1.5V)
6.0Gbps PARAMETER a, b
NOP/DESELECT commands required upon powerdown and self refresh entry Power down exit time
5.5Gbps UNIT NOTES MIN
3 15
SYMBOL MIN
tCPDED tXPN 4 17
MAX
-
MAX
tCK tCK
Miscellaneous Timings
MODE REGISTER SET command period PLL enabled to PLL lock delay PLL standby time DVS voltage stabilization time REFRESH to calibration update complete delay Active termination setup time Active termination hold time READ to data out delay in address training mode tMRD tLK tSTDBTY tVS tKO tATS tATH tADR 4 TBD 10 10 0.5*tCK+ 0 10 5000 TBD 40 0.5*tCK+ 10 0.5*tCK+ 10 11 11 4 TBD 10 10 0.5*tCK+ 0 10 5000 TBD 40 0.5*tCK+ 10 0.5*tCK+ 10 11 11 tCK tCK us us ns ns ns tCK q ax
Address training exit to DQ in ODT state delay Vendor ID on Venodr ID off Temperature sensor enable delay
tADZ tWRIDON tWRIDOFF tTSEN
ns ns ns us
Rev. 1.0 /Nov. 2009
135
H5GQ1H24AFR
Table 44. AC Timings (@1.5V)
5.0Gbps PARAMETER a, b SYMBOL MIN CK and WCK Timings
PLL on CK Clock cycle time PLL off CK Clock high-level width CK Clock low-level width Min CK Clock half period Max CK Clock frequency with bank groups disabled Max CK Clock frequency with bank groups enabled and tCCDL=3tCK Max CK Clock frequency with WCK2CK alignment at pins Max CK Clock frequency in RDQS Mode Max CK Clock frequency for device operation with VREFD2 Max CK Clock frequency for WCK-to-CK auto synchronization in WCK2CK training mode Max CK Clock frequency for device operation with Low Frequency Mode enabled PLL on WCK Clock cycle time PLL off WCK Clock high-level width WCK Clock low-level width Min WCK Clock half period tWCKH tWCKL tWCKHP tWCK 0.4 0.470 0.470 0.470 10 0.530 0.530 0.444 0.470 0.470 0.470 10 0.530 0.530 tWCK tWCK tWCK k,l k,l tCH tCL tHP fCKBG fCKBG4 tCK 0.8 0.470 0.470 0.470 20 0.530 0.530 1250 1250 0.89 0.470 0.470 0.470 20 0.530 0.530 1125 1125 tCK tCK tCK MHz MHz d d C C 0.8 2 0.89 2 ns
4.5Gbps UNIT NOTES MIN MAX
MAX
fCKPIN fCKRDQS fCKVREFD2
-
1250 TBD TBD
-
1125 TBD TBD
MHz MHz MHz
e f g
fCKAUTOSYNC
-
1250
-
1125
MHz
h
fCKLF
0.4
900 1
0.444
900 1
MHz
i
ns
j
Command and Address Input Timings
Command input setup time Command input hold time Command input pulse width Address input setup time Address input hold time Address input pulse width tCMDS tCMDH tCMDPW tAS tAH tAPW 0.25 0.25 0.7 0.1 0.1 0.36 0.25 0.25 0.7 0.125 0.125 0.4 ns ns ns ns ns ns m,n m,n m,n,o m,n,p m,n,p m,n,o,p
Rev. 1.0 /Nov. 2009
136
H5GQ1H24AFR
Table 44. AC Timings (@1.5V)
5.0Gbps PARAMETER a, b SYMBOL MIN WCK2CK Timings
WCK stop to MRS delay for entering WCK2CK training MRS to WCK restart delay after entering WCK2CK training WCK start to WCK phase movement delay WCK phase change to phase detector out delay WCK Clock high-level width during WCK2CK training WCK Clock low-level width during WCK2CK training PLL on;MR6A0=0 (at phase detector) WCK2CK offset when zero offset at phase detector or at pins PLL on;MR6A0=1 (at pins) tWCK2CKPIN PLL off;MR6A0=0 (at phase detector) PLL off;MR6A0=1 (at pins) MR6A0=0 (at phase detector) tWCK2CKSYNC MR6A0=1 (at pins) MR6A0=0 (at phase detector) WCK2CK phase offset MR6A0=1 (at pins) tWCK2CK -0.4 0.4 -0.4 0.4 ns -0.25 0.25 -0.25 0.25 ns -0.2 0.2 -0.2 0.2 tWCK2MRS 3 3 ns
4.5Gbps UNIT NOTES MIN MAX
MAX
tMRSTWCK tWCK2TR tWCK2PH tWCKHTR
10 10 5 0.42
0.58
10 10 5 0.42
0.58
ns tCK ns tWCK
q
k,l,r
tWCKLTR
0.42
0.58
0.42
0.58
tWCK
k,l,r
-0.2
0.2
-0.2
0.2
-0.2
0.2
-0.2
0.2 ns s
-0.2
0.2
-0.2
0.2
-0.25
0.25
-0.25
0.25
tCK t
WCK2CK phase offset upon WCK2CK training exit
-0.4
0.4
-0.4
0.4
tCK u
PLL Input and Output Timings
WCK to DQ/DBI# offset for input data WCK to DQ/DBI#/EDC/ offset for output data DQ/DBI# input pulse width PLL on tWCK2DQI PLL off PLL on tWCK2DQO PLL off tDIPW 1.1 0.18 2.2 1.1 0.197 2.2 ns y,z,aa 0.7 1.1 1.7 2.2 0.7 1.1 1.7 2.2 ns w,x 0.7 1.7 0.7 1.7 ns v
Rev. 1.0 /Nov. 2009
137
H5GQ1H24AFR
Table 44. AC Timings (@1.5V)
5.0Gbps PARAMETER a, b
PLL on tDIVW PLL off tDQDQI tDQDQO 0.12 -0.1 -0.125 0.1 0.125 0.13 -0.1 -0.125 0.1 0.125 ns ns ac ad
4.5Gbps UNIT NOTES MIN
0.13
SYMBOL MIN MAX
-
MAX
ns y,z,ab
DQ/DBI# data input valid window
0.12
DQ/DBI# input skew within double byte DQ/DBI#/EDC output skew within double byte
Row Access Timings
Active to Active command period Active to PRECHARGE command period Active to READ command delay Active to WRITE command delay Active to RDTR command delay Active to WRTR command delay Active to LDFF command delay REFRESH to RDTR or WRTR command delay Active bank A to Active bank B command delay same bank group Active bank A to Active bank B command delay different bank groups Four bank activate window Thirty two bank activate window READ to PRECHARGE command delay same bank with bank groups enabled READ to PRECHARGE command delay same bank with bank groups disabled PRECHARGE to PRECHARGE command delay PRECHARGE command period WRITE recovery time Auto precharge write recovery + precharge time tRC tRAS tRCDRD tRCDWR tRCDRTR tRCDWTR tRCDLTR tREFTR tRRDL 40 28 12 10 10 10 10 10 5.5 9*tREFI 40 28 12 10 10 10 10 10 5.5 9*tREFI ns ns ns ns ns ns ns ns ns af ae
tRRDS tFAW t32AW tRTPL
5.5 23 184 2
-
5.5 23 184 2
-
ns ns ns tCK
ag ah ai aj
tRTPS tPPD tRP tWR tDAL
2 1 12 12 24
-
2 1 12 12 24
-
tCK ns ns ns tCK
ak
al
Column Access Timings
RD/WR bank A to RD/WR bank B command delay same bank group RD/WR bank A to RD/WR bank B command delay different bank groups Rev. 1.0 /Nov. 2009 tCCDL 3 3 tCK af,am
tCCDS
2
-
2
-
tCK
ag,an 138
H5GQ1H24AFR
Table 44. AC Timings (@1.5V)
5.0Gbps PARAMETER a, b
LDFF to LDFF command cycle time LDFF(111) to LDFF command cycle time LDFF(111) to RDTR command cycle delay READ or RDTR to LDFF command delay WRITE to LDFF command delay WRTR to RDTR command delay
4.5Gbps UNIT NOTES MIN
4 4 4 4 WL+5 WLtWLmin WL+tCR CWL+2 5
SYMBOL MIN
tLTLTR tLTL7TR tLTRTR tRDTLT tWRTLT tWTRTR 4 4 4 4 WL+5 WLtWLmin WL+tCR CWL+2 5
MAX
-
MAX
tCK tCK tCK tCK tCK tCK ao
WRITE to WRTR command delay Internal WRITE to READ command delay same bank group Internal WRITE to READ command delay different bank groups READ or RDTR to WRITE or WRTR command delay Write Latency
tWRWTR
-
-
tCK
tWTRL
-
-
ns
af
tWTRS
5
[CLmrs+(BL /4)+2WLmrs]*tC K
-
5
[CLmrs+(BL /4)+2WLmrs]*tC K
-
ns
ag
tRTW
-
-
tCK
ap
tWL
3
7
3
7
tCK
aq
Power-Down and Refresh Timings
CKE# min high and low pulse width Valid CK Clock required after self refresh entry Valid CK Clock required before self refresh exit READ to SELF REFRESH ENTRY or POWER DOWN ENTRY command delay WRITE to SELF REFRESH ENTRY or POWER DOWN ENTRY command delay REFRESH command period Exit self refresh to non-READ/WRITE command delay Exit self refresh to READ/WRITE command delay Refresh period Average periodic refresh interval Min Power down entry to exit time Rev. 1.0 /Nov. 2009 8k rows tREFI 16k rows tPD 12 1.9 11 1.9 tCK 139 tCKE tCKSRE tCKSRX tRDSRE 12 12 12 CL+2tCK 11 11 11 CL+2tCK tCK tCK tCK tCK ar
tWRSRE tRFC tXSNRW
TBD 65 tRFC tRFC+ tRCD -
-
TBD 65 tRFC tRFC+ tRCD -
-
tCK ns ns
as
tXSRW tREF
32 3.9
32 3.9
tCK ms us
at
au
H5GQ1H24AFR
Table 44. AC Timings (@1.5V)
5.0Gbps PARAMETER a, b
NOP/DESELECT commands required upon powerdown and self refresh entry Power down exit time
4.5Gbps UNIT NOTES MIN
3 11
SYMBOL MIN
tCPDED tXPN 3 13
MAX
-
MAX
tCK tCK
Miscellaneous Timings
MODE REGISTER SET command period PLL enabled to PLL lock delay PLL standby time DVS voltage stabilization time REFRESH to calibration update complete delay Active termination setup time Active termination hold time READ to data out delay in address training mode tMRD tLK tSTDBTY tVS tKO tATS tATH tADR 4 TBD 10 10 0.5*tCK+ 0 10 5000 TBD 40 0.5*tCK+ 10 0.5*tCK+ 10 11 11 4 TBD 10 10 0.5*tCK+ 0 10 5000 TBD 40 0.5*tCK+ 10 0.5*tCK+ 10 11 11 tCK tCK us us ns ns ns tCK q ax
Address training exit to DQ in ODT state delay Vendor ID on Venodr ID off Temperature sensor enable delay
tADZ tWRIDON tWRIDOFF tTSEN
ns ns ns us
Rev. 1.0 /Nov. 2009
140
H5GQ1H24AFR
Table 44. AC Timings (@1.5V)
4.0Gbps PARAMETER a, b SYMBOL MIN CK and WCK Timings
PLL on CK Clock cycle time PLL off CK Clock high-level width CK Clock low-level width Min CK Clock half period Max CK Clock frequency with bank groups disabled Max CK Clock frequency with bank groups enabled and tCCDL=3tCK Max CK Clock frequency with WCK2CK alignment at pins Max CK Clock frequency in RDQS Mode Max CK Clock frequency for device operation with VREFD2 Max CK Clock frequency for WCK-to-CK auto synchronization in WCK2CK training mode Max CK Clock frequency for device operation with Low Frequency Mode enabled PLL on WCK Clock cycle time PLL off WCK Clock high-level width WCK Clock low-level width Min WCK Clock half period tWCKH tWCKL tWCKHP tWCK 0.5 0.470 0.470 0.470 10 0.530 0.530 tWCK tWCK tWCK k,l k,l tCH tCL tHP fCKBG fCKBG4 tCK 1 0.470 0.470 0.470 20 0.530 0.530 1000 1000 tCK tCK tCK MHz MHz d d C C 1 2 ns
UNIT NOTES MIN MAX
MAX
fCKPIN fCKRDQS fCKVREFD2
-
1000 TBD TBD
MHz MHz MHz
e f g
fCKAUTOSYNC
-
100
MHz
h
fCKLF
0.5
800 1
MHz
i
ns
j
Command and Address Input Timings
Command input setup time Command input hold time Command input pulse width Address input setup time Address input hold time Address input pulse width tCMDS tCMDH tCMDPW tAS tAH tAPW 0.25 0.25 0.7 0.125 0.125 0.45 ns ns ns ns ns ns m,n m,n m,n,o m,n,p m,n,p m,n,o,p
Rev. 1.0 /Nov. 2009
141
H5GQ1H24AFR
Table 44. AC Timings (@1.5V)
4.0Gbps PARAMETER a, b SYMBOL MIN WCK2CK Timings
WCK stop to MRS delay for entering WCK2CK training MRS to WCK restart delay after entering WCK2CK training WCK start to WCK phase movement delay WCK phase change to phase detector out delay WCK Clock high-level width during WCK2CK training WCK Clock low-level width during WCK2CK training PLL on;MR6A0=0 (at phase detector) WCK2CK offset when zero offset at phase detector or at pins PLL on;MR6A0=1 (at pins) tWCK2CKPIN PLL off;MR6A0=0 (at phase detector) PLL off;MR6A0=1 (at pins) MR6A0=0 (at phase detector) tWCK2CKSYNC MR6A0=1 (at pins) MR6A0=0 (at phase detector) WCK2CK phase offset MR6A0=1 (at pins) tWCK2CK -0.4 0.4 ns -0.25 0.25 ns -0.2 0.2 tWCK2MRS 3 ns
UNIT NOTES MIN MAX
MAX
tMRSTWCK tWCK2TR tWCK2PH tWCKHTR
10 10 5 0.42
0.58
ns tCK ns tWCK
q
k,l,r
tWCKLTR
0.42
0.58
tWCK
k,l,r
-0.2
0.2
-0.2
0.2 ns s
-0.2
0.2
-0.25
0.25
tCK t
WCK2CK phase offset upon WCK2CK training exit
-0.4
0.4
tCK u
PLL Input and Output Timings
WCK to DQ/DBI# offset for input data WCK to DQ/DBI#/EDC/ offset for output data DQ/DBI# input pulse width PLL on tWCK2DQI PLL off PLL on tWCK2DQO PLL off tDIPW 1.1 0.225 2.2 ns y,z,aa 0.7 1.1 1.7 2.2 ns w,x 0.7 1.7 ns v
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Table 44. AC Timings (@1.5V)
4.0Gbps PARAMETER a, b
PLL on tDIVW PLL off tDQDQI tDQDQO 0.15 -0.1 -0.125 0.1 0.125 ns ns ac ad
UNIT NOTES MIN MAX
ns y,z,ab
SYMBOL MIN MAX
0.15
DQ/DBI# data input valid window
DQ/DBI# input skew within double byte DQ/DBI#/EDC output skew within double byte
Row Access Timings
Active to Active command period Active to PRECHARGE command period Active to READ command delay Active to WRITE command delay Active to RDTR command delay Active to WRTR command delay Active to LDFF command delay REFRESH to RDTR or WRTR command delay Active bank A to Active bank B command delay same bank group Active bank A to Active bank B command delay different bank groups Four bank activate window Thirty two bank activate window READ to PRECHARGE command delay same bank with bank groups enabled READ to PRECHARGE command delay same bank with bank groups disabled PRECHARGE to PRECHARGE command delay PRECHARGE command period WRITE recovery time Auto precharge write recovery + precharge time tRC tRAS tRCDRD tRCDWR tRCDRTR tRCDWTR tRCDLTR tREFTR tRRDL 40 28 12 10 10 10 10 10 5.5 9*tREFI ns ns ns ns ns ns ns ns ns af ae
tRRDS tFAW t32AW tRTPL
5.5 23 184 2
-
ns ns ns tCK
ag ah ai aj
tRTPS tPPD tRP tWR tDAL
2 1 12 12 24
-
tCK ns ns ns tCK
ak
al
Column Access Timings
RD/WR bank A to RD/WR bank B command delay same bank group RD/WR bank A to RD/WR bank B command delay different bank groups Rev. 1.0 /Nov. 2009 tCCDL 3 tCK af,am
tCCDS
2
-
tCK
ag,an 143
H5GQ1H24AFR
Table 44. AC Timings (@1.5V)
4.0Gbps PARAMETER a, b
LDFF to LDFF command cycle time LDFF(111) to LDFF command cycle time LDFF(111) to RDTR command cycle delay READ or RDTR to LDFF command delay WRITE to LDFF command delay WRTR to RDTR command delay
UNIT NOTES MIN MAX
tCK tCK tCK tCK tCK tCK ao
SYMBOL MIN
tLTLTR tLTL7TR tLTRTR tRDTLT tWRTLT tWTRTR 4 4 4 4 WL+5 WLtWLmin WL+tCR CWL+2 5
MAX
-
WRITE to WRTR command delay Internal WRITE to READ command delay same bank group Internal WRITE to READ command delay different bank groups READ or RDTR to WRITE or WRTR command delay Write Latency
tWRWTR
-
tCK
tWTRL
-
ns
af
tWTRS
5
[CLmrs+(BL /4)+2WLmrs]*tC K
-
ns
ag
tRTW
-
tCK
ap
tWL
3
7
tCK
aq
Power-Down and Refresh Timings
CKE# min high and low pulse width Valid CK Clock required after self refresh entry Valid CK Clock required before self refresh exit READ to SELF REFRESH ENTRY or POWER DOWN ENTRY command delay WRITE to SELF REFRESH ENTRY or POWER DOWN ENTRY command delay REFRESH command period Exit self refresh to non-READ/WRITE command delay Exit self refresh to READ/WRITE command delay Refresh period Average periodic refresh interval Min Power down entry to exit time Rev. 1.0 /Nov. 2009 8k rows tREFI 16k rows tPD 10 1.9 tCK 144 tCKE tCKSRE tCKSRX tRDSRE 10 10 10 CL+2tCK tCK tCK tCK tCK ar
tWRSRE tRFC tXSNRW
TBD 65 tRFC tRFC+ tRCD -
-
tCK ns ns
as
tXSRW tREF
32 3.9
tCK ms us
at
au
H5GQ1H24AFR
Table 44. AC Timings (@1.5V)
4.0Gbps PARAMETER a, b
NOP/DESELECT commands required upon powerdown and self refresh entry Power down exit time
UNIT NOTES MIN MAX
tCK tCK
SYMBOL MIN
tCPDED tXPN 2 10
MAX
-
Miscellaneous Timings
MODE REGISTER SET command period PLL enabled to PLL lock delay PLL standby time DVS voltage stabilization time REFRESH to calibration update complete delay Active termination setup time Active termination hold time READ to data out delay in address training mode tMRD tLK tSTDBTY tVS tKO tATS tATH tADR 4 TBD 10 10 0.5*tCK+ 0 10 5000 TBD 40 0.5*tCK+ 10 0.5*tCK+ 10 11 11 tCK tCK us us ns ns ns tCK q ax
Address training exit to DQ in ODT state delay Vendor ID on Venodr ID off Temperature sensor enable delay
tADZ tWRIDON tWRIDOFF tTSEN
ns ns ns us
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Table 44. AC Timings (@1.35V)
3.2Gbps PARAMETER a, b SYMBOL MIN CK and WCK Timings
PLL on CK Clock cycle time PLL off CK Clock high-level width CK Clock low-level width Min CK Clock half period Max CK Clock frequency with bank groups disabled Max CK Clock frequency with bank groups enabled and tCCDL=3tCK Max CK Clock frequency with WCK2CK alignment at pins Max CK Clock frequency in RDQS Mode Max CK Clock frequency for device operation with VREFD2 Max CK Clock frequency for WCK-to-CK auto synchronization in WCK2CK training mode Max CK Clock frequency for device operation with Low Frequency Mode enabled PLL on WCK Clock cycle time PLL off WCK Clock high-level width WCK Clock low-level width Min WCK Clock half period tWCKH tWCKL tWCKHP tWCK 0.625 0.470 0.470 0.470 10 0.530 0.530 tWCK tWCK tWCK k,l k,l tCH tCL tHP fCKBG fCKBG4 tCK 1.25 0.470 0.470 0.470 20 0.530 0.530 800 800 tCK tCK tCK MHz MHz d d C C 1.25 2 ns
UNIT NOTES MIN MAX
MAX
fCKPIN fCKRDQS fCKVREFD2
-
800 TBD TBD
MHz MHz MHz
e f g
fCKAUTOSYNC
-
800
MHz
h
fCKLF
0.625
700 1
MHz
i
ns
j
Command and Address Input Timings
Command input setup time Command input hold time Command input pulse width Address input setup time Address input hold time Address input pulse width tCMDS tCMDH tCMDPW tAS tAH tAPW 0.3 0.3 1.0 0.15 0.15 0.55 ns ns ns ns ns ns m,n m,n m,n,o m,n,p m,n,p m,n,o,p
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Table 44. AC Timings (@1.35V)
3.2Gbps PARAMETER a, b SYMBOL MIN WCK2CK Timings
WCK stop to MRS delay for entering WCK2CK training MRS to WCK restart delay after entering WCK2CK training WCK start to WCK phase movement delay WCK phase change to phase detector out delay WCK Clock high-level width during WCK2CK training WCK Clock low-level width during WCK2CK training PLL on;MR6A0=0 (at phase detector) WCK2CK offset when zero offset at phase detector or at pins PLL on;MR6A0=1 (at pins) tWCK2CKPIN PLL off;MR6A0=0 (at phase detector) PLL off;MR6A0=1 (at pins) MR6A0=0 (at phase detector) tWCK2CKSYNC MR6A0=1 (at pins) MR6A0=0 (at phase detector) WCK2CK phase offset MR6A0=1 (at pins) tWCK2CK -0.4 0.4 ns -0.25 0.25 ns -0.2 0.2 tWCK2MRS 3 ns
UNIT NOTES MIN MAX
MAX
tMRSTWCK tWCK2TR tWCK2PH tWCKHTR
10 10 5 0.42
0.58
ns tCK ns tWCK
q
k,l,r
tWCKLTR
0.42
0.58
tWCK
k,l,r
-0.2
0.2
-0.2
0.2 ns s
-0.2
0.2
-0.25
0.25
tCK t
WCK2CK phase offset upon WCK2CK training exit
-0.4
0.4
tCK u
PLL Input and Output Timings
WCK to DQ/DBI# offset for input data WCK to DQ/DBI#/EDC/ offset for output data DQ/DBI# input pulse width PLL on tWCK2DQI PLL off PLL on tWCK2DQO PLL off tDIPW 1.1 0.295 2.2 ns y,z,aa 0.7 1.1 1.7 2.2 ns w,x 0.7 1.7 ns v
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Table 44. AC Timings (@1.35V)
3.2Gbps PARAMETER a, b
PLL on tDIVW PLL off tDQDQI tDQDQO 0.19 -0.1 -0.125 0.1 0.125 ns ns ac ad
UNIT NOTES MIN MAX
ns y,z,ab
SYMBOL MIN MAX
0.19
DQ/DBI# data input valid window
DQ/DBI# input skew within double byte DQ/DBI#/EDC output skew within double byte
Row Access Timings
Active to Active command period Active to PRECHARGE command period Active to READ command delay Active to WRITE command delay Active to RDTR command delay Active to WRTR command delay Active to LDFF command delay REFRESH to RDTR or WRTR command delay Active bank A to Active bank B command delay same bank group Active bank A to Active bank B command delay different bank groups Four bank activate window Thirty two bank activate window READ to PRECHARGE command delay same bank with bank groups enabled READ to PRECHARGE command delay same bank with bank groups disabled PRECHARGE to PRECHARGE command delay PRECHARGE command period WRITE recovery time Auto precharge write recovery + precharge time tRC tRAS tRCDRD tRCDWR tRCDRTR tRCDWTR tRCDLTR tREFTR tRRDL 48 32 16 14 16 14 14 14 12 9*tREFI ns ns ns ns ns ns ns ns ns af ae
tRRDS tFAW t32AW tRTPL
7 30 245 2
-
ns ns ns tCK
ag ah ai aj
tRTPS tPPD tRP tWR tDAL
2 1 16 16 32
-
tCK ns ns ns tCK
ak
al
Column Access Timings
RD/WR bank A to RD/WR bank B command delay same bank group RD/WR bank A to RD/WR bank B command delay different bank groups Rev. 1.0/Nov. 2009 tCCDL 3 tCK af,am
tCCDS
2
-
tCK
ag,an 148
H5GQ1H24AFR
Table 44. AC Timings (@1.35V)
3.2Gbps PARAMETER a, b
LDFF to LDFF command cycle time LDFF(111) to LDFF command cycle time LDFF(111) to RDTR command cycle delay READ or RDTR to LDFF command delay WRITE to LDFF command delay WRTR to RDTR command delay
UNIT NOTES MIN MAX
tCK tCK tCK tCK tCK tCK ao
SYMBOL MIN
tLTLTR tLTL7TR tLTRTR tRDTLT tWRTLT tWTRTR 4 4 4 4 WL+5 WLtWLmin WL+tCR CWL+2 5
MAX
-
WRITE to WRTR command delay Internal WRITE to READ command delay same bank group Internal WRITE to READ command delay different bank groups READ or RDTR to WRITE or WRTR command delay Write Latency
tWRWTR
-
tCK
tWTRL
-
ns
af
tWTRS
5
[CLmrs+(BL /4)+2WLmrs]*tC K
-
ns
ag
tRTW
-
tCK
ap
tWL
3
7
tCK
aq
Power-Down and Refresh Timings
CKE# min high and low pulse width Valid CK Clock required after self refresh entry Valid CK Clock required before self refresh exit READ to SELF REFRESH ENTRY or POWER DOWN ENTRY command delay WRITE to SELF REFRESH ENTRY or POWER DOWN ENTRY command delay REFRESH command period Exit self refresh to non-READ/WRITE command delay Exit self refresh to READ/WRITE command delay Refresh period Average periodic refresh interval Min Power down entry to exit time Rev. 1.0/Nov. 2009 8k rows tREFI 16k rows tPD 11 1.9 tCK 149 tCKE tCKSRE tCKSRX tRDSRE 11 11 11 CL+2tCK tCK tCK tCK tCK ar
tWRSRE tRFC tXSNRW
TBD 120 tRFC tRFC+ tRCD -
-
tCK ns ns
as
tXSRW tREF
32 3.9
tCK ms us
at
au
H5GQ1H24AFR
Table 44. AC Timings (@1.35V)
3.2Gbps PARAMETER a, b
NOP/DESELECT commands required upon powerdown and self refresh entry Power down exit time
UNIT NOTES MIN MAX
tCK tCK
SYMBOL MIN
tCPDED tXPN 2 10
MAX
-
Miscellaneous Timings
MODE REGISTER SET command period PLL enabled to PLL lock delay PLL standby time DVS voltage stabilization time REFRESH to calibration update complete delay Active termination setup time Active termination hold time READ to data out delay in address training mode tMRD tLK tSTDBTY tVS tKO tATS tATH tADR 4 TBD 10 10 0.5*tCK+ 0 10 5000 TBD 40 0.5*tCK+ 10 0.5*tCK+ 10 11 11 tCK tCK us us ns ns ns tCK q ax
Address training exit to DQ in ODT state delay Vendor ID on Venodr ID off Temperature sensor enable delay
tADZ tWRIDON tWRIDOFF tTSEN
ns ns ns us
a. All parameters assume proper device initialization. b. Tests for AC timing may be considered at norminal supply voltage levels, but the related specification and device operation are guaranteed for the full voltage and temperature range specified. c. CK and CK# single-ended input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFC crossing and VIXCK(AC) d. Parameter fCKBG4 is required for those devices supporting both 3*tCK and 4*tCK setting for bank groups. Devices supporting only 3*tCK or 4*tCK need only to specify fCKBG. e. Parameter fCKPIN applies when the alignment point in MR6, bit A0 is set to "at pins", the phase difference between the WCK and CK clocks at the DRAM pins is within tWCK2CKSYNC or tWCK2CK for pin mode and no phase search in WCK2CK training is performed. f. Parameter fCKRDQS applies when RDQS mode is enabled in AR3, bit A5. g. Parameter fCKBREFD2 applies when the data input reference voltage in MR7, bit A7 (Half VREFD) is set to VREFD2. h. Parameter fCKAUTOSYNC applies when WCK2CK Auto Synchronization is enabled in MR7, bit A4. i. Parameter fCKLF applies when Low Frequency Mode is enabled in MR7, bit A3. j. By definition the norminal WCK clock cycle time always is 1/2 of the CK clock cycle time (not including jitter). k. WCK and WCK# single-ended input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFD crossing and VIXWCK(AC). Rev. 1.0/Nov. 2009 150
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l. The phase relationship between WCK/WCK# and CK/CK# clocks must meet the tWCK2CK specification. m. Command and address input timings are referenced to VREFC. n. Command and address input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFC crossing and VIHA(AC) or VILA(AC). o. Command and address input pulse widths are design targets. The value will be characterized but not tested on each device. p. Address input timings are only valid with ABI beging enabled and a maximum of 4 address input driven LOW. q. Parameter may be specified as a combination of tCK and ns. r. Parameters tWCKHTR and tWCKLTR specify the max. allowed WCK clock-to-clock phase shift during WCK2CK training. For READ and WRITE bursts use tWCKH and tWCKL. s. Parameter tWCK2CKPIN defines the WCK2CK phase offset range at the CK and WCK pins for ideal (phase=0 ) clock alignment at the GDDR5 SGRAM's phase detector (when the alignment point in MR6, bit A0 is set to "at phase detector"), or at the WCK and CK pins (when the alignment in MR6, bit A0 is set to "at pins"). The minimum and maximum values could be negative or positive numbers, depending on the selected WCK2CK alignment point, PLL-on or PLL-off mode and design implementation. t. Parameter tWCK2CKSYNC defines the max. phase offset from the ideal (phase = 0 ) clock alignment at the GDDR5 SGRAM's phase detector (when the alignment point in MR6, bit A0 is set to "at the phase detector"), or at the WCK and CK pins (when the alignment point in MR6, bit A0 is set to "at pins"), where the internal logic synchronizes the CK and WCK clocks; it is expected to be a fraction of tWCK2CK. u. Parameter tWCK2CK defines the max. phase offset from the ideal (phase = 0 ) clock alignment at the GDDR5 SGRAM's phase detector (when the alignment point in MR6, bit A0 is set to "at phase detector") or at the WCK and CK pins (when the alignment point in MR6, bit A0 is set to "at pins"), for stable device operation. v. Parameter tWCK2DQI defines the WCK to DQ/DBI# time delay range for WRITEs for PLL-on and PLL-off mode. The minimum and maximum values could be negative or positive numbers, depending on design implementation and PLL-on or PLL-off mode. They also vary across PVT. Data training is required to determine the actual tWCK2DQI value for reliable WRITE operation. w. Parameter tWCK2DQO defines the WCK to DQ/DBI# time delay range for READs for PLL-on and PLL-off mode. The minimum and maxium values could be negative or positive numbers, depending on design implementation and PLL-on or PLL-off mode. They also vary across PVT. Data training is required to determind the actual tWCK2DQO value for reliable READ operation. x. Outputs measured with equivalent load terminated with 60 Ohms to VDDQ y. DQ/DBI# input timings are valid only with DBI being enabled and a maximum of 4 data inputs per byte driven LOW. z. Data input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFD crossing and VIHD(AC) or VILD(AC). aa. The data input pulse width, tDIPW, defines the minimum positive or negative input pulse width for any worst-case channel required for proper propagation of an external signal to the receiver. tDIPW is measured at the pins. tDIPW is independent of the PLL mode. In general tDIPW is larger than tDIVW ab. The data input valid width, tDIVW, defines the time region where input data must be valid for reliable data capture at the receiver for any one worst case channel. It accounts for jitter between data and clock at the latching point introduced in the path between DARM pads and the latching point. Any additional jitter introduced into the source signals (e.g. within the system before the DRAM pad) must be accounted for in the final timing budget together with the chosen PLL mode and bandwidth. tDIVW is measured at the pins. tDIVW is defined for PLL off and on mode separately. In the case of PLL on, tDIVW must be specified for each supported bandwidth. In general, tDIVW is smaller than tDIPW. ac. tDQDQI defines the maximum skew among all DQ/DBI# inputs of a double byte (when configured to x 32 mode) or a single byte (when configured to x 16 mode) under worst case conditions. Parameter tWCK2DQI defines the mean value of the earliest and latest DQ/DBI# pin, tDQDQI(min) the negative offset to tWCK2DQI for the earliest DQ/DBI# pin and tDQDQI(max) the positive offset to tWCK2DQI for the latest DQ/DBI# pin. ad. tDQDQO defines the maximum skew among all DQ/DBI# outputs of a double byte (when configured to x 32mode) or a single byte (when configured to x 16 mode) under worst case conditions. Parameter tWCK2DQO defines the mean value of of the earliest and latest DQ/DBI# /EDC pin, tDQDQO(min) the negative offset to tWCK2DQO for earliest DQ/DBI#/EDC pin and tDQDQO(max) the positive offset to tWCK2DQO for the latest DQ/DBI#/EDC pin. ae. For READs and WRITEs with AUTO PRECHARGE enabled the device will hold off the internal PRECHARGE until tRAS(min) has been satisfied. af. Parameter applies when bank groups are enabled and consecutive commands access the same bank group. ag. Parameter applies when bank groups are disabled or consecutive commands access different bank group. ah. Not more than 4 ACTIVE commands are allowed within period. ai. Not more than 32 ACTIVE commands are allowed within t32AW period. The parameter need not to be specified in case t32AW(min) would not be greater than 8*tFAW(min). aj. Parameter applies when bank groups are enabled and READ and PRECHARGE commands access the same bank. ak. Parameter applies when bank groups are disabled or READ and PRECHARGE commands access the same bank. al. tDAL = (tWR/tCK) + ( tRP/tCK). For each of the terms, if not already an integer, round up to the next integer. am. tCCDL is either for gapless consecutive READ or gapless consecutive WRITE commands an. tCCDS is either for gapless consecutive READ or RDTR (any combination), gapless consecutive WRITE, or gapless consecutive WRTR commands. ao. The min. value does not exceed 8 tCK ap. tRTW is not a device limit but determined by the system bus turnaround time. The difference between tWCK2DQO and tWCK2DQI shall be considered in the calculation of the bus turnaround time.
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aq. The WRITE latency WLmrs cna be set to 3 to 7 clocks. When the WRITE latency is set to small values (3 ~ 4 clocks), the input buffers are always on, reducing the latency but adding power. When the WRITE latency is set to larger values (5 ~ 7 clocks), the input buffers are turned on with the WRITE command, thus saving power. ar. Read data including CRC data must have been clocked out before entering self refresh or power down mode. as. Write data must have been written to the memory core and CRC data must have been clocked out before entering self refresh or power down mode. at. Time for WCK2CK training and data training not included. au. A maximum of 8 consecutive REFRESH commands can be posted to a GDDR5 SGRAM device, meaning that the maximum absolute interval between any REFRESH command and the next REFRESH command is 9*tREFI. av. Replaces parameter tLK when PLL Fast Lock has been neabled prior to the PLL enable or reset. aw. Replaces parameter tLK when PLL Standby has been enabed and the WCK clock frequency has not charged while in standby mode. ax. The PLL standby time tSTDBY ismeasured from self refresh entry until after self refresh exit a subsequent PLL reset is given (with PLL Standby enabled)
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6.3 CLOCK-TO-DATA TIMING SENSITIVITY
Theavailabilityofclocktodata(WCK2DQ)timingsensitivityinformationprovidesthecontrollerthe opportunitytoanticipatetheimpacttotimingsfromvariationsinenvironmentalconditions(suchas changesinvoltageortemperature)allowingthecontrollertotakecorrectiveactionifnecessary(e.g. realigningWCKandDQ). VariationsinrelativetimingbetweenWCKanddataarereportedforREADandWRITEpaths.Thisspeci ficationcallsoutonezoneeachforVDDQ,VDD,andTcasetemperatureoveraspecifiedrange.Vendors maychoosetoprovideinformationforadditionalzonescovering,intotal,awiderrangeorafinergranu larityorboth. However,withinagivenzoneifanapproximatedvalue(i.e.thespecifiedslope)deviatesfromthecharac terizedslopetosuchadegreethattheapproximatedWCKtoDQtimedelaywouldbeinerrorbymore than5%ofoneUIrelativetothecharacterizeddelaythenthesplittingofthiszoneintomorethanonezone isrequired. Allzonesandtheirassociatedspecifiedslopesmustformacontinuouspiecewiselinearcurvesuchthat, aftercalibrationduringnormaloperation,traversingtheapproximatedcurve(i.e.thesetofspecified slopes)doesnotleadtotimedelayerrorsinexcessofthe5%ofoneUI. Tables45,46,and47belowdescribetheminimumsetofdefinedzones.
Table 45. VDDQ Voltage Zone
VDDQHigh Zone_VQ1 VDDQmax VDDQLow VDDQmin Notes
a
a.VDDQ(max)isthemaximumspecifiedoperatingvoltage.VDDQ(min)istheminimumspecifiedoperating voltage.
Table 46. VDD Voltage Zone
VDDHigh Zone_VD1 VDDmax VDDLow VDDmin Notes
a
a.VDD(max)isthemaximumspecifiedoperatingvoltage.VDD(min)istheminimumspecifiedoperating voltage.
Table 47. Tcase Temperature Zone
TcaseHigh Zone_T1 Tcasemax TcaseLow 10C Notes
a
a.Tcase(max)isthemaximumspecifiedoperatingtemperature.
Asnoted,variationsinrelativetimingarereportedforREADandWRITEpaths.Tables48,49and50below provideinformationforREADtimingswhileTables51,52and53provideinformationforWRITEtimings
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Table 48. WCK-to-Data READ Timing Sensitivity to VDDQ
Parameter WCK2DQOSensitivitytovariationsinVDDQfor zone_VQ1 PLLon PLLoff Symbol Values TBD ps/V TBD Units Notes
ab
tO2VQSensZ1
,
a.CalculationoftO2VQSensZ1isperformedasfollows: tO2VQSensZ1equalsthequantity(tWCK2DQO(Zone_VQ1(max))tWCK2DQO(Zone_VQ1(min))) dividedby(VDDQ(Zone_VQ1(max))VDDQ(Zone_VQ1(min))) =(tWCK2DQO(VDDQ(max))tWCK2DQO(VDDQ(min)))/(VDDQ(max)VDDQ(min)). b.VDD(typ),Tcase=85C,worstcaseprocesscorner.
Table 49. WCK-to-Data READ Timing Sensitivity to VDD
Parameter PLLon WCK2DQOSensitivitytovariationsinVDDforzone_VD1 PLLoff Symbol Values TBD ps/V TBD Units Notes
a,b
tO2VDSensZ1
a.CalculationoftO2VDSensZ1isperformedasfollows: tO2VDSensZ1equalsthequantity(tWCK2DQO(Zone_VD1(max))tWCK2DQO(Zone_VD1(min))) dividedby(VDD(Zone_VD1(max))VDD(Zone_VD1(min))) =(tWCK2DQO(VDD(max))tWCK2DQO(VDD(min)))/(VDD(max)VDD(min)). b.VDDQ(typ),Tcase=85C,worstcaseprocesscorner.
Table 50. WCK-to-Data READ Timing Sensitivity to Tcase
Parameter PLLon WCK2DQOSensitivitytovariationsinTcaseforzone_T1 PLLoff Symbol Values TBD ps/C TBD Units Notes
ab
tO2TSensZ1
,
a.CalculationoftO2TSensZ1isperformedasfollows: tO2TSensZ1equalsthequantity(tWCK2DQO(Zone_T1(max))tWCK2DQO(Zone_T1(min))) dividedby(Tcase(Zone_T1(max))Tcase(Zone_T1(min))) =(tWCK2DQO(Tcase(max))tWCK2DQO(Tcase(min)))/(Tcase(max)Tcase(min)). b.VDDQ(typ),VDD(typ),worstcaseprocesscorner.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 154
H5GQ1H24AFR
Tables51,52and53belowprovideinformationforWRITEtimings. .
Table 51. WCK-to-Data WRITE Timing Sensitivity to VDDQ
Parameter PLLon WCK2DQISensitivitytovariationsinVDDQforzone_VQ1 PLLoff Symbol Values TBD ps/V TBD Units Notes
a,b
tI2VQSensZ1
a.CalculationoftI2VQSensZ1isperformedasfollows: tI2VQSensZ1equalsthequantity(tWCK2DQI(Zone_VQ1(max))tWCK2DQI(Zone_VQ1(min))) dividedby(VDDQ(Zone_VQ1(max))VDDQ(Zone_VQ1(min))) =(tWCK2DQI(VDDQ(max))tWCK2DQI(VDDQ(min)))/(VDDQ(max)VDDQ(min)). b.VDD(typ),Tcase=85C,worstcaseprocesscorner.
Table 52. WCK-to-Data WRITE Timing Sensitivity to VDD
Parameter PLLon WCK2DQISensitivitytovariationsinVDDforzone_VD1 PLLoff Symbol Values TBD ps/V TBD Units Notes
a,b
tI2VDSensZ1
a.CalculationoftO2VDSensZ1isperformedasfollows: tI2VDSensZ1equalsthequantity(tWCK2DQI(Zone_VD1(max))tWCK2DQI(Zone_VD1(min))) dividedby(VDD(Zone_VD1(max))VDD(Zone_VD1(min))) =(tWCK2DQI(VDD(max))tWCK2DQI(VDD(min)))/(VDD(max)VDD(min)). b.VDDQ(typ),Tcase=85C,worstcaseprocesscorner.
Table 53. WCK-to-Data WRITE Timing Sensitivity to Tcase
Parameter PLLon WCK2DQISensitivitytovariationsinTcaseforzone_T1 PLLoff Symbol Values TBD ps/C TBD Units Notes
a,b
tI2TSensZ1
a.CalculationoftI2TSensZ1isperformedasfollows: tI2TSensZ1equalsthequantity(tWCK2DQI(Zone_T1(max))tWCK2DQI(Zone_T1(min))) dividedby(Tcase(Zone_T1(max))Tcase(Zone_T1(min))) =(tWCK2DQI(Tcase(max))tWCK2DQI(Tcase(min)))/(Tcase(max)Tcase(min)). b.VDDQ(typ),VDD(typ),worstcaseprocesscorner.
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H5GQ1H24AFR 7.PACKAGESPECIFICATION
1
VSSQ VDDQ VSSQ VDDQ VSSQ VDDQ VDD VSS
MF
2
DQ1 DQ3
3 4 BYTE0
VSSQ VDDQ VSSQ
DQ0 DQ2
5
VPP,
NC
6
7 A B C D E F G H J K L M N P R T U
8
9
10
VREFD
11
DQ8
12 13 BYTE1
VSSQ VDDQ VSSQ VDDQ VSSQ VDDQ
CS# DQ9
14
VSSQ VDDQ VSSQ VDDQ VSSQ VDDQ VDD VSS
VREFC
VSS VDD
VSS VDD VSS VDDQ VSSQ VSS
BA3 A3 SEN BA1 A5
DQ10
DQ11
EDC0
VSSQ
VSSQ VDD
DQ12
EDC1
DBI0#
VDDQ WCK01 WCK01# VSSQ VDDQ
RAS# DQ4
DBI1#
DQ5
VDDQ VSSQ VSS
A9 A1
A12 RFU, NC
DQ13
DQ7
DQ6
DQ14
DQ15
VDDQ VSSQ
VDD
A10 A0 ABI# A8 A7
VDD
BA0 A2 CK# BA2 A4
VDDQ VSSQ
ZQ
VDDQ
VDDQ
CK
RESET# CKE#
VSS VDD VDDQ VSSQ VDDQ VSSQ VDDQ VSSQ
VSSQ VDDQ
DQ31
VDDQ
CAS#
A11 A6
VDDQ
WE#
VSSQ VDDQ
DQ23
VSS VDD VDDQ VSSQ VDDQ VSSQ VDDQ VSSQ
VDD
DQ30 DQ28
VSS VSSQ VDDQ
VSS VSSQ VDDQ VSS VDD VSS
VREFD
VDD
DQ22
VDDQ VSSQ
VDDQ VSSQ VDDQ VSSQ VDDQ VSSQ
DQ29
DBI3#
DQ20
DQ21
DBI2#
VDDQ WCK23 WCK23# VSSQ VDDQ VSSQ VSSQ
DQ26 DQ24
VDD VSSQ
DQ18
EDC3 DQ27
VDD VSS VPP,
NC
EDC2 DQ19
DQ25
DQ16
DQ17
BYTE3
x32mode:ON x16mode:ON
x32mode:ON x16mode:OFF
BYTE2
Note) Top View (as seen thru package), MF = LOW (MF = 0)
Figure 81. GDDR5 SGRAM 170ball BGA Ball-out MF=0
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 156
H5GQ1H24AFR
1
VSSQ VDDQ VSSQ VDDQ VSSQ VDDQ VDD VSS
MF
2
DQ25
3 4 BYTE3
VSSQ VDDQ VSSQ
DQ24
5
VPP,
NC
6
7 A B C D E F G H J K L M N P R T U
8
9
10
VREFD
11
DQ16
12 13 BYTE2
VSSQ VDDQ VSSQ VDDQ VSSQ VDDQ
WE# DQ17
14
VSSQ VDDQ VSSQ VDDQ VSSQ VDDQ VDD VSS
VREFC
DQ27 EDC3
DQ26
VSS VDD
VSS VDD VSS VDDQ VSSQ VSS
BA1 A5 SEN BA3 A3
DQ18
DQ19
VSSQ
VSSQ VDD
DQ20
EDC2
DBI3#
VDDQ WCK23 WCK23# VSSQ VDDQ
CAS# DQ28 DQ30
DBI2#
DQ29 DQ31
VDDQ VSSQ VSS
A11 A6
A12 RFU, NC
DQ21
DQ22
DQ23
VDDQ VSSQ
VDD
A8 A7 ABI# A10 A0
VDD
BA2 A4 CK# BA0 A2
VDDQ VSSQ
ZQ
VDDQ
VDDQ
CK
RESET# CKE#
VSS VDD VDDQ VSSQ VDDQ VSSQ VDDQ VSSQ
VSSQ VDDQ
DQ7
VDDQ
RAS#
A9 A1
VDDQ
CS#
VSSQ VDDQ
DQ15
VSS VDD VDDQ VSSQ VDDQ VSSQ VDDQ VSSQ
VDD
DQ6 DQ4
VSS VSSQ VDDQ
VSS VSSQ VDDQ VSS VDD VSS
VREFD
VDD
DQ14
VDDQ VSSQ
VDDQ VSSQ VDDQ VSSQ VDDQ VSSQ
DQ5
DQ12
DQ13
DBI1#
DBI0#
VDDQ WCK01 WCK01# VSSQ VDDQ VSSQ VSSQ
DQ2 DQ0
VDD VSSQ
DQ10
EDC0
VDD VSS VPP,
NC
EDC1 DQ11
DQ3
DQ1
DQ8
DQ9
BYTE0
x32mode:ON x16mode:ON
x32mode:ON x16mode:OFF
BYTE1
Note)TopView(asseenthrupackage),MF=HIGH(MF=1)
Figure 82. GDDR5 SGRAM 170ball BGA Ball-out MF=1
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 157
H5GQ1H24AFR
7.1.SIGNALS Table 54. Ball-out Description
SYMBOL
CK,CK#
TYPE
Input
DESCRIPTION
Clock:CKandCK#aredifferentialclockinputs.Commandinputsarelatchedontherising edgeofCK.AddressinputsarelatchedontherisingedgeofCKandtherisingedgeofCK#. AlllatenciesarereferencedtoCK.CKandCK#areexternallyterminated. WriteClocks:WCKandWCK#aredifferentialclocksusedforWRITEdatacaptureandREAD dataoutput.WCK01/WCK01#isassociatedwithDQ0DQ15,DBI0#,DBI1#,EDC0andEDC1. WCK23/WCK23#isassociatedwithDQ16DQ31,DBI2#,DBI3#,EDC2andEDC3. ClockEnable:CKE#LOWactivatesandCKE#HIGHdeactivatestheinternalclock,device inputbuffers,andoutputdrivers.TakingCKE#HIGHprovidesPRECHARGEPOWER DOWNandSELFREFRESHoperations(allbanksidle),orACTIVEPOWERDOWN(row ACTIVEinanybank).CKE#mustbemaintainedLOWthroughoutreadandwriteaccesses. ThevalueofCKE#latchedatpowerupwithRESET#goingHighdeterminesthetermination valueoftheaddressandcommandinputs. ChipSelect:CS#LOWenablesandCS#HIGHdisablesthecommanddecoder.Allcommands aremaskedwhenCS#isregisteredHIGH.CS#providesforexternalrankselectiononsystems withmultipleranks.CS#isconsideredpartofthecommandcode. CommandInputs:RAS#,CAS#,andWE#(alongwithCS#)definethecommandbeing entered. BankAddressInputs:BA0BA3definetowhichbankanACTIVE,READ,WRITE,or PRECHARGEcommandisbeingapplied.BA0BA3alsodeterminewhichModeRegisteris accessedwithanMODEREGISTERSETcommand.BA0BA3aresampledwiththerising edgeofCK. AddressInputs:A0A11(A12)providetherowaddressforACTIVEcommands,A0A5(A6) providethecolumnaddressandA8definestheautoprechargefunctionforREAD/WRITE commands,toselectonelocationoutofthememoryarrayintherespectivebank.A8sampled duringaPRECHARGEcommanddetermineswhetherthePRECHARGEappliestoonebank (A8LOW,bankselectedbyBA0BA3)orallbanks(A8HIGH).Theaddressinputsalso providetheopcodeduringaMODEREGISTERSETcommandandthedatabitsduringa LDFFcommand.A8A11(A12)aresampledwiththerisingedgeofCKandA0A7are sampledwiththerisingedgeofCK#. DataInput/Output:32bitdatabus DataBusInversion.DBI#0isassociatedwithDQ0DQ7,DBI#1isassociatedwithDQ8DQ15, DBI#2isassociatedwithDQ16DQ23,DBI#3isassociatedwithDQ24DQ31. ErrorDetectionCode.ThecalculatedCRCdataistransmittedonthesepins.Inadditionthese pinsdrivea`hold'patternwhenidleandcanbeusedasanRDQSfunction.EDC0is associatedwithDQ0DQ7,EDC1isassociatedwithDQ8DQ15,EDC2isassociatedwith DQ16DQ23,EDC3isassociatedwithDQ24DQ31. AddressBusInversion I/OPowerSupply.Isolatedonthedieforimprovednoiseimmunity. I/OGround:Isolatedonthedieforimprovednoiseimmunity. PowerSupply Ground ReferenceVoltageforDQ,DBI#,andEDCpins. ReferenceVoltageforaddressandcommandpins. PumpVoltage MirrorFunction:VDDQCMOSinput.Mustbetiedtopowerorground. ExternalReferencePinforautocalibration
WCK01, WCK01#, WCK23, WCK23# CKE#
Input
Input
CS#
Input
RAS#, CAS#,WE# BA0-BA3
Input Input
A0-A11 (A12)
Input
DQ0-31 DBI#03 EDC03
I/O I/O Output
ABI# VddQ VssQ Vdd Vss Vrefd Vrefc Vpp MF ZQ
Input Supply Supply Supply Supply Supply Supply Supply Reference Reference
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 158
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Table 54. Ball-out Description
SYMBOL
RFU NC SEN RESET# Input Input
TYPE
ReservedforFutureUse
DESCRIPTION
Notconnected Scanenable.VDDQCMOSinput.Mustbetiedtothegroundwhennotinuse. ResetPin.VDDQCMOSinput.RESET#Lowasynchronouslyinitiatesafullchipreset.With RESET#LowallODTsaredisabled.
Figure clarifiestheuseoftheMF=0andMF=1balloutsinx16modeandwhythebytesarerenumberedto givethecontrollertheviewofthesamebytesthatacontrollerseeswithasinglex32device.Thisisimpor tantforAddressTraining,DMandEDCfunctionality.Formoredetailsseethex16enableandMFenable section.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 159
H5GQ1H24AFR
0
1
0
1
+
2 3
=
3 2
Topviewthrupackage (PCBbelow)
TopviewthruPCB (PCBabove)
Controllerview
x16MF=0
x16MF=0
x16MF=1
Legend: DQ ADDRESS/COMMAND(exceptCS#) CS#
x16MF=1
Figure 83. Byte Orientation in Clamshell Topology
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 160
H5GQ1H24AFR
7.2.ONDIETERMINATION(ODT)
GDDR5SGRAMssupportmultipleterminationmodesforitshighspeedinputsignals.Whenthetermina tionisenabledforareceiver,animpedancedefinedforthatterminationmodeisappliedbetweenthat inputreceiverandtheVDDQsupplyrail.ThisiscommonlyreferredtoasVDDQtermination.Registers havebeendefinedtocontroltheterminationmodes.ADD/CMDTerminationiscontrolledusingMR1bits A4andA5.DataterminationiscontrolledusingMR1bitsA2andA3.WCKterminationiscontrolled usingMR3bitsA8andA9. Table55includesallthehighspeedGDDR5SGRAMsignalswhosereceiversincludeondieterminationto VDDQandwhethertheirterminationcanbedisabledbyADD/CMDTerm,DQTerm,orWCKTerm.A "Yes"indicateswhetherthemoderegisterfieldcontrolsterminationforthesignal.
Table 55. Signals Affected by Termination Control Registers
ADD/CMDTerm MR1(A4,A5) Signal RAS#,CAS#,WE,CS#,CKE# A10/A0,A9/A1,BA0/A2,BA3/A3, BA2/A4,BA1/A5,A11/A6,A8/A7, A12/RFU/(NC),ABI# DQ[7:0],DBI0# DQ[15:8],DBI1# DQ[23:16],DBI2# DQ[31:24],DBI3# WCK01,WCK01#,WCK23,WCK23# x32 Yes Yes No No No No No x16 Yes Yes No Disabled No Disabled No DQTerm MR1(A2,A3) x32 No No Yes Yes Yes Yes No x16 No No Yes Disabled Yes Disabled No WCKTerm MR3(A8,A9) x32 No No No No No No Yes x16 No No No Disabled No Disabled Yes
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 161
H5GQ1H24AFR
7.3.PACKAGEOUTLINE
TOPVIEW
SIDEVIEW
pkgheight
U T R p N M L K
BOTTOMVIEW (170ball)
H G F E D
B A
pkgstandoff 5x0.8=4.0 13x0.8=10.4 pkgx 12 0.8
Figure 84. Package Dimensions
Table 56. Package Height Parameters
Nominal pkgstandoff pkgheight 0.350 1.100 Variation +/0.050 +/0.100
Notes: 1)GDDR5packageheightspecificationiscomplianttoMO207RevL,variationDAAz
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 162
0.8
C
14
J
16x0.8=12.8
pkgY
H5GQ1H24AFR
7.4.MIRRORFUNCTION(MF)ENABLEandx16MODEENABLE
TheGDDR5SGRAMprovidesamirrorfunction(MF)pintochangethephysicallocationofthecommand, address,data,andWCKpinsassistinginroutingdevicesbacktoback.TheMFballshouldbetieddirectly toVSSQorVDDQdependingonthecontrollineorientationdesired. TheGDDR5SGRAMcanoperateinax32modeorax16modetoallowaclamshellconfigurationwitha pointtopointconnectiononthehighspeeddatasignal.Thedisabledpinsinx16modeshouldallbeina HiZstate,nonterminating. Thex16modeisdetectedatpoweruponthepinatlocationC13whichisEDC1whenconfiguredtoMF=0 andEDC2whenconfiguredtoMF=1.Forx16modethispinistiedtoVSSQ;thepinispartofthetwobytes thataredisabledinthismodeandthereforenotneededforEDCfunctionality.Forx32modethispinis activeandalwaysterminatedtoVDDQinthesystemorbythecontroller.Theconfigurationissetwith RESET#goingHigh.Oncetheconfigurationhasbeenset,itcannotbechangedduringnormaloperation. Usuallytheconfigurationisfixedinthesystem.Detailsofthex16modedetectionaredepictedinFigure . Acomparisonofx32modeandx16modesystemsisshowninFigure .
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 163
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VDDQ enable Termination EDCdatafrom otherDRAM
GDDR5 inx16mode MF=0
EDC1 EDCData
RX
EDC1
EDC x16
TX EN
Controller
RESET#
VSSQ
RX
D
0=x16
RESET#
RESET#
VDDQ enable Termination EDC2 EDC x16 TX EN EDCdatafrom otherDRAM
GDDR5 inx16mode MF=1
EDCData
RX
EDC2
Controller
RESET# RESET#
VSSQ
RX
D
0=x16
RESET#
VDDQ enable Termination
GDDR5 inx32mode MF=0or1
EDC1 x32 1=x32 VSSQ RX D EDCData
RX
EDC1
EDC
TX EN
Controller
RESET# RESET# RESET#
Figure 85. Enabling x16 mode
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 164
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Table 57. x16 mode and MF
MODE x16nonmirrored x32nonmirrored x16mirrored x32mirrored MF VSSQ VSSQ VDDQ VDDQ EDC1(MF=0)orEDC2(MF=1) VSSQ VDDQ(terminatedbythesystemorcontroller) VSSQ VDDQ(terminatedbythesystemorcontroller)
GDDR5 x32
DQ0DQ7,DBI0# EDC0 WCK01,WCK01# DQ8DQ15,DBI1# EDC1
GDDR5 x16
DQ0DQ7,DBI0# EDC0 WCK01,WCK01#
GDDR5 x16
Byte0
Byte0
EDC1 EDC2
Byte1
DQ8DQ15,DBI1# EDC1
Byte1
Controller
Controller
DQ16DQ23,DBI2# EDC2 WCK23,WCK23# DQ24DQ31,DBI3# EDC3 AddressBus CommandBus CK,CK# RESET#
Byte2
DQ16DQ23,DBI2# EDC2 WCK23,WCK23#
Byte2
Byte3
DQ24DQ31,DBI3# EDC3 AddressBus
Byte3
ADD/ CMD
CommandBus CK,CK# RESET
ADD/ CMD
MF VSSQ
MF VSSQ
MF VDDQ
Figure 86. System view for x32 mode vs. x16 mode
Figure86andFigure87showexamplesoftheboardchannelsandtopologiesthataresupportedin GDDR5inordertoillustratetheexpectedusageofx16modeandtheMFpin.
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32bitchannel
16DQ (P2P) 32DQ (P2P) ADD/CMD (P22P) 16DQ (P2P) ADD/CMD (P2P)
64bitchannel
32DQ (P2P)
ADD/CMD (P22P) 32DQ (P2P)
Figure 87. Example Channel Topologies
ForflexibilityofPCBroutingGDDR5SGRAMdevices,theballoutincludesdefinitionofbothMF=0and MF=1.ThefollowingsimpleblockdiagramsinFigure88demonstratesomeoftheflexibilityofPCBrout ing.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 166
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Singlesideconfigurations
x32MF=0
1
x32MF=0
x32MF=0
x32MF=0
x32MF=0
1
x32MF=1
x32MF=0
x32MF=1
x32MF=1
1
x32MF=1 x32MF=1
x32MF=1
x16MF=0
x16MF=1
Clamshellconfigurations
x32MF=0
1
x16MF=0 x32MF=1 x32MF=1
1
x16MF=1 x16MF=1
x32MF=1 x32MF=0
1
x16MF=0
Legend:
x32MF=0
Note1:32bitchannelisshownasanexample. Alsoapplieswithx16ona16bitchannel.
DQ ADDRESS/COMMAND(exceptCS#) CS#
Figure 88. Example GDDR5 PCB Layout Topologies
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 167
H5GQ1H24AFR
BOUNDARY SCAN
TheGDDR5SGRAMincorporatesamodifiedboundaryscantestmode.Thismodedoesnotoperatein accordancewithIEEEStandard1149.11990.TosavethecurrentGDDR5SGRAM'sballout,thismodewill scantheparalleldatainputandoutputthescanneddataonEDC0locatedatC2controlledbyanaddon pin,SENwhichislocatedatJ10ofthe170ballpackage. Scanmodeisentereddirectlyafterpowerupwhilethedeviceisinresetstate.Thisensuresthatno unwantedaccesscommandsarebeingexecutedpriortoscanmode. Boundaryscandoesnotdistinguishbetweenx16andx32modes,anddataiscapturedonallpins.Theuser hastomakesuretomaskthosebitsinthetestprogramwhicharenotwiredinthesystem. Fornormaldeviceoperation,i.e.afterscanmodeoperation,itisrequiredthatdevicereinitialization occursthroughdevicepowerdownandthenpowerup. ItispossibletooperatetheGDDR5SGRAMwithoutusingtheboundaryscanfeature.SENshouldbetied Lowtopreventthedevicefromenteringtheboundaryscanmode.Theotherpinswhichareusedforscan mode(RESET#,MF,EDC0andCS#)willbeoperatingasnormalwhenSENisdeasserted.
Table 58. Boundary Scan Exit Order
BIT# 1 2 3 4 5 6 7 8 9 10 11 12 BALL D5 D4 D2 E4 E2 F4 F2 G3 H5 H4 J5 J4 BIT# 13 14 15 16 17 18 19 20 21 22 23 24 BALL J3 K4 K5 L3 M2 M4 N2 N4 P2 P4 P5 R2 BIT# 25 26 27 28 29 30 31 32 33 34 35 36 BALL T2 T4 U2 U4 U11 U13 T11 T13 R13 P13 N11 N13 BIT# 37 38 39 40 41 42 43 44 45 46 47 48 BALL M11 M13 L12 K10 K11 J13 J12 J11 H11 H10 F13 F11 BIT# 49 50 51 52 53 54 55 56 57 58 59 60 BALL E13 E11 D13 C13 B13 B11 A13 A11 A4 A2 B4 B2
Note:Whenthedeviceisinscanmode,mirrorfunctionisdisabled(MF=0)andnoneofthepinsareremapped.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 168
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Table 59. Scan Pin Description
PACKAGE SYMBOL BALL J2 SSH NORMAL FUNCTION RESET# TYPE Input DESCRIPTION ScanShift:capturethedatainputfromthepadatlogicLOW andshiftthedataonthechainatlogicHIGH. ScanClock.Notatrueclock,couldbeasinglepulseorseriesof pulses.Allscaninputswillbereferencedtotherisingedgeof thescanclock. ScanOutput. ScanEnable:logicHIGHenablesscanmode.Scanmodeis disabledatlogicLOW.MustbetiedtoVSSQwhennotinuse. ScanOutputEnable:enables(registeredLOW)anddisables (registeredHIGH)SOUTdata.ThispinwillbetiedtoVDDQor GNDthrougharesistor(typically1KOhm)fornormal operation.Testerneedstooverdrivethispintoguaranteethe requiredinputlogiclevelinscanmode.
G12 C2 J10
SCK SOUT SEN
CS# EDC0 RFU
Input Output Input
J1
SOE#
MF
Input
Notes: 1. WhenSENisasserted,nocommandsaretobeexecutedbytheGDDR5SGRAM.Thisappliestobothuser commandsandmanufacturingcommandswhichmayexistwhileRESET#isdeasserted. 2. Allscanfunctionalityisvalidonlyaftertheappropriatepowerup(Steps14ofinitializationsequence). 3. Inscanmode,allODTwillbedisabled.
Table 60. Scan AC Electrical Characteristics
PARAMETER/CONDITION SYMBOL MIN MAX UNIT S NOTES
Clock Clockcycletime ScanCommandTime Scanenablesetuptime Scanenableholdtime ScancommandsetuptimeforSSH,SOE#andSOUT ScancommandholdtimeforSSH,SOE#andSOUT ScanCaptureTime Scancapturesetuptime Scancaptureholdtime tSDS tSDH 10 10 ns ns 1 1 tSES tSEH tSCS tSCH 20 20 14 14 ns ns ns ns 1 1 1 1 tSCK 40 ns 1
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Table 60. Scan AC Electrical Characteristics
PARAMETER/CONDITION SYMBOL MIN MAX UNIT S NOTES
ScanShiftTime Scanclocktovalidscanoutput Scanclocktoscanoutputhold
Notes: 1. TheparameterappliesonlywhenSENisasserted.
tSAC tSOH
1.5
6
ns ns
1 1
SCK tSES SEN SSH
Notatrueclock,butasinglepulse oraseriesofpulses
(Low) tSCS
SOE# tSDS Pins under Test tSDH
VALID
Figure. 89 Scan Capture Timing
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 170
H5GQ1H24AFR
SCK tSES SEN SSH tSCS SOE# tSOH SOUT tSAC ScanOut bit1 tSCS
ScanOut bit2
ScanOut bit3
ScanOut bit4
Figure. 90 Scan Shift Timing
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H5GQ1H24AFR
VDD VDDQ VREF RESET#
(SSHin ScanMode)
tSCS
SEN
tSES
tSCK
SCK tSCS SOE# tSCS ScanOut bit1
SOUT tSDS Pins under Test 200us Powerup RESETatpowerup VDDstable tSDH
tSAC
VALID
BoundaryScanMode Don'tCare
Figure 91. Scan Initialization Sequence
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H5GQ1H24AFR
DQ3
D
SET
Q
DedicatedScanDFFpersignalundertest
CLR
Q
DQ2
D
SET
Q
CLR
Q
Signalsinscanchain: DQ[31:0],EDC[3:1],DBI#[3:0], WCK01,WCK01#,WCK23,WCK23#, RAS#,CAS#,WE#,CKE#,ABI#, A[7:0]***,CK,CK#,ZQ Note:A[7:0]***aremultiplexedpinsand representA[12:8]andBA[3:0] Signalsnotinthescanchain: VDDQ,VSSQ,VDD,VSS,VREFx
Pinsundertest DQ1
D
SET
Q
CLR
Q
WCK01# SSH,ScanShiftPinRESET# SCK,ScanClockPinCS# SEN,ScanEnablePinSEN SOE#,ScanOutputEnablePinMF
D
SET
Q
SOUT,ScanOutPinEDC0
CLR
Q
Figure. 92 Internal Block Diagram
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 173

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