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MB39C007
PIN ASSIGNMENT
(Top View)
LX2 DGND2 DGND2 DGND1 DGND1 LX1 18 DVDD2 19 17 16 15 14 13 12 DVDD1
DVDD2
20
11
DVDD1
OUT2
21
10
OUT1
MODE2
22
9
MODE1
VREFIN2
23
8
VREFIN1
XPOR
24 1 CTLP 2 CTL2 3 CTL1 4 AGND 5 AVDD 6 VREF
7
VDET
(LCC-24P-M09)
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PIN DESCRIPTIONS
Pin No. 1 2, 3 4 5 6 7 8, 23 9, 22 10, 21 11, 12 19, 20 13, 18 14, 15 16, 17 24 Pin Name CTLP CTL2, CTL1 AGND AVDD VREF VDET VREFIN1, VREFIN2 MODE1, MODE2 OUT1, OUT2 DVDD1 DVDD2 LX1, LX2 DGND1 DGND2 XPOR O O O I I I I I/O I I Description Voltage detection circuit block control input pin. (L : Voltage detection function stop / H : Normal operation) DC/DC converter block control input pins. (L : Shut down / H : Normal operation) Control block ground pin. Control block power supply pin. Reference voltage output pin. Voltage detection input pin. Error amplifier (Error Amp) non-inverted input pins. Operation mode switch pins. (L : PFM/PWM mode / OPEN : PWM mode) Output voltage feedback pins. Drive block power supply pins. Inductor connection output pins. High impedance during shut down. Drive block ground pins. VDET circuit output pin. Connected to an N-ch MOS open drain circuit.
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I/O PIN EQUIVALENT CIRCUIT DIAGRAM
VDD
VDD
LX1, LX2
VREF
GND
GND
VDD
VREFIN1, VREFIN2, VDET
OUT1, OUT2
GND
VDD
CTL1, CTL2, CTLP
GND
VDD
XPOR
MODE1, MODE2
GND
GND
* : ESD Protection device
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BLOCK DIAGRAM
VIN AVDD CTL1 3 ON/OFF OUT1 10 x3 S + Error Amp DVDD1 5 DVDD1 11, 12 DVDD2 19, 20
IOUT Comp. VREFIN1 DAC 8 L:PFM/PWM OPEN:PWM MODE1 9 VIN CTLP VDET VREF CTL2 1 7 S 1.30 V 6 VREF 2 ON/OFF x3 S + Error Amp DVDD2 + ON/OFF 24 XPOR Mode Control VIN PFM/PWM Logic Control LX1 13 VOUT1
OUT2
21
IOUT Comp. VREFIN2 23 L:PFM/PWM OPEN:PWM MODE2 22 Mode Control PFM/PWM Logic Control LX2 18 VOUT2
4 AGND
14, 15 DGND1
16, 17 DGND2
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Current mode * Original voltage mode type : Stabilize the output voltage by comparing two items below and on-duty control. - Voltage (VC) obtained through negative feedback of the output voltage by Error Amp - Reference triangular wave (VTRI) * Current mode type : Instead of the triangular wave (VTRI), the voltage (VIDET) obtained through I-V conversion of the sum of currents that flow in the oscillator (rectangular wave generation circuit) and SW FET is used. Stabilize the output voltage by comparing two items below and on-duty control. - Voltage (VC) obtained through negative feedback of the output voltage by Error Amp - Voltage (VIDET) obtained through I-V conversion of the sum of current that flow in the oscillator (rectangular wave generation circuit) and SW FET
Voltage mode type model
VIN
Current mode type model
VIN
Oscillator
Vc VTRI
S +
Vc VIDET
S
+
S R
Q
SR-FF
Vc VTRI ton
VIDET Vc toff
toff
ton
Note : The above models illustrate the general operation and an actual operation will be preferred in the IC.
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FUNCTION OF EACH BLOCK
* PFM/PWM Logic control circuit In normal operation, frequency (2.0 MHz) which is set by the built-in oscillator (square wave oscillation circuit) controls the built-in P-ch MOS FET and N-ch MOS FET for the synchronous rectification operation. In the light load mode, the intermittent (PFM) operation is executed. This circuit protects against pass-through current caused by synchronous rectification and against reverse current caused in a non-successive operation mode. * IOUT Comparator circuit This circuit detects the current (ILX) which flows to the external inductor from the built-in P-ch MOS FET. By comparing VIDET obtained through I-V conversion of peak current IPK of ILX with the Error Amp output, the builtin P-ch MOS FET is turned off via the PFM/PWM Logic Control circuit. * Error Amp phase compensation circuit This circuit compares the output voltage to reference voltages such as VREF. This IC has a built-in phase compensation circuit that is designed to optimize the operation of this IC. This needs neither to be considered nor addition of a phase compensation circuit and an external phase compensation device. * VREF circuit A high accuracy reference voltage is generated with BGR (bandgap reference) circuit. The output voltage is 1.30 V (Typ). * Voltage Detection (VDET) circuit The voltage detection circuit monitors the VDET pin voltage. Normally, use the XPOR pin through pull-up with an external resistor. When the VDET pin voltage reaches 0.6 V, it reaches the H level. Timing chart example : (XPOR pin pulled up to VIN)
VIN VUVLO
CTLP
VDET
VTHHPR VTHLPR
XPOR
VUVLO : UVLO threshold voltage VTHHPR, VTHLPR : XPOR threshold voltage * Protection circuit This IC has a built-in over-temperature protection circuit. The over-temperature protection circuit turns off both N-ch and P-ch switching FETs when the junction temperature reaches + 135 C. When the junction temperature comes down to + 110 C, the switching FET is returned to the normal operation. Since the PFM/PWM control circuit of this IC is in the control method in current mode, the current peak value is also monitored and controlled as required. DS04-27246-2E 7
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* Function table Input CTL1 CTL2 L H L H L H L H L H L H L L H H * : Don't care H Open L H H L H L Operation Stopped H L L H L CTLP MODE * Operation Stopped Stopped Operation Stopped PFM/PWM mode Operation CH1 function CH2 function
Output VDET function VREF function Switching operation
Stopped
Operation Stopped Operation Stopped Stopped Operation Operation Stopped Operation Stopped PWM fixed mode Operation 1.3 V output
Operation Stopped Operation Stopped Stopped Operation Operation
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RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage VREFIN voltage CTL voltage LX current Symbol VDD VREFIN VCTL ILX CTLP, CTL1, CTL2 pins ILX1, ILX2 2.5 V AVDD = DVDD1 = DVDD2 < 3.0 V 3.0 V AVDD = DVDD1 = DVDD2 5.5 V 2.2 Condition AVDD = DVDD1 = DVDD2 Value Min 2.5 0.15 0 Typ 3.7 Max 5.5 1.30 5.0 800 0.5 mA 1 1 mA H Unit V V V mA
VREF output current
IROUT
XPOR current Inductor value
IPOR L
Note : The output current from this device has a situation to decrease if the power supply voltage (VIN) and the DC/DC converter output voltage (VOUT) differ only by a small amount. This is a result of slope compensation and will not damage this device. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.
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ELECTRICAL CHARACTERISTICS
(Ta = +25 C, AVDD = DVDD1 = DVDD2 = 3.7 V, VOUT1/VOUT2 setting value = 2.5 V, MODE1/MODE2 = 0 V) Parameter Input current Output voltage Input stability Load stability OUT pin input impedance LX Peak current DC/DC converter block PFM/PWM switch current Oscillation frequency Rise delay time SW NMOS-FET OFF voltage SW PMOS-FET ON resistance SW NMOS-FET ON resistance LX leak current Overheating protection (Junction Temp.) SymPin No. bol IREFIN VOUT LINE LOAD ROUT IPK IMSW fosc tPG VNOFF RONP 13, 18 RONN ILEAKM ILEAKH TOTPH TOTPL VTHHUV VTHLUV VHYSUV 5, 11, 12, 19, 20 LX1/LX2 = S100 mA 0 LX VDD*2 V
DD*2
Condition VREFIN = 0.15 V to 1.3 V VREFIN = 0.833 V, OUT = S100 mA
Value Min S 100 2.45 Typ 0 2.50 Max + 100 2.55 10 10 0.6 0.9 1.0 1.2 30 1.6 2.0 45 S 10* 2.4 80 1.5 1.7
Unit nA V mV mV M A mA MHz s mV
8, 23
10, 21
2.5 V AVDD = DVDD1 = DVDD2 5.5 V* 1 S100 mA OUT OUT = 2.0 V Output shorted to GND S800 mA
13, 18
2, 3, 10, 21
C1/C2 = 4.7 F, OUT = 0 A, OUT1/OUT2 : 0 90% VOUT
LX1/LX2 = S100 mA
0.30 0.20 S 1.0 S 2.0 + 120* + 95* 2.17 2.03 0.08 575 + 135* + 110* 2.30 2.15 0.15 600 583 17
0.48 0.42 + 8.0 + 16.0 + 160* + 125* 2.43 2.27 0.25 625 608 A A C C V V V mV mV mV 0.1 1.0 V A
VDD = 5.5 V, 0 LX
Protection UVLO threshold circuit voltage block UVLO hysteresis width
XPOR threshold VTHHPR voltage VTHLPR
7
558
Voltage detection circuit block
XPOR hysteresis width XPOR output voltage XPOR output current
VHYSPR VOL 24 IOH XPOR = 5.5 V XPOR = 25 A
* : This value is not be specified. This should be used as a reference to support designing the circuits. (Continued) DS04-27246-2E 11
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(Continued) (Ta = +25 C, AVDD = DVDD1 = DVDD2 = 3.7 V, VOUT1/VOUT2 setting value = 2.5 V, MODE1/MODE2 = 0 V) Parameter CTL threshold voltage CTL pin input current Symbol Pin No. VTHHCT VTHLCT IICTL VREF LOADREF IVDD1 IVDD1H 6 1, 2, 3 0 V CTLP/CTL1/CTL2 3.7 V VREF = 0 A VREF = S1.0 mA CTLP/CTL1/CTL2 = 0 V, State of all circuits OFF*3 CTLP/CTL1/CTL2 = 0 V, VDD = 5.5 V, State of all circuits OFF*3 1. CTLP = 0 V,CTL1 = 3.7 V, CTL2 = 0 V 2. CTLP = 0 V, CTL1 = 0 V, CTL2 = 3.7 V, OUT = 0 A CTLP = 0 V, CTL1/CTL2 = 3.7 V, OUT = 0 A 1. CTLP = 0 V, CTL1 = 3.7 V, CTL2 = 0 V, MODE1/ MODE2 = OPEN 5, 11, 2. CTLP = 0 V, CTL1 = 0 V, 12, 19, CTL2 = 3.7 V, MODE1/ 20 MODE2 = OPEN, OUT = 0 A CTLP = 0 V, CTL1/CTL2 = 3.7 V, MODE1/MODE2 = OPEN, OUT = 0 A CTLP = 3.7 V, CTL1/CTL2 = 0 V 1. CTL1 = 3.7 V, CTL2 = 0 V 2. CTL1 = 0 V, CTL2 = 3.7 V, VOUT1/VOUT2 = 90%, OUT = 0 A*4 30 1.274 1.300 Condition Value Min 0.55 0.40 Typ 0.95 0.80 Max 1.45 1.30 1.0 1.326 20 1.0 1.0 Unit V V A V mV A A
Control block
Reference VREF voltage voltage VREF Load block stability
Shut down power supply current
Power supply current at DC/DC operation 1 (PFM mode)
IVDD21
48
A
IVDD22
50
80
A
General
Power supply current at DC/DC operation 2 (PWM mode)
IVDD31
3.5
10.0
mA
IVDD32 Power supply current (voltage detection mode) Power-on invalid current
7.0
20.0
mA
IVDD5
15
24
A
IVDD
1000
2000
A
*1 : The minimum value of AVDD = DVDD1 = DVDD2 is the 2.5 V or VOUT setting value + 0.6 V, whichever is higher. *2 : The + leak at the LX pin includes the current of the internal circuit. *3 : Sum of the current flowing into the AVDD, the DVDD1, and the DVDD2 pins. *4 : Current consumption based on 100% ON-duty (High side FET in full ON state). The SW FET gate drive current is not included because the device is in full ON state (no switching operation). Also the load current is not included.
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TEST CIRCUIT FOR MEASURING TYPICAL OPERATING CHARACTERISTICS
VDD SW CTL1/CTL2 R1 1M SW MODE1/MODE2 AVDD DVDD1/DVDD2 C2 4.7 F C3 0.1 F L1 2.2 H MB39C007 VDD VIN
R3-1 20 k R3-2 150 k R4 300 k
R5 510 k R6 100 k
VREF VDET
LX1/LX2 OUT1/OUT2 C1 4.7F
VOUT1/ VOUT2 IOUT
DGND1/DGND2 VREFIN1/VREFIN2 AGND
GND
C6 0.1 F
VOUT = 2.97 x VREFIN
Component R1 R3-1 R3-2 R4 R5 R6 C1 C2 C3 C6 L1
Specification 1M 20 k 150 k 300 k 510 k 100 k 4.7 F 4.7 F 0.1 F 0.1 F 2.2 H
Vendor KOA SSM SSM SSM KOA SSM TDK TDK TDK TDK TDK
Part Number RK73G1JTTD D 1 M RR0816-203-D RR0816-154-D RR0816-304-D RK73G1JTTD D 510 k RR0816-104-D C2012JB1A475K C2012JB1A475K C1608JB1E104K C1608JB1H104K VLF4012AT-2R2M
Remarks
VOUT1/VOUT2 = 2.5 V Setting
For adjusting slow start time
Note : These components are recommended based on the operating tests authorized. TDK : TDK Corporation SSM : SUSUMU Co., Ltd KOA : KOA Corporation
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[2] Output voltage setting The output voltage VOUT (VOUT1 or VOUT2) of this IC is defined by the voltage input to VREFIN (VREFIN1 or VREFIN2) . Supply the voltage for inputting to VREFIN from an external power supply, or set the VREF output by dividing it with resistors. The output voltage when the VREFIN voltage is set by dividing the VREF voltage with resistors is obtained by the following formula. R2 R1 + R2
VOUT = 2.97 x V
REFIN,
VREFIN =
xV
REF
(VREF = 1.30 V)
MB39C007
VREF R1
VREF
VREFIN R2
VREFIN
Note : Refer to " APPLICATION CIRCUIT EXAMPLES" for the an example of this circuit. Although the output voltage is defined according to the dividing ratio of resistance, select the resistance value so that the current flowing through the resistance does not exceed the VREF current rating (1 mA) .
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[3] About conversion efficiency The conversion efficiency can be improved by reducing the loss of the DC/DC converter circuit. The total loss (PLOSS) of the DC/DC converter is roughly divided as follows : PLOSS = PCONT + PSW + PC PCONT PSW PC : Control system circuit loss (The power used for this IC to operate, including the gate driving power for internal SW FETs) : Switching loss (The loss caused during switching of the IC's internal SW FETs) : Continuity loss (The loss caused when currents flow through the IC's internal SW FETs and external circuits )
The IC's control circuit loss (PCONT) is extremely small, less than 100 mW* (with no load). As the IC contains FETs which can switch faster with less power, the continuity loss (PC) is more predominant as the loss during heavy-load operation than the control circuit loss (PCONT) and switching loss (PSW) . Furthermore, the continuity loss (PC) is divided roughly into the loss by internal SW FET ON-resistance and by external inductor series resistance. PC = IOUT2 x (RDC + D x RONP + (1 S D) x RONN) D RONP RONN RDC IOUT : Switching ON-duty cycle ( = VOUT / VIN) : Internal P-ch SW FET ON resistance : Internal N-ch SW FET ON resistance : External inductor series resistance : Load current
The above formula indicates that it is important to reduce RDC as much as possible to improve efficiency by selecting components. * : The loss in the successive operation mode. This IC suppresses the loss in order to execute the PFM operation in the low load mode (less than 100 A in no load mode). Mode is changed by the current peak value IPK which flows into switching FET. The threshold value is about 30 mA.
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[4] Power dissipation and heat considerations The IC is so efficient that no consideration is required in most cases. However, if the IC is used at a low power supply voltage, heavy load, high output voltage, or high temperature, it requires further consideration for higher efficiency. The internal loss (P) is roughly obtained from the following formula : P = IOUT2 x D RONP RONN IOUT (D x RONP + (1 S D) xR
ONN)
: Switching ON-duty cycle ( = VOUT / VIN) : Internal P-ch SW FET ON resistance : Internal N-ch SW FET ON resistance : Output current
The loss expressed by the above formula is mainly continuity loss. The internal loss includes the switching loss and the control circuit loss as well but they are so small compared to the continuity loss they can be ignored. In this IC with RONP greater than RONN, the larger the on-duty cycle, the greater the loss. When assuming VIN = 3.7 V, Ta = + 70 C, for example, RONP = 0.36 and RONN = 0.30 according to the graph "MOS FET ON resistance vs. Operating ambient temperature". The IC's internal loss P is 123 mW at VOUT = 2.5 V and IOUT = 0.6 A. According to the graph "Power dissipation vs. Operating ambient temperature", the power dissipation at an operating ambient temperature Ta of + 70 C is 300 mW and the internal loss is smaller than the power dissipation.
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[5] XPOR threshold voltage setting [VPORH, VPORL] Set the detection voltage by applying voltage to the VDET pin via an external resistor calculated according to this formula. VPORH = VPORL = R3 + R4 R4 R3 + R4 R4 xV xV
THHPR
THLPR
VTHHPR = 0.600 V VTHLPR = 0.583 V Example for setting detection voltage to 3.7 V R3 = 510 k R4 = 100 k 510 k 510 k + 100 k + 100 k
VPORH = VPORL =
100 k 100 k
x 0.600 = 3.66 = 3.7 [V] : x 0.583 = 3.56 = 3.6 [V] :
MB39C007
VIN
AVDD R3 1M VDET R4 XPOR XPOR
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[6] Transient response Normally, IOUT is suddenly changed while VIN and VOUT are maintained constant, responsiveness including the response time and overshoot/undershoot voltage is checked. As this IC has built-in Error Amp with an optimized design, it shows good transient response characteristics. However, if ringing upon sudden change of the load is high due to the operating conditions, add capacitor C6 (e.g. 0.1 F). (Since this capacitor C6 changes the start time, check the start waveform as well.) This action is not required for DAC input.
MB39C007
VREF R1
VREF
VREFIN R2 C6
VREFIN1/ VREFIN2
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[7] Board layout, design example The board layout needs to be designed to ensure the stable operation of this IC. Follow the procedure below for designing the layout. * Arrange the input capacitor (Cin) as close as possible to both the VDD and GND pins. Make a through-hole (TH) near the pins of this capacitor if the board has planes for power and GND. * Large AC currents flow between this IC and the input capacitor (Cin), output capacitor (Co), and external inductor (L). Group these components as close as possible to this IC to reduce the overall loop area occupied by this group. Also try to mount these components on the same surface and arrange wiring without throughhole wiring. Use thick, short, and straight routes to wire the net (The layout by planes is recommended.). * Arrange a bypass capacitor for AVDD as close as possible to both the ADVV and AGND pins. Make a through-hole (TH) near the pins of this capacitor if the board has planes for power and GND. * The feedback wiring to the OUT should be wired from the voltage output pin closest to the output capacitor (Co). The OUT pin is extremely sensitive and should thus be kept wired away from the LX pin of this IC as far as possible. * If applying voltage to the VREFIN1/VREFIN2 pins through dividing resistors, arrange the resistors so that the wiring can be kept as short as possible. Also arrange them so that the GND pin of VREFIN1/VREFIN2 resistor is close to the IC's AGND pin. Further, provide a GND exclusively for the control line so that the resistor can be connected via a path that does not carry current. If installing a bypass capacitor for the VREFIN, put it close to the VREFIN pin. * If applying voltage to the VDET pin through dividing resistors, arrange the resistors so that the wiring can be kept as short as possible. Also arrange so that the GND pin of the VDET resistor is close to the IC's AGND pin. Further, provide a GND exclusively for the control line so that the resistor can be connected via a path that does not carry current. * Try to make a GND plane on the surface to which this IC will be mounted. For efficient heat dissipation when using the QFN-24 package, FUJITSU MICROELECTRONICS recommends providing a thermal via in the footprint of the thermal pad. Example of arranging IC SW system parts
Co
Co
L
GND
L
VIN
Cin
Cin
VIN
Feedback line
Feedback line
1pin
GND
VIN
AVDD bypass capacitor
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EXAMPLE OF STANDARD OPERATION CHARACTERISTICS
(Shown below is an example of characteristics for connection according to " TEST CIRCUIT FOR MEASURING TYPICAL OPERATING CHARACTERISTICS".) * Characteristics CH1 Conversion efficiency vs. Load current (PFM/PWM mode)
100 VIN = 3.7 V
Conversion efficiency vs. Load current (PFM/PWM mode)
100 VIN = 3.7 V
(%)
90
(%)
VIN = 3.0 V
90 VIN = 3.0 V 80
Conversion efficiency
80
VIN = 4.2 V
70
VIN = 5.0 V Ta = +25C VOUT = 2.5 V MODE = L
Conversion efficiency
70
VIN = 4.2 V Ta = +25C VOUT = 1.2 V MODE = L
60
60
VIN = 5.0 V
50 1 10 100 1000
50
1
10
100
1000
Load current IOUT (mA)
Load current IOUT (mA)
Conversion efficiency vs. Load current (PFM/PWM mode)
100 VIN = 3.7 V
Conversion efficiency vs. Load current (PFM/PWM mode)
100 VIN = 3.7 V
(%)
90
(%) Conversion efficiency
VIN = 3.0 V
90 VIN = 4.2 V
Conversion efficiency
80 VIN = 4.2 V 70 VIN = 5.0 V
Ta = +25C
80
70
VIN = 5.0 V
60
VOUT = 1.8 V
60
Ta = +25C
VOUT = 3.3 V MODE = L
1 10 100 1000
50
1
10
100
1000
50
Load current IOUT (mA)
Load current IOUT (mA) (Continued)
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Conversion efficiency vs. Load current (PWM fixed mode)
100 90 VIN = 3.0 V
Conversion efficiency vs. Load current (PWM fixed mode)
100 90 VIN = 3.7 V
(%)
80 70 VIN = 3.7 V
(%)
80 70 VIN = 3.0 V VIN = 4.2 V
Conversion efficiency
60 50 40 30 20 10 0
1 10
Conversion efficiency
60 50 40 30 20 10
VIN = 4.2 V VIN = 5.0 V Ta = +25C VOUT = 2.5 V MODE = OPEN
100 1000
VIN = 5.0 V
Ta = +25C
VOUT = 1.2 V MODE = OPEN
0
1 10 100 1000
Load current IOUT (mA)
Load current IOUT (mA)
Conversion efficiency vs. Load current (PWM fixed mode)
100 VIN = 3.7 V
Conversion efficiency vs. Load current (PWM fixed mode)
100 90 80 70 60 50 40 30 20 10 0
1 10 100 1000
(%)
80 70 60 50 40 30 20 10 0
1
VIN = 3.0 V
Conversion efficiency
Conversion efficiency
(%)
90
VIN = 3.7 V
VIN = 4.2 V
VIN = 4.2 V VIN = 5.0 V
Ta = +25C
VIN = 5.0 V
Ta = +25C VOUT = 3.3 V MODE = OPEN
VOUT = 1.8 V MODE = OPEN
10
100
1000
Load current IOUT (mA)
Load current IOUT (mA) (Continued)
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MB39C007
Output voltage vs. Input voltage (PFM/PWM mode)
2.60 2.58 Ta = +25C VOUT = 2.5 V MODE = L IOUT = 0 A 2.60 2.58
Output voltage vs. Input voltage (PWM fixed mode)
Ta = +25C VOUT = 2.5 V MODE = OPEN IOUT = 0 A
Output voltage VOUT (V)
Output voltage VOUT (V)
2.56 2.54 2.52 2.50 2.48 2.46 2.44 2.42 2.40 2.0 3.0 4.0
2.56 2.54 2.52 2.50 2.48 2.46 2.44 2.42
IOUT = -100 mA
IOUT = -100 mA
5.0
6.0
2.40
2.0
3.0
4.0
5.0
6.0
Input voltage VIN (V)
Input voltage VIN (V)
Output voltage vs. Load current (PFM/PWM mode)
2.60 2.58 Ta = +25C VIN = 3.7 V VOUT = 2.5 V MODE = L
2.60 2.58
Output voltage vs. Load current (PWM fixed mode)
Ta = +25C
VIN = 3.7 V VOUT = 2.5 V MODE = OPEN
Output voltage VOUT (V)
Output voltage VOUT (V)
800
2.56 2.54 2.52 2.50 2.48 2.46 2.44 2.42 2.40 0 200 400
2.56 2.54 2.52 2.50 2.48 2.46 2.44 2.42
600
2.40 0 200 400 600 800
Load current IOUT (mA)
Load current IOUT (mA)
(Continued)
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Reference voltage vs. Input voltage
1.40 1.38 Ta = +25C VOUT = 2.5 V 1.40 1.38
Reference voltage vs. Operating ambient temperature
VIN = 3.7 V VOUT = 2.5 V IOUT = 0 A
Reference voltage VREF (V)
1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 2.0 3.0 4.0 5.0 6.0
Reference voltage VREF (V)
1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 -50 0
IOUT = 0 A
IOUT = -100 mA
+50
+100
Input voltage VIN (V) Input current vs. Input voltage (PFM/PWM mode)
50 45 40
Operating ambient temperature Ta ( C)
Input current vs. Input voltage (PWM fixed mode)
10 9 8
Input current IIN (A)
Input current IIN (mA)
35 30 25 20 15 10 5 0 2.0 3.0 4.0 5.0 6.0 Ta = +25C VOUT = 2.5 V MODE = L
7 6 5 4 3 2 1 0 Ta = +25C VOUT = 2.5 V MODE = OPEN
2.0
3.0
4.0
5.0
6.0
Input voltage VIN (V)
Input voltage VIN (V) (Continued)
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MB39C007
Input current vs. Operating ambient temperature
(PFM/PWM mode)
50 45 40 35 30 25 20 15 10 5 0 -50 0 +50 +100 VIN = 3.7 V VOUT = 2.5 V MODE = L
Input current vs. Operating ambient temperature (PWM fixed mode)
10 9 8
Input current IIN (mA)
Input current IIN (A)
7 6 5 4 3 2 1 0
-50 0 +50 +100
VIN = 3.7 V VOUT = 2.5 V MODE = OPEN
Operating ambient temperature Ta ( C)
Operating ambient temperature Ta ( C)
Oscillation frequency vs. Power supply voltage
2.4
Oscillation frequency vs. Operating ambient temperature
2.4
Oscillation frequency fOSC (MHz)
Oscillation frequency fOSC (MHz)
2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6
Ta = +25C VOUT = 1.8 V IOUT = -100 mA
2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6
VIN = 3.7 V VOUT = 2.5 V IOUT = -100 mA
2.0
3.0
4.0
5.0
6.0
-50
0
+50
+100
Power supply voltage VIN (V)
Operating ambient temperature Ta ( C)
(Continued)
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MOS FET ON resistor vs. Input voltage
0.6 0.6
P-ch MOS FET ON resistor vs. Operating ambient temperature P-ch MOS FET ON resistor RONP ( )
MOS FET ON resistor RON ( )
0.5 0.4 0.3 0.2 N-ch 0.1 Ta = +25C 0 P-ch
0.5 0.4 0.3 0.2 0.1 0
VIN = 3.7 V
VIN = 5.5 V
2.0
3.0
4.0
5.0
6.0
-50
0
+50
+100
Input voltage VIN (V)
Operating ambient temperature Ta ( C)
N-ch MOS FET ON resistor vs. Operating ambient temperature
0.6
N-ch MOS FET ON resistor RONN ( )
0.5 VIN = 3.7 V 0.4 0.3 0.2 VIN = 5.5 V 0.1 0 -50
0
+50
+100
Operating ambient temperature Ta ( C)
(Continued)
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27
MB39C007
MODE VTH vs. Input voltage
4.0 3.5 3.0
1.4 1.2
CTL VTH vs. Input voltage
VTHHCT VTHLCT
MODE VTH (V)
VTHMMD
1.0
CTL VTH (V)
2.5 2.0 1.5 1.0 0.5 0.0 2.0 VTHLMD Ta = +25C VOUT = 2.5 V
0.8 0.6 0.4 0.2 0.0 2.0 Ta = +25C VOUT = 2.5 V
VTHHCT : Circuit OFFON VTHLCT : Circuit ON OFF
3.0 4.0 5.0 6.0
3.0
4.0
5.0
6.0
Input voltage VIN (V)
Input voltage VIN (V)
VXPOR vs. Input voltage
6.0 Ta = +25C 5.0
4.0
VXPOR (V)
3.0 VPORL VPORH
2.0
1.0 0.0
2.0
3.0
4.0
5.0
6.0
Input voltage VIN (V)
(Continued)
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MB39C007
(Continued) Power dissipation vs. Operating ambient temperature (with thermal via)
3500
3125
Power dissipation vs. Operating ambient temperature (without thermal via)
3500 3000
3000
Power dissipation PD (mW)
2500 2000 1500 1000 500 0
-50 0 +50
Power dissipation PD (mW)
2500 2000
1563
1250
1500 1000
625
500 0
+85
+100
+85
-50
0
+50
+100
Operating ambient temperature Ta ( C)
Operating ambient temperature Ta ( C)
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MB39C007
* Switching waveform PFM/PWM operation
2 s/div VO1 : 20 mV/div (AC)
1
1
2 s/div VO2 : 20 mV/div (AC)
VLX1 : 2.0 V/div
VLX2 : 2.0 V/div
2
2
lLX1 : 500 mA/div
4
4
lLX2 : 500 mA/div
VIN = 3.7 V, IO1 = S5 mA, V
O1
= 2.5 V, MODE = L ,Ta = +25 C
VIN = 3.7 V, IO2 = S5 mA, V
O2
= 1.8 V, MODE = L ,Ta = +25 C
PWM operation
2 s/div VO1 : 20 mV/div (AC)
1
1
2 s/div VO2 : 20 mV/div(AC)
VLX1 : 2.0 V/div
VLX2 : 2.0 V/div
2
2
lLX1 : 500 mA/div
4
4
lLX2 : 500 mA/div
VIN = 3.7 V, VO1 = 2.5 V, IO1 = S800 mA, MODE = L ,Ta = +25 C
VIN = 3.7 V, VO2 = 1.8 V, IO2 = S800 mA, MODE = L ,Ta = +25 C
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* Output waveforms at sudden load changes 0A S 800 mA
100 s/div VO1 : 200 mV/div
1
100 s/div VO2 : 200 mV/div
1
2
VLX1 : 2.0 V/div
2
VLX2 : 2.0 V/div
S800 mA lO1 : 1 A/div
4
lO2 : 1 A/div
4
S800 mA
0A VIN = 3.7 V, VO1 = 2.5 V, MODE = L ,Ta = +25 C
0A VIN = 3.7 V, VO2 = 1.8 V, MODE = L ,Ta = +25 C
S 20 mA
S 800 mA
100 s/div
100 s/div VO2 : 200 mV/div
1
VO1 : 200 mV/div
1
2
VLX1 : 2.0 V/div
2
VLX2 : 2.0 V/div
800 mA lO1 : 1 A/div
4
4
lO2 : 1 A/div 20 mA
800 mA
20 mA VIN = 3.7 V, VO1 = 2.5 V, MODE = L ,Ta = +25 C
VIN = 3.7 V, VO2 = 1.8 V, MODE = L ,Ta = +25 C
S 100 mA
S 800 mA
100 s/div
VO1 : 200 mV/div
1
100 s/div VO2 : 200 mV/div
1
2
VLX1 : 2.0 V/div
2
VLX2 : 2.0 V/div
lO1 : 1 A/div
4
800 mA 100 mA
4
lO2 : 1 A/div 100 mA
800 mA
VIN = 3.7 V, VO1 = 2.5 V, MODE = L ,Ta = +25 C
VIN = 3.7 V, VO2 = 1.8 V, MODE = L ,Ta = +25 C
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MB39C007
* CTL start-up waveform No load, No VREFIN capacitor
10 s/div
1
10 s/div
3
CTL1 : 5 V/div
CTL2 : 5 V/div
VO1 : 1 V/div
VO2 : 1 V/div
1
2
VLX1 : 5 V/div
2
VLX2 : 5 V/div
3
ILX1 : 1 A/div
4
ILX2 : 1 A/div
4
VIN = 3.7 V, VO1 = 2.5 V, MODE = L, Ta = + 25 C
VIN = 3.7 V, VO2 = 1.8 V, MODE = L, Ta = + 25 C
Maximum load, No VREFIN capacitor
10 s/div
1
10 s/div
3
CTL1 : 5 V/div
CTL2 : 5 V/div
VO1 : 1 V/div
VO2 : 1 V/div
1
2
VLX1 : 5 V/div
2
VLX2 : 5 V/div
3
ILX1 : 1 A/div
4
ILX2 : 1 A/div
4
VIN = 3.7 V, VO1 = 2.5 V, IO1 = S800 mA , MODE = L, Ta = + 25 C
VIN = 3.7 V, VO2 = 1.8 V, IO2 = S800 mA , MODE = L, Ta = + 25 C
(Continued)
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MB39C007
(Continued) No load, VREFIN capacitor = 0.1 F
1 ms/div
1 ms/div
1
1
CTL1 : 5 V/div
CTL2 : 5 V/div
2
VO1 : 1 V/div VLX1 : 5 V/div
2
VO2 : 1 V/div VLX2 : 5 V/div
3
3
ILX1 : 1 A/div
4
4
ILX2 : 1 A/div
VIN = 3.7 V, VO1 = 2.5 V, MODE = L, Ta = + 25 C
VIN = 3.7 V, VO2 = 1.8 V, MODE = L, Ta = + 25 C
Maximum load, VREFIN capacitor = 0.1 F
1 ms/div
1 ms/div
1
1
CTL1 : 5 V/div
CTL2 : 5 V/div
VO1 : 1 V/div
2
VLX1 : 5 V/div
2
3
VO2 : 1 V/div
VLX2 : 5 V/div
3
ILX1 : 1 A/div
4
ILX2 : 1 A/div
4
VIN = 3.7 V, VO1 = 2.5 V, IO1 = S800 mA , MODE = L, Ta = + 25 C
VIN = 3.7 V, VO2 = 1.8 V, IO2 = S800 mA , MODE = L, Ta = + 25 C
* CTL stop waveform Maximum load, VREFIN capacitor
= 0.1 F
10 s/div
10 s/div CTL2 : 5 V/div
1
CTL1 : 5 V/div
1
VO1 : 1 V/div
VO2 : 1 V/div
2
2
VLX1 : 5 V/div
3
VLX2 : 5 V/div
3
ILX1 : 1 A/div
4
ILX2 : 1 A/div
4
VIN = 3.7 V, VO1 = 2.5 V, IO1 = S800 mA , MODE = L, Ta = + 25 C
VIN = 3.7 V, VO2 = 1.8 V, IO2 = S800 mA , MODE = L, Ta = + 25 C
DS04-27246-2E
33
MB39C007
* Current limitation waveform
100 s/div
100 s/div
VO1 : 1 V/div
VO2 : 1 V/div
1
1
1.5 A ILX1 : 1 A/div 600 mA
4
ILX2 : 1 A/div 600 mA
4
1.5 A
VIN = 3.7 V, VO1 = 2.5 V, MODE = OPEN, Ta = +25 C
VIN = 3.7 V, VO2 = 1.8 V, MODE = OPEN, Ta = +25 C
* Voltage detection waveform
1 ms/div
1
VIN : 3 V/div
2
VVDET : 1 V/div
3
VXPOR : 3 V/div
VIN = 3.7 V, CTLP = VIN, Ta = +25 C Pull-up XPOR to VIN at 1 k.
* Waveform of dynamic output voltage transition (VO1 1.8 V
VO1 : 200 mV/div
2.5 V)
10 s/div
2.5 V
1.8 V 1.8 V
1
VVREFIN1 : 200 mV/div
840 mV
3
610 mV
VIN = 3.7 V, lO1 = 800 mA , 576 mA ( 3.125 ) , MODE = L, Ta = +25 C, No VREFIN capacitor
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APPLICATION CIRCUIT EXAMPLES
* APPLICATION CIRCUIT EXAMPLE 1 * An external voltage is input to the reference voltage external input (VREFIN1, VREFIN2) , and the VOUT voltage is set to 2.97 times the VOUT setting gain.
MB39C007 DVDD1 11 12 DGND1 14 15 DVDD2 19 20 DAC1 8 VREFIN1 DGND2 16 17 AVDD 2 CTL2 R8 1M AGND 4 5
C3 4.7 F
VIN
CPU R7 1M
3 CTL1
C4 4.7 F
C5 0.1 F
DAC2
23 VREFIN2 LX1 13
L1 2.2 H
VOUT1 C1 4.7 F
9 MODE1 L = PFM/PWM OPEN = PWM 22 MODE2
OUT1 10
APLI1
L2 2.2 H LX2 18
VOUT2
C2 4.7 F
6 VREF OUT2 21 7 VDET
APLI2
1 CTLP
XPOR 24
VOUT = 2.97 x V
REFIN
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35
MB39C007
* APPLICATION CIRCUIT EXAMPLE 2 * The voltage of VREF pin is input to the reference voltage external input (VREFIN1, VREFIN2) by dividing resistors. The VOUT1 voltage is set to 2.5 V and VOUT2 voltage is set to 1.8 V.
MB39C0007 DVDD1 11 12 DGND1 14 15 DVDD2 19 20 8 VREFIN1 R2 300 k AVDD 5 DGND2 16 17
C3 4.7 F
VIN
CPU R7 1M
3 CTL1
C4 4.7 F
R1 163 k ( 13 k + 150 k )
C5 0.1 F 2 CTL2 R8 1M L1 2.2 H R5 343 k ( 13 k + 330 k ) 23 VREFIN2 R6 300 k 6 VREF LX2 18 C2 4.7 F OUT2 21 APLI2 L2 2.2 H OUT1 10 LX1 13 VOUT1 C1 4.7 F APLI1 AGND 4
VOUT2
9 MODE1 L = PFM/PWM OPEN = PWM 22 MODE2 7 VDET 1 CTLP
XPOR 24 VOUT1 = 2.97 x V VREFIN1 =
REFIN1
R2 xV R1 + R2
REF
(VREF = 1.30 V) VOUT1 = 2.97 x 300 k 163 k + 300 k 300 k 343 k + 300 k x 1.30 V = 2.5 V
VOUT2 = 2.97 x
x 1.30 V = 1.8 V
36
DS04-27246-2E
MB39C007
* APPLICATION CIRCUIT EXAMPLE COMPONENTS LIST Component Item Part Number L1 L2 C1 C2 C3 C4 C5 R1 R2 R5 R6 R7 R8 Inductor Inductor Ceramic capacitor Ceramic capacitor Ceramic capacitor Ceramic capacitor Ceramic capacitor Resistor Resistor Resistor Resistor Resistor Resistor VLF4012AT-2R2M MIPW3226D2R2M VLF4012AT-2R2M MIPW3226D2R2M C2012JB1A475K C2012JB1A475K C2012JB1A475K C2012JB1A475K C1608JB1E104K RK73G1JTTD D 13 k RK73G1JTTD D 150 k RK73G1JTTD D 300 k RK73G1JTTD D 13 k RK73G1JTTD D 330 k RK73G1JTTD D 300 k RK73G1JTTD D 1 M RK73G1JTTD D 1 M
Specification 2.2 H, RDC = 76 m 2.2 H, RDC = 100 m 2.2 H, RDC = 76 m 2.2 H, RDC = 100 m 4.7 F (10 V) 4.7 F (10 V) 4.7 F (10 V) 4.7 F (10 V) 0.1 F (50 V) 13 k 150 k 300 k 13 k 330 k 300 k 1M 1M 0.5% 0.5%
Package SMD SMD SMD SMD 2012 2012 2012 2012 2012 1608 1608 1608 1608 1608 1608 1608 1608
Vendor TDK FDK TDK FDK TDK TDK TDK TDK TDK KOA KOA KOA KOA KOA KOA KOA KOA
TDK : TDK Corporation FDK : FDK Corporation KOA : KOA Corporation
DS04-27246-2E
37
MB39C007
USAGE PRECAUTIONS
1. Do not configure the IC over the maximum ratings
If the lC is used over the maximum ratings, the LSl may be permanently damaged. It is preferable for the device to normally operate within the recommended usage conditions. Usage outside of these conditions adversely affect the reliability of the LSI.
2. Use the devices within recommended operating conditions
The recommended operating conditions are the conditions under which the LSl is guaranteed to operate. The electrical ratings are guaranteed when the device is used within the recommended operating conditions and under the conditions stated for each item.
3. Printed circuit board ground lines should be set up with consideration for common impedance 4. Take appropriate static electricity measures
* * * * Containers for semiconductor materials should have anti-static protection or be made of conductive material. After mounting, printed circuit boards should be stored and shipped in conductive bags or containers. Work platforms, tools, and instruments should be properly grounded. Working personnel should be grounded with resistance of 250 k to 1 M between body and ground.
5. Do not apply negative voltages
The use of negative voltages below S0.3 V may create parasitic transisto rs on LSI lines, which can cause abnormal operation.
ORDERING INFORMATION
Part number MB39C007QN Package 24-pin plastic QFN (LCC-24P-M09) Remarks
RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION
The LSI products of FUJITSU MICROELECTRONICS with "E1" are compliant with RoHS Directive, and has observed the standard of lead, cadmium, mercury, hexavalent chromium, polybrominated biphenyls (PBB) , and polybrominated diphenyl ethers (PBDE). A product whose part number has trailing characters "E1" is RoHS compliant.
38
DS04-27246-2E
MB39C007
MARKING FORMAT (LEAD FREE VERSION)
Lead-free version
X XXXXX
INDEX
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MB39C007
LABELING SAMPLE (LEAD FREE VERSION)
Lead-free mark JEITA logo JEDEC logo
MB123456P - 789 - GE1
(3N) 1MB123456P-789-GE1 1000
G
Pb
(3N)2 1561190005 107210
QC PASS
PCS 1,000 MB123456P - 789 - GE1
2006/03/01
ASSEMBLED IN JAPAN
1/1
MB123456P - 789 - GE1
0605 - Z01A 1000
1561190005
The part number of a lead-free product has the trailing characters "E1".
"ASSEMBLED IN CHINA" is printed on the label of a product assembled in China.
40
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MB39C007
RECOMMENDED MOUNTING CONDITIONS OF MB39C007QN
[FUJITSU MICROELECTRONICS Recommended Mounting Conditions] Item Condition Mounting Method IR (infrared reflow), warm air reflow Mounting times 2 times Before opening Please use it within two years after Storage period From opening to the 2nd manufacture. reflow Storage conditions 5 C to 30 C, 70%RH or less (the lowest possible humidity) [Parameters for Each Mounting Method] IR (infrared reflow)
260 C 255 C
170 C to 190 C
RT
(b)
(c)
(d)
(e)
(a)
(d')
H rank : 260 C Max (a) Temperature Increase gradient (b) Preliminary heating (c) Temperature Increase gradient (d) Actual heating (d') : Average 1 C/s to 4 C/s : Temperature 170 C to 190 C, 60s to 180s : Average 1 C/s to 4 C/s : Temperature 260 C Max; 255 C or more, 10s or less : Temperature 230 C or more, 40s or less or Temperature 225 C or more, 60s or less or Temperature 220 C or more, 80s or less : Natural cooling or forced cooling
(e) Cooling
Note : Temperature : the top of the package body
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MB39C007
EVALUATION BOARD SPECIFICATION
The MB39C007 Evaluation Board provides the proper for evaluating the efficiency and other characteristics of the MB39C007. * Terminal information Symbol Power supply terminal In standard condition 3.1 V to 5.5 V* VIN * : When the VIN/VOUT difference is to be held within 0.6 V or less, such as for devices with a standard output voltage (VOUT1 = 2.5 V) when VIN < 3.1 V, FUJITSU MICROELECTRONICS recommends changing the output capacity (C1, C2) to 10 F. Output terminals (VOUT1: CH1, VOUT2: CH2) Power supply terminal for setting the CTL1, CTL2 and CTLP terminals. Use by connecting with VIN (When SW is mounted). Direct supply terminal of CTL (CTL1 : for CH1, CTL2 : for CH2) CTL1, CTL2 = 0 V to 0.8 V (Typ.) : Shutdown CTL1, CTL2 = 0.95 V (Typ.) to VIN (5 V Max) : Normal operation Direct supply terminal of MODE (CH1 : for MODE1, CH2 : for MODE2) MODE1, MODE2 = 0 V to 0.4 V(Max) : PFM/PWM mode MODE1, MODE2 = OPEN(Remove R1 and R4) : PWM mode Reference voltage output terminal VREF = 1.30 V (Typ.) External reference voltage input terminals (VREFIN1 : for CH1, VREFIN2 : for CH2) When an external reference voltage is supplied, connect it to the terminal for each channel. Voltage input terminal for voltage detection Voltage detection circuit block control terminal CTLP = L : Voltage detection circuit block stop CTLP = H : Normal operation Voltage detection circuit output terminal The N-ch MOS open drain circuit is connected. Pull-up voltage terminal for the XPOR terminal Ground terminal Connect power supply GND to the PGND terminal next to the VIN terminal. Connect output (load) GND to the PGND terminal between the VOUT1 terminal and the VOUT2 terminal. Ground terminal
Functions
VOUT1, VOUT2 VCTL
CTL1, CTL2
MODE1, MODE2
VREF
VREFIN1, VREFIN2
VDET CTLP
XPOR VXPOR
PGND
AGND
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MB39C007
* Startup terminal information Terminal name Condition CTL1 L : Open H : Connect to VIN L : Open H : Connect to VIN L : Open H : Connect to VIN ON/OFF switch for CH1 L : Shutdown H : Normal operation. ON/OFF switch for CH2 L : Shutdown H : Normal operation. ON/OFF switch for the voltage detection block L: Stops the voltage detection circuit H: Normal operation.
Functions
CTL2
CTLP
* Jumper information JP JP1 JP2 JP3 JP6 *
Functions Short-circuited in the layout pattern of the board (normally used shorted). Short-circuited in the layout pattern of the board (normally used shorted). Not mounted Normally used shorted (0 )
Setup and checkup
(1) Setup 1. Connect the CTL1 terminal and the CTL2 terminal to the VIN terminal. 2. Put it into "L" state by connecting the CTLP terminal to the AGND pad. 3. Connect the power supply terminal to the VIN terminal, and the power supply GND terminal to the PGND terminal. Make sure PGND is connected to the PGND terminal next to the VIN terminal. (Example of setting power-supply voltage : 3.7 V) (2) Checkup Supply power to VIN. The IC is operating normally if VOUT1 = 2.5 V (Typ) and VOUT2 = 1.8 V (Typ).
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MB39C007
* Component layout on the evaluation board (Top View)
MB39C007EVB-06Rev. 2.0 VOUT2 PGMD MODE2 C2 L2 M1 VREFIN2 R4 C4 C7 R5 R4-2 C3 C6 R1-1R1-2 C5 R4-1 JP6 OFF R2 R7 R6-2 R6-1 VDET VREF R1 VREFIN1 L1 C1 VIN MODE1 VOUT1
XPOR R3 VXPOR SW1
R9
JP3
CTLP
CTL2
CTL1
AGND
CTL2 R8
44
1 VCTL CTL1 R10 CTLP
4
DS04-27246-2E
MB39C007
* Evaluation board layout (Top View)
Top Side (Layer1)
Inside GND (Layer2)
Inside VIN & GND (Layer3)
Bottom Side (Layer4)
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MB39C007
PACKAGE DIMENSION
24-pin plastic QFN Lead pitch Sealing method 0.50 mm Plastic mold
(LCC-24P-M09)
24-pin plastic QFN (LCC-24P-M09)
4.000.10 (.157.004)
2.700.10 (.106.004)
INDEX AREA
4.000.10 (.157.004)
2.700.10 (.106.004)
0.250.05 (.010.002)
3-R0.20 (3-R.008) 0.50(.020) TYP
0.400.10 (.016.004) 1PIN CORNER (C0.25(C.010))
0.08(.003) 0.00(.000) MIN
C
0.85(.033) MAX 0.20(.008)
2006-2008 FUJITSU MICROELECTRONICS LIMITED C24059S-c-2-3
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/
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MB39C007
MEMO
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