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| NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor (Preliminary) P9006EDG TO-252 Lead-Free D PRODUCT SUMMARY V(BR)DSS -60V RDS(ON) 90m ID -8A G S 1. GATE 2. DRAIN 3. SOURCE ABSOLUTE MAXIMUM RATINGS (TC = 25 C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Power Dissipation 1 SYMBOL VDS VGS LIMITS -60 20 -7 -6 -30 28 18 -55 to 150 275 UNITS V V TC = 25 C TC = 70 C ID IDM A TC = 25 C TC = 70 C PD Tj, Tstg TL W Operating Junction & Storage Temperature Range Lead Temperature ( /16" from case for 10 sec.) 1 C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE Junction-to-Case Junction-to-Ambient 1 2 SYMBOL RJc RJA TYPICAL MAXIMUM 3 75 UNITS C / W C / W Pulse width limited by maximum junction temperature. Duty cycle 1% ELECTRICAL CHARACTERISTICS (TC = 25 C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS STATIC Drain-Source Breakdown Voltage Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Current1 V(BR)DSS VGS(th) IGSS IDSS ID(ON) VGS = 0V, ID = -250A VDS = VGS, ID = -250A VDS = 0V, VGS = 20V VDS = -48V, VGS = 0V VDS = -44V, VGS = 0V, TJ = 125 C VDS = -5V, VGS = -10V -32 -60 -1 -2 -3 250 nA 1 10 A A V LIMITS UNIT MIN TYP MAX OCT-21-2004 1 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor (Preliminary) P9006EDG TO-252 Lead-Free Drain-Source On-State Resistance1 Forward Transconductance1 RDS(ON) gfs VGS = -4.5V, ID = -6A VGS = -10V, ID = -7A VDS = -10V, ID = -7A DYNAMIC 100 70 9 135 90 m S Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge 2 Ciss Coss Crss Qg Qgs Qgd td(on) tr 2 760 VGS = 0V, VDS = -30V, f = 1MHz 90 40 15 VDS = 0.5V(BR)DSS, VGS = -10V, ID = -7A 2.5 3.0 7 VDS = -20V ID -1A, VGS = -10V, RGS = 6 10 19 12 14 20 34 22 nS nC pF Gate-Source Charge2 Gate-Drain Charge 2 2 Turn-On Delay Time2 Rise Time Turn-Off Delay Time Fall Time2 td(off) tf SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 C) Continuous Current Pulsed Current 3 IS ISM VSD trr Qrr IF = IS, VGS = 0V IF = -7 A, dlF/dt = 100A / S 15.5 7.9 -1.3 -2.6 -1 A V nS nC Forward Voltage1 Reverse Recovery Time Reverse Recovery Charge 1 2 Pulse test : Pulse Width 300 sec, Duty Cycle 2 . Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH "P9006EDG", DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name. OCT-21-2004 2 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor (Preliminary) P9006EDG TO-252 Lead-Free TYPICAL PERFORMANCE CHARACTERISTICS Body Diode Forward Voltage Variation with Source Current and Temperature 100 V GS = 0V 10 -Is - Reverse Drain Current(A) 1 T A = 125 C 0.1 25 C -55 C 0.01 0.001 0 0.2 0.6 0.8 1.0 0.4 -VSD - Body Diode Forward Voltage(V) 1.2 1.4 OCT-21-2004 3 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor (Preliminary) P9006EDG TO-252 Lead-Free OCT-21-2004 4 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor (Preliminary) P9006EDG TO-252 Lead-Free TO-252 (DPAK) MECHANICAL DATA mm Dimension Min. A B C D E F G 9.35 2.2 0.45 0.89 0.45 0.03 5.2 Typ. Max. 10.4 2.4 0.6 1.5 0.69 0.23 6.2 H I J K L M N Dimension Min. 0.89 6.35 5.2 0.6 0.5 3.96 4.57 Typ. Max. 2.03 6.80 5.5 1 0.9 5.18 mm A B F C H G L 3 1 K M 2 J I D E OCT-21-2004 5 |
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