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TM
Future Technology Devices International Ltd.
TM
VDIP1
Vinculum VNC1L Prototyping Module
http://www.vinculum.com
Copyright (c) Future Technology Devices International Ltd. 2006-2007
Page
1. I n t r o d u c t i o n a n d F e a t u r es
1.1 Introduction
The VDIP1 module is an MCU to embedded USB host controller development module for the VNC1L I.C. device. The VDIP1 is supplied on a PCB designed to fit into a 24 pin DIP socket, and provides access to the UART, parallel FIFO, and SPI interface pins on the VNC1L device, via its AD and AC bus pins. Not only is it ideal for developing and rapid prototyping of VNC1L designs, but also an attractive quantity discount structure makes this module suitable for incorporation into low and medium volume finished product designs. The Vinculum VNC1L is the first of F.T.D.I.'s Vinculum family of Embedded USB host controller integrated circuit devices. Not only is it able to handle the USB Host Interface, and data transfer functions but owing to the inbuilt MCU and embedded Flash memory, Vinculum can encapsulate the USB device classes as well. When interfacing to mass storage devices such as USB Flash drives, Vinculum also transparently handles the FAT File structure communicating via UART, SPI or parallel FIFO interfaces via a simple to implement command set. Vinculum provides a new cost effective solution for providing USB Host capability into products that previously did not have the hardware resources available. The VNC1L is available in Pb-free (RoHS compliant) compact 48-Lead LQFP package.
1.2 Features
* * * * * * * * * * * * ses F.T.D.I.s VNC1L emedded host controller I.C. device. type socet to interace with peripheral devices econd interace port availale via module pins i reuired. umper selectale T parallel FIF or PI MC interaces. ingle V supply input. uiliary . V / 200 m power output to eternal logic. gmupmvFlhkvART/plllFIFO/I VNC1mpgmmglpROG#RT#bughujump VDIP1 is a P-ree oH complaint development module. VI1mulupplp-lhVulumVAm hmmlvlbllmhVinculum wesite. hm m l vlbl l m h
VDIP1 Vinculum VNC1L Prototyping Module Datasheet Version 0.92
(c) Future Technology Devices Intl Ltd. 2006-2007
Page
2. P i n O u t a n d S i g n a l D e s criptions
2.1 Module Pin Out
D6 1 D7 C0 C1 C2 GN C C4 C # G# V 24
4
12
D D4 D D2 D1 GN D0 1M 1P LD2 LD1
I D FT
12.000
1
V0
Figure 1 - VDIP1 Module Pin ut
VDIP1 Vinculum VNC1L Prototyping Module Datasheet Version 0.92
(c) Future Technology Devices Intl Ltd. 2006-2007
Page
2.2 Pin Signal Descriptions
Tale 1 - VDIP1 module pin descriptions Pin No.
1 2
Name
V0 1
Pin Name on PCB
V0 LD1
Type
PW Input utput
Description
.0 V module supply pin. This pin provides the .0V output on the type socet and also the .V supply to VNC1L via an on-oard . V L.D.. p1vyThphgb the PC. It is also rought out onto this pin which allows or the possiility o ringguluhVI1bFxmplh VI1bughuumplvy could e mounted along side it. p2vyThphgb the PC. It is also rought out onto this pin which allows or the possiility o ringguluhVI1bFxmplh VI1bughuumplvy could e mounted along side it. host / slave port 1 - Data ignal Plus with integrated pull up / pull down resisMulhb27Thpbbughulg with pin to provide a second port i reuired. host / slave port 1 - Data ignal Minus with integrated pull up / pull down Mulhb27Thpbbughu along with pin 4 to provide a second port i reuired. V sae idirectional data / control us D it 0 Module ground supply pin V sae idirectional data / control us D it 1 V sae idirectional data / control us D it 2 V sae idirectional data / control us D it V sae idirectional data / control us D it 4 V sae idirectional data / control us D it V sae idirectional data / control us D it 6 V sae idirectional data / control us D it 7 V sae idirectional data / control us C it 0 V sae idirectional data / control us C it 1 V sae idirectional data / control us C it 2 Module ground supply pin V sae idirectional data / control us C it V sae idirectional data / control us C it 4 V sae idirectional data / control us C it Can e used y an eternal device to reset the VNC1L. This pin can e used in comihROG#hART/plllFIFO/Ipgmm into the VNC1L. ThpumbhhRT#phART/plllFIFO/ IpgmmhVNC1 .V output rom VDIP1s on oard .V L.D..
2
LD2
utput
4
D1P
1P
I/
D1M
1M
I/
6 7 8 9 10 11 12 1 14 1 16 17 18 19 20 21 22
D0 GN D1 D2 D D4 D D6 D7 C0 C1 C2 GN C C4 C RT#
D0 GN D1 D2 D D4 D D6 D7 C0 C1 C2 GN C C4 C R#
I/ PW I/ I/ I/ I/ I/ I/ I/ I/ I/ I/ PW I/ I/ I/ Input
2 24
ROG# V
G# V
Input PW utput
VDIP1 Vinculum VNC1L Prototyping Module Datasheet Version 0.92
(c) Future Technology Devices Intl Ltd. 2006-2007
2.3I/OConfigurationUsingTheJumperPinHeader
Page
ThyjumpphpvllmplguhI/Olbu pins o the VDIP1. This is done y a comination o pulling up or pulling down the VNC1Ls C (pin 46) and AC6(p47)ThlvphVI1mulhmhgu7bl Fgu2-VI1O-bjumppgu
VNC1L-1A
ACBUS5 ACBUS6
46 47
3V3 47k 47k J3 1 2 3
J4 1 2 3
Tale 2 - Port election umper Pins ACBUS6 (VNC1L pin 47)
Pull-p Pull-p Pull-Down Pull-Down
GND
ACBUS5 (VNC1L pin 46)
Pull-p Pull-Down Pull-p Pull-Down
I/O Mode
erial T PI Parallel FIF erial T
Tbl3-lbugup Pin Name No. Pin Name on PCB
D0 D1 D2 D D4 D D6 D7 C0 C1 C2 C C4
Type
Description
Data and Control Bus Configuration Options UART Parallel SPI I/O Port Interface FIFO Slave Interface Interface
6 8 9 10 11 12 1 14 1 16 17 19 20
D0 D1 D2 D D4 D D6 D7 C0 C1 C2 C C4
I/ I/ I/ I/ I/ I/ I/ I/ I/ I/ I/ I/ I/
V sae idirectional data / control us D it 0 V sae idirectional data / control us D it 1 V sae idirectional data / control us D it 2 V sae idirectional data / control us D it V sae idirectional data / control us D it 4 V sae idirectional data / control us D it V sae idirectional data / control us D it 6 V sae idirectional data / control us D it 7 V sae idirectional data / control us C it 0 V sae idirectional data / control us C it 1 V sae idirectional data / control us C it 2 V sae idirectional data / control us C it V sae idirectional data / control us C it 4
TXD XD RT# CT# TR# R# C# RI# TXN#
D0 D1 D2 D D4 D D6 D7 RXF# TX# R# W
CLK DI D C
PortD0 PortD1 PortD2 PortD PortD4 PortD PortD6 PortD7 PortC0 PortC1 PortC2 PortC PortC4
VDIP1 Vinculum VNC1L Prototyping Module Datasheet Version 0.92
(c) Future Technology Devices Intl Ltd. 2006-2007
2.4UARTInterfaceSignalDescriptions
Page
Tale 4 - Data and Control us ignal Mode ptions - T Interace Pin No.
6 8 9 10 11 12 1 14 1
Name
TXD XD RT# CT# TR# R# C# RI# TXN#
Type
utput Input utput Input utput Input Input Input Input
Description
Transmit asynchronous data output eceive asynchronous data input euest To end Control utput / Handshae signal Clear To end Control Input / Handshae signal Data Terminal eady Control utput / Handshae signal Data et eady Control Input / Handshae signal Data Carrier Detect Control Input RgIClIpuWhhRmWkuppblhROMkgRI# low can e used to resume the PC Host controller rom suspend. blTmR485g
VDIP1 Vinculum VNC1L Prototyping Module Datasheet Version 0.92
(c) Future Technology Devices Intl Ltd. 2006-2007
2.5ParallelFIFOInterfaceSignalDescriptionsandTimingDiagrams
Page
Tale - Data and Control us ignal Mode ptions - Parallel FIF Interace Pin No.
6 8 9 10 11 12 1 14 1 16 17 19
Name
D0 D1 D2 D D4 D D6 D7 RXF# TX# R# W
Type
I/ I/ I/ I/ I/ I/ I/ I/ TPT TPT INPT INPT
Description
FIF Data us it 0 FIF Data us it 1 FIF Data us it 2 FIF Data us it FIF Data us it 4 FIF Data us it FIF Data us it 6 FIF Data us it 7 When high do not read data rom the FIF. When low there is data availale in the FIF which can bbybgR#lhhghg When high do not write data into the FIF. When low data can e written into the FIF y stroing W high then low. blhuFIFOby07hlFhhxFIFOby(vlbl)mhvFIFObuhR#gmhghl Writes the data yte on the D0...D7 pins into the transmit FIF uer when W goes rom high to low.
Figure - FIF ead Cycle
T6
RXF#
T1
T5 T2
RD#
T3
T4 Valid Data
D[7...0]
Tale 6 - FIF ead Cycle Timings Time
T1 T2 T T4 T T6
Description
D ctive Pulse Width D to D Pre-Charge Time D ctive to Valid Data* Valid Data Hold Time rom D Inactive* RIvRXF# XF Inactive ter D Cycle
Min
0 0 + T6 20 0 0 80
Max
0 2 -
Unit
ns ns ns ns ns ns
* Load = 0pF
VDIP1 Vinculum VNC1L Prototyping Module Datasheet Version 0.92
(c) Future Technology Devices Intl Ltd. 2006-2007
Page
Figure 4 - FIF Write Cycle
T11
T12
TXE# WR D[7...0]
Tale 7 - FIF Write Cycle Timings Time
T7 T8 T9 T10 T11 T12
T7
T8
T9 Valid Data
T10
Description
W ctive Pulse Width W to D Pre-Charge Time Data etup Time eore W Inactive Data Hold Time rom W Inactive WRIvTX# TXIvAWRCyl
Min
0 0 20 0 80
Max
2 -
Unit
ns ns ns ns ns ns
VDIP1 Vinculum VNC1L Prototyping Module Datasheet Version 0.92
(c) Future Technology Devices Intl Ltd. 2006-2007
2.6SPIInterfaceSignalDescriptionsandTimingDiagrams
Page
Tale 8 - Data and Control us ignal Mode ptions - PI Interace Pin No.
6 8 9 10
Name
CLK DI D C
Type
Input Input utput Input
Description
PI Cloc input 12MHz maimum. PI erial Data Input PI erial Data utput PI Chip elect Input
Figure - PI lave Data ead Cycle
/W DD D7 PICLK PI C PI Data In 1 PI Data ut
tart
D6
D
D4
D
D2
D1
D0
1
0
From tart - PI C must e held high or the entire read cycle and must e taen low or at least one cloc period hmplThbIIhR/Wb-pug`1hllbm the chip. The net it is the address it DD which is used to indicate whether the data register (0) or the status register (1) is read rom. During the PI read cycle a yte o data will start eing output on PI Data ut on the net lkylhbMAhhblkuhhphuI ut should e checed to see i the data read is new data. 0 level here on PI Data ut means that the data read is new data. 1 indicates that the data read is old data and the read cycle should e repeated to get new data. ememer that C must e held low or at least one cloc period eore eing taen high again to continue with the net read or write cycle. Figure 6 - PI lave Data Write Cycle
/W DD D7 PICLK PI C PI Data In PI Data ut 1 0 0
D6
D
D4
D
D2
D1
D0
tart
From tart - PI C must e held high or the entire write cycle and must e taen low or at least one cloc period hmplThbIIhR/Wb-pug`0hllb to the chip. The net it is the address it DD which is used to indicate whether the data register (0) or the status
VDIP1 Vinculum VNC1L Prototyping Module Datasheet Version 0.92 (c) Future Technology Devices Intl Ltd. 2006-2007
tatus
tatus
Page 10
register (1) is written to. During the PI write cycle a yte o data can e input to PI Data In on the net cloc cycle hbMAhhblkhhphuIOuhulb checed to see i the data read was accepted. 0 level on PI Data ut means that the data write was accepted. 1 indicates that the internal uer is ull and the write should e repeated. ememer that C must e held low or at least one cloc period eore eing taen high again to continue with the net read or write cycle. Figure 7 - PI lave Data Timing Diagrams
T1
PICLK
T2
T
PIC / PI DT IN
T6
T4
T
PI DT T
T7
Tale 9 - PI lave Data Timing Time
T1 T2 T T4 T T6 T7
Description
PICLK Period PICLK High PICLK Low Input etup Time Input Hold Time utput Hold Time utput Valid Time
Min
8 20 20 10 10 2 -
Typical
-
Max
20
Unit
ns ns ns ns ns ns ns
Tale 10 - tatus egister (DD = 1) Bit
0 1 2 4 6 7
Description
RXF# TX# RXFIRQ TXIRQ -
VDIP1 Vinculum VNC1L Prototyping Module Datasheet Version 0.92
(c) Future Technology Devices Intl Ltd. 2006-2007
Page 11
3. D i m e n s i o n s
3.1 VDIP1 Board Dimensions
The VDIP1 oard dimensions are shown elow.
4.4mm (1.71")
18.10mm (0.71")
14.6mm (0.7")
2.00mm (0.08") 1.60mm (0.06")
7.20mm (0.28")
1.70mm (0.4") 2.4mm (0.10")
Figure 8 - VDIP1 dimensions top view.
18.10mm (0.71")
7.00mm (0.28")
8.80mm (0.")
4.9mm (0.19")
2.4mm (0.10")
Figure 9 - VDIP1 dimensions side view.
VDIP1 Vinculum VNC1L Prototyping Module Datasheet Version 0.92
(c) Future Technology Devices Intl Ltd. 2006-2007
17.0mm (0.69")
1.24mm (0.60")
21 0 0 .0
FT D I
Page 1
4.V D I P 1 E x t e r n a l C i r c u i t Configuration
4.1AddingaSecondUSBPort
Thxlugughphvyhblgu 10.
5V
Ferrite Bead
USBA Connector
1 2 3 4
+
47pF
5
3V3
+
47pF
GND
V0 V
3V3
12.000
D FT I
USBPort activityLED circuit 330R
LED1
LD1 LD2 1P
G# # C C4 C GN C2 C1 C0 D7 D6
LED1
1M D0 GN D1 D2
GND
D D4 D
GND
Fgu10-Alpgu
VDIP1 Vinculum VNC1L Prototyping Module Datasheet Version 0.92
(c) Future Technology Devices Intl Ltd. 2006-2007
Disclaimer
Copyright (c) Future Technology Devices International Limited , 2006.
Version 0.91 - Initial Datasheet Created ugust 2006 Version 0.92 - Datasheet update March 2007
Page 1
Neither the whole nor any part o the inormation contained in or the product descried in this manual may e adapted or reproduced in any material or electronic orm without the prior written consent o the copyright holder. This product and its documentation are supplied on an as-is asis and no warranty as to their suitaility or any particular purpose is either made or implied. Future Technology Devices International Ltd. will not accept any claim or damages howsoever arising as a result o use or ailure o this product. Your statutory rights are not aected. This product or any variant o it is not intended or use in any medical appliance device or system in which the ailure hpumghblybxpulpljuy Thumpvplmymhmybubjhghu
Contact FTDI
HeadOffice- Future Technology Devices International Ltd. 7 cotland treet GlgG58Q nited Kingdom Tel. : +(44) 141 429 2777 Fa. : +(44) 141 429 278 -Ml(l): sales1@ftdichip.com -Ml(upp):support1@ftdichip.com -Ml(Glqu):admin1@ftdichip.com RegionalSalesOffices- Future Technology Devices International Ltd. (Taiwan) 4F No 18- 6MyuR Neihu District Taipei 114 Taiwan .o.C. Tel.: +886 2 8791 70 Fa: +886 2 8791 76 -Ml(l):tw.sales1@ftdichip.com -Ml(upp):tw.support@ftdichip.com -Ml(Glqu):tw.admin@ftdichip.com FTDI company wesite L : http://www.ftdichip.com Vinculum product wesite L : http://www.vinculum.com Future Technology Devices International Ltd. (USA) 7235vgky uite 600 Hillsoro 97124-80 Tel.: +1 (0) 47-0988 Fa: +1 (0) 47-0987 -Ml(l):us.sales@ftdichip.com -Ml(upp):us.support@ftdichip.com -Ml(Glqu):us.admin@ftdichip.com
VDIP1 Vinculum VNC1L Prototyping Module Datasheet Version 0.92
(c) Future Technology Devices Intl Ltd. 2006-2007

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