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NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor ( Preliminary) P01N02LJA J-LEAD8 D PRODUCT SUMMARY V(BR)DSS 25V RDS(ON) 70m ID 1.2A 4 :GATE 5,6,7,8 :DRAIN 1,2,3 :SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Power Dissipation 1 SYMBOL VGS LIMITS 15 1.2 1.0 12 0.6 0.5 -55 to 150 275 UNITS V TC = 25 C TC = 100 C TC = 25 C TC = 100 C ID IDM PD Tj, Tstg TL A W Operating Junction & Storage Temperature Range Lead Temperature ( /16" from case for 10 sec.) THERMAL RESISTANCE RATINGS THERMAL RESISTANCE Junction-to-Case Junction-to-Ambient 1 1 C SYMBOL RJC RJA TYPICAL MAXIMUM 65 230 UNITS C / W Pulse width limited by maximum junction temperature. ELECTRICAL CHARACTERISTICS (TC = 25 C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS STATIC Drain-Source Breakdown Voltage Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Current1 Drain-Source On-State Resistance1 Forward Transconductance1 V(BR)DSS VGS(th) IGSS IDSS ID(ON) RDS(ON) gfs VGS = 0V, ID = 250 A VDS = VGS, ID = 250 A VDS = 0V, VGS = 15V VDS = 20V, VGS = 0V VDS = 20V, VGS = 0V, TJ = 125 C VDS = 10V, VGS = 10V VGS = 7V, ID = 1.2A VGS = 10V, ID = 1.2A VDS = 20V, ID = 1.2A 1.2 120 70 16 180 120 25 0.7 1.0 2.5 250 25 250 V nA A A m S LIMITS UNIT MIN TYP MAX 1 AUG-30-2002 NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor ( Preliminary) P01N02LJA J-LEAD8 DYNAMIC Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge 2 2 Ciss Coss Crss Qg Qgs Qgd 2 120 VGS = 0V, VDS = 15V, f = 1MHz 100 85 11 VDS = 0.5V(BR)DSS, VGS = 10V, ID = 1A 3.0 5.8 7 VDS = 15V, RL = 1 ID 1A, VGS = 10V, RGS = 50 20 13 19 nS nC pF Gate-Source Charge Gate-Drain Charge Rise Time2 2 Turn-On Delay Time td(on) tr td(off) tf Turn-Off Delay Time2 Fall Time2 SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 C) Continuous Current Pulsed Current3 Forward Voltage1 Reverse Recovery Time Reverse Recovery Charge 1 2 IS ISM VSD trr Qrr IF = IS, VGS = 0V IF = IS, dlF/dt = 100A / S 1.2 12 1.3 70 0.22 A V nS C Pulse test : Pulse Width 300 sec, Duty Cycle 2. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH "102B" 2 AUG-30-2002 NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor ( Preliminary) P01N02LJA J-LEAD8 J-LEAD8 MECHANICAL DATA mm Min. Typ. 0.50 0.15 1.65 2.00 1.80 0.70 2.20 2.00 0.90 0.3 1.85 2.40 2.20 1.00 1.10 Max. mm Min. 0.10 0.048 0 0.35 1.80 0.45 2.10 0.1 0.55 2.40 Typ. Max. 0.20 Dimension A B C D E F G Dimension H I J K L M N 3 AUG-30-2002 |
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