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PEDL9090-02
Semiconductor ML9090-01,-02
LCD Driver with Key Scanner and RAM
This version: Jan. 2000 Previous version: Nov. 1998
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GENERAL DESCRIPTION
The ML9090-01 and ML9090-02 are LCD drivers that contain internal RAM and a key scan function. They are best suited for car audio displays. Since 1-bit data of the display RAM corresponds to the light-on or light-off of 1-dot of the LCD panel (a bit map system), a flexible display is possible. A single chip can implement a graphic display system of a maximum of 80 16 dots (80 8 dots for the ML9090-01, 80 16 dots for the ML9090-02) and an arbitrator display system of 80 2 dots. Since containing voltage multipliers, the ML9090-01 and ML9090-02 require no power supply circuit to drive the LCD. Since the internal 5 5 scan circuit has eliminated the needs of key scanning by the CPU, the ports of the CPU can be efficiently used.
FEATURES
* Logic voltage: VDD 2.7 to 5.5 V * LCD drive voltage: VBI 6 to 16 V (positive voltage) * 80 segment outputs,10 common outputs for ML9090-01 and 18 common outputs for ML909002 * Built-in bit-mapped RAM (ML9090-01: 80 10 = 800 bits, ML9090-02: 80 18 = 1440 bits) * 4-pin serial interface with CPU: CS, CP, DI/O, KREQ * Built-in LCD drive bias resistors * Built-in voltage doubler and tripler circuits * Built-in 5 5 key scanner * Port A output : 1 pin, output current: -15mA: (may be used for LED driving) * Port B output : 8 pins Output current (available for the ML9090-01 only) -2mA : 5 pins -15mA : 3 pins * Temperature range: -40 to +85C * Package: 128-pin plastic QFP (QFP128-P-1420-0.50-K) (Product name: ML9090-01GA) (Product name: ML9090-02GA)
Model Display duty No. of display lines No. of port B outputs 1/8 8 8 ML9090-01 1/9 9 8 1/10 10 8 1/16 16 -- ML9090-02 1/17 17 -- 1/18 18 --
APPLICATION
* Car audio
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PEDL9090-02 Semiconductor ML9090-01,-02
BLOCK DIAGRAM
ML9090-01
COM1 VIN VC1 VC2 VS1 VS2 DT VOLTAGE DOUBLER/ TRIPLER
COM10 PB0
PB7
SEG1
SEG80
10-OUT COMMON DRIVER SHIFT REGISTER
8-PORT 80-OUT SEGMENT DRIVER DRIVER
DATA LATCH
LINE ADDRESS DECODER
V2 V3B
LCD BIAS
Y ADDRESS COUNTER
DIVIDING V3A CIRCUIT
Y ADDRESS DECODER
Y ADDRESS REGISER
VOLTAGE
DISPLAY DATA RAM 80 10 BITS
INPUT OUTPUT INTERFACE
CP DI/O
CONTROL REGISTER
CS
I/O BUFFER
X ADDRESS DECODER
X ADDRESS COUNTER TIMING GENERATOR X ADDRESS REGISTER
OSC1 OSC2
OSCILLATION CIRCUIT
1 PORT DRIVER RESET TEST VDD VSS PA0
55 KEY SCANNER
CO C1 C2 C3 C4
R0 R1 R2 R3 R4 KREQ
DISPLAY LINE COUNTER
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PEDL9090-02 Semiconductor ML9090-01,-02
BLOCK DIAGRAM
ML9090-02
COM1 VIN VC1 VC2 VS1 VS2 DT VOLTAGE DOUBLER/ TRIPLER
COM18
SEG1
SEG80
18-OUT COMMON DRIVER
80-OUT SEGMENT DRIVER
SHIFT REGISTER V2 V3B DIVIDING V3A CIRCUIT LCD BIAS
DATA LATCH
LINE ADDRESS DECODER
Y ADDRESS COUNTER
Y ADDRESS DECODER
Y ADDRESS REGISER
VOLTAGE
DISPLAY DATA RAM 80 18 BITS
INPUT OUTPUT INTERFACE
CP DI/O
CONTROL REGISTER
CS
I/O BUFFER
X ADDRESS DECODER
X ADDRESS COUNTER TIMING GENERATOR X ADDRESS REGISTER
OSC1 OSC2
OSCILLATION CIRCUIT
1 PORT DRIVER RESET TEST VDD VSS PA0
55 KEY SCANNER
CO C1 C2 C3 C4
R0 R1 R2 R3 R4 KREQ
DISPLAY LINE COUNTER
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PEDL9090-02 Semiconductor ML9090-01,-02
PIN CONFIGURATION (TOP VIEW)
ML9090-01
SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VDD OSC2 OSC1 DT V2 V3B V3A VIN VC1 VC2 VS1 VS2 VSS TEST RESET KREQ DI/O CS CP C0 C1 C2 C3 C4 R0 R1 R2 R3 R4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9
SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
128-Pin Plastic QFP
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PEDL9090-02 Semiconductor ML9090-01,-02
PIN CONFIGURATION (TOP VIEW)
ML9090-02
SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 PA0
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VDD OSC2 OSC1 DT V2 V3B V3A VIN VC1 VC2 VS1 VS2 VSS TEST RESET KREQ DI/O CS CP C0 C1 C2 C3 C4 R0 R1 R2 R3 R4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9
SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
128-Pin Plastic QFP
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PEDL9090-02 Semiconductor ML9090-01,-02
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Bias Voltage Voltage Multiplier Reference Voltage Input Voltage Symbol VDD VBI VIN Condition Ta = 25C Ta = 25C Ta = 25C *1 Ta = 25C *2 Ta = 25C Ta = 25C Ta = 25C Ta = 85C -- Rating -0.3 to +7.0 -0.3 to +18.0 -0.3 to +9.84 -0.3 to +7.36 -0.3 to VDD+0.3 -20 -3 190 -55 to +150 Unit Applicable Pins V V V VDD VC1, VC2, VS1, VS2, V2, V3A, V3B VIN CS, CP, DI/O, VI V mA mA mW C OSC1, RESET, DT, TEST, C0 to C4 Output Current Power Dissipation Storage Temperature IO PD Tstg PA0, PB5 to PB7 PB0 to PB4 -- --
*1: *2:
When Ta = 25C and the voltage doubler is used, use voltage multiplier reference voltage VIN values within a range that does not exceed the maximum bias voltage. When Ta = 25C and the voltage tripler is used, use voltage multiplier reference voltage VIN values within a range that does not exceed the maximum bias voltage.
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Bias Voltage Voltage Multiplier Reference Voltage Operating Frequency Operating Temperature Symbol VDD VBI VIN Fop Top Condition -- *1 *2 *3 R = 56kW 2% -- Range 2.7 to 5.5 6.0 to 16.0 3.0 to 8.8 2.0 to 6.6 480 to 1200 -40 to +85 Unit Applicable Pins V V V kHz C VDD VS2 VIN OSC1 --
*1: *2: *3:
For the bias voltage, VS2 is the maximum voltage potential and VSS is the minimum voltage potential. VS2 > V2 V3A, V3B > VSS. When the voltage doubler is used, use voltage multiplier reference voltage VIN values within a range that does not exceed the maximum bias voltage. When the voltage tripler is used, use voltage multiplier reference voltage VIN values within a range that does not exceed the maximum bias voltage.
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PEDL9090-02 Semiconductor ML9090-01,-02
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 to 5.5 V, VBI = 6 to 16 V, Ta = -40 to +85C) Parameter "H" Input Voltage 1 "H" Input Voltage 2 "H" Input Voltage 3 "H" Input Voltage 4 "L" Input Voltage 1 "L" Input Voltage 2 "L" Input Voltage 3 "L" Input Voltage 4 Hysteresis Voltage 1 Hysteresis Voltage 2 Hysteresis Voltage 3 "H" Input Current 1 "H" Input Current 2 "H" Input Current 3 "H" Input Current 4 "L" Input Current 1 "L" Input Current 2 "L" Input Current 3 "L" Input Current 4 "H" Output Voltage 1 "H" Output Voltage 2 "H" Output Voltage 3 "H" Output Voltage 4 "H" Output Voltage 5 "L" Output Voltage 1 "L" Output Voltage 2 "L" Output Voltage 3 "L" Output Voltage 4 LCD Driving Bias Resistance Segment Output Voltage 1 (1/4 bias) Symbol VIH1 VIH2 VIH3 VIH4 VIL1 VIL2 VIL3 VIL4 VHIS1 VHIS2 VHIS3 IIH1 IIH2 IIH3 IIH4 IIL1 IIL2 IIL3 IIL4 VOH1 VOH2 VOH3 VOH4 VOH5 VOL1 VOL2 VOL3 VOL4 LBR VOS0 VOS1 VOS2 VOS3 Condition -- -- -- -- -- -- -- -- VDD = 5 V VDD = 5 V VDD = 5 V VI = VDD VI = VDD VI = VDD VI = VDD VDD = 5 V, VI = 0 V VDD = 5 V, VI = 0 V VI = 0 V VI = 0 V Min. 0.85VDD 0.85VDD 0.85VDD 0.8VDD 0 0 0 0 -- -- -- -- -- -- -- -0.02 -0.18 -- -- Typ. -- -- -- -- -- -- -- -- 0.3 0.4 0.4 -- -- -- -- -0.05 -0.45 -- -- -- -- -- -- -- -- -- -- -- 9 -- -- -- -- Max. VDD VDD VDD VDD 0.15VDD 0.15VDD 0.15VDD 0.2VDD -- -- -- 10 10 10 1 -0.1 -0.9 -10 -1 -- -- -- -- -- 0.4 0.1VDD 0.4 0.7 13 -- 2/4VS2+0.6 2/4VS2+0.6 VSS+0.6 Unit Applicable Pins V V V V V V V V V V V mA mA mA mA mA mA mA mA V V V V V V V V V kW V V V V SEG1 to SEG80 OSC1 RESET CP CS, DI/O, C0 to C4 OSC1 RESET CP CS, DI/O, C0 to C4 OSC1 CP RESET RESET C0 to C4 DI/O OSC1, CS, CP, DT, TEST RESET C0 to C4 DI/O OSC1, CS, CP, DT, TEST DI/O, KREQ OSC2 PA0, PB5 to PB7 PB0 to PB4 R0 to R4 DI/O, KREQ OSC2 PA0, PB0 to PB7 R0 to R4 V2 to V3A
IO = -0.4mA VDD-0.4 IO = -40mA IO = -2mA IO = 0.4mA IO = 40mA IO = 1mA IO = 1.8mA -- IO = -10mA 0.9VDD VDD-1.2 -- -- -- -- 6.3 VS2-0.6 IO = -15mA VDD-1.7 IO = -50mA VDD-2.0
IO = 10mA 2/4VS2-0.6 IO = 10mA 2/4VS2-0.6 IO = +10mA --
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PEDL9090-02 Semiconductor ML9090-01,-02
(VDD = 2.7 to 5.5 V, VBI = 6 to 16 V, Ta = -40 to +85C) Parameter Common Output Voltage 1 (1/4 bias) Symbol VOC0 VOC1 VOC2 VOC3 VOS0 Segment Output Voltage 2 (1/5 bias) VOS1 VOS2 VOS3 VOC0 Common Output Voltage 2 (1/5 bias) VOC1 VOC2 VOC3 Voltage Multiplier Voltage 1 Voltage Multiplier Voltage 2 Supply Current 1 Supply Current 2 VDB VTR IDD1 IDD2 Condition IO = -10mA Min. VS2-0.3 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- 3/4VS2+0.3 1/4VS2+0.3 VSS+0.3 -- 3/5VS2+0.6 2/5VS2+0.6 VSS+0.6 -- 4/5VS2+0.3 1/5VS2+0.3 VSS+0.3 -- -- 0.95 0.7 Unit Applicable Pins V V V V V V V V V V V V V V mA mA VS1 VS2 VDD VDD C0M1 to C0M18 SEG1 to SEG80 C0M1 to C0M18
IO = 10mA 3/4VS2-0.3 IO = 10mA 1/4VS2-0.3 IO = +10mA IO = -10mA -- VS2-0.6
IO = 10mA 3/5VS2-0.6 IO = 10mA 2/5VS2-0.6 IO = +10mA IO = -10mA -- VS2-0.3
IO = 10mA 4/5VS2-0.3 IO = 10mA 1/5VS2-0.3 IO = +10mA = 740KHz *1 = 740KHz *1 R = 56KW2% *1 External clock = 740KHz *1 -- -0.5 -1.0 -- -- External clock VIN1.83 External clock VIN2.46
*1:
Refer to Measuring Circuits
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PEDL9090-02 Semiconductor Measuring Circuits ML9090-01,-02
Voltage multiplier voltage 1 When voltage doubler is used. 2.7-5.5V 2.5-8V 4.7mF - VDD VIN VC1 VC2 VS1 VS2 100mA DT OSC1 V2 OPEN V3B V3A TEST f = 740kHz VSS PAO OSC2 OPEN OPEN VDR
V
Voltage multiplier voltage 2 When voltage tripler is used. 2.7-5.5V 2.5-7V OPEN VDD SEG1 - SEG80 COM1 - COM10
OPEN SEG1 - SEG80 COM1 - COM10
+ 4.7mF + VDB
V
VIN VC1 - 4.7mF + VC2 4.7mF VS1 + 4.7mF VS2 +
VSS PAO OSC2 OPEN OPEN
RESET CS *1 CP COM11 - COM18/ DI/O PB0 - PB7 C0 - C4 R0 - R4 OPEN
VDD
OSC1 100mA VDD DT f = 740kHz TEST OPEN V2 V3B V3A RESET VDD CS *1 CP COM11 - COM18/ DI/O PB0 - PB7 C0 - C4 R0 - R4 OPEN
Supply current 1 IDDI A VDD - VIN VC1 VSS PAO OSC2 OSC1 VDD DT TEST OPEN V2 V3B V3A RESET CS *1 CP COM11 - COM18/ DI/O PB0 - PB7 C0 - C4 R0 - R4 OPEN OPEN R = 56kW 2% OPEN SEG1 - SEG80 COM1 - COM10 5.5V 6.0V 4.7mF IDD2 A VDD - VIN VC1
Supply current 2 OPEN SEG1 - SEG80 COM1 - COM10
5.5V 6.0V
4.7mF
+ VC2 4.7mF V S1 + 4.7mF V S2 +
+ VC2 4.7mF V S1 + 4.7mF V S2 +
VSS PAO OSC2 OSC1 OPEN OPEN
VDD
VDD DT f = 740kHz TEST OPEN V2 V3B V3A RESET VDD CS *1 CP COM11 - COM18/ DI/O PB0 - PB7 C0 - C4 R0 - R4 OPEN
*1: PB0 - PB7 for ML9090-01, and COM11 - COM18 for ML9090-02
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PEDL9090-02 Semiconductor Switching Characteristics
(VDD = 2.7 to 5.5 V, VBI = 6 to 16 V, Ta = -40 to +85C) Parameter CP Clock Cycle Time CP "H" Pulse Width CP "L" Pulse Width CS "H" Pulse Width CP Clock Rise/fall Time CS Setup Time CS Hold Time DI/O Setup Time DI/O Hold Time DI/O Output Delay Time DI/O Output OFF Delay Time RESET Pulse Width External Clock Cycle Time External Clock "H" Pulse Width External Clock "L" Pulse Width External Clock Rise/fall Time Symbol tSYS tWH tWL tWCH tr, tf tCSU tCHD tDSU tDHD tDOD tDOFF tWRE tSES tWEH tWEL trE, tfE Condition -- -- -- -- -- -- -- -- -- CL = 50pF CL = 50pF -- -- -- -- -- Min 1000 400 400 200 -- 60 290 100 15 -- -- 2 833 316 316 -- -- -- -- 100 Max -- -- -- -- 100 -- -- -- -- 200 200 Unit ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns
ML9090-01,-02
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PEDL9090-02 Semiconductor Clock synchronous serial interface timing diagrams Clock synchronous serial interface input timing
CS VIL4 tCSU tSYS tr tWH tr CP VIH3 VIL3 tDSU DI-O VIH4 VIL4
VIH3 VIH3
ML9090-01,-02
tWCH VIH4 tCHD VIL4 VIH4
tWL VIH3 VIL3 VIH3
VIL3 tDHD VIH4 VIL4
Clock synchronous serial interface input/output timing
CS VIH4 tCSU tSYS tr tWH tr tWL 1 Clock CP VIH3 VIL3 tDSU DI-O VIH4 VIH4 VIL4 VIL4 Hiz VOH1 VOL1
VIH3 VIH3
tWCH VIH4 VIL4
VIL4
tCHD
8 Clock VIH3 VIL3 VIL3 tDOD tDOFF VOH1 VOL1 VIH3 VIL3 tDHD
Reset timing
tWRE RESET VIL2 VIL2
External clock
trE tWEH trE tWEL OSC1
VIL1
VIH1 VIH1
VIL1
VIL1
tSES
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PEDL9090-02 Semiconductor ML9090-01,-02
FUNCTIONAL DESCRIPTIONS
Pin Functional Descriptions
No.of pins 1 1 1 1 1 1 1
Function
Symbol CS
Pin name Chip Select Clock Pulse Data I/O Key Request OSC1 OSC2 RESET Doubler Tripler Select TEST Column Input Row Output Port Output Port Output Seg Output Com Output Com Output VDD VSS VIN VC1, VC2 VS1 VS2 V2, V3A, V3B
Type I I I/O O I O I
Description Chip select signal input pin Shift clock signal input pin. This pin is connected to an internal Schmitt circuit Serial data signal I/O pin Key request signal output pin Connect external resistors. Initial settings can be established by pulling
CPU interface
CP DI/O KREQ OSC1 OSC2 RESET
Oscillation
the reset input to a "L" level. This pin is connected to an internal Schmitt circuit. Input pin for selecting the voltage doubler or voltage tripler. Test input pin. This pin is connected to the VSS pin. Input pins that detect status of key switches Key switch scan signal pins Port A output Port B outputs (for ML9090-01) Outputs for LCD segment drivers Outputs for LCD common drivers (for ML9090-01) Outputs for LCD common drivers (for ML9090-02) Logic power supply pin GND pin Voltage multiplier reference voltage power supply pin Capacitor connection pins for voltage multiplier Voltage doubler output pin Voltage tripler output pin LCD bias pins
Control signals
DT TEST
I I I O O O O O O -- -- -- -- -- -- --
1 1 5 5 1 8 80 10 18 1 1 1 2 1 1 3
Key scan signals Port outputs
C0 to C4 R0 to R4 PA0 PB0 to PB7 SEG1 to SEG80 COM1 to
LCD driver outputs
COM10 COM1 to COM18 VDD VSS VIN
Power supply
VC1, VC2 VS1 VS2 V2, V3A, V3B
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PEDL9090-02 Semiconductor Register List
RS R/W 0 1 0 0 0 0 0 0 1 1/0 0 0 0 0 0 0 Register number 3 0 0 0 0 0 0 1 1 2 0 0 0 0 1 1 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 1 0 1 0 1 Register symbol KR DRAM XAD YAD PTA PTB FCR1 FCR2 Register name Key scan register X address register Y address register Port register A Port register B Control register 1 Control register 2 Data bits 7 6 D6 -- -- -- 5 D5 -- -- -- 4 D4 -- Y4 -- 3 S3 D3 X3 Y3 -- 2 S2 D2 X2 Y2 -- 1 S1 D1 X1 Y1 0 S0 D0 X0 Y0 ST2 ST1 ST0 S4 -- -- --
ML9090-01,-02
Display data register D7
-- PA0
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 INC WLS KT SHL -- -- -- T4 T3 T2 -- DTY1 DTY0 T1 -- DISP
RS Register select bit R/W Read/write select bit
1: RAM 1: Read
0: Register 0: Write
ST0 to ST2 : Scan status S0 to S4 : Key scan data D0 to D7 : Display data and RAM read data X0 to X3 : X address Y0 to Y4 : Y address PA0 : Port A data PB0 to PB7 : Port B data (ML9090-01 only) INC : Address increment 1: X direction, 0: Y direction WLS : Word length select 1: 6 bits, 0: 8 bits KT : Key scan cycle select 1: 10 ms, 0: 5 ms DTY0, DTY1: Display duty select (1/8, 1/9, 1/10) (ML9090-01) (1/16, 1/17, 1/18) (ML9090-02) SHL : Common driver shift direction select bit 1: COM10AECOM1, 0 : COM1AECOM10 (ML9090-01) 1: COM18AECOM1, 0 : COM1AECOM18 (ML9090-02) DISP : Display ON/OFF select 1: Display ON, 0: Display OFF T1 to T4 : Write "0" -- : Don't care
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PEDL9090-02 Semiconductor Pin Functional Descriptions * CS Chip select input pin. An "L" level selects the chip, and an "H" level does not select the chip. During the "L" level, internal registers can be accessed. * CP Clock input pin for serial interface data I/O. An internal Schmitt circuit is connected to this pin. Data input to the DI/O pin is synchronized to the rising edge of the clock. Output from the DI/ O pin is synchronized to the falling edge of the clock. * DI/O Serial interface data I/O pin. This pin is in the output state only during the interval beginning when key scan data read or RAM read commands (to be described later) are written (after the rising edge of the 8th CP clock during start byte setup, the CPU changes from output to input and the DI/O output interval begins at the CP falling edge) until the CS signal rises. At all other times this pin is in the input state. (When reset, the input state is set.) The relation between data level of this pin and operation is listed below.
Data level "H" "L" LCD display Light ON Light OFF Port "H" "L" Key status ON OFF
ML9090-01,-02
* KREQ Key scan read READY signal output pin. Two scan cycles after a key switch is switched ON, this pin goes to an "H" level. When all key switches are OFF, this pin returns to an "L" level. Begin the key scan read operation after this pin goes to an "H" level. * OSC1 Input pin for RC oscillation. An oscillation circuit is formed by connecting a resistor (R) of 56kW 2% to this pin and the OSC2 pin. If an external master oscillation clock is to be input, input the master oscillation clock to this pin.
OSC1 R = 56kW 2% R OSC2
* OSC2 Input pin for RC oscillation. An oscillation circuit is formed by connecting a resistor (R) of 56kW 2% to this pin and the OSC1 pin. If an external master oscillation clock is to be input, leave this pin unconnected (open).
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PEDL9090-02 Semiconductor ML9090-01,-02
* RESET Reset signal input pin. The initial state can be set by pulling this pin to an "L" level. Refer to the "Pin and Register States in Response to Reset Input" page for the initial states of each register and display. An internal pull-up resistor is connected to this pin. An external capacitor is connected for poweron-reset operation. * TEST Test signal input pin. This pin is used for testing by Oki. Connect this pin to VSS. When a different connection is made, proper operation cannot be guaranteed. * R0 to R4 Key switch scan signal output pins. During the scan operation, "L" level signals are output in the order of R0, R1, ...R4. (Refer to the page entitled "Key scan" for further details.) * C0 to C4 Input pins that detect the key switch status. Internal pull-up resistors are connected to these pins. Assemble a key matrix between these pins and the R0 to R4 pins. * PA0 General-purpose port A output pin. Because this pin can output a current of 15mA, it is best suited as an LED driver. If this pin is used as an LED driver, insert an external current limiting resistor in series with the LED. * PB0 to PB7 General-purpose port B output pins. Each of the PB5 to PB7 pins has the same driving capability as the PA0 pin. These pins are only applicable to the ML9090-01. * SEG1 to SEG80 Segment signal output pins for LCD driving. Leave unused pins unconnected (open). * COM1 to COM10 Common signal output pins for LCD driving. Leave unused pins unconnected (open). * COM1 to COM18 Common signal output pins for LCD driving. Leave unused pins unconnected (open). These pins are applicable to the ML9090-02. * VDD Logic power supply connection pin. * VSS Power supply GND connection pin.
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PEDL9090-02 Semiconductor ML9090-01,-02
* DT This pin selects the voltage multiplier circuit. If this pin is connected to the VSS pin, the voltage doubler circuit is selected. If this pin is connected to the VDD pin, the voltage tripler circuit is selected. Do not change the value of the setting after power is turned on. * VC1, VC2 Capacitor connection pins for the voltage multiplier. Connect a 4.7mF capacitor between the VC1 and VC2 pins. If an electrolytic capacitor is used, connect the (+) side to pin VC2. * VS1 Voltage doubler voltage output pin. This pin outputs the doubled voltage that has been input to VIN. To increase stability of the power supply, connect a 4.7mF capacitor between this pin and VSS. When using the doubled voltage, connect this pin and VS2. * VS2 Voltage multiplier voltage output pin. Voltage multiplied by the factor specified by the DT pin setting is output from this pin. When the voltage tripler is used, to increase stability of the power supply, connect a 4.7mF capacitor between this pin and VSS. When using the voltage doubler, connect this pin and VS1. * VIN Voltage multiplier voltage input pin. The doubled or tripled voltage input to this pin is output from VS2. * V2, V3A, V3B LCD bias pins for segment drivers. These pins are connected to internal bias dividing resistors. When using the ML9090-01 (at 1/4 bias), connect V2 and V3A pins, and leave V3B unconnected (open). When using the ML9090-02 (at 1/5 bias), connect V3A and V3B pins, and leave V2 unconnected (open).
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PEDL9090-02 Semiconductor Clock Synchronous Serial Transfer Example (WRITE)
Transfer start CS Transfer complete
ML9090-01,-02
1 CP
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
DI/O
"1"
"1" RS R/W D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Register bits 1st byte Start byte Instruction
Clock Synchronous Serial Continuous Data Transfer Example (WRITE)
Transfer start CS Transfer complete
1 CP
2
7
8
9
10 15 16 17 18 23 24 41 42 47 48
DI/O
Start byte
Instruction 1
Instruction 2
Instruction 5
Clock Synchronous Serial Continuous Data Transfer Example (READ)
Transfer start CS Transfer complete
1 CP
2
8
9
10 11 15 16 17 18 23 24 41 42 47 48
DI/O
Start byte
READ DATA1
READ DATA2 Output state
READ DATA5
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PEDL9090-02 Semiconductor Register Descriptions This IC is constructed from a start byte register and data registers. 1. Start byte register
D7 "1" D6 "1" D5 RS D4 R/W D3 D2 D1 D0
ML9090-01,-02
Register number
The start byte register selects 8 types of data registers. (1) D7, D6 (fixed at "1") When selecting the start byte register, always write a "1" to bits D7 and D6. If the RESET pin is pulled to a "L" level, these bits are reset to "0". (2) D5 RS (Register Select bit) 1: RAM is selected 0: Register is selected This bit specifies whether the selected data register is DRAM (display data register) or registers different from the display data register. To select DRAM, write a "1" to this bit. To select registers other than DRAM, write a "0" to this bit. If the RESET pin is pulled to a "L" level, this bit is reset to "0". (3) D4 R/W (Read mode, Write mode select bit) 1: Read mode is selected 0: Write mode is selected This bit specifies either read mode or write mode for the selected data register. To select read mode, write a "1" to this bit. To select write mode, write a "0" to this bit. If the RESET pin is pulled to a "L" level, this bit is reset to "0". (4) D3 to D0 (Register number) These bits select the data register. The correspondence between each bit and each register is listed in the table below. If the RESET pin is pulled to a "L" level, these bits are reset to "0".
Code 0 1 2 3 4 5 8 9 D3 0 0 0 0 0 0 1 1 D2 0 0 0 0 1 1 0 0 D1 0 0 1 1 0 0 0 0 D0 0 1 0 1 0 1 0 1 Register name Key scan register Display data register X address register Y address register Port A register Port B register Control register 1 Control register 2
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PEDL9090-02 Semiconductor 2. Instructions (Data Registers) * Key scan register (KR)
D7 ST2 D6 ST1 D5 ST0 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0
ML9090-01,-02
(1) D7 to D5 ST2 to ST0 (Scan read counter) When reading 25-bit key scan data, these bits indicate the number of times scan data has been read. Every time key scan data is read, these bits (ST2 to ST0) are automatically incremented over the range of "000" to "100". After counting to "100", this key scan data read counter is reset to "000". If the RESET pin is pulled to a "L" level, these bits are reset to "0". (2) D4 to D0 S4 to S0 (Key scan read data bits) These bits are read as 25-bit serial data that expresses the key switch status (1 = ON, 0 = OFF). Data is divided into 5 groups and read. (For the read order, refer to the description below.) The read count is indicated by bits ST2 to ST0. S4 to S0 key scan data corresponds to each SWN0 of the key matrix shown in figure 1. The relation between the key scan data, key matrix signal and each SWN0 of the key matrix is shown below. If the RESET pin is pulled to a "L" level, these bits are reset to "0".
ST2 0 0 0 0 1 ST1 0 0 1 1 0 ST0 0 1 0 1 0 S4 SW04 SW14 SW24 SW34 SW44 S3 SW03 SW13 SW23 SW33 SW43 S2 SW02 SW12 SW22 SW32 SW42 S1 SW01 SW11 SW21 SW31 SW41 S0 SW00 SW10 SW20 SW30 SW40 R0 R1 R2 R3 R4
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PEDL9090-02 Semiconductor ML9090-01,-02
ML9090-01, -02 C0 C1 C2 C3 C4
R0 SW00 SW01 SW02 SW03 SW04 R1 SW10 SW11 SW12 SW13 SW14 R2 SW20 SW21 SW22 SW23 SW24 R3 SW30 SW31 SW32 SW33 SW34 R4 SW40 SW41 SW42 SW43 SW44
Figure 1
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PEDL9090-02 Semiconductor * Display data register (DRAM)
D7 -- D6 D5 D4 8-bit DATA 6-bit DATA D3 D2 D1 D0
ML9090-01,-02
The display data register writes and reads display data to and from the liquid crystal display RAM. The contents of this register are written to or read from the address set by the X address register and Y address register. The bit length of display data can be selected by the WLS bit of control register 1. If 6-bit data has been selected, writing to D7 and D6 is invalid, and if read, their values will always be "0". D7 is the MSB (D5 in the case of 6-bit data) and D0 is the LSB. The X address and Y address should be set immediately before writing or reading display data. However, only one-time settings of X address and Y address are required immediately before successive writings or readings. Either X address or Y address may be set first. Even if the RESET pin is pulled to a "L" level, the contents of this register will not change. * X address register (XAD)
D7 D6 -- D5 D4 D3 D2 XAD D1 D0
The X address register sets the X address for the display RAM. The address setting range is 0 to 9 (00H to 09H) when 8-bit data has been selected by the WLS bit (D6 bit) of control register 1, and 0 to 13 (00H to 0DH) when 6-bit data has been selected. Proper operation is not guaranteed if values outside this range are set. Writing to bits D7 through D4 is invalid, and if read, their values will always be "0". If the RESET pin is pulled to a "L" level, these bits are reset to "0". * Y address register (YAD)
D7 D6 -- -- D5 D4 D3 D2 YAD (ML9090-02) D1 D0
YAD (ML9090-01)
The Y address register sets the Y address for the display RAM. The address setting range for the ML9090-01 is 0 to 7 (00H to 07H) when 1/8 duty has been selected by the DTY0 and DTY1 bits of control register 1, 0 to 8 (00H to 08H) when 1/9 duty has been selected, and 0 to 9 (00H to 09H) when 1/10 duty has been selected. The address setting range for the ML9090-02 is 0 to 15 (00H to 0FH) when 1/16 duty has been selected by the DTY0 and DTY1 bits of control register 1, 0 to 16 (00H to 10H) when 1/17 duty has been selected, and 0 to 17 (00H to 11H) when 1/18 duty has been selected. Proper operation is not guaranteed if values outside these ranges are set. Writing to the D4 bit of the ML9090-01 is valid. Therefore, memory (8 80 bits) corresponding to Y addresses 10 through 17 can be used as a general-purpose memory. Writing to bits D7 through D5 is invalid, and if read, their values will always be "0". When using the ML9090-02, writing to bits D7 through D5 is invalid, and if read, their values will always be "0". If the RESET pin is pulled to a "L" level, these bits are reset to "0".
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PEDL9090-02 Semiconductor * Port register A (PTA)
D7 D6 D5 D4 -- D3 D2 D1 D0 PTA
ML9090-01,-02
The port register A sets (to "1") and resets (to "0") general-purpose port A data. The setting of the PTA bit (D0 bit) corresponds to the PA0 output pin. If the RESET pin is pulled to a "L" level, this register is reset to "0" and the PA0 pin goes to high impedance. After the RESET pin is pulled to a "H" level, if port data is set in this register, the PA0 pin is released from its high impedance state and outputs the corresponding port data. * Port register B (PTB)
D7 PTB7 D6 PTB6 D5 PTB5 D4 PTB4 D3 PTB3 D2 PTB2 D1 PTB1 D0 PTB0
The port register sets (to "1") and resets (to "0") general-purpose port B data. The settings of the PTB0 to PTB7 bits (D0 to D7 bits) correspond to the PTB0 to PTB7 output pins. If the RESET pin is pulled to a "L" level, this register is reset to "0" and pins PTB0 through PTB7 go to high impedance. After the RESET pin is pulled to a "H" level, if port data is set in this register, pins PTB0 through PTB7 are released from their high impedance states and output the corresponding port data. * Control register 1 (FCR1)
D7 INC D6 WLS D5 KT D4 SHL D3 -- D2 -- D1 DTY1 D0 DTY0
(1) D7 INC Address increment direction 1: X direction address increment 0: Y direction address increment This bit sets the address increment direction of the display RAM. The display RAM address is automatically incremented by 1 every time data is written to the display data register. Writing a "1" to this bit sets "X address increment", and writing a "0" sets "Y address increment". For further details regarding address incrementing, refer to the page entitled "X, Y Address Counter Auto Increment", Even if the RESET pin is pulled to a "L" level, the value of this bit will not change. (2) D6 WLS (Word Length Select) 1: 6-bit word length select 0: 8-bit word length select This bit selects the word length of data to be written to and read from the display RAM. If "1" is written to this bit, data will be read from and written to the display RAM in 6-bit units. If "0" is written to this bit, data will be read from and written to the display RAM in 8-bit units. Even if the RESET pin is pulled to a "L" level, the value of this bit will not change.
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PEDL9090-02 Semiconductor ML9090-01,-02
(3) D5 KT (Key scan time) Key scan time select bit 1: 10ms 0: 5ms This bit selects the key scan cycle time. In the case of a 740kHz oscillating frequency, writing a "1" to this bit sets the key scan cycle time at 10ms, writing a "0" sets the key scan cycle time at 5ms. Even if the RESET pin is pulled to a "L" level, the value of this bit will not change. (4) D4 SHL (Common driver shift direction select bit) This bit selects the shift direction of common drivers. The relationship between this bit and shift directions are shown below. Even if the RESET Pin is set to "L", this bit remains unchanged.
Model SHL 1 ML9090-01 0 Duty 1/8 1/9 1/10 1/8 1/9 1/10 1/16 1 ML9090-02 0 1/17 1/18 1/16 1/17 1/18 Shift direction COM8 COM9 COM10 COM1 COM1 COM1 COM16 COM17 COM18 COM1 COM1 COM1 AE AE AE AE AE AE AE AE AE AE AE AE COM1 COM1 COM1 COM8 COM9 COM10 COM1 COM1 COM1 COM16 COM17 COM18
(5) D1 to D0 DTY (Display duty select bit) This bit selects the display duty. The correspondence between each bit and display duty is shown in the chart below. Even if the RESET pin is pulled to a "L" Level, the values of these bits will not change.
Model Code 0 ML9090-01 1 2 3 0 ML9090-02 1 2 3 DTY1 0 0 1 1 0 0 1 1 DTY0 0 1 0 1 0 1 0 1 Display duty 1/8 1/9 1/10 1/10 1/16 1/17 1/18 1/18
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PEDL9090-02 Semiconductor * Control register 2 (FCR2)
D7 -- D6 D5 T4 D4 T3 D3 T2 D2 T1 D1 -- D0 DISP
ML9090-01,-02
(1) D0 DISP (Display ON/OFF mode bit) 1: Display ON mode 0: Display OFF mode This bit selects whether the display is ON or OFF. Writing a "1" to this bit selects the display ON mode. Writing a "0" to this bit selects the display OFF mode. At this time, the COM and SEG pins will be at the VSS level. Even if this bit is set to "0", the display RAM contents will not change. If the RESET pin is pulled to a "L" level, this register is reset to "0". (2) D2 to D5 T1 to T4 (Test mode select bit) These bits are used to test the IC. "0" must be written to these bits.
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PEDL9090-02 Semiconductor Display screen and memory address The ML9090 contains an internal bit-mapped display RAM (80 18 bits). As shown in figure 2, display data is written to display memory such that the MSB of the display data is written to the (Xn, Yn) memory address and the LSB is written to the (Xn+7, Yn) address. Writing a "1" to the display memory turns on the display of the LCD panel and writing a "0" turns off the display. As shown in figure 3, address allocation is different depending upon whether an 8-bit or 6-bit word length is selected. For an 8-bit word length, addresses are allocated from 0 to 9, and for a 6-bit word length, addresses are allocated from 0 to 13. When 6-bits/word are selected and the X address is 13, the display memory is only 2 bits; 2 bits from the MSB of the display data (D5 and D4) are written to memory and the remaining 4 bits (D3 to D0) are invalid.
SEG80 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8
ML9090-01,-02
COM1 COM2
80 18 dot LCD panel COM18 X direction X79 X0 X1 X2 X3 X4 X5 0 X6 1 X7 0
Y0 Y1
1
0
1
0
1
(MSB)
(LSB) 80 18 dit display RAM
Y17
Figure 2 Correspondence Between Display Screen and Memory
Address Allocation for 8 bits/Word 0 0 1 (8 bits) 1 2 9 0 1 0
Address Allocation for 6 bits/Word 1 2 13
(6 bits)
(2 bits)
17
17
Figure 3 Display Memory Addresses
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PEDL9090-02 Semiconductor X, Y address Counter Auto Increment The display RAM of the ML9090-01 and ML9090-02 has an X address counter and a Y address counter. Both counters have an auto increment function. Writing or reading display data will cause either the X or Y address counter to be incremented. The INC bit (D7 bit) setting of control register 1 selects either the X address or Y address to be incremented. (When X address is selected) (INC = "1") The address count cycle of the X address counter differs depending upon whether the word length is 8 bits or 6 bits. If the word length is 8 bits, X addresses in the range of 0 to 9 are counted. If the word length is 6 bits, X addresses in the range of 0 to 13 are counted. When the X address count value returns from its maximum value (9 in the case of 8-bit word length, 13 in the case of 6-bit word length) to 0, the Y address is also automatically incremented. (When Y address is selected) (INC = "0") The address count cycle of the Y address counter differs depending upon whether the display duty is 1/8, 1/9, 1/10, 1/16, 1/17, or 1/18. If the display duty is 1/8, Y addresses in the range of 0 to 7 are counted. If the display duty is 1/9, Y addresses in the range of 0 to 8 are counted. If the display duty is 1/10, Y addresses in the range of 0 to 9 are counted. If the display duty is 1/16, Y addresses in the range of 0 to 15 are counted. If the display duty is 1/17, Y addresses in the range of 0 to 16 are counted. If the display duty is 1/18, Y addresses in the range of 0 to 17 are counted. When the Y address count value returns from its maximum value (7 in the case of 1/8 display duty, 8 in the case of 1/9 display duty, 9 in the case of 1/10 display duty, 15 in the case of 1/16 display duty, 16 in the case of 1/17 display duty, and 17 in the case of 1/18 display duty) to 0, the X address is also automatically incremented. Note: If an address outside the count cycle range of the X, Y address counter is set, proper operation of the X, Y address counter is not guaranteed. 1. X address increment example (8-bit word length, 1/18 duty)
X address 0 0 1 2 9 0 1 1 0 1
ML9090-01,-02
2. Y address increment example (8-bit word length, 1/18 duty)
X address 9 0
Y address
17
0
Y address
2
17
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PEDL9090-02 Semiconductor Output pin, I/O Pin and Register States When Reset is Input Pin and register states while the RESET input is pulled to a "L" level are listed below. ML9090-01,-02
Output pin, I/O pin DI/O KREQ OSC2 R0 to R4 PBA PB0 to PB7 (for ML9090-01) SEG1 to SEG80 COM1 to COM10 (for ML9090-01) COM1 to COM18 (for ML9090-02) Register Key scan register Display data register X address register Y address register Port A register Port B register Control register 1 Control register 2 Reset to "0" Input state "L" (VSS)
State
Oscillating state "L" (VSS) High impedance High impedance "L" (VSS) "L" (VSS) "L" (VSS) State Display data is retained Reset to "0" Reset to "0" Reset to "0" Reset to "0" No change from value prior to reset input Display OFF
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PEDL9090-02 Semiconductor Power-On Flow Chart ML9090-01,-02
Power turned on Reset is input CS = "L" Start byte register setting Data register settings CS = "H" 5ms external reset or power-on reset Chip enable Control register 1 setting INC, WLS, KT, DTY1, DTY2 settings according to specifications
CS = "L" Start byte register settings Data register settings CS = "H" Port register A, port register B, display data register settings according to specifications PA0, PB0 to PB7, D0 to D7 settings
NO
Is input of initial screen data complete? YES CS = "L" Start byte register setting Data register setting CS = "H" Normal operation Control register 1 setting Setting the DISP bit to "1" starts the initial screen display.
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PEDL9090-02 Semiconductor Key Scan Key scan operation begins after a key switch turns ON. Key scan operation is halted after all key switches are detected as OFF. Two cycles after key scan operation starts, the KREQ signal changes from an "L" to "H" level. This signal can be used as a flag. The KREQ signal is reset when all key switches have been detected as OFF and an "L" level is input to the RESET pin. ML9090-01,-02
R0 R1 R2 R3 R4 Key switch ON Start scan KREQ Start reading key data Key switch OFF Halt scan
Note 1:
Pressing three or more key switches simultaneously may result in incorrect recognition (a switch that was not pressed may be recognized as a switch that was pressed). Therefore, if it is necessary to recognize three or more pressed switches, connect a diode in series with each switch. If three or more pressed switches are not to be recognized, data should be ignored if there are three or more "1s" in the key data that is read by software.
Note 2 : Because changes in the key status are detected as changes in the column inputs (C0 to C4), changes will not be detected if multiple switches connected to the same column are pressed.
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PEDL9090-02 Semiconductor Liquid Crystal Driving Waveform Example 1/8 duty (1/4 bias) (ML9090-01) ML9090-01,-02
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3 VS2 V1
C0M1
V2, V3A, V3B V4 VSS VS2 V1
C0M2
V2, V3A, V3B V4 VSS VS2 V1
C0M8
V2, V3A, V3B V4 VSS
A non-selectable waveform is output from COM9 and COM10 outputs.
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3 VS2 V1 V2, V3A, V3B
SEGn
V4 VSS
Light ON Light OFF
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PEDL9090-02 Semiconductor Liquid Crystal Driving Waveform Example 1/9 duty (1/4 bias) (ML9090-01) ML9090-01,-02
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1 VS2 V1
C0M1
V2, V3A, V3B V4 VSS VS2 V1
C0M2
V2, V3A, V3B V4 VSS VS2 V1
C0M9
V2, V3A, V3B V4 VSS
A non-selectable waveform is output from the COM10 output.
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1 VS2 V1 V2, V3A, V3B
SEGn
V4 VSS
Light ON Light OFF
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PEDL9090-02 Semiconductor Liquid Crystal Driving Waveform Example 1/10 duty (1/4 bias) (ML9090-01) ML9090-01,-02
10 1
2
3
4
5
6
7
8
9 10 1
2
3
4
5
6
7
8
9 10 VS2 V1
C0M1
V2, V3A, V3B V4 VSS VS2 V1
C0M2
V2, V3A, V3B V4 VSS VS2 V1
C0M10
V2, V3A, V3B V4 VSS
10 1
2
3
4
5
6
7
8
9 10 1
2
3
4
5
6
7
8
9 10 VS2 V1 V2, V3A, V3B
SEGn
V4 VSS
Light ON Light OFF
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PEDL9090-02 Semiconductor Liquid Crystal Driving Waveform Example 1/16 duty (1/5 bias) (ML9090-02) ML9090-01,-02
15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6
VS2 V1 C0M1 V2 V3A, V3B V4 VSS VS2 V1 C0M2 V2 V3A, V3B V4 VSS VS2 V1 C0M16 V2 V3A, V3B V4 VSS
A non-selectable waveform is output from COM17 and COM18 outputs.
15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6
VS2 V1 SEGn V2 V3A, V3B V4 VSS Light ON Light OFF
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PEDL9090-02 Semiconductor ML9090-01,-02
APPLICATION CIRCUITS
Application Example 1 (1/10 duty, voltage doubler)
LCD panel 80 8 dot (graphic) 80 2 dot (arbitrator)
COM1 - COM10 VCC
Temperature compensating and stabilizing circuits
SEG1 - SEG80 VDD DT VSS PA0 OSC1 56kW OSC2
VIN 4.7mF + VC1 VC2 VS1
+ 4.7mF
VS2
V2 TEST OPEN V3B V3A ML9090-01 RESET 1mF
CS R4 PORT OR SIRIAL PORT CP DI/O KREQ PB0 - PB7 CO C1 C2 C3 C4 R3 R2 R1 R0
General-purpose ports
55 Key Matrix
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PEDL9090-02 Semiconductor Application Example 2 (1/18 duty, voltage tripler) ML9090-01,-02
LCD panel 80 16 dot (graphic) 80 2 dot (arbitrator)
COM1 - COM18 VCC
Temperature compensating and stabilizing circuits
SEG1 - SEG80 VDD DT VSS PA0 OSC1 56kW OSC2
VIN 4.7mF + + VC1 VC2 VS1 VS2
4.7mF + 4.7mF
OPEN
V2 ML9090-02 V3B V3A CS
TEST RESET 1mF
R4 PORT OR SIRIAL PORT CP DI/O KREQ CO C1 C2 C3 C4 R3 R2 R1 R0
55 Key Matrix
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PEDL9090-02 Semiconductor ML9090-01,-02
[Cautions] * When the power supply is ON or OFF, the following power supply sequence should be used. At the time of power supply ON: Logic power supply ON AE multiplied reference voltage (VIN) supply ON At the time of power supply OFF: Multiplied reference voltage (VIN) supply OFF AE logic power supply OFF or both OFF * The lines between output pins, and between output pins and other pins (input pins, I/O pins or power supply pins) should not be short circuited.
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PEDL9090-02 Semiconductor ML9090-01,-02
PACKAGE DIMENSIONS
QFP128-P-1420-0.50-K
(Unit : mm)
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.19 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 37/38
PEDL9090-02
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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9.
Copyright 2000 Oki Electric Industry Co., Ltd.
Printed in Japan
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