View KB8825_1259770.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
INTRODUCTION
16-TSSOP-0044 The KB8825 is a high performance dual frequency synthesizer with two integrated high frequency pre-scalers for RF operation up to 1.1 GHz. The KB8825 is composed of modulus pre-scalers providing 64 and 66, no dead-zone PFD, selectable charge pump current, selectable power down mode circuits, lock detector output, and loop filter's time constant switch. It is fabricated using the ASP5HB Bi-CMOS process and is available 16-TSSOP with surface mount plastic packaging. Serial data is transferred into the KB8825 via three-wire interface (CK, DATA, EN).
FEATURES
* * * Two systems for receiver and transmitter Very low operating current consumption: Icc = Typ. 5.5mA @ 3.0V Low operating power supply voltage : 2.2 ~ 5.5V ( 200MHz ~ 550MHz Operating ) 2.7 ~ 3.6V ( 550MHz ~ 1.1GHz Operating ) * * * * * * Modulus pre-scaler: 64 / 66 No dead-zone PFD Colpitt type local oscillation Selectable charge pump current Selectable power down mode TSSOP 16-pin package (0.65 mm pitch)
ORDERING INFORMATION
Device +KB8825
+: New product
Package 16-TSSOP-0044
Operating Temperature -30 C to + 85 C
APPLICATIONS
* * * * Cordless telephone systems Portable wireless communications (PCS) Wireless Local Area Networks (WLANs) Other wireless communication systems
1
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
BLOCK DIAGRAM
Fin1 1
Pre_Amp
1/2
Prescaler 1 32, 33
Buffer
Prescaler 1 32, 33
Buffer
1/2
Pre_Amp
16 Fin2
VCC
2 Charge Pump Phase Detector Lock Detector 6 2
15 VCC 2 Charge Pump Phase Detector Switch 14 CP2 13 GND
CP1 3
GND 4
Channel 1 Programable Divider
Channel 2 Programable Divider
LD
5
12
SW
CK
6 Control Circuit Reference Divider
Local OSC 1/2 Buffer
11 OSCI
DATA 7
10 OSCO
17
12
EN
8
9
BO
PIN CONFIGURATION
Fin1 VCC CP1 GND LD CK DATA EN
1 2 3 4 5 6 7 8
16 15 14 13
Fin2 VCC CP2 GND SW OSCI OSCO BO
KB8825
12 11 10 9
16TSSOP
2
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
PIN DESCRIPTION
Pin No. 1 2, 15 3 4, 13 5 6 7 8 9 10 11 12 14 16 Symbol Fin1 Vcc CP1 GND LD CK DATA EN BO OSCO OSCI SW CP2 Fin2 I/O I - O - O I I I O O I O 0 I Description Input terminal of channel 1 RF signal. Power supply voltage input. PIN2 and PIN15 are connected together. Output terminal of channel 1 charge pump. Charge pump is constant current output circuit, and output current is selected by input serial data. Terminal of GND. PIN4 and PIN13 are connected in common. Output terminal of lock detection. It is the open drain output. Input terminal of clock. Input terminal of data. Input terminal of enable signal. Output terminal of buffer amplifier. The signal of local oscillation is output through the buffer amplifier. Output terminal of local oscillation signal. Input terminal of local oscillation signal. In case of external input, connecting it to this terminal. Switchover terminal for the time constant of loop filter. It is an open drain output. If you don't switch the time constant of loop filter, general output is available. Output terminal of channel 2 charge pump. Charge pump is a constant current output circuit, and the output current is selected by input serial data. Input terminal of channel 2 RF signal.
ABSOLUTE MAXIMUM RATINGS
Characteristic Power Supply Voltage Power Dissipation Operating temperature Storage temperature Take care ! ESD sensitive device Symbol Vcc PD TOPR TSTG Value 6 600 -30 ~ + 85 -55~ +150 Unit V mW C C
3
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
ELECTRICAL CHARACTERISTICS
(Ta = 25C, VCC = 3V, unless otherwise specified) Characteristic Operating Power supply voltage Operating current consumption Standby current Fin operating frequency Symbol VCC ICC ISB Fin Test Conditions Fin1=Fin2= 200MHz ~ 550MHz Fin1=Fin2= 550MHz ~ 1.1GHz Fin1=Fin2=1.1GHz/ -5dBm input Standby mode Fin1 = Fin2 = - 5dBm Vcc=2.2V Fin1 = Fin2 = 200MHz Vcc=3.0V Vcc=5.5V Vcc=2.2V Fin input sensitivity Fin Fin1 = Fin2 = 550MHz Vcc=3.0V Vcc=5.5V Vcc=2.7V Fin1 = Fin2 = 1.1GHz OSCI operating frequency Fosc Vcc=3.0V Vcc=3.6V VFin = 0dBm, sinewave Vcc=2.2V fosc = 10MHz OSCI input voltage Vosc fosc = 20MHz Vcc=3.0V Vcc=5.5V Vcc=2.2V Vcc=3.0V Vcc=5.5V Serial data input high voltage (CK, DATA, EN) Serial data input low voltage (CK, DATA, EN) Charge pump output current VIH VIL ICP1 ICP2 ICP3 ICP4 Charge pump leakage ICPL VCC = 2.2 to 5.5V VCC = 2.2 to 5.5V CP1 = 0, CP2 = 0 CP1 = 0, CP2 = 1 CP1 = 1, CP2 = 0 CP1 = 1, CP2 = 1 VCP = 1.5 V VCP = 1.5V VCP = 1.5V VCP = 1.5V Min. 2.2 2.7 3.5 - 200 - 15 - 15 - 10 -15 -15 - 10 - 10 - 10 - 10 5 - 10 - 10 0 - 10 - 10 -5 VCC - 0.4 - - - - - -1 Typ. 3.0 3.0 5.5 0 - - - - - - - - - - 0 0 0 0 0 - - 100 200 400 800 - Max. 5.5 3.6 7.5 10 1100 0 0 0 0 0 0 0 0 0 25 5 5 5 5 5 5 - 0.4 - - - - +1 V V A A A A A dBm MHz dBm Unit V V mA A MHz
Standby mode, Vcp = 1.5V
4
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT AND TIMING CK (Pin6), DATA (Pin7), EN (Pin8) terminals in KB8825 are used for MICOM (MPU) serial data interface (MSB: 1st input data; LSB: Last input data). Serial data controls the programmable reference divider, programmable divider (CH1), programmable divider (CH2), and control latch separately by means of group code. Binary serial data is entered via the DATA pin. One bit of data is shifted into the internal shift register on the rising edge of the clock. When EN pin is high, stored data is latched. The three terminals, CK, DATA, and EN, contain Schmitt trigger circuits to keep the data from errors caused by noise, etc. < Notice > 1. When power supply of KB8825 is disconnected, CLK, DATA, EN port from MCU should be pulled low. 2. When power goes up first, R counter data should be entered earlier than N1 and N2 counter data. 3. When power goes up first, control data should be entered earlier than N1 and N2 counter data. 1us 0.2us
0.2us
CK DATA
MSB
N1 (R1)
0.2us
N2 (R2) N3 (R3) N16 (R11) N17 (R12) GC2
LSB
GC1
MSB
0.1us
EN
0.1us
0.2us
0.2us Figure 1.
NOTE: Start data input with MSB first
SERIAL DATA GROUP AND GROUP CODE The IC can be controlled through 4 kinds of group selection. Each group is identified by selective a 2-bit group code given below. Serial Bits GC1 (LSB) 0 0 1 1 GC2 (LSB-1) 0 1 0 1 Control Latch Ch 1 N Latch Ch 2 N Latch OSC R Latch Group Location
5
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
CONTROL LATCH The control register executes the following functions: * * * * * Mode selection (H: test mode, L: normal mode) Charge pump's polarity and output current selection for each channel. Output state selection for Lock Detector. Standby control of each channel and reference divider. ON / OFF control in filter switch.
MSB
CH1
CH2 GC2 "0"
LSB GC1 "0"
T
CP
CP1
CP2
SB1
CP1
CP2
SB2
SBR
LD1
LD2
SW
Group Code
Figure 2.
Bit Name Description
Bit 1 T test mode
Bit 2 CP charge pump out polarity
Bit 3 CP1 channel 1 charge pump output current
Bit 4 CP2 channel 1 charge pump output current
Bit 5 SB1 channel 1 standby
Bit 6 CP1 channel 2 charge pump output current
Bit 7 CP2 channel 2 charge pump output current
Bit Name Description
Bit 8 SB2 channel 2 standby
Bit 9 SBR reference divider standby
Bit 10 LD1 lock detector control 1
Bit 11 LD2 lock detector control 2
Bit 12 SW filter switch
Bit 13 GC2 group code "0"
Bit 14 GC1 group code "0"
6
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
CHARGE PUMP OUTPUT POLARITY (CP) In normal operation, the CP should be "0". In reverse operation, the CP should be "1". Depending upon VCO characteristics, CP should be set accordingly; When VCO characteristics are like (1), CP should be set low When VCO characteristics are like (2), CP should be set high.
VCO Characteristics (1) VCO Output Frequency
(2) VCO Input Voltage
CHARGE PUMP OUTPUT CURRENT (CP1, CP2) The KB8825 includes a constant current output type charge pump circuit. Output current is varied according to control bit "CP1" and "CP2". In order to get high speed lock-up, select the best charge pump output current. Control Bit CP1 0 0 1 1 CP2 0 1 0 1 Charge Pump Output Current 100 A 200 A 400 A 800 A
7
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
TEST MODE AND LOCK DETECTOR OUTPUT (T, LD1, LD2) When T is normal "0", LD (Pin5)state is varied by controlling "SB1", "SB2", "LD1" and "LD2". When T is high "1", LD (Pin5) state is changed to be useful for test T SB1 SB2 LD1 0 0 0 1 1 0 0 0 1 1 1 0 0 0 0 1 1 1 0 1 0 1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 1 0 1 0 x x LD2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x x LD Output State low channel2 channel1 channel1. AND. channel2 low high channel1 channel1 low channel2 high channel2 low high high high low pres2 fpll2 fref div4 pres1 fpll1 fosc/2 low low
8
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
LOCK DETECTOR OUTPUT When the phase comparator detects a phase difference, LD (Pin5) outputs "L". When the phase comparator locks, LD outputs "H". On standby, it outputs "H". When T is less than 2/fosc (T<2 /fosc ) for more than three cycles of reference divider output as in the figure below, the lock detector outputs "H".
A Reference Divider output Channel Divider output T Charge pump output T<2/fosc Lock detector output
B
Figure 3. Lock Detector Output fosc: OSCI operating frequency (LOCAL OSC). T: time difference of the pulse between reference divider output and channel divider output. A= Number of divisions by reference divider fosc 2 fosc (s) (s)
B=
PROGRAMMABLE STANDBY MODE (SB1, SB2, SBR) Standby mode can be controlled by 3-control bits such as SB1, SB2 and SBR. SB1 and SB2 can control standby mode of channel 1 and channel2. The "SBR" bit can do ON / OFF control of reference divider. Control Bit SB1 0 0 1 1 1 SB2 0 1 0 1 1 SBR x x x 0 1 CH1 ON ON OFF OFF OFF CH2 ON OFF ON OFF OFF Standby Mode State REF ON ON ON ON OFF Mode Status Inter locking Mode CH1 Locking Mode CH2 Locking Mode REF On Mode Standby Mode
9
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
FILTER SWITCH CONTROL (SW) The operation mode of the SW terminal is set by bit "SW". SW control is useful for switching the time canstant of the loop filter. Output type of this terminal is an open drain output. High lock mode or normal lock mode can be used, taking advantage of filter switch control (SW) with the charge pump output current. When fast lock function can't be used, normal lock mode is available. Control Bits SW 0 0 0 0 1 1 1 1 CP1 0 0 1 1 0 0 1 1 CP2 0 1 0 1 0 1 0 1 High Lock Mode
GND SW R
Operation Mode
(SW and LPF example) The third order LPF
Normal Lock Mode
CP1 R R
CRYSTAL OSCILLATOR CIRCUIT (OSCI, OSCO) AND BUFFER OUT (BO) External capacitors C1, C2, C3, and C4 are required to set the proper crystal's load capacitance and oscillation frequency as shown in figure 4. The value of the capacitors is dependent on the crystal chosen. The BO (Pin9) outputs local oscillation signal with buffer amplifier. This terminal (Pin9) can be applied to the 2nd mixer input
C4 1000pF OSCI
C1 C2
OSCI C3 C2 OSCO 1000pF 1000pF 2'nd MIX or OPEN BO
Reference Oscillator
OSCO
BO
2'nd MIX or OPEN
Figure 4.
10
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
PROGRAMMABLE REFERENCE COUNTER
This block generates the reference frequency for the PLL. The reference divider is composed of 12-bit reference divider and a half fixed divider Sending certain data to the reference divider allows the setting of any of 6 to 8190 divisions (multiple of two).
MSB LSB
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10 R11 R12
GC2 "1"
GC1 "1"
Division Ratio of the R counter, R
Group Code
R = R1 x 20 + R2 x 21 + ... + R12 x 211 Division ratio: 2 x R = 2 x (3~4095) = 6 ~ 8190 Data is shifted in MSB first. Division Ratio 3 4 * 4095 R12 0 0 * 1 R11 0 0 * 1 R10 0 0 * 1 0 0 * 1 R9 0 0 * 1 R8 0 0 * 1 R7 0 0 * 1 R6 0 0 * 1 R5 0 0 * 1 R4 0 1 * 1 R3 1 0 * 1 R2 1 0 * 1 R1
Example) A 21.25MHz X-tal oscillator is connected, and divided into 25kHz steps. (Reference frequency is 12.5kHz) 21.25 MHz / 12.5 kHz = 1700 1700 = 2 x R R = (850)10 = (1101010010)2
MSB
LSB
0
1
0
0
1
0
1
0
1
1
0
0
1
1
11
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
CHANNEL 1, CHANNEL 2 PROGRAMMABLE N COUNTER
These programmable dividers are composed of a 5-bit swallow counter (5-bit programmable divider), 12-bit programmable main counter, and two-modulus prescalers providing 64 and 66 divisions. Sending certain data to the swallow counter and the 12-bit programmable main counter allows the setting of any of 2048 to 262142 divisions (multiple of two). The 12-bit programmable divider and swallow counter are set by each channel; each channel is identified by a group code.
MSB
Swallow counter N2 N3 N4 N5 N6 N7 N8 N9 N10
main counter N11 N12 N13 N14 N15 N16 N17 N18
LSB
N1
N19
Division Ratio of the N Counter, N
Group Code CH1 = "10" CH2 = "01"
Figure 5. 5-BIT SWALLOW COUNTER DIVISION RATIO (A COUNTER) A = N1 x 20 + N2 x 21 ... N5 x 24 Division ratio: 0 to 31, B A Division Ratio (A) 0 1 * 31 N5 0 0 * 1 N4 0 0 * 1 N3 0 0 * 1 N2 0 0 * 1 N1 0 1 * 1
12-BIT MAIN COUNTER DIVISION RATIO (B COUNTER) B = N6 x 20 + N7 x 21 + N7 x 22 ... N17x 211 Division ratio: 3 to 4095 Data is shifted in MSB first Division Ratio (B) 3 4 * 4095 N17 0 0 * 1 N16 0 0 * 1 N15 0 0 * 1 N14 0 0 * 1 N13 0 0 * 1 N12 0 0 * 1 N11 0 0 * 1 N10 0 0 * 1 N9 0 0 * 1 N8 0 0 * 1 N7 1 0 * 1 N6 1 0 * 1
12
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
Channel1 and 2 Programmable Counter Division Ratio, N N = 2 x (32 x B + A), B A Division ratio: 192 ~ 262142 Example) A Signal of 453 MHz is entered into Fin1, and divided into 25 kHz steps. (Reference frequency is 12.5 kHz) 453 MHz / 12.5 kHz = 36240 36240 = 2 x (32 x B + A) B = (1132)10 = (10001101100)2, A = (16)10 = (10000)2
MSB
LSB
0
0
0
0
1
0
0
1
1
0
1
1
0
0
0
1
0
1
0
Example) A Signal of 462.9 MHz is entered into Fin2, and divided into 25 kHz step. (Reference frequency is 12.5 kHz) 462.9 MHz / 12.5 kHz = 37032 37032 = 2 x (32 x B + A) B = (1157)10 = (10010000101)2, A = (8)10 = (01000)2
MSB
LSB
0
0
0
1
0
1
0
1
0
0
0
0
1
0
0
1
0
0
1
PHASE DETECTOR AND CHARGE PUMP CHARACTERISTICS Phase difference detection Range: -2 ~ +2 When SW = Low
fr fp
LD CPO fr > fp fr = fp fr < fp fr < fp fr < fp
Figure 6.
13
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
APPLICATION CIRCUIT ( HANDSET )
RX_VCC RX_VCC
C19
1.5N 2 1 1 1 2
C20 C21
100p 1.2N
C22
220p
2
2
2 1
1
C17 R8
10N 330
TP2
IF
TP1 1 1 AF_OUT R10
6.8K 1
R14 R12
23 2.2K 1
1
1 1
1
TP3
1 RSSI
1 1
2
R11
100K 2
2.7K 2
C23
2 2 1 6.8N 13 12 11 10
R13 2 1
6.8K
2
2
C6 R5
220 220N 2 1 1 1
1
C18
2 2 1 1 16 15 10N 2
C24
100N 3 2 1 14 9
Q6
1
3
KSC1623Y
C2
220N 2 1
R3
2 220 1
C8
1 2 10N
2
C11 L5
220N 3.3uH 1
C13
150p
C3
1 2 10N 1
R9
22K
Q5
1 KSC1623Y 1
AFLT1
AFLT2
AFO
RFIN-
RFIN+
IFLT1
IIFLT2
RSSI
R4
47K 2
1 1
1
L4 C9
2 1 6p 6p 2 1 2 3
C14
1N 1 2 2 1
F1
2 1
C16
10N 2 3 2 2
2 3 4 1 2
Q3
L2 C4
1 21 1 5p 2 2 3
Q4
KSC2223Y 1
R15 U1
DEMO GND TMC
R2
4.7K
L3
2
KA8532
DECPL IFLT4 IFLT3 OSC VCC 2 2 3 4 5 6 7 8
100
1
2 2 1
Q2
1
C4228
C10 R6
10K 1 2
SGM2016M
ANT1
1
C12
10N 1 2
R7
560 1
C1510.7MHz
N.A
2
Q1
1
C5
6p 2
C7
2p
2 2
C4228
1
R1
1 2 2 4.7K
C28
1 15N
C1
6p 2 1
2
2
1
R272
220
RX_VCC
C25
560p
RSSI AF_OUT
1 2 1 2
2
L1
C47 R28
680 1
C46
220N 1
100N
RX VCO
2 1 RX_VCC
1
2
902~905MHz
3.9nH
C50
7p 1 2
2
2 1
C30 R17
4.7N 10K 1 1 1 2
C29
100N
2
2
C32 C31
39p 100p 1 1 1
C76
5p 1
2
1
L15 L14
8.2nH 1 1
R16
470 2
C75
1 2 4p
F2
SF X033H 1 25 3 4 6
C26 C27
1.5N 100N 1
C33
2~6p 2
1
L8 R26 C49
RX_VCO 1 15p 3p 2 18K 1 2 23
R18
2 2 1K 2 2
TP5
CP1
TP4 1
1
1 6p
2
Q8
1 C4228 1
2 2
L7
R24
5.6K
Y1
10.63MHz
1
1 1
C51 C48
2 1
Q7
C4228 1
C42
2 1 2p 1 2 2
C39
1 2 3p 1
C35
1 2
1 2 1
1
3
R22
2 10K 2 1
R21 2
2.2K 2 2
47p
C34
2 9 1 1N
L13 C45
TX_VCC 2 2p 1 2
C43
3p 1 2
C40
2p 12
D1
1SV239
C38 C37
8.2N 8.2N 1 12 1
R20
51K 2
16
15
14
13
12
11
10
R23 C44
1p 1 2 10K 2 2
FIN2
VCC
CP2
GND
S/W
OSCI
OSCO
BO
1
1
R25
220
925~927MHz
1 2 1
C41
2p 1
R19 C36
220N 100
C74
2 1 2 1N 1
R45
2 220
C71
220N
KB8825
DATA GND FIN1 VCC CP1 CLK EN LD 1 2 3 4 5 6 7 8
2 1
1
L6
0.5X1.0X1.5t RX_VCO
C69
1 TX_VCO1 1 2 2 1 15p 1
R33
2 51
R42 1
220 1
TX_VCC
TX VCO
2 1
RX_VCC TX_VCC
CNT1
12 10 8 6 4 2
C72
100N 2 2
1
Q11 2
C4228
1
C66 L12
2
100N
1
C64
220N 2 1 2
R32
100
R44
5.6K 1
R31 R29 R30
1K 1K 1K
C52
100p
L11 R43
18K
RX_VCC 2 2 2
11 RX VCC 9 AF_OUT 7 GND GND 5 RSSI LDT TX VCC CLK 3 DATA 1 AF IN GND EN
1
1
1 1
2
2 1
2
C70
2 1 47p
C68
2 1
3
2 1 3
C53
220N
C73
N.A
100p
1
2
1
C67
3p 2 1
Q10
C4228
TP6 R40
5.6K CP2 1
Q9
C4228 1
1
2
L10
23 1 2 1
C61
2 1 1p 1 2 2
C58
1 3p 2
R36
1 10K 2
R35
2 7.5K 1 2 1
1
C65
2 2p 1
C62
3p 2 2 1
C59
2p 1 2
R34
30K
C54
10N
1
R39 C63
1p 10K
L9
D2
1SV239 2
C56
1 10N 1
2
2
R41
220 1 2
0.5X1.0X1.5t 2 1
C60
1 2p
C55
220N 2
1
R37
2 560 2 1 1
R38
15K
C57
1N 2
1
14
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
APPLICATION CIRCUIT ( BASESET )
RX_VCC RX_VCC
C19
1.5N 2 1 1 1 2
C20 C21
100p 1.2N
C22
220p
2
2
2 1
1
C17 R8
10N 330
TP2
IF
TP1 1 1 AF_OUT R10
6.8K 1 2
R14 R12
23 2.2K 1
1
1 1
1
TP3
1 RSSI
1 1
2
R11
100K 2
2.7K 2
C23
2 1 1 6.8N 13 12 11 10 9
C24
100N 3
R13 2 1
6.8K
2
2
C6 R5
220 220N 2 1 1 1
1
C18
2 2 1 1 16 15 10N 2
Q6
1
3 2
KSC1623Y
C2
220N 21 1
R3
21 220
C8
1 2 10N
2
14
C11 L1
220N 3.3uH 1
C13
150p
C3
1 2 10N
R9
22K
Q5
1 KSC1623Y 1
AFLT1
AFLT2
AFO
RFIN-
RFIN+
IFLT1
IIFLT2
RSSI
R4
47K 23
1
1
L2 C9
1 6p 6p 2 1 2 1 2
C14
1N 1 2 2 1
F1
2 1
C16
10N 2 3 2 2
2 3 4 1 2
Q3
L3 C4
1 5p 2 21 1 2 3
Q4
KSC2223Y 1
R15 U1
DEMO TMC GND
R2
4.7K
L4
2
KA8532
DECPL IFLT4 IFLT3 OSC VCC 2 2 3 4 5 6 7 8
100
1
2 2 1
Q2
1
C4228
C10 R6
10K 1 2
SGM2016M
ANT1
1
C12
10N 1 2
R7
560 1
C1510.7MHz
N.A
2
Q1
C4228 1
C5
6p 2
C7
2p
2 2
1
R1
1 2 2 4.7K
C28
1 15N
C1
6p 2
RX_VCC
2
2
1
C25
560p
RSSI AF_OUT
R272 1 C47
220 100N
11 2
2
2
L6
C46
220N 1
RX VCO
2 1 RX_VCC
1
2
902~905MHz
L7
3.9nH
C50
7p 1 2
2
2
R28
680
1
1
C30 R17
4.7N 10K 1 1 1 2
C29
100N
2
2
C32 C31
39p 100p 1 1 1
C76
5p 1
2
1
L8
8.2nH 1 1
R16
470 2
C75
1 2 4p
F2
SF X034B 1 25 3 4 6
C26 C27
1.5N 100N 1
C33
1~10p 2
1
L9 C49 TP4 1 RX_VCO
1 1 6p 1 15p 3p 2 2 23
R26
18K 1
R18
2 2 1.8K 2 2
TP5 L10 R24
5.6K 2 1 1 2 CP1 1
Q8
1 C4228 1
2
Y1
10.63MHz
1
C51 C48
2 1
Q7
C4228 1
C42
2 1 2p 1 2 2
C39
1 2 3p 1
C35
1 2
1
3 2
R22
2 10K 2 1
R21 2
2.2K 2 2
47p
C34
2 9 1 1N
1
L11 C45
2 2p 1 2
C43
3p 1 2
C40
2p 12
D1
1SV239
C38 C37
8.2N 8.2N 1 12 1
R20
51K 2
16
15
14
13
12
11
10
R23 C44
1p 1 2 10K 2 2
FIN2
VCC
CP2
GND
S/W
OSCI
OSCO
BO
1
1
R25
220
925~927MHz
1 2 1
C41
1p 1
R19 C36
220N 100
C74
2 1 2 1N 1
R45
2 220
C71
220N
KB8825
DATA FIN1 VCC GND CP1 CLK EN LD
2 1
1
L12
0.5X1.0X1.5t RX_VCO
C69
1 TX_VCO1 1 TX_VCC 2 220 2 1 1
R33
2 51 1 2 3 4 5 6 7 8 RX_VCC TX_VCC 2 1
R42 TX_VCC 1 15p
1
TX VCO
R32
100 2 1 1 1 1 1 1K 1K 1K 2 2 2 2 RX_VCC
CNT1
11 RX VCC 9 AF_OUT 7 GND GND 5 RSSI LDT CLK 3 TX VCC DATA 1 AF IN GND EN 12 10 8 6 4 2
C72
220N 2 2
1
Q11 2
C4228
1
C66 L13
2
100N
1
C64
220N 2 1 2
R44
5.6K 1
R31 R29 C52 R30
100p
2
L14 R43
18K
3
C70
2 1 47p
C68
2 1 100p
2 1 3
C53
220N
1
C73
N.A
2
1
C67
2p 2 1
Q10
C4228
TP6 R40
5.6K CP2 1
Q9
C4228 1
1
2
L15
23 1 2 1
C61
2 1 1p 1 2 2
C58
1 3.5p
2 R36 1 10K
R35
2 7.5K 1 2 1
1
C65
2 2p 1
C62
3p 2 21
C59
2p 1 2
R34
30K
C54
10N
2
1
R39 C63
2p 10K
L16
D2
1SV239 2
C56
1 10N 1
2
2
R41
220 1 2
0.5X1.0X1.5t 2 1
C60
1 2p
C55
220N 2
1
2 R37 1 560 2 1
R38
15K
C57
1N 2
1
15
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
CHARACTERISTIC GRAPH
800E
400E
200E
100E
100E 200E
400E
800E
16
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
100E 200E
400E
800E
800E
400E
200E 100E
17
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
INPUT SENSITIVITY INPUT FREQUENCY (Fin1) INPUT SENSITIVITY Vin1 (dBm) 30 20 10 0 10 20 30 40 0 100 200 300 400 500 600 700 800 900 1000 1100 INPUT FREQUENCY Fin1 (MHz) .
INPUT SENSITIVITY - POWER SUPPLY VOLTAGE (Fin1)
INPUT SENSITIVITY Vin1 (dBm)
30 20 10 0 10 20 30 40 2.2 2.5 3 3.5 4 4.5 5 5.5 6
500M_min 500M_Max 1100M_mi 1100M_Max
INPUT FREQUENCY Fin1 (MHz )
18
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
INPUT SENSITIVITY INPUT FREQUENCY (Fin2) INPUT SENSITIVITY Vin2 (dBm) 30 20 10 0 10 20 30 0 100 200 300 400 500 600 700 800 900 1000 1100
INPUT FREQUENCY Fin2 (MHz)
INPUT SENSITIVITY - POWER SUPPLY VOLTAGE (Fin2) 30 INPUT SENSITIVITY Vin2 (dBm) 20 10 0 10 20 30 40 2.2 2.5 3 3.5 4 4.5 5 5.5 6 500_min 500_Max 1 1 0 0 _ min 1100_Max
INPUT FREQUENCY Fin2 (MHz)
19
Final version ( 99.4.30 )
KB8825
1.1GHZ DUAL PLL
X I N I N P U T S E N S IT IV IT Y 30 20 10 Vxin (dBm) 0 -1 0 -2 0 -3 0 -4 0 5 10 15 Fxin (M Hz ) 20 25
CURRENT CONSUMPTION- POWER SUPPLY VOLTAGE 7
CURRENT CONSUMPTION Icc (mA)
6
5
4
3
2
1
0 0 1 2 3 4 5 6 POWER SUPPLY VOLTAGE VCC (V)
20
Final version ( 99.4.30 )
1.1GHZ DUAL PLL
KB8825
NOTES
21

▲Up To Search▲

Price & Availability of KB8825

	To Download KB8825 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .