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| CED71A3/CEU71A3 Dec. 2002 N-Channel Logic Level Enhancement Mode Field Effect Transistor FEATURES 30V , 65A , RDS(ON)=10m @VGS=10V. RDS(ON)=14m @VGS=5.0V. Super high dense cell design for extremely low RDS(ON). High power and current handling capability. TO-252 & TO-251 package. D 6 G D G S G D S CEU SERIES TO-252AA(D-PAK) CED SERIES TO-251(l-PAK) S ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous -Pulsed Drain-Source Diode Forward Current Maximum Power Dissipation @Tc=25 C Derate above 25 C Operating and Storage Temperature Range Symbol VDS VGS ID IDM IS PD TJ, TSTG Limit 30 20 65 100 65 69 0.56 -55 to 150 Unit V V A A A W W/ C C THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient R JC R JA 6-67 1.8 40 C/W C/W CED71A3/CEU71A3 ELECTRICAL CHARACTERISTICS (TC=25 C unless otherwise noted) Parameter OFF CHARACTERISTICS Drain-Source Breakdown Voltage BVDSS IDSS IGSS VGS(th) RDS(ON) ID(ON) gFS b Symbol Condition VGS = 0V, ID = 250A VDS = 30V, VGS = 0V VGS = 20V, VDS = 0V VDS = VGS, ID = 250A VGS = 10V, ID = 15A VGS = 5.0V, ID = 13A VGS = 10V, VDS = 5V VDS = 5V, ID = 12A Min Typ Max Unit 30 1 V A 100 nA 1 8.5 65 26 2152 965 234 3 10 11.5 14 V m m A S 6 Zero Gate Voltage Drain Current Gate-Body Leakage ON CHARACTERISTICS a Gate Threshold Voltage Drain-Source On-State Resistance On-State Drain Current Forward Transconductance DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS b PF PF PF VDS =15V, VGS = 0V f =1.0MHZ SWITCHING CHARACTERISTICS Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge tD(ON) tr tD(OFF) tf Qg Qgs Qgd VDD = 15V, ID =1A, VGS = 10V, RGEN =6 30 63 73 59 55 60 110 130 100 67 ns ns ns ns nC nC nC VDS =10V, ID = 15A, VGS =10V 6-68 9 18 CED71A3/CEU71A3 ELECTRICAL CHARACTERISTICS (TC=25 C unless otherwise noted) Parameter Diode Forward Voltage Symbol VSD Condition VGS = 0V, Is = 2.3A Min Typ Max Unit 0.9 1.3 V DRAIN-SOURCE DIODE CHARACTERISTICS a Notes a.Pulse Test:Pulse Width 300 s, Duty Cycle 2%. b.Guaranteed by design, not subject to production testing. 60 VGS=10,8,6,4V 50 50 60 6 ID, Drain Current (A) ID, Drain Current (A) 40 30 20 10 0 0 1 2 3 4 5 40 30 -55 C 20 25 C 10 0 1 2 3 4 Tj=125 C VGS=3V VDS, Drain-to-Source Voltage (V) VGS, Gate-to-Source Voltage (V) Figure 1. Output Characteristics 3000 Figure 2. Transfer Characteristics 1.80 RDS(ON), Normalized RDS(ON), On-Resistance(Ohms) 2500 1.60 1.40 1.20 1.00 0.80 ID=15A VGS=10V C, Capacitance (pF) Ciss 2000 1500 1000 500 0 0 5 10 15 20 25 30 Coss Crss 0.60 -50 -25 0 25 50 75 100 125 150 VDS, Drain-to Source Voltage (V) TJ, Junction Temperature( C) Figure 3. Capacitance Figure 4. On-Resistance Variation with Temperature 6-69 CED71A3/CEU71A3 BVDSS, Normalized Drain-Source Breakdown Voltage Vth, Normalized Gate-Source Threshold Voltage 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 -50 -25 0 25 50 75 100 125 150 VDS=VGS ID=250 A 1.15 ID=250 A 1.10 1.05 1.00 0.95 0.90 0.85 -50 -25 6 0 25 50 75 100 125 150 Tj, Junction Temperature ( C) Tj, Junction Temperature ( C) Figure 5. Gate Threshold Variation with Temperature 50 Figure 6. Breakdown Voltage Variation with Temperature 50 gFS, Transconductance (S) Is, Source-drain current (A) 40 30 20 10 VDS=5V 0 0 10 20 30 40 10 1.0 0.1 0.4 0.6 0.8 1.0 1.2 1.4 IDS, Drain-Source Current (A) VSD, Body Diode Forward Voltage (V) Figure 7. Transconductance Variation with Drain Current 10 8 6 4 2 0 0 15 30 45 60 Figure 8. Body Diode Forward Voltage Variation with Source Current 2 VGS, Gate to Source Voltage (V) VDS=15V ID=15A 10 1m 1 RD O S( L N) im it s 10 m ID, Drain Current (A) s 10 10 0m s 1s D C 10 0 -1 10 10 -2 TA=25 C R JA=40 C/W Single Pulse 10 -1 10 0 10 1 10 -2 10 2 Qg, Total Gate Charge (nC) VDS, Drain-Source Voltage (V) Figure 9. Gate Charge 6-70 Figure 10. Maximum Safe Operating Area CED71A3/CEU71A3 4 V IN D VGS RGEN G 90% VDD t on RL VOUT VOUT 10% toff tr 90% td(on) td(off) 90% 10% tf INVERTED 6 S VIN 50% 10% 50% PULSE WIDTH Figure 11. Switching Test Circuit Figure 12. Switching Waveforms 10 0 r(t),Normalized Effective Transient Thermal Impedance D=0.5 0.2 10 -1 0.1 0.05 0.02 PDM t1 0.01 t2 1. R JA (t)=r (t) * R JA 2. R JA=See Datasheet 3. TJM-TA = P* R JA (t) 4. Duty Cycle, D=t1/t2 10 -2 10 -2 Single Pulse -3 10 10 -4 10 -3 10 -1 10 0 10 1 10 2 Square Wave Pulse Duration (sec) Figure 13. Normalized Thermal Transient Impedance Curve 6-71 |
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