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Cable Equalizer with 2-system Switching Function
CXB1441R
Description
The CXB1441R is a cable equalizer that compensates the attenuation resulting from cable transfer of smallamplitude differential NRZ signals. This chip has two sets of input ports comprising three pairs of differential data signals and one pair of differential clock signals. It equalizes and quantizes the signals from the optional ports and then outputs the signal from the output ports. NRZ signals from 250Mb/s to 1.65Gb/s are supported. (Applications: High-speed digital video signal switching and compensation of cable attenuation)
Features
Two sets of input ports comprising three pairs of differential data signals and one pair of differential clock signals 50 termination pull-up resistors built into differential data and clock inputs Low differential data and clock input capacitance facilitates the design and manufacture of TDR standard compatible equipment Equalizer circuit that compensates cable attenuation improves the signal eye pattern Output 50 load drive, voltage amplitude 0.5Vp-p Single +3.3V power supply Low power consumption Lead-free 48-pin plastic LQFP package (7mm x 7mm)
Package
48-pin LQFP (Plastic)
Absolute Maximum Ratings
Supply voltage Storage temperature VCC Tstg -0.3 to +4.0 -65 to +150 V
C
Recommended Operating Conditions
Supply voltage Operating temperature VCC Ta 3.135 to 3.465 -20 to +75 V
C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E05516-PS
CXB1441R
Pin Configuration
ADT1N
ADT0N
ADT1P
ADT0P
ACKP
SEL
ACKN
GND
GND
VCC
VCC 26
36 VCC 37 VCC 38 ADT2N 39 ADT2P 40 GND 41 VCC 42 VCC 43 GND 44 BCKN 45 BCKP 46 VCC 47 VCC 48
35
34
33
32
31
30
29
28
27
25 24 YCKN 23 YCKP 22 GND 21 YDT0N 20 YDT0P 19 VCC 18 VCC 17 YDT1N 16 YDT1P 15 GND 14 YDT2N 13 YDT2P
1 TEST
2 VCC
3 BDT0N
4 BDT0P
5 GND
6 BDT1N
7 BDT1P
8 GND
9 BDT2N
10 BDT2P
11 VCC
12 REXT
-2-
CE
CXB1441R
Pin Description
Pin No. 2, 11, 18, 19, 26, 35, 37, 38, 42, 43, 47, 48 Symbol Type Equivalent circuit
Vcc
Description
VCC
Power supply
GND
Power supply. Connect to 3.3V 5%.
Vcc
5, 8, 15, 22, 29, 32, 41, 44
GND
GND
GND. Connect to 0V.
GND
Vcc
28
ACKP Differential input
ACKP 28 ACKN 27
A port differential clock input.
27
ACKN
GND
Vcc
31
ADT0P Differential input
ADT0P 31 ADT0N 30
A port differential data input 0.
30
ADT0N
GND
Vcc
34
ADT1P Differential input
ADT1P 34 ADT1N 33
A port differential data input 1.
33
ADT1N
GND
Vcc
40
ADT2P Differential input
ADT2P 40 ADT2N 39
A port differential data input 2.
39
ADT2N
GND
-3-
CXB1441R
Pin No.
Symbol
Type
Equivalent circuit
Vcc
Description
46
BCKP Differential input
BCKP 46 BCKN 45
B port differential clock input.
45
BCKN
GND
Vcc
4
BDT0P Differential input
BDT0P 4 BDT0N 3
B port differential data input 0.
3
BDT0N
GND
Vcc
7
BDT1P Differential input
BDT1P 7 BDT1N 6
B port differential data input 1.
6
BDT1N
GND
Vcc
10
BDT2P Differential input
BDT2P 10 BDT2N 9
B port differential data input 2.
9
BDT2N
GND
Vcc
CE
25
CE
CMOS in
25
Chip enabled by High input.
GND
Vcc
SEL
36
SEL
CMOS in
36
A ports selected by High input, B ports selected by Low input.
GND
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CXB1441R
Pin No.
Symbol
Type
Equivalent circuit
Vcc
Description
REXT
12
REXT
Analog
12
Connect to GND through a 4.7k 1% input impedance adjusting resistor.
GND
Vcc
TEST
1
TEST
CMOS in
1
Test function control. Fix Low.
GND Vcc
23
YCKP Differential output
YCKP 23 YCKN 24
Differential clock output.
24
YCKN
GND
Vcc
20
YDT0P Differential output
YDT0P 20 YDT0N 21
Differential data output 0.
21
YDT0N
GND
Vcc
16
YDT1P Differential output
YDT1P 16 YDT1N 17
Differential data output 1.
17
YDT1N
GND
Vcc
13
YDT2P Differential output
YDT2P 13 YDT2N 14
Differential data output 2.
14
YDT2N
GND
-5-
CXB1441R
Electrical Characteristics
DC characteristics
(Under the recommended operating conditions) Item CMOS input High level voltage CMOS input Low level voltage CMOS input High level current CMOS input Low level current Differential input pin resistance relative to VCC Differential input dynamic range Differential output High level current Differential output Low level current Supply current (operating) Supply current (standby)
*1
Symbol VIH_M VIL_M IIH_M IIL_M RTERM VI IOH IOL ICC Istby
Min. VCC - 0.5 -0.3
Typ.
Max. VCC + 0.3 0.5 1
Unit V V A A
Remarks
@VIN = VCC @VIN = 0 @CE = VCC, IIN = -10mA, *1
-1 45 VCC - 0.8 0 8 110 10 50 55 VCC + 0.2 0.05 12 165 30
V mA mA mA A
CE = H, differential input open CE = L, differential input open
The resistance value when CE = Low is 55 (typ.).
AC Characteristics
(Under the recommended operating conditions) Item Clock frequency Symbol fCK Min. 25 5 Maximum equalizer gain G_EQ 6 9 12 Differential data and clock output rise/fall time Tr Tf 150 150 Typ. Max. 165 Unit MHz dB dB dB dB ns ns Remarks 1/10 the differential data rate @125MHz @200MHz @400MHz @740MHz 20 to 80% 80 to 20%
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CXB1441R
Electrical Characteristics Measurement Circuit
Video Data Generator
A/B input selection signal Chip enable signal 36 SEL 37 Vcc 38 Vcc 39 ADT2N 40 ADT2P 41 GND 42 Vcc 43 Vcc 44 GND 45 BCKN 46 BCKP 47 Vcc BDT0N BDT1N BDT2N BDT0P BDT1P TEST 48 Vcc BDT2P CXB1441R 35 Vcc 34 ADT1P 33 ADT1N 32 GND 31 ADT0P 30 ADT0N 29 GND 28 ACKP 27 ACKN 26 Vcc 25 CE YCKN 24
YCKP 23 GND 22 YDT0N 21 YDT0P 20 Vcc 19 Vcc 18 YDT1N 17 YDT1P 16 GND 15 YDT2N 14 REXT YDT2P 13 Vcc Logic Analyzer
GND
1
2
3
4
5
6
7
GND
Vcc
8
9
10
11
12 Vcc 3.3V 0.1F x4 to 5 33F
REXT 4.7k
Video Data Generator
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CXB1441R
Description of Functions
The CXB1441R has two sets of input ports comprising three pairs of differential data signals and one pair of differential clock signals. The A ports are selected when a High signal is applied to the CMOS input pin SEL, and the B ports are selected when a Low signal is applied. Shaping is performed by the equalizer to compensate the signal deterioration of the selected port data signals and clock signals caused by transfer cable attenuation, and then these signals are quantized and reproduced on the output ports. The CXB1441R inputs have built-in 50 pull-up resistors that act as transfer termination resistors, and parasitic capacitance is suppressed to a level that does not deteriorate the TDR characteristics of the equipment. The outputs employ a 10mA differential current output format in order to drive external 50 pull-up resistors. This output current is driven only when a High signal is applied to the CMOS input pin CE and the clock signal of the selected input port is in differential mode. When a Low signal is applied to the CMOS input pin CE, the CXB1441R enters standby mode to reduce the power consumption. The CXB1441R can be controlled by operating only the CMOS input pins CE and SEL.
Termination Input switching circuit resistor ADTnP ADTnN Equalizer BDTnP BDTnN Quantizer Output buffer YDTnP YDTnN
n = 1, 2, 3 Termination resistor ACKP ACKN Equalizer BCKP BCKN SEL Clock Detector Quantizer Output buffer YCKP YCKN Input switching circuit
Output Current Control Circuit
REXT
CE
Function Block Diagram
-8-
CXB1441R
Application Circuit
A/B input selection signal Receptacle A 36 ESD protective device SEL 37 Vcc 38 Vcc 39 ADT2N 40 ADT2P 41 GND 42 Vcc 43 Vcc 44 GND 45 BCKN 46 BCKP 47 Vcc BDT0N BDT1N BDT0P BDT1P BDT2P TEST 48 Vcc ESD protective device Receptacle B REXT 4.7k 0.1F x4 to 5 33F BDT2N CXB1441R 35 Vcc 34 ADT1P 33 ADT1N 32 GND 31 ADT0P 30 ADT0N 29 GND 28 ACKP 27 ACKN 26 Vcc 25 CE 24 Chip enable signal
YCKN
YCKP 23 GND 22 YDT0N 21 YDT0P 20 Vcc 19 Vcc 18 YDT1N 17 YDT1P 16 GND 15 YDT2N 14 REXT YDT2P 13 Vcc Frame internal wiring Cable/FPC receptacle
GND
1
2
3
4
5
6
7
GND
Vcc
8
9
10
11
12 Vcc 3.3V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
-9-
CXB1441R
Equalizer Characteristics
Example of cable jitter improvement effects
0.8 Without CXB1441R With CXB1441R Without CXB1441R With CXB1441R Without CXB1441R With CXB1441R Clock = 27MHz Clock = 27MHz Clock = 74MHz Clock = 74MHz Clock = 148MHz Clock = 148MHz
0.7
0.6
Standardized cable jitter
0.5
0.4
0.3
0.2
0.1
0 0 5 10 15 20 25 30 35 40 45 50 Cable length [m]
Notes On Handling
The guideline for cable attenuation that can be compensated by the equalizer is the maximum equalizer gain. However, this rule does not apply when skin effects cause the attenuation characteristics to deviate greatly from the square root of the frequency response, or for cables with a large skew.
- 10 -
CXB1441R
Package Outline
(Unit: mm)
48PIN LQFP (PLASTIC)
9.0 0.2 36 37 7.0 0.1 25 24 S
(8.0)
A 48 1 0.5 b + 0.2 1.5 - 0.1 12 13
B
(0.22)
0.13 M
0.1 0.1 0.1
0.5 0.2
S
b =0.18 0.03
0 to 10
0.5 0.2
DETAIL B: PALLADIUM DETAIL A NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 P-LQFP48-7x7-0.5 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.2g
- 11 -
0.127 0.04
Sony Corporation

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