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ISL8118
Data Sheet August 1, 2006 FN6325.0
3.3V to 20V, Single-Phase PWM Controller with Integrated 2A/4A MOSFET Drivers
The ISL8118 is a single-phase PWM controller featuring an input voltage range of +3.3V to +20V and integrated MOSFET drivers. Utilizing voltage-mode operation with input voltage feed-forward compensation, the ISL8118 maintains a constant loop gain, providing optimal transient response for applications with a wide input operating voltage range. The output voltage can be precisely regulated down to 0.591V with a system tolerance of 0.85% over the commercial temperature range and line and load variations. A external reference input is provided to bypass the internal reference for voltage tracking or DDR memory applications. The compact 28 Ld 5x5 QFN package, integrated linear regulator as well as the external linear regulator drive option, integrated differential remote sense amplifier and integrated voltage margining with adjustable upper and lower settings decrease external component count and reduce board space requirements. Programmable soft-start with pre-biased load capability, adjustable operating frequency from 250kHz to 2MHz, sourcing and sinking overcurrent protection, overvoltage and undervoltage protection, and power-good indication with programmable delay combine to make the ISL8118 a superior choice for many power supply systems.
Features
* Wide Input Voltage Range: +3.3V to +20V * High-Speed 2A/4A MOSFET Gate Drivers That Operate from 2.9V to 5.6V * 0.591V Internal Reference * External Reference Input * Input Voltage Feed-forward Compensation * Internal Linear Regulator * External Linear Regulator Drive Available * High System Accuracy: - 0.85% over the range of 0C to +70C - 1.25% over the range of -40C to +85C * Programmable Operating Frequency from 250kHz to 2MHz * Programmable Soft-Start with Pre-biased Load Capability * Integrated Unity-Gain Differential Remote Sense Amplifier * Enable Input with Voltage Monitoring Capability * Integrated Voltage Margining with Independent Upper and Lower Settings * Overvoltage and Undervoltage Protection * Low-Side and High-Side MOSFET Current Sensing * Overcurrent Protection for Sourcing and Sinking Currents * Power-Good Indicator with Programmable Delay * Compact 28 Ld 5x5 QFN Package * Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
ISL8118 (28 LD 5x5 QFN) TOP VIEW
COMP VDIFF BSOC FSET TSOC GND
Applications
* Telecom and Datacom Servers * Point of Load Modules * Routers and Switchers * High Current Distributed Power Supplies
21 20 19 BOOT TGATE LX PGND BGATE PVCC EXDRV
28 VSENSP VSENSN REFOUT REFIN SS OFSP OFSN 1 2 3
27
26
FB
25
24
23
22
Ordering Information
PART NUMBER* (Note) PART MARKING TEMP. RANGE (C) 0 to 70 -40 to 85 PACKAGE (Pb-Free) PKG. DWG. #
GND 4 5 6 7 8 VCC 9 MARGIN 10 PGDLY 11 PGOOD 12 EN 13 VFF 14 VIN BOTTOM SIDE PAD 18 17 16 15
ISL8118CRZ ISL8118CRZ ISL8118IRZ ISL8118IRZ
28 Ld 5x5 QFN L28.5x5 28 Ld 5x5 QFN L28.5x5
*Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
Block Diagram
EN VCC VIN EXDRV
POWER-ON REFIN REFERENCE VREF = 0.591V RESET (POR) INTERNAL SERIES LINEAR EXTERNAL SERIES LINEAR DRIVER TSOC REFOUT
2
100A MARGIN OFSP OFSN SOFT-START AND FAULT LOGIC OTA BOOT SOURCE OCP TGATE VOLTAGE MARGINING SS FB COMP PVCC VCC 800mV OV/UV COMP SOURCE OCP PGND PGOOD COMP VSENSP G = -1 VSENSN G=1 UNITY GAIN DIFF AMP 100A SINKING OCP GND GND OSCILLATOR BGATE PWM COMP
ISL8118
EA
GATE CONTROL LOGIC
LX
VDIFF
FN6325.0 August 1, 2006
PGDLY PGOOD
BSOC
VFF
FSET
ISL8118 Typical Application I (Internal Linear Regulator with Remote Sense)
+3.3V to +20V RCC LIN CF2 CF1 VCC VIN VFF CF3 CTSOC TGATE VCC EN REFIN REFOUT PGOOD CPGDLY PGDLY FSET LX CHFOUT BGATE PGND Q2 RBSOC 10 10 CBOUT Q1 LOUT VOUT Internal 5.6V Bias Linear Regulator PVCC BOOT TSOC RTSOC CBOOT RBOOT DBOOT CHFIN CBIN
ISL8118
BSOC
RFSET
CBSOC COMP C2 C1 ZFB R2 FB R1
C3
R3 ZIN
MARGIN ROFSP OFSP RMARG ROFSN OFSN
VDIFF VSENSP CSEN ROS VSENSN EXDRV GND GND VSENSERFB VSENSE+
SS CSS
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ISL8118 Typical Application II (External Linear Regulator without Remote Sense)
+3.3V to +20V LIN CF2 CLC RLC CF1 RCC VCC PVCC BOOT EXDRV TSOC VIN CF3 VFF VCC REFOUT REFIN EN PGOOD CPGDLY PGDLY FSET COMP LX BGATE PGND Q2 CHFOUT CBOUT TGATE CTSOC Q1 LOUT VOUT RTSOC CBOOT RBOOT DBOOT CHFIN CBIN
RDRV
ISL8118
BSOC
RBSOC
RFSET
CBSOC C2
ZFB C1 MARGIN ROFSP OFSP FB
C3
R3 ZIN R1
R2
RMARG ROFSN OFSN
VDIFF VCC VSENSP SS
ROS
Rvdiff1 VSENSN GND GND RvdiffOS
CSS
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ISL8118 Typical Application III (Dual Data Rate I or II)
VDDQ 1.8V or 2.5V LIN 5V RCC CF2 CF1 VIN REN1 VFF EN REN2 CF4 TGATE 1K REFIN 15nF REFOUT 1K DIMM PGOOD CPGDLY PGDLY FSET LX CHFOUT BGATE PGND Q2 RBSOC CBOUT VCC PVCC BOOT TSOC RTSOC CBOOT CTSOC Q1 LOUT VTT 1.25V (DDR I) 0.9V (DDR II) DBOOT CHFIN CBIN
ISL8118
BSOC
RFSET
COMP
CBSOC C2
ZFB C1 MARGIN ROFSP OFSP FB VDIFF RMARG ROFSN VSENSP OFSN VSENSN SS CSS EXDRV GND GND
C3
R3
R2 R1
ZIN
RFB CSEN
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ISL8118
Absolute Maximum Ratings
Input Voltage, VIN, VFF . . . . . . . . . . . . . . . . . . . . . . -0.3V to +22.0V Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +36V LX Voltage, VLX . . . . . . . . . . . . . . . . . VBOOT - 6V to VBOOT + 0.3V Boot to LX Voltage, VBOOT - VLX . . . . . . . . . . . . . . . . . . . . . . . . .6V Other Input or Output Voltages . . . . . . . . . . . . . -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Notes 1, 2) JA (C/W) JC (C/W) QFN Package . . . . . . . . . . . . . . . . . . 32 5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C
Recommended Operating Conditions
Input Voltage, VIN, VFF . . . . . . . . . . . . . . . . . . . . 3.3V to 20V 10% Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . 2.9V to 5.6V Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . 2.9V to 5.6V Boot to LX Voltage (Overcharged), VBOOT - VLX . . . . . . . . . . . .<6V Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-40C to 85C Junction Temperature Range. . . . . . . . . . . . . . . . . . .-40C to 125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. 2. JC, "case temperature" location is at the center of the package underside exposed pad. See Tech Brief TB379 for details. 3. Test conditions identified as "GBD" are guaranteed by design simulation.
Electrical Specifications
PARAMETER INPUT SUPPLY CURRENTS Nominal Vin Supply Current Nominal VCC Supply Current Nominal PVCC Supply Current Shutdown VIN Supply Current Shutdown VCC Supply Current Shutdown PVCC Supply Current ENABLE Input Reference Voltage Hysteresis Source Current Maximum Input Voltage OSCILLATOR Nominal Frequency Range Total Variation
Recommended Operating Conditions, Unless Otherwise Noted SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
IVIN IVCC IPVCC IVIN_S IPVCC_S IVCC_S VEN_REF IEN_HYS VEN
VIN = VCC = PVCC = 5V; Fs = 600kHz, TGATE and BGATE Open VIN = VCC = PVCC = 5V, Fs = 600kHz, TGATE and BGATE Open VIN = VCC = PVCC = 5V; Fs = 600kHz, TGATE and BGATE Open EN = 0V, VCC = PVCC = VIN = 5V EN = 0V, VCC = PVCC = VIN = 5V EN = 0V, VCC = PVCC = VIN = 5V
-
1 8 5 1 7 1
-
mA mA mA mA mA mA
0.480 7 -
0.496 10 VCC+0.3
0.512 15 -
V A V
OSCRANGE OSCCOM OSCIND VOSC VOSC_MIN VFF
GBD FSET = 250kHz, 600kHz, VFF = 3.3V to 20V FSET = 250kHz, 600kHz, VFF = 3.3V to 20V
250 -17 -22 -
0.16*VFF 1.0 3.3
2000 +17 +22 -
kHz % % VP-P V V
Ramp Amplitude Ramp Bottom Minimum Usable VFF Voltage POWER-ON RESET Rising VCC Threshold Falling VCC Threshold
VCC = 5V
-
PORVCC_R PORVCC_F
2.58
-
2.90 -
V V
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ISL8118
Electrical Specifications
PARAMETER VCC Hysteresis Rising PVCC Threshold Falling PVCC Threshold PVCC Hysteresis Rising VFF Threshold Falling VFF Threshold VFF Hysteresis REFERENCE Reference Voltage VREF_COM VREF_IND System Accuracy VSYS_COM VSYS_IND REFERENCE TRACKING Input Voltage Range External Reference Offset Maximum Drive Current Output Voltage Range Maximum Output Voltage Offset Minimum Load Capacitance Input Disable Voltage ERROR AMPLIFIER DC Gain Unity Gain-Bandwidth Slew Rate DIFFERENTIAL AMPLIFIER DC Gain Unity Gain Bandwidth Slew Rate Offset Negative Input Source Current Input Common Mode Range Max Input Common Mode Range Min VSENSN Disable Voltage VVSEN_DIS CSS = 0.1F, at SS Pin CSS = 0.1F, at SS Pin Leading and Trailing-edge Modulation Leading and Trailing-edge Modulation IVSENSN UG UGBW SR COMP = 10pF Standard Instrumentation Amplifier -3 0 20 10 0 6 VCC-1.8 -0.2 VCC 3 dB MHz V/s mV A V V V UGBW SR RL = 10k, CL = 100p, at COMP Pin RL = 10k, CL = 100p, at COMP Pin RL = 10k, CL = 100p, at COMP Pin 88 15 6 dB MHz V/s VREFIN VREFIN_OS IREFOUT VREFOUT VREFOUT_OS CREFOUT_MIN VREFIN_DIS REFIN = 0.6V CL = 1F, VCC = 5V, REFOUT = 1.25V CL = 1F CL = 1F REFOUT = 1.25V REFOUT = 1.25V 0.07 -1.2 0.01 -6 0 19 1.0 VCC VCC-1.8V 1.8 VCC-1.8V 9 V mV mA V mV F V TA = 0C to 70C TA = -40C to 85C TA = 0C to 70C TA = -40C to 85C 0.586 0.584 -0.85 -1.20 0.591 0.591 0.595 0.596 0.70 0.85 V V % % Recommended Operating Conditions, Unless Otherwise Noted (Continued) SYMBOL PORVCC_H PORPVCC_R PORPVCC_F PORPVCC_H PORVFF_R PORVFF_F PORVFF_H TEST CONDITIONS MIN 184 2.58 187 1.35 124 TYP 202 204 135 MAX 217 2.90 223 1.54 146 UNITS mV V V mV V V mV
OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA) DC Gain Drive Capability PWM Maximum Duty Cycle Minimum Duty Cycle GATE DRIVERS TGATE Source Resistance RTGATE 500mA Source Current, PVCC = 5.0V 1.0 DMAX DMIN 100 0 % % 28 88 38 50 dB A
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ISL8118
Electrical Specifications
PARAMETER TGATE Source Saturation Current TGATE Sink Resistance TGATE Sink Saturation Current Bgate Source Resistance Bgate Source Saturation Current Bgate Sink Resistance Bgate Sink Saturation Current INTERNAL LINEAR REGULATOR Maximum Current Saturated Equivalent Impedance Linear Regulator Voltage EXTERNAL LINEAR REGULATOR Maximum Sinking Drive Current OVERCURRENT PROTECTION (OCP) Bottom Side OCP (BSOC) Current Source BSOC Maximum Offset Error Top Side OCP (TSOC) Current Source IBSOC BSOC = 0V to Vcc - 1.0V, TA = 0C to 70C BSOC = 0V to Vcc - 1.0V, TA = -40C to 85C IBSOC_OFSET ITSOC Vcc = 2.9V and 5.6V TSAMPLE < 10s TSOC = 0.8V to 22V TA = 0C to 70C TSOC = 0.8V to 22V TA = -40C to 85C ITSOC_LOW TSOC Maximum Offset Error POWER GOOD MONITOR Undervoltage Rising Trip Point Undervoltage Falling Trip Point Overvoltage Rising Trip Point Overvoltage Falling Trip Point PGOOD Delay PGOOD Delay Source Current PGOOD Delay Threshold Voltage PGOOD Low Output Voltage Maximum Sinking Current Maximum Open Drain Voltage MARGINING CONTROL Minimum Margining Voltage of Internal Reference Maximum Margining Voltage of Internal Reference Margining Transfer Ratio Positive Margining Threshold Negative Margining Threshold Tri-state Input Level VMARG VMARG NMARG
MARGIN MARGIN MARGIN
VUVR VUVF VOVR VOVF TPGDLY IPGDLY VPGDLY IPG_LOW IPG_MAX VPG_MAX
Recommended Operating Conditions, Unless Otherwise Noted (Continued) SYMBOL ITGATE RTGATE ITGATE RBGATE IBGATE RBGATE IBGATE TEST CONDITIONS VTGATE-LX = 2.5V, PVCC = 5.0V 500mA Sink Current, PVCC = 5.0V VTGATE-LX = 2.5V, PVCC = 5.0V 500mA Source Current, PVCC = 5.0V VBGATE = 2.5V, PVCC = 5.0V 500mA Sink Current, PVCC = 5.0V VBGATE = 2.5V, PVCC = 5.0V MIN TYP 2.0 1.0 2.0 1.0 2.0 0.4 4.0 MAX UNITS A A A A
IVIN RLIN
PVCC
VIN = 3.3V VIN = 22V, Load = 0 to 100mA 5.42
200 2 5.6
3.25 5.72
mA V
EXDRV
0.25
-
0.9
mA
79 76 92 92 86 -
98 98 2 100 100 2
118 122 112 115 115 -
A A mV A
TSOC = 0.3V to 0.8V VCC = 2.9V and 5.5V TSAMPLE < 10s
A mV
ITSOC_OFSET
-7% -13% 13% 7% CPGDLY = 0.1F 27 1.44 IPGOOD = 5mA VPGOOD = 0.8V VCC = 3.3V 10 -
-9% -15% 15% 9% 5 30 1.48 6
-11% -17% 17% 11% 33 1.56 0.200 -
VSS VSS VSS VSS ms A V V mA V
RMARG = 10k, ROFSN = 6.01k, MAR_CRTL = 0V RMARG = 10k, ROFSP = 6.01k, MAR_CRTL = VCC NMARG = (VOFSN-VOFSP)/VMARG
-185 185 4.9 -
-197 197 5 1.5 0.8 1.325
-208 208 5.1 -
mV mV
V V V
Disable Mode
-
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FN6325.0 August 1, 2006
ISL8118 Functional Pin Description
VSENSP (Pin 1)
This pin provides differential remote sense for the ISL8118. It is the positive input of a standard instrumentation amplifier topology with unity gain, and should connect to the positive rail of the load/processor. The voltage at this pin should be set equal to the internal system reference voltage (0.591V typical.)
OFSN (Pin 7)
This pin sets the negative margining offset voltage. Resistors should be connected to GND (ROFSN) and OFSP (RMARG) from this pin. With MARGIN logic low, the internal 0.591V reference is developed at the OFSN pin across resistor ROFSN. The voltage on OFSN is driven from OFSP through RMARG. The resulting voltage differential between OFSP and OFSN is divided by 5 and imposed on the system reference. The maximum designed offset of -1V between OFSP and OFSN pins translates to a -200mV offset of the system reference.
VSENSN (Pin 2)
This pin provides differential remote sense for the regulator. It is the negative input of the instrumentation amplifier, and should connect to the negative rail of the load/processor. Typically 6A is sourced from this pin. The output of the remote sense buffer is disabled (High Impedance) by pulling VSENSN to VCC.
VCC (Pin 8, Analog Circuit Bias)
This pin provides power for the ISL8118 analog circuitry. The pin should be connected to a 2.9V to 5.6V bias through an RC filter from PVCC to prevent noise injection into the analog circuitry. This pin can be powered off the internal or external linear regulator options.
REFOUT (Pin 3)
This pin connects to the unmargined system reference through an internal buffer. It has a 19mA drive capability with an output common mode range of GND to VCC. The REFOUT buffer requires at least 1F of capacitive loading to be stable. This pin should not be left floating.
MARGIN (Pin 9)
The MARGIN pin controls margining function, a logic high enables positive margining, a logic low sets negative margining, a high impedance disables margining.
REFIN (Pin 4)
When the external reference pin (REFIN) is NOT within ~800mV of VCC, the REFIN pin is used as the system reference instead of the internal 0.591V reference. The recommended REFIN input voltage range is ~60mV to VCC - 1.8V.
PGDLY (Pin 10)
Provides the ability to delay the output of the PGOOD assertion by connecting a capacitor from this pin to GND. A 0.1F capacitor produces approximately a 5ms delay.
PGOOD (Pin 11)
Provides an open drain Power Good signal when the output is within 9% of nominal output regulation point with 6% hysteresis (15%/9%), and after soft-start is complete. PGOOD monitors the VDIFF pin.
SS (Pin 5)
This pin provides softstart functionality for the ISL8118. A capacitor connected to ground along with the internal 38A Operational Transconductance Amplifier (OTA), sets the soft-start interval of the converter. This pin is directly connected to the non-inverting input of the Error Amplifier. To prevent noise injection into the error amplifier the SS capacitor should be located within 150 mils of the SS and GND pins.
EN (Pin 12)
This pin is compared with an internal 0.49V reference and enables the soft-start cycle. This pin also can be used for voltage monitoring. A 10A current source to GND is active while the part is disabled, and is inactive when the part is enabled. This provides functionality for programmable hysteresis when the EN pin is used for voltage monitoring.
OFSP (Pin 6)
This pin sets the positive margining offset voltage. Resistors should be connected to GND (ROFSP) and OFSN (RMARG) from this pin. With MARGIN logic low, the internal 0.591V reference is developed at the OFSP pin across resistor ROFSP. The voltage on OFSP is driven from OFSN through RMARG. The resulting voltage differential between OFSP and OFSN is divided by 5 and imposed on the system reference. The maximum designed offset of 1V between OFSP and OFSN pins translates to a 200mV offset.
VFF (Pin 13)
The voltage at this pin is used for input voltage feed forward compensation and sets the internal oscillator ramp peak to peak amplitude at 0.16*VFF. An external RC filter may be required at this pin in noisy input environments. The minimum recommended VFF voltage is 2.97V.
VIN (Pin 14, Internal Linear Regulator Input)
This pin should be tied directly to the input rail when using the internal or external linear regulator options. It provides power to the External/Internal Linear drive circuitry. When used with an external 3.3V to 5V supply, this pin should be tied directly to PVCC.
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ISL8118
EXDRV (Pin 15, External Linear Regulator Drive)
This pin allows the use of an external pass element to power the IC for input voltages above 5.0V. It should be connected to GND when using an external 5V supply or the internal linear regulator. When using the external linear regulator option, this pin should be connected to the gate of a PMOS pass element, a pull-up resistor must be connected between the PMOS device's gate and source for proper operation.
TSOC (Pin 22)
The top side sourcing current limit is set by connecting this pin with a resistor and capacitor to the drain of the top side MOSEFT. A 100A current source develops a voltage across the resistor which is then compared with the voltage developed across the top side MOSFET. An initial ~120ns blanking period is used to eliminate sampling error due to the switching noise before the current is measured.
PVCC (Pin 16, Driver Bias Voltage)
This pin is the output of the internal series linear regulator. It also provides the bias for both bottom side and top side MOSFET drivers. The maximum voltage differential between PVCC and PGND is 6V. Its recommended operational voltage range is 2.9V to 5.6V. At minimum a 10F capacitor is required for decoupling PVCC to PGND. For proper operation the PVCC capacitor must be within 150 mils of the PVCC and the PGND pins and must be connected to these pins with dedicated traces.
BSOC (Pin 23)
The bottom side source and sinking current limit is set by placing a resistor (RBSOC) and capacitor between this pin and PGND. A 100A current source develops a voltage across RBSOC which is then compared with the voltage developed across the bottom side MOSFET when on. The sinking current limit is set at 1x of the nominal sourcing limit in ISL8118. An initial ~120ns blanking period is used to eliminate the sampling error due to switching noise before the current is measured.
BGATE (Pin 17)
This pin provides the drive for the bottom side MOSFET and should be connected to its gate.
FSET (Pin 24)
This pin provides oscillator switching frequency adjustment by placing a resistor (RFSET) from this pin to GND.
PGND (Pin 18, Power Ground)
This pin connects to the bottom side MOSFET's source and provides the ground return path for the lower MOSFET driver and internal power circuitries. In addition, PGND is the return path for the bottom side MOSFET's rDS(ON) current sensing circuit.
COMP (Pin 25)
This pin is the error amplifier output. It should be connected to the FB pin through the desired compensation network.
FB (Pin 26)
This pin is the inverting input of the error amplifier and has a maximum usable voltage of VCC-1.8V. When using the internal differential remote sense functionality, this pin should be connected to VDIFF by a standard feedback network. In the event the remote sense buffer is disabled, the VDIFF pin should be connected to VOUT by a resistor divider along with FB's compensation network.
LX (Pin 19)
This pin connects to the source of the top side MOSFET and the drain of the bottom side MOSFET. This pin represents the return path for the top side gate driver. During normal switching, this pin is used for top side and bottom side current sensing.
GND (Pin 27, Analog Ground)
Signal ground for the IC. All voltage levels are measured with respect to this pin. This pin should not be left floating.
TGATE (Pin 20)
This pin provides the drive for the top side MOSFET and should be connected to its gate.
VDIFF (Pin 28)
This pin is the output of the differential remote sense instrumentation amplifier. It is connected internally to the OV/UV/PGOOD comparators. The VDIFF pin should be connected to the FB pin by a standard feedback network. In the event of the remote sense buffer is disabled, the VDIFF pin should be connected to VOUT by a resistor divider along with FB's compensation network. An RC filter should be used if VDIFF is to be connected directly to FB instead of to VOUT through a separate resistor divider network.
BOOT (Pin 21)
This pin provides the bootstrap bias for the top side driver. The absolute maximum voltage differential between BOOT and LX is 6.0V (including the voltage added due to the overcharging of the bootstrap capacitor); its operational voltage range is 2.5V to 5.6V with respect to LX. It is recommended that a 2.2 resistor be placed in series with the bootstrap diode to prevent over charging of the BOOT capacitor during normal operation.
GND (Bottom Side Pad, Analog Ground)
Signal ground for the IC. All voltage levels are measured with respect to this pin. This pin should not be left floating.
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ISL8118 Functional Description
Initialization
The ISL8118 automatically initializes upon receipt of power without requiring any special sequencing of the input supplies. The Power-On Reset (POR) function continually monitors the input supply voltages (PVCC,VFF, VCC) and the voltage at the EN pin. Assuming the EN pin is pulled to above ~0.49V, the POR function initiates soft-start operation after all input supplies exceed their POR thresholds.
HIGH = ABOVE POR; LOW = BELOW POR VCC POR VFF POR PVCC POR EN POR AND SOFT-START
Soft-start
The POR function activates the internal 38A OTA which begins charging the external capacitor (CSS) on the SS pin to a target voltage of VCC. The ISL8118's soft-start logic continues to charge the SS pin until the voltage on COMP exceeds the bottom of the oscillator ramp, at which point, the driver outputs are enabled, with the bottom side MOSFET first being held low for 200ns to provide for charging of the bootstrap capacitor. Once the driver outputs are enabled, the OTA's target voltage is then changed to the margined (if margining is being used) reference voltage (VREF_MARG), and the SS pin is ramped up or down accordingly. This method reduces start-up surge currents due to a pre-charged output by inhibiting regulator switching until the control loop enters its linear region. By ramping the positive input of the error amplifier to VCC and then to VREF_MARG, it is even possible to mitigate surge currents from outputs that are pre-charged above the set output voltage. As the SS pin connects directly to the non-inverting input of the Error Amplifier, noise on this pin should be kept to a minimum through careful routing and part placement. To prevent noise injection into the error amplifier the SS capacitor should be located within 150 mils of the SS and GND pins. Soft-start is declared done when the drivers have been enabled and the SS pin is within 3mV of VREF_MARG.
FIGURE 1. SOFT-START INITIALIZATION LOGIC
With all input supplies above their POR thresholds, driving the EN pin above 0.49V initiates a soft-start cycle. In addition to normal TTL logic, the enable pin can be used as a voltage monitor with programmable hysteresis through the use of the internal 10A sink current and an external resistor divider. This feature is especially designed for applications that have input rails greater than a 3.3V and require specific input rail POR and Hysteresis levels for better undervoltage protection. Consider for a 12V application choosing RUP = 100k and RDOWN = 5.76k there by setting the rising threshold (VEN_RTH) to 10V and the falling threshold (VEN_FTH) to 9V, for 1V of hysteresis (VEN_HYS). Care should be taken to prevent the voltage at the EN pin from exceeding VCC when using the programmable UVLO functionality.
VIN RUP VREF
Power Good
The power good comparator references the voltage on the soft-start pin to prevent accidental tripping during margining. The trip points are shown on Figure 3. Additionally, power good will not be asserted until after the completion of the soft-start cycle. A 0.1F capacitor at the PGDLY pin will add an additional ~5ms delay to the assertion of power good. PGDLY does not delay the deassertion of power good.
VDIFF +15% +9%
Sys_Enable
VREF_MARG
RDOWN
-9% IEN_HYS=10A -15%
V EN_HYS R UP = ------------------------I EN_HYS R UP * V EN_REF R DOWN = -------------------------------------------------------V EN_FTH - V EN_REF V EN_FTH = V EN_RTH - V EN_HYS FIGURE 2. ENABLE POR CIRCUIT
GOOD UV OV
GOOD UV
FIGURE 3. UNDERVOLTAGE-OVERVOLTAGE WINDOW 1.5V T PGDLY = C PGDLY -------------30A
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ISL8118
Under and Overvoltage Protection
The Undervoltage (UV) and Overvoltage (OV) protection circuitry compares the voltage on the VDIFF pin with the reference that tracks with the margining circuitry to prevent accidental tripping. UV and OV functionality is not enabled until the end of soft-start. An OV event is detected asynchronously and causes the top side MOSFET to turn off, the bottom side MOSFET to turn on (effectively a 0% duty cycle), and PGOOD to pull low. The regulator stays in this state and overrides sourcing and sinking OCP protections until the OV event is cleared. A UV event is detected asynchronously and results in the PGOOD pulling low. The ISL8118's sinking current limit is set to the same voltage as its sourcing limit. In sinking applications, when the voltage across the MOSFET is greater than the voltage developed across the resistor (RBSOC) a sinking OCP event is triggered. To avoid non-synchronous operation at light load, the peak to peak output inductor ripple current should not be greater than twice of the sinking current limit. The top side sourcing current limit is set by connecting the TSOC pin with a resistor (RTSOC) and a capacitor to the drain of the top side MOSEFT. A 100A current source develops a voltage across the resistor which is then compared with the voltage developed across the top side MOSFET while on. When the voltage drop across the MOSFET exceeds the voltage drop across the resistor, a sourcing OCP event occurs. A 1000pF or greater filter capacitor should be used in parallel with RTSOC to prevent on chip parasitics from impacting the accuracy of the OCP measurement and to smooth the voltage across RTSOC in the presence of switching noise on the input bus. Sourcing OCP faults cause the regulator to disable (TGATE and BGATE drives pulled low, PGOOD pulled low, soft-start capacitor discharged) itself for a fixed period of time after which a normal soft-start sequence is initiated. The period of time the regulator waits before attempting a soft-start sequence is set by three charge and discharge cycles of the soft-start capacitor. Simple Top Side OCP Equation
I OC_SOURCE * r DS ( ON )T R TSOC = ------------------------------------------------------------------100A
Overcurrent Protection
The ISL8118 monitors both the top side MOSFET and bottom side MOSFET for overcurrent events. Dual sensing allows the ISL8118 to detect overcurrent faults at the very low and very high duty cycles that can result from the ISL8118's wide input range. The OCP function is enabled with the drivers at start-up and detects the peak current during each sensing period. A resistor and a capacitor between the BSOC pin and GND set the bottom side source and sinking current limits. A 100A current source develops a voltage across the resistor which is then compared with the voltage developed across the bottom side MOSFET at conduction mode. The measurement comparator uses offset correcting circuitry to provide precise current measurements with roughly 2mV of offset error. An ~120ns blanking period, implemented on the upper and lower MOSFET current sensing circuitries, is used to reduce the current sampling error due to the leading-edge switching noise. An additional 120ns low pass filter is used to further reduce measurement error due to noise. In sourcing current applications, the BSOC voltage is inverted and compared with the voltage across the MOSFET while on. When this voltage exceeds the BSOC set voltage, a sourcing OCP fault is triggered. A 1000pF or greater filter capacitor should be used in parallel with RBSOC to prevent on chip parasitics from impacting the accuracy of the OCP measurement. Simple Bottom Side OCP Equation
I OC_SOURCE * r DS ( ON )Botside R BSOC = -----------------------------------------------------------------------------------100A
Detailed Top Side OCP Equation
I I + ---- * r OC_SOURCE 2 DS ( ON )T R TSOC = -----------------------------------------------------------------------------------I TSOC * N T N T = Number of top side MOSFETs
Detailed Bottom Side OCP Equations
I I + ---- * r OC_SOURCE 2 DS ( ON )B R BSOC = ------------------------------------------------------------------------------------I BSOC * N B V IN - V OUT V OUT I = ------------------------------- * --------------FS L V IN I BSOC * N B * R BSOC I I OC_SINK = --------------------------------------------------------- - ---2 r DS ( ON )B N B = Number of Bottom side MOSFETs
Sinking OCP faults cause the bottom side MOSFET drive to be disabled, effectively operating the ISL8118 in a nonsynchronous manner. The fault is maintained for three clock cycles at which point it is cleared and normal operation is restored. OVP fault implementation overrides sourcing and sinking OCP events, immediately turning on the bottom side MOSFET and turning off the top side MOSFET. The OC trip point varies mainly due to the MOSFETs rDS(ON) variations and system noise. To avoid overcurrent tripping in the normal operating load range, find the RTSOC and/or RBSOC resistor from the previous detailed equations with: 1. Maximum rDS(ON) at the highest junction temperature; 2. Minimum IBSOC and/or ITSOC from specification table; 3. Determine the overcurrent trip point greater than the maximum output continuous current at maximum inductor ripple current.
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ISL8118
Frequency Programming
By tying a resistor to GND from FSET pin, the switching frequency can be set between 250kHz and 2MHz. linear regulator is to provide power for both the internal MOSFET drivers through the PVCC pin and the analog circuitry through the VCC pin. The VCC pin should be connected to the PVCC pin with an RC filter to prevent high frequency driver switching noise from entering the analog circuitry. When VIN drops below 5.6V, the pass element will saturate; PVCC will track VIN, minus the dropout of the linear regulator: PVCC = VIN-2xIVIN. When used with an external 5V supply, the VIN pin should be tied directly to PVCC.
Oscillator/VFF
The Oscillator is a triangle waveform, providing for leading and falling edge modulation. The bottom of the oscillator waveform is set at 1.0V. The ramp's peak to peak amplitude is determined from the voltage on the VFF (Voltage Feed Forward) pin by the equation: DVosc = 0.16*VFF. An internal RC filter of 233k and 2pF (341kHz) provides filtering of the VFF voltage. An external RC filter may be required to augment this filter in the event that it is insufficient to prevent noise injection or control loop interactions. Voltages below 2.9V on the VFF pin may result in undesirable operation due to extremely small peak to peak oscillator waveforms. The oscillator waveform should not exceed VCC -1.0V. For high VFF voltages the internal/external 5.6V linear regulator should be used. 5.6V on VCC provides sufficient headroom for 100% duty cycle operation when using the maximum VFF voltage of 22V. In the event of sustained 100% duty cycle operation, defined as 32 clock cycles where no BG pulse is detected, BG will be pulsed on to refresh the design's Bootstrap capacitor.
100
External Series Linear Regulator
The EXDRV pin provides sinking drive capability for an external pass element linear regulator controller. The external linear options are especially useful when the internal linear dropout is too large for a given application. When using the external linear regulator option, the EXDRV pin should be connected to the gate of a PMOS device, and a resistor should be connected between its gate and source. A resistor and a capacitor should be connected from gate to source to compensate the control loop. A PNP device can be used instead of a PMOS device in which case the EXDRV pin should be connected to the base of the PNP pass element. The maximum sinking capability of the EXDRV pin is 0.5mA, and should not be exceeded if using an external resistor for a PMOS device. The designer should take care in designing a stable system when using external pass elements. The VCC pin should be connected to the PVCC pin with an RC filter to prevent high frequency driver switching noise from entering the analog circuitry.
RESISTANCE (k)
10
High Speed MOSFET Gate Driver
The integrated driver has similar drive capability and features to Intersil's ISL6605 stand alone gate driver. The PWM tri-state feature helps prevent a negative transient on the output voltage when the output is being shut down. This eliminates the Schottky diode that is used in some systems for protecting the microprocessor from reversed-outputvoltage damage. See the ISL6605 datasheet for specification parameters that are not defined in the current ISL8118 electrical specifications table. A 1-2 resistor is recommended to be in series with the bootstrap diode when using VCCs above 5.0V to prevent the bootstrap capacitor from overcharging due to the negative swing of the trailing edge of the LX node.
1 100
1000
10000
FREQUENCY (kHz) FIGURE 4. RFS RESISTANCE vs FREQUENCY Fs [ Hz ] 1.178 x10
10
* RT [ ]
- 0.973
(R T TO GND)
Internal Series Linear Regulator
The VIN pin is connected to PVCC with a 2 internal series linear regulator, which is internally compensated. The external Series Linear regulator option should be used for applications requiring pass elements of less than 2. When using the internal regulator, the EXDRV pin should be connected directly to GND. The PVCC and VIN pins should have a bypasses capacitor (at least 10F on PVCC is required) connected to PGND. For proper operation the PVCC capacitor must be within 150 mils of the PVCC and the PGND pins, and be connected to these pins with dedicated traces. The internal series linear regulator's input (VIN) can range between 3.3V to 20V 10%. The internal
Margining Control
When MARGIN is pulled high or low, the positive or negative margining functionality is respectively enabled. When MARGIN is left floating, the function is disabled. Upon positive margining, an internal buffer drives the OFSN pin from VCC to maintain OFSP at 0.591V. The resistor divider, RMARG and ROFSP, causes the voltage at OFSN to be increased. Similarly, upon Negative margining, an internal buffer drives the OFSP pin from VCC to maintain OFSN at 0.591V. The resistor divider, RMARG and ROFSN, causes
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ISL8118
the voltage at OFSP to be increased. In both modes the voltage difference between OFSP and OFSN is then sensed with an instrumentation amplifier and is converted to the desired margining voltage by a 5:1 ratio. The maximum designed margining range of the ISL8118 is 200mV, this sets the MINIMUM value of ROFSP or ROFSN at approximately 5.9k for an RMARG of 10k for a MAXIMUM of 1V across RMARG. The OFS pins are completely independent and can be set to different margining levels. The maximum usable reference voltage for the ISL8118 is VCC - 1.8V, and should not be exceeded when using the margining functionality, i.e, VREF_MARG < VCC - 1.8V.
V REF R MARG V MARG_POS = -------------- * -------------------5 R OFSP V REF R MARG V MARG_NEG = -------------- * -------------------5 R OFSN
VCC REFERENCE VREF = 0.591V ISL8118 STATE MACHINE
REFIN 800mV
REFOUT
MARGINING BLOCK
VREF_MARG
OTA
FIGURE 5. SIMPLIFIED REFERENCE BUFFER
Internal Reference and System Accuracy
The internal reference is trimmed to 0.591V. The total DC system accuracy of the system is within 0.85% over commercial temperature range, and 1.25% over industrial temperature range. System accuracy includes error amplifier offset, OTA error, and bandgap error. Differential remote sense offset error is not included. As a result, if the differential remote sense is used, then an extra 3mV of offset error enters the system. The use of REFIN may add up to 1.8mV of additional offset error.
An alternative calculation provides for a desired percentage change in the output voltage when using the internal 0.591V reference:
R MARG V PCT_POS = 20 * -------------------R OFSP R MARG V PCT_NEG = 20 * -------------------R OFSN
When not used in a design OFSP, OFSN, and MARGIN should be left floating. To prevent damage to the part, OFSP and OFSN should not be tied to VCC or PVCC.
Differential Remote Sense Buffer
The differential remote sense buffer is essentially an instrumentation amplifier with unity gain. The offset is trimmed to 3mV for high system accuracy. As with any instrumentation amplifier typically 6A are sourced from the VSENSN pin. The output of the remote sense buffer is connected directly to the internal OV/UV comparator. As a result, a resistor divider should be placed on the input of the buffer for proper regulation, as shown in Figure 6. The VDIFF pin should be connected to the FB pin by a standard feed-back network. A small capacitor, CSEN in Figure 6, can be added to filter out noise, typically CSEN is chosen so the corresponding time constant does not reduce the overall phase margin of the design, typically this is 2x to 10x switching frequency of the regulator. As some applications will not use the differential remote sense, the output of the remote sense buffer can be disabled (high impedance) by pulling VSENSN within 800mV of VCC. As the VDIFF pin is connected internally to the OV/UV/PGOOD comparator, an external resistor divider must then be connected to VDIFF to provide correct voltage information for the OV/UV comparator. An RC filter should be used if VDIFF is to be connected directly to FB instead of to VOUT through a separate resistor divider network. This filter prevents noise injection from disturbing the OV/UV/PGOOD comparators on VDIFF. VDIFF may also be connected to the SS pin, which completely bypasses the OV/UV/PGOOD functionality.
Reference Output Buffer
The internal buffer's output tracks the unmargined system reference. It has a 19mA drive capability, with maximum and minimum output voltage capabilities of VCC and GND respectively. Its capacitive loading can range from 1F to above 17.6F, which is designed for 1 to 8 DIMM systems in DDR (Dual Data Rate) applications. 1F of capacitance should always be present on REFOUT. It is not designed to drive a resistive load and any such load added to the system should be kept above 300k total impedance.
Reference Input
The REFIN pin allows the user to bypass the internal 0.591V reference with an external reference. Asynchronously if REFIN is NOT within ~800mV of VCC, the external reference pin is used as the control reference instead of the internal 0.591V reference. The minimum usable REFIN voltage is ~60mV while the maximum is VCC - 1.8V - VMARG (if present). The limitation is set by the error amplifier's maximum common mode input range of VCC - 1.8V for the industrial temperature ranges.
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ISL8118
VSENSE(REMOTE) VOUT (LOCAL) 10 VSENSE+ (REMOTE)
GND (LOCAL)
10 ROS CSEN
RFB
ZIN VSENSP VDIFF FB
ZFB COMP
VCC
VSENSN
800mV GAIN = 1 VSS
OV/UV COMP
ERROR AMP
FIGURE 6. SIMPLIFIED UNITY GAIN DIFFERENITAL SENSING IMPLEMENTATION
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding.
VIN
components shown in Figure 8 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the ISL8118 within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs' gate and source connections from the ISL8118 must be sized to handle up to 4A peak current. Proper grounding of the IC is important for correct operation in noisy environments. The PGND pin should be connected to board ground at the source of the bottom side MOSFET with a wide short trace. The GND pin should be connected to a large copper fill under the IC which is subsequently connected to board ground at a quite location on the board, typically found at an input or output bulk (electrolytic) capacitor.
BOOT +VIN D1 Q1 LO VOUT LOAD
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ISL8118
TGATE LX CIN BGATE PGND Q2
Q1
LO
VOUT
CBOOT
ISL8118
CO LOAD SS
LX +5V PVCC Q2 CO
CSS GND RETURN
CPVCC
PGND
FIGURE 7. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS
FIGURE 8. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES
Figure 7 shows the critical power components of the converter. To minimize the voltage overshoot/undershoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The
Figure 8 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS pin and locate the capacitor, CSS
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ISL8118
close to the SS pin (as described earlier) as the internal current source is only 38A. Provide local decoupling between PVCC and PGND pins as described earlier. Locate the capacitor, CBOOT as close as practical to the BOOT and LX pins.
C2
COMP
R2 -
C1
R3
C3
Compensating the Converter
The ISL8118 single-phase converter is a voltage-mode controller. This section highlights the design considerations for a voltage-mode controller requiring external compensation. To address a broad range of applications, a type-3 feedback network is recommended (see Figure 9).
C2 R2 C1 E/A
FB + VREF VDIFF + VSENSP VSENSN
R1
RFB CSEN ROS
COMP FB
OSCILLATOR VIN PWM CIRCUIT VOSC L
VOUT
C3 R3 R1
ISL8118
VDIFF
TGATE HALF-BRIDGE DRIVE
DCR
LX
C ESR
FIGURE 9. COMPENSATION CONFIGURATION FOR ISL8118 WHEN USING DIFFERENTIAL REMOTE SENSE
BGATE
Figure 10 highlights the voltage-mode control loop for a synchronous-rectified buck converter, when using an internal differential remote sense amplifier. The output voltage (VOUT) is regulated to the reference voltage, VREF, level. The error amplifier output (COMP pin voltage) is compared with the oscillator (OSC) triangle wave to provide a pulse-width modulated wave with an amplitude of VIN at the LX node. The PWM wave is smoothed by the output filter (L and C). The output filter capacitor bank's equivalent series resistance is represented by the series resistor ESR. The modulator transfer function is the small-signal transfer function of VOUT /VCOMP. This function is dominated by a DC gain, given by dMAXVIN /VOSC, and shaped by the output filter, with a double pole break frequency at FLC and a zero at FCE . For the purpose of this analysis C and ESR represent the total output capacitance and its equivalent series resistance.
1 F LC = --------------------------2 L C 1 F CE = -------------------------------2 C ESR
ISL8118
EXTERNAL CIRCUIT
FIGURE 10. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN
The compensation network consists of the error amplifier (internal to the ISL8118) and the external R1-R3, C1-C3 components. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (F0; typically 0.1 to 0.3 of FSW) and adequate phase margin (better than 45). Phase margin is the difference between the closed loop phase at F0dB and 180. The equations that follow relate the compensation network's poles, zeros and gain to the components (R1 , R2 , R3 , C1 , C2 , and C3) in Figures 9 and 10. Use the following guidelines for locating the poles and zeros of the compensation network: 1. Select a value for R1 (1k to 10k, typically). Calculate value for R2 for desired converter bandwidth (F0). If setting the output voltage to be equal to the reference set voltage as shown in Figure 9, the design procedure can be followed as presented. However, when setting the output voltage via a resistor divider placed at the input of the differential amplifier (as shown in Figure 10), in order to compensate for the attenuation introduced by the resistor divider, the below obtained R2 value needs be multiplied by a factor of (ROS+RFB)/ROS. The remainder of the calculations remain unchanged, as long as the compensated R2 value is used.
V OSC R 1 F 0 R 2 = -------------------------------------------d MAX V IN F LC
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A small capacitor, CSEN in Figure 10, can be added to filter out noise, typically CSEN is chosen so the corresponding time constant does not reduce the overall phase margin of the design, typically this is 2x to 10x switching frequency of the regulator. As the ISL8118 supports 100% duty cycle, dMAX equals 1. The ISL8118 also uses feed-forward compensation, as such VOSC is equal to 0.16 multiplied by the voltage at the VFF pin. When tieing VFF to VIN the above equation simplifies to:
0.16 R 1 F 0 R 2 = ---------------------------------F LC
As before when tieing VFF to VIN terms in the above equations can be simplified as follows:
1 V IN d MAX V IN ----------------------------- = -------------------------- = 6.25 V OSC 0.16 V IN
COMPENSATION BREAK FREQUENCY EQUATIONS
1 F Z1 = -----------------------------2 R 2 C 1 1 F Z2 = ------------------------------------------------2 ( R 1 + R 3 ) C 3 1 F P1 = -------------------------------------------C1 C2 2 R 2 -------------------C1 + C2 1 F P2 = -----------------------------2 R 3 C 3
2. Calculate C1 such that FZ1 is placed at a fraction of the FLC, at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to desired number). The higher the quality factor of the output filter and/or the higher the ratio FCE/FLC, the lower the FZ1 frequency (to maximize phase boost at FLC).
1 C 1 = ---------------------------------------------2 R 2 0.5 F LC
3. Calculate C2 such that FP1 is placed at FCE.
C1 C 2 = ------------------------------------------------------2 R 2 C 1 F CE - 1
4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3 such that FP2 is placed below FSW (typically, 0.5 to 1.0 times FSW). FSW represents the regulator's switching frequency. Change the numerical factor to reflect desired placement of this pole. Placement of FP2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the HF ripple component at the COMP pin and minimizing resultant duty cycle jitter.
R1 R 3 = --------------------F SW ----------- - 1 F LC 1 C 3 = -----------------------------------------------2 R 3 0.7 F SW
Figure 11 shows an asymptotic plot of the DC/DC converter's gain vs. frequency. The actual modulator gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown. Using the above guidelines should yield a compensation gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 against the capabilities of the error amplifier. The closed loop gain, GCL, is constructed on the log-log graph of Figure 11 by adding the modulator gain, GMOD (in dB), to the feedback compensation gain, GFB (in dB). This is equivalent to multiplying the modulator transfer function and the compensation transfer function and then plotting the resulting gain.
FZ1 FZ2 GAIN FP1 FP2 MODULATOR GAIN COMPENSATION GAIN CLOSED LOOP GAIN OPEN LOOP E/A GAIN
R2 20 log ------- R1 0
d MAX V IN 20 log --------------------------------V OSC
GFB GCL
It is recommended that a mathematical model is used to plot the loop response. Check the loop gain against the error amplifier's open-loop gain. Verify phase margin results and adjust as necessary. The following equations describe the frequency response of the modulator (GMOD), feedback compensation (GFB) and closed-loop response (GCL):
d MAX V IN 1 + s ( f ) ESR C G MOD ( f ) = ----------------------------- ---------------------------------------------------------------------------------------------------------2 V OSC 1 + s ( f ) ( ESR + DCR ) C + s ( f ) L C 1 + s ( f ) R2 C1 G FB ( f ) = --------------------------------------------------- s ( f ) R1 ( C1 + C2 ) 1 + s ( f ) ( R1 + R3 ) C3 ----------------------------------------------------------------------------------------------------------------------- C1 C2 -------------------- ( 1 + s ( f ) R3 C3 ) 1 + s ( f ) R2 C 1 + C 2 G CL ( f ) = G MOD ( f ) G FB ( f ) where, s ( f ) = 2 f j
LOG
GMOD LOG FLC FCE F0 FREQUENCY
FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A stable control loop has a gain crossing with close to a -20dB/decade slope and a phase margin greater than 45. Include worst case component variations when determining phase margin. The mathematical model presented makes a number of approximations and is generally not accurate at frequencies approaching or exceeding half the switching frequency. When designing compensation networks, select target crossover frequencies in the range of 10% to 30% of the switching frequency, FSW.
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ISL8118 Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. For example, Intel recommends that the high frequency decoupling for the Pentium Pro be composed of at least forty (40) 1.0F ceramic capacitors in the 1206 surface-mount package. Follow on specifications have only increased the number and quality of required ceramic decoupling capacitors. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL8118 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load:
L O x I TRAN t RISE = ------------------------------V IN - V OUT L O x I TRAN t FALL = -----------------------------V OUT
where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a lower input source such as 1.8V or 3.3V, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately below.
I IN, RMS =
OR
Output Inductor Selection
The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations:
V IN - V OUT V OUT I = ------------------------------- * --------------FS x L V IN
I 2 2 I O ( D - D 2 ) + ------- D 12
VO D = ---------VIN
VOUT= I x ESR
I IN, RMS = K ICM * I O
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0.60 0.50
0.5Io
0.40
KICM
0.30
0.25Io
dissipation for both the top and the bottom MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equations below). The upper MOSFET exhibits turn-on and turn-off switching losses as well as the reverse recover loss, while the synchronous rectifier exhibits body-diode conduction losses during the leading and trailing edge dead times.
r DS ( ON )B I 2 P BOTTOM = I O 2 + ------- * ------------------------- * ( 1 - D ) + P DEAD N 12
B
0.20
I = 0Io
0.10 0.00 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
DUTY CYCLE (D)
I I P DEAD = I O + ----- * V DT * t DT + I O - ----- * V DB * t DB * F S 12 12 r DS ( ON ),T I 2 P TOP = I O 2 + ------- * --------------------------- * D + P SW + P Qrr - N 12
T
0.8 0.9
1
FIGURE 12. INPUT-CAPACITOR CURRENT MULTIPLIER FOR SINGLE-PHASE BUCK CONVERTER
I I P SW = I O + ----- * t OFF + I O - ----- * t ON * VIN * F S 12 12 P Qrr = Q rr * VIN * F S
For a through hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MVGX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested.
where D is the duty cycle = VO / VIN; Qrr is the reverse recover charge; tDLand tDT are leading and trailing edge dead time, and tON & tOFF are the switching intervals. These equations do not include the gate-charge losses that are proportional to the total gate charge and the switching frequency and partially dissipated by the internal gate resistance of the MOSFETs. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.
MOSFET Selection/Considerations
The ISL8118 requires 2 N-Channel power MOSFETs. These should be selected based upon rDS(ON), gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power
ISL8118 DC/DC Converter Application Circuit
Detailed information on the application circuit, including a complete Bill-of-Materials and circuit board description, can be found in application note AN1204. See Intersil's home page on the web: http://www.intersil.com.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 19
FN6325.0 August 1, 2006
ISL8118 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
2X A 9 D1 D1/2 6 INDEX AREA N 1 2 3 E1/2 E1 9 2X 0.15 C B 2X 0.15 C A 0 4X C TOP VIEW A2 A / / 0.10 C 0.08 C SIDE VIEW NX b 4X P D2 (DATUM B) 4X P 1 (DATUM A) 6 INDEX AREA NX L Ne 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 2 3 E2 7 E2/2 8 (Ne-1)Xe REF. D2 2N 5 0.10 M C A B 7 8 NX k A3 A1 9 B E/2 E 2X 0.15 C B D D/2 0.15 C A
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE I) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L N Nd Ne P 0.20 0.50 2.95 2.95 0.18 MIN 0.80 NOMINAL 0.90 0.02 0.65 0.20 REF 0.25 5.00 BSC 4.75 BSC 3.10 5.00 BSC 4.75 BSC 3.10 0.50 BSC 0.60 28 7 7 0.60 12 0.75 3.25 3.25 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5,8 9 7,8 9 7,8 8 2 3 3 9 9 Rev. 1 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.
SEATING PLANE
9 CORNER OPTION 4X
C L
SECTION "C-C" C L
8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation.
L1 e CC
10
L L1 e
10
L
TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE
20
FN6325.0 August 1, 2006

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