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M44C260/M48C260
MARC4 - 4-bit Microcontroller
The M44C260 and M48C260 are members of the TEMIC family of 4-bit single chip microcontrollers. The M48C260 is the user programmable version of the M44C260. It contains an EEPROM program memory instead of a ROM. Both microcontroller types contain RAM, EEPROM data memory, parallel I/O ports, one timer with watchdog function, two 8/16-bit multifunction timer/counter and the on-chip clock generation.
Features
D D D D D D D D D D
4-bit HARVARD architecture 1 s instruction cycle 4K 8-bit application program memory 256 4-bit RAM 16 8-bit EEPROM 16 bidirectional I/O's 8 hard and software interrupt levels 2 8-bit multifunction timer/counter Interval timer with watchdog 32 kHz on-chip oscillator
NWP VSS V DD NRST TE
Benefits
D Low power consumption D Power-down mode < 1 A D 2.4 to 6.2 V supply voltage D Self-test functions D High-level programming language in qFORTH D User programmable with the application program
TCL
OSCIN
OSCOUT
Reset
Test Sleep
Clock
ROM or EEPROM EEPROM 16 x 8 bit
4K x 8 bit
RAM
256 x 4 bit
Timer 1 Watchdog Intervall timer
Timer 2 Timer B
MARC4 4-bit CPU core
Timer A
I/O bus
I/O
I/O
I/O
I/O
Interrupt inputs
Input Port 4
INT6 Port 0 Port 1 Port 2 Port 3 IP43 TA TB
94 9038
IP40
Figure 1. Block diagram
Rev. A2, 01-Oct-98
1 (51)
M44C260/M48C260
BP02 1 BP03 2 NWP 3 TE
OSC OUT OSC IN VDD 4 5 6 7
28 BP01
27 BP00 26 BP33 25 BP32 24 BP31 BP02 1 BP03 2 TE 3 OSC OUT 4 OSC IN 5 VDD 6 NRST 7 BP20 8 BP10 9 BP11 10 20 BP01 19 BP00 18 BP31 17 BP30
M44C260 M48C260
23 BP30 22 VSS 21 TCL 20 IP40-INT6 19 IP41-TA 18 IP42-TB 17 IP43 16 BP13 15 BP12
94 9039
M44C260
16 VSS 15 TCL IP40 14 INT6- IP41 13 TA- 12 BP13 11 BP12
NRST 8 BP20
9
BP21 10 BP22 11 BP23 12
BP10 BP11 13 14
Figure 2. Pin connections for SSO28-FN Table 1. Pin description
Figure 3. Pin connections for SSO20
A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
VDD VSS BP00 - BP03 BP10 - BP13 BP20 - BP23 BP30 - BP33 IP40-INT6 IP41-TA IP42-TB IP43 NWP OSCIN OSCOUT NRST TCL TE Power supply voltage +2.4 to +6.2 V Circuit ground 4 bidirectional I/O lines of Port 0 * 4 bidirectional I/O lines of Port 1 * 4 bidirectional I/O lines of Port 2 4 bidirectional I/O lines of Port 3 with alternate interrupt function. A negative transition on BP30/BP31 requests an INT2-, and on BP32/BP33 an INT3-interrupt if the corresponding interrupt-mask is set. Input port 40 line/interrupt 6 input * A negative transition on this input requests an INT6 interrupt if the IM6 mask bit is set. Timer/counter I/O/Input Port 41 line * This line can be used as programmable I/O of counter A or as Port 41 input. Timer/counter I/O/input Port 42 line * This line can be used as programmable I/O of counter B or as Port 42 input. Input Port 43 line *) EEPROM write protect input, a logic low on this input protects EEPROM rows 12 to 15. Oscillator input (32-kHz crystal). Oscillator output (32-kHz crystal). Reset input/output, a logic low on this pin resets the device. An internal watchdog reset is indicated by a low level on this pin. External system clock I/O. This pin can be used as input to provide the mC with an external clock or as output of the internal system clock. Testmode input. This input is used to control the test modes and the function of the TCL pin.
*)
Name
Function
The I/O ports have CMOS output buffers. As input they are available with pull-up or pull-down resistors. Please see the ordering information.
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Rev. A2, 01-Oct-98
M44C260/M48C260
Contents
1 MARC4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Components of MARC4 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 Program Memory (ROM or EEPROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 Data Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4 ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.5 Self-Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.6 Instruction Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.7 I/O Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.8 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.1 Clock Status/Control Register (CSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 TCL Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Addressing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Input Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Bidirectional Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.3 External Interrupt Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 T1C - Timer 1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 WDC - Watchdog Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Timer 2 Status/Control Register (T2SC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Timer 2 Subport (T2SUB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 Timer 2 Reload Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4 Timer 2 Capture Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.5 Timer A Mode Register 1 (TAM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.6 Timer A Mode Register 2 (TAM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.7 Timer B Mode Register 1 (TBM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.8 Timer B Mode Register 2 (TBM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.9 Timer 2 Prescaler Control Register (T2PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.10 Timer 2 Interrupt Control Register (T2IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.11 Timer I/O (TA/TB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 EEPROM SubPort (ESUB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 EEPROM Mode/Status Register (EMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5 5 6 7 8 8 8 8 9 10 10 10 11 12 12 12 13 13 15 15 16 17 18 18 19 21 22 22 23 23 24 24 25 25 26 27 28 28 29 3 (51)
2
Rev. A2, 01-Oct-98
M44C260/M48C260
Contents (continued)
3 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Programming the EEPROM Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 MARC4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 MARC4 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 qFORTH Language Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 The qFORTH Language - Quick Reference Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Arithmetic/Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Control Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Stack Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 Memory Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.6 Predefined Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.7 Assembler Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 DC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Schmitt-Trigger Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Design of M48C260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information for M44C260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 30 30 31 32 33 33 33 34 34 35 36 36 38 38 38 39 45 46 48 49 50
4
5 6 7 8
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Rev. A2, 01-Oct-98
M44C260/M48C260
1
1.1
MARC4 Architecture
General Description
Reset
Reset Clock
System clock
Sleep
The MARC4 microcontroller consists of an advanced stack based 4-bit CPU core and on-chip peripherals. The CPU is based on the HARVARD architecture with a physically separate program memory (ROM or EEPROM) and data memory (RAM). Three independent buses the instruction bus, the memory bus and the I/O bus are used for parallel communication between program memory, RAM and peripherals. This enhances program execution speed by allowing both instruction prefetching, and simultaneous communication to the on-chip peripheral circuitry. The integrated powerful interrupt controller with eight prioritized interrupt levels, supports fast processing of hardware events. The MARC4 is designed for the high level programming language qFORTH. The core contains both FORTH stacks, expression stack and return stack. This architecture allows high level language programming without any loss in efficiency or code density.
1.2
Components of MARC4 Core
The core contains a program memory, RAM, ALU, program counter, RAM address register, instruction decoder
Rev. A2, 01-Oct-98
IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII
MARC4 CORE
PC X Y SP RP
Program memory
RAM
256 x 4-bit
Instruction bus
Instruction decoder Interrupt controller
Memory bus
TOS
CCR
ALU
I/O bus
On-chip peripheral modules
Figure 4. MARC4 core
94 8973
and interrupt controller. The following sections describe each of these parts.
1.2.1
Program Memory (ROM or EEPROM)
The ROM is mask programmed with the application program during the fabrication of the microcontroller. The EEPROM is programmed by the customer using a special programming device (see chapter "Progamming the EEPROM Program Memory"). The program memory is addressed by a 12-bit wide program counter, thus limiting the program size to a maximum of 4 Kbytes. The M44C260 contains an additional 1 Kbyte ROM for test software. The program memory starts with a 512 byte segment (zero page) which contains predefined start addresses for interrupt service routines and special subroutines accessible with single byte instructions (SCALL). The corresponding memory map is shown in the figure 4.Look-up tables of constants can also be held in the program memory and are accessed via the MARC4's built-in TABLE instruction.
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M44C260/M48C260
FFFh
Program memory
(4K x 8-bit)
1F8h 1F0h 1E8h 1E0h
1E0h 1C0h
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
SCALL addresses
180h
Zero page
140h 100h 0C0h 080h 040h
1FFh 000h
Self test bank (1K) only M44C260
3FFh
Zero page
000h
020h 018h 010h 008h 000h
1.2.2
Data Memory (RAM)
The MARC4 contains a 256 x 4-bit wide static random access memory (RAM). It is used for the expression stack, the return stack and data memory for variables and arrays. The RAM is addressed by any of the four 8-bit wide RAM address registers SP, RP, X and Y.
D Expression Stack
The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All arithmetic, I/O and memory reference operations take their operands from, and return their result to the expression stack. The MARC4 performs the operations with the top of stack items (TOS and TOS-1). The TOS register contains the
FCh
FFh Global variables
X
RAM address register:
Y SP RP
TOS-1
Expression stack
Return stack
11 0 RP
04h 00h
Return stack Global v 07h variables 03h
Figure 6. RAM map
6 (51)
IIIII
III III
IIIII IIIII IIIII IIIIIII I IIIIIII IIIIIII I IIIIIII IIIIIII IIII
IIIII IIIII
IIIIII IIIIII
008h 000h
$RESET $AUTOSLEEP
94 8974
Figure 5. Program memory map
top element of the expression stack and works like an accumulator. This stack is also used for passing parameters between subroutines, and as a scratchpad area for temporary storage of data.
D Return Stack
The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for storing return addresses of subroutines, interrupt routines and for keeping loop index counts. The return stack can also be used as a temporary storage area. The MARC4 instruction set supports the exchange of data between the top elements of the expression stack and the return stack. The two stacks within the RAM have a user definable location and maximum depth.
(256 x 4-bit) Autosleep
RAM
Expression stack
3 0 TOS TOS-1 TOS-2 4-bit SP
12-bit
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Rev. A2, 01-Oct-98
M44C260/M48C260
1.2.3 Registers
11 0
PC
The MARC4 controller has six programmable registers and one condition code register. They are shown in figure 7.
D Program Counter (PC)
The program counter (PC) is a 12-bit register that contains the address of the next instruction to be fetched from the program memory. Instructions currently being executed are decoded in the instruction decoder to determine the internal micro operations. For linear code (no calls or branches) the program counter is incremented with every instruction cycle. If a branch-, call-, return-instruction or an interrupt is executed the program counter is loaded with a new address. The program counter is also used with the TABLE instruction to fetch 8-bit wide ROM constants. RAM Address Register The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These registers allow access to any of the 256 RAM nibbles.
D Expression Stack Pointer (SP)
The stack pointer (SP) contains the address of the next-totop 4-bit item (TOS-1) of the expression stack. The pointer is automatically pre-incremented if a nibble is moved onto the stack, or post-decremented if a nibble is Rev. A2, 01-Oct-98
IIIII IIIII IIIII IIIII IIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIIIIIII IIIIIIIIIIIIII
7 0
Program counter Return stack pointer Expression stack pointer RAM address register (X) RAM address register (Y) Top of stack register Condition code register
Interrupt enable Branch Unused Carry / borrow
RP SP X Y
00
7
0
7
0
7
0
3
0
TOS
3
0
CCR C - B I
94 8976
Figure 7. Programming model
removed from the stack. Every post-decrement operation moves the item (TOS-1) to the TOS register before the SP is decremented. After a reset, the stack pointer has to be initialized with " >SP $xx " to allocate the start address of the expression stack area.
D Return Stack Pointer (RP)
The return stack pointer points to the top element of the 12-bit wide return stack. The pointer automatically preincrements if an element is moved onto the stack or it post-decrements if an element is removed from the stack. The return stack pointer increments and decrements in steps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location is left unwritten. This location is used by the qFORTH compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initialized with " >RP FCh ".
D RAM Address Register (X and Y)
The X and Y registers are used to address any 4-bit item in the RAM. A fetch operation moves the addressed nibble onto the TOS. A store operation moves the TOS to the addressed RAM location. By using either the pre-increment or post-decrement addressing mode arrays in the RAM can be compared, filled or moved.
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M44C260/M48C260
D Top Of Stack (TOS)
The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory reference and I/O operations use this register. The TOS register gets the data from the ALU, the program memory, the RAM or via the I/O bus. D Condition Code Register (CCR) The 4-bit wide condition code register contains the branch, the carry and the interrupt enable flag. These bits indicate the current state of the CPU. The CCR flags are set or reset by ALU operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow a direct manipulation of the condition code register. Carry/Borrow (C) The carry/borrow flag indicates that borrow or carry out of arithmetic logic unit (ALU) occurred during the last arithmetic operation. During shift and rotate operations this bit is used as a fifth bit. Boolean operations have no affect on the C flag. Branch (B) The branch flag controls the conditional program branching. When the branch flag has been set by one of the previous instructions a conditional branch is taken. This flag is affected by arithmetic, logic, shift, and rotate operations. Interrupt Enable (I) The interrupt enable flag enables or disables the interrupt processing on a global basis. After reset or by executing the DI instruction, the interrupt enable flag is reset and all interrupts are disabled. The C does not process further interrupt requests until the interrupt enable flag is set again by either executing an EI, RTI or SLEEP instruction. ; Note: The corresponding file ROM_TEST.INC has to be included into the project's main file. The conditional execution is stimulated during the production test.
1.2.5
Self-Check
To cover the ROM block during production testing the ROM_TEST2 routine has to be included into the $RESET routine.
: $RESET
>SP >RP Port7
S0 FCh IN Fh = ROM_Test2
IF THEN \***
main program
1.2.6
Instruction Cycles
1.2.4
ALU
A MARC4 instruction word is one or two bytes long and is executed within one or four machine-cycles. A machine-cycle consists of two system clocks (SYSCL). The MARC4 is a zero address machine. Most of the instructions are one byte long and are executed only in one machine-cycle. The CPU has an instruction pipeline, which allows the controller to fetch the next instruction from program memory at the same time as the present instruction is being executed. For more information see the section "MARC4 Instruction Set Overview".
The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two elements of the expression stack (TOS and TOS-1) and returns its result to the TOS. The ALU operations affect the carry/borrow and branch flag in the condition code register (CCR).
1.2.7
I/O Bus
RAM
SP
TOS-1 TOS-2 TOS-3 TOS-4
TOS
The I/O ports and the registers of the peripheral modules (Timer 1, Timer 2, EEPROM) are I/O mapped. The communication between the core and the on-chip peripherals takes place via the I/O bus and the associated I/O control bus. These buses are used for different functions: for read and write accesses, for the interrupt generation, to reset peripherals and for the SLEEP mode. With the MARC4 IN-instruction and OUT-instruction the I/O bus allows a direct read or write access to one of the 16 I/O addresses. More about the I/O access to the on-chip peripherals is described in the section "Peripheral modules". The I/O buses are internal buses and are not accessible by the customer on the final microcontroller device, but they are used as the interface for the MARC4 emulation (see also the section "Emulation").
IIII III IIII III IIII IIIIII IIIIIIIIIII III II I II IIIIIIIIIII III IIIIII II II I IIII IIIIIIIIII I I IIIIIIIIIIIIIII I IIIIII IIII III
ALU CCR
94 8977
Figure 8. ALU zero address operations
8 (51)
Rev. A2, 01-Oct-98
M44C260/M48C260
1.2.8 Interrupt Structure
The MARC4 can handle interrupts with eight different priority levels. They can be generated from the internal and external interrupt sources or by a software interrupt from the CPU itself. Each interrupt level has a hard-wired priority and an associated vector for the service routine in the ROM (see table 2). The programmer can enable or disable interrupts all together by setting or resetting the interrupt enable flag (I) in the CCR. Interrupt Processing For processing the eight interrupt levels, the MARC4 contains an interrupt controller with the 8-bit wide interrupt pending and interrupt active register. The interrupt controller samples all interrupt requests during every non-I/O instruction cycle and latches them in the interrupt pending register. If no higher priority interrupt is present in the interrupt active register it signals the CPU to interrupt the current program execution. If the interrupt enable bit is set the processor enters an interrupt acknowledge cycle. During this cycle a SHORT CALL instruction to
INT7
the service routine is executed and the current PC is saved on the return stack. An interrupt service routine is finished with the RTI instruction. This instruction sets the interrupt enable flag, resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the program counter. When the interrupt enable flag is reset (interrupts are disabled), the execution of interrupts is inhibited but not the logging of the interrupt requests in the interrupt pending register. The execution of the interrupt will be delayed until the interrupt enable flag is set again. But note that interrupts are lost if an interrupt request occurs during the corresponding bit in the pending register is still set. After the reset (power-on, external or watchdog reset), the interrupt enable flag and the interrupt pending and interrupt active register are reset. Interrupt Latency The interrupt latency is the time from the falling edge of the interrupt to the interrupt service routine being activated. In the MARC4 this takes between 3 to 5 machine cycles depending on the state of the core.
7 6 Priority level 5 4 3 2 1 0
Rev. A2, 01-Oct-98
AAAA AAAAA AAAA AAAAA AAIIIIII AA AAIIIIII AA AAIIIIIII AA AAAA AAIIAAAA AA A AIIIII AAAA AAAA AAA AAAA AAA AAAA AAAA AAAA
INT7 active INT5 RTI INT5 active INT3 RTI INT2 INT3 active RTI INT2 pending INT2 active RTI SWI0 INT0 pending INT0 active RTI Main / Autosleep Main / Autosleep
Time
94 8978
Figure 9. Interrupt handling
9 (51)
M44C260/M48C260
Table 2. Interrupt priority table
Interrupt INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7
Priority lowest
A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AA A AAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A A A AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAA A A A A A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAA A AA A AA
100h E0h (SCALL 100h) 140h 180h 1C0h 1E0h E8h (SCALL 140h) F0h (SCALL 180h) F8h (SCALL 1C0h) highest FCh (SCALL 1E0h)
Vector Address 040h 080h 0C0h
Interrupt Opcode (Acknowledge) C8h (SCALL 040h) D0h (SCALL 080h) D8h (SCALL 0C0h)
Function Software interrupt (SWI0) EEPROM write ready External hardware interrupt, neg. edge at BP30 or BP31 External hardware interrupt, neg. edge at BP32 or BP33 Timer 1 interrupt Timer 2 interrupt External hardware interrupt, neg. edge at IP40 pin Software interrupt (SWI7)
Software Interrupts
The programmer can generate interrupts by using the software interrupt instruction (SWI) which is supported in qFORTH by predefined macros named SWI0 to SWI7. The software triggered interrupt operates exactly as any hardware triggered interrupt. The SWI instruction takes the top two elements from the expression stack and writes the corresponding bits via the I/O bus to the interrupt
Table 3. Hardware interrupts
pending register. By using the SWI instruction in thius way, interrupts can be re-prioritized or lower priority processes scheduled for later execution.
Hardware Interrupts
The M44C260/M48C260 incorporates eleven hardware interrupt sources with six different levels. Each of these sources can be enabled or disabled separately with an interrupt mask bit in the IMR1 or IMR2 register.
Interrupt EEPROM write ready External interrupt Port 3 (BP30 OR BP31) External interrupt Port 3 (BP32 OR BP33) Timer 1 interrupt Timer 2 interrupt
Priority INT1 INT2 INT3 INT4 INT5
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A AAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A A A AAAA AAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAA
Ext. interrupt IP40 input INT6 EEPROM end of write cycle Negative edge at BP30 Negative edge at BP31 Negative edge at BP32 Negative edge at BP33 Timer 1 Timer A end of space/underflow Timer A end of pulse/capture Timer B end of space/underflow Timer B end of pulse/capture Negative edge at IP40 input
Mask Register Bit EMS IMEP IMR1 IM30 IM31 IMR1 IM32 IM33 IMR2 IMT1 T2IC IMAS IMAP IMBS IMBP IMR2 IM6
Interrupt Source
1.3
Reset
The reset puts the CPU into a well-defined condition. The reset can be triggered by switching on the supply voltage, by a break-down of the supply voltage, by the watchdog timer or by pulling the NRST pad to low.
During the reset-cycle the I/O bus control signals are set to 'reset mode' thereby initializing all on-chip peripherals. A reset is finished with a short call instruction (opcode C1h) to the program memory address 008h. This activates the initialization routine $RESET. With that routine the stack pointers, variables in the RAM and the peripheral must be initialized.
After any reset the branch-, carry- and interrupt enable flag in the Condition Code Register (CCR) , the interrupt pending register and the interrupt active register are reset.
10 (51)
Rev. A2, 01-Oct-98
M44C260/M48C260
Power-on Reset The M44C260/M48C260 incorporates an on-chip power-on reset (POR) circuitry which provides internal chip reset for most power-up situations. The power-on reset ensures that the core is not activated before the operating supply voltage has been reached. The mC will function normally at > 2.4 V under all conditions. For VDD below 2.4 V, the device will either function normally or the device reset will be globally activated by the brown-out circuit. The actual brown-out trip point is a function of temperature and process parameters. External Reset (NRST) An external reset can be triggered with the NRST pin. For the external reset the pin should be low for a minimum of two machine-cycles. Watchdog Timer Reset If the watchdog timer function of Timer 1 is enabled, a reset is triggered with every watchdog counter overflow. To suppress that, the watchdog counter must be reset by an access to the CWD-register (see also Timer 1/watchdog counter). The power-on reset and the watchdog reset are indicated in the same way as an external reset on the NRST pad.
1.4
Clock Generation
The M44C260/M48C260 has two oscillators, one RC oscillator for the system clock generation and an additional 32-kHz crystal oscillator. The system clock generator provides the core and Timer 2 with the clock. The system clock frequency is programmable for 1 or 2 MHz. The crystal oscillator is used as an exact time base for Timer 1. If no exact timing is required, the controller does not need an external crystal. In this case Timer 1 is provided with the system clock. The configuration for both oscillators is programmable with the clock status control register (CSC), which is a subport register located in port CSUB. The required configuration has to be initialized after reset in the $RESET routine. The default setting after a reset is 1 MHz system clock and an active 32-kHz crystal oscillator. After power-on or a SLEEP instruction the clock generator needs a start-up time until it runs with an exact timing. The CRDY bit in the CSC register indicates the start-up phase.
OSCIN
Q1
OSCOUT
OSC32
Stop
fOSC= 32 kHz
OSCS = 0 OSCS = 1
CL32
TIMER 1
CSC :
OSCS T1R TAR TBR EERDY SLEEP
CSC3 OSCS CRDY CCS
EEPROM
fG <= 32 kHz
OSC
Stop
/122 /2 /4 CCS = 1
Systemclock - Generator
SYSCL TIMER 2 CORE
TCL
TE
Figure 10. Clock module
Rev. A2, 01-Oct-98
III III
CCS = 0
II II
TCL - Controllogic
94 8979
11 (51)
M44C260/M48C260
1.4.1 Clock Status/Control Register (CSC)
Address: Ch Subaddress: 2h
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A A A AA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA A A A A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
CSC CSC3 OSCS CRDY CCS Reset value: 0000h CSC3 This bit must always be zero Oscillator Stop OSCS OSCS = 0 the mC runs with the 32-kHz crystal oscillator for Timer 1 OSCS = 1 the 32-kHz oscillator stops. For mC operation without crystal, this bit must be set after reset. In that case Timer 1 is provided from the internal RC oscillator. CRDY = 0 indicates the start-up time of the oscillators. CRDY = 1 indicates that the clock is ready and has the exact timing. CCS = 0 selects 1 MHz system clock (SYSCL/TCL) CCS = 1 selects 2 MHz system clock (SYSCL/TCL) CRDY CCS Clock Ready (status bit) Core Clock Select
Bit 3
Bit 2
Bit 1
Bit 0
1.4.2
TCL Signal
The TCL pin can be used as input to supply the controller with an external clock. For this configuration, the TCL pin must be held low for at least 0.5 ms during the reset cycle. The controller is working with clock frequencies up to 2.5 MHz. It is also possible to use the TCL pin as output to supply peripherals with the system clock. In this case the TE pin must be connected to VDD level and the TCL pin must have a high impedance load.
The sleep mode can only be kept when none of the interrupt pending or active register bits are set. The application of the $AUTOSLEEP routine ensures the correct function of the sleep mode. The total power consumption is directly proportional to the active time of the C. For a rough estimation of the expected average system current consumption, the following formula should be used: Itotal (VDD, fOsc) = ISleep + (IDD * Tactive/Ttotal)
1.5
Power Down Modes
IDD depends on VDD and fOsc. Systemclock Generator Stop The M44C260/M48C260 has different power down modes. When the MARC4 core enters the sleep mode and no on-chip peripheral needs a clock signal (SYSCL), the system clock oscillator is stopped. Therefore the programmer should stop Timer 1 and Timer 2 during the sleep mode if they are not required. If the 32-kHz oscillator is not used, it should be stopped. Under this condition, the power consumption is extremely low (see following table). RC Osc. 32-kHzOsc. [OSCS] STOP RUN STOP RUN STOP RUN PowerConsumption < 1.0 A < 1.0 A < 1 mA < 1 mA < 3 mA < 3 mA
The sleep mode is a shutdown condition which is used to reduce the average system power consumption in applications where the C is not fully utilized. In this mode the system clock is stopped. The sleep mode is entered with the SLEEP instruction. This instruction sets the interrupt enable bit (I) in the condition code register to enable all interrupts and stops the core. During the sleep mode the peripheral modules remain active and are able to generate interrupts. The C exits the sleep mode with any interrupt or a reset.
Table 4. Power consumption at different power down modes
Mode
CPUCore SLEEP SLEEP SLEEP SLEEP RUN RUN
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1 2 3 4 5 6 STOP STOP RUN RUN RUN RUN 12 (51) Rev. A2, 01-Oct-98
TIMER 1 [T1R] TIMER 2 [TAR, TBR] EEPROM [EERDY] T1R=0 AND TAR=0 AND TBR=0 AND EERDY=1 T1R=X, TAR=0 AND TBR=0 AND EERDY=1 T1R=1 OR TAR=1 OR TBR=1 OR EERDY=0 T1R=X, TAR=1 OR TBR=1 OR EERDY=0 T1R=X, TAR=X, TBR=X, EERDY=X T1R=X, TAR=X, TBR=X, EERDY=X
M44C260/M48C260
2
2.1
Peripheral Modules
Addressing Peripherals
lows the access to 16 subports. The first OUT-instruction writes the subport address to the subaddress register, the second IN- or OUT-instruction reads data from or writes data to the addressed subport.
The access to the peripheral modules (ports, registers) is executed via the I/O bus. The IN- or OUT-instruction allows the direct addressing of 16 I/O ports. For peripherals with a large number of registers, extended addressing is used. With two I/O operations, an extended I/O port alTable 5. I/O-addressing
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII AAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
I/O Operation Port 0, 1, 2, 3, 4, T2SC, EMS I/O read I/O write T2SUB, CSUB Extended I/O read Extended I/O write qFORTH Instructions Description port IN data port OUT Read data from port Write data to port Extended I/O short read ESUB Extended I/O read (byte) subaddress port OUT port IN subaddress port OUT data port OUT port IN subaddress port OUT port IN port IN subaddress port OUT data port OUT data port OUT Write subaddress to port Read data from subaddress Write subaddress to port Write data to subaddress Read data from current subaddress Extended I/O write (byte) Write subaddress to port Read data high nibble from subaddress Read data low nibble from subaddress Write subaddress to port Write data low nibble to subaddress Write data high nibble to subaddress
Subport Fh Subport Eh Subport Dh Subaddress Register subaddress port OUT Subport 3 Subport 2 Subport 1 Subport 0 data port OUT port IN
I/O port
Subport
I/O port
I/O bus
Figure 11. Extended I/O addressing
94 8980
Rev. A2, 01-Oct-98
13 (51)
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Table 6. Peripheral addresses
M44C260/M48C260
14 (51) Addr. 0 1 2 3 4 5 6 7 8 9 D E F A B C
Name Port 0 Port 1 Port 2 Port 3 Port 4 --- --- --- T2SC T2SUB
EMS ESUB CSUB
--- --- ---
Subport for EEPROM Subport for watchdog, Timer 1, interrupt masks, and clock generator
Subport for Timer 2
Bidirectional port Bidirectional port Bidirectional port Bidirectional port Input port
Subaddress 0 1 2 3 4 5 6 7-F
address 0
Timer 2 status and control register SubName Register
6 7 8 9 A B C D E F
5
2 3 4
1
TBRH TBRL TAM1 TAM2 TBM1 TBM2 T2IC T2PC --- --- EEPROM status register Row 0 - Row F Name Register
TARH TARL TBRCH
TARCH
TBRCL
TARCL
WDC CWD CSC --- T1C IMR1 IMR2 ---
Function
Timer 1 control register Interrupt mask register 1 Interrupt mask register 2
Watchdog control register Clear watchdog counter Clock status/control register
Timer 2A space reload/capture register, high nibble Timer 2A space reload/capture register, low nibble Timer 2A pulse reload register Timer 2A pulse reload register Timer 2B space reload/capture register, high nibble Timer 2B space reload/capture register, low nibble Timer 2B pulse reload register Timer 2B pulse reload register Timer 2A mode register 1 Timer 2A mode register 2 Timer 2B mode register 1 Timer 2B mode register 2 Timer 2 interrupt control Timer 2 prescaler control
Rev. A2, 01-Oct-98
M44C260/M48C260
2.1.1 Input Port 4
Port 4 is the input port for the pins IP40, IP43, TA and TB. IP40 is also the interrupt input for INT6, and TA and TB are normally used for timer I/O functions.
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Input Port 4 IP43 TB/IP42 TA/IP41 IP40/INT6
V DD V DD * *
Bit 3
Bit 2
Bit 1
Bit 0
Pull-up I/O bus I/O bus
V DD *
Pull-up
IP40/INT6
IP43 INT6
Pull-down
* optional
94 8981
Figure 12. Input port IP40, IP43
2.1.2
Bidirectional Ports
Ports 0, 1, 2 and 3 are bidirectional 4-bit wide ports and may be used for data input or output. The data direction is programmable for a complete port only. The port is switched to output with an OUT-instruction and to input with an IN-instruction. The data written to a port will be stored into the output latches and appears immediately after the OUT-instruction at the port pin. After RESET all output latches are set to Fh and the ports are switched to input mode. Note: Care must be taken when switching bidirectional ports from output to input. The capacitive load at this port may cause the data read to be the same as the last data written to this port. To avoid this when switching the direction, one of the following approaches should be used.
D Use two IN-instructions and DROP the first data
nibble read. The first IN switches the port from output to input, DROP removes the first invalid nibble and the second IN reads the valid nibble.
D Use an OUT-instruction followed by an IN-instruction. With the OUT-instruction, the capacitive load is charged or discharged depending on the optional pull-up /pull-down configuration. Write a "1" for pins with pull-up resistors and a "0" for pins with pulldown resistors.
Rev. A2, 01-Oct-98
15 (51)
M44C260/M48C260
I/O bus VDD
*
VDD D Q
BPxy
R Reset OUT IN / Reset
*
S R Q NQ *) optional pull-up / pull-down resistor
94 8982
Figure 13. Bidirectional port
Interrupt logic (INT2 / INT3) VDD
I/O bus
*
VDD D Q
BP3y
R Reset PortX_OUT PortX_IN / Reset
*
S R Q NQ *) optional pull-up / pull-down resistor
94 8983
Figure 14. Bidirectional Port 3 with interrupt input
2.1.3
External Interrupt Inputs
The pins IP40 and BP30 - BP33 can be used as external interrupt inputs. IP40 is used for INT6, BP32 and BP33 are used for INT3, and BP30 and BP31 are used for INT2. Pin IP40 is also used as an input port and BP30 - BP33 as
a bidirectional port (see figure 14). Each of these external interrupt sources can be enabled or disabled with individual interrupt mask bits. A negative transition at one of these inputs requests an interrupt, when the corresponding mask bit is set. The interrupt masks are placed in the subport registers IMR1 and IMR2 of port CSUB.
16 (51)
Rev. A2, 01-Oct-98
M44C260/M48C260
IMR1: IM33 IM32 IM31 IM30
BP33 BP32 BP31 BP30 IP40
Interrupt interface Interrupt interface Interrupt interface
INT3
INT2
INT6
IMR2:
IM6 IMT1
94 8984
Figure 15. External interrupt inputs
2.2
Timer 1
interrupt is maskable with the IMT1 bit. The time interval for a watchdog reset can be programmed with the watchdog control register for 0.5, 2.0, 8.0 or 16.0 s. When the watchdog is active (WDR = 1) the controller is reset with the overflow of the 3-bit watchdog counter. The application software has to ensure that the watchdog counter is reset by a write access to the CWD port before it overflows.
1 0 0 1 0 1 1 1 0 1 1 1
Timer 1 is an interval timer for generating interrupts. Additionally, the Timer 1 can be used as watchdog timer. The timer consists of a programmable 18 stage divider which is supplied with a 32-kHz clock and a 3-bit counter for the watchdog function (see figure 16). The time interval for a Timer 1 interrupt (INT4) can be programmed with the timer control register from 1 ms up to 8.0 s. The Timer 1
T1C2 T1C1 T1C0 0 0 0 0 0 1 0 1 0 0 1 1
T1C
T1R
T1C2 T1C1 T1C0
Decoder 3 : 8
DIVIDER CL32
Q5 Q6 Q8 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q18
RESET Decoder 2 : 4 WRITE (T1C)
Divider
WDC
WDR
WDC1 WDC0
Rev. A2, 01-Oct-98
IIIIIIIIIIII IIIIIIIIIIII III
IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII
IMR2
WDR=0
IMT1=0 INT4 IMT1=1 IM6 IMT1
Watchdog counter
Divider /8
RESET (NRST)
Divider RESET
WDC1 WDC0
0 0
0 1
1 0
1 1
WDR=1
WRITE CWD
94 8985
Figure 16. Timer 1
17 (51)
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2.2.2
WDM0 WDM1 WDR WDC
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2.2.1
T1C0 T1C1 T1C2 T1R T1C2 0 0 0 0 1 1 1 1 TIC
The registers of Timer 1 are I/O-mapped. They are subport register of port CSUB the access is made by extended I/O operations. The interval timer is controlled by the
Timer 1 register
M44C260/M48C260
18 (51)
WDC - Watchdog Control Register
T1C - Timer 1 Control Register
Both these bits control the time interval for the watchdog reset.
Watchdog mode 0
Watchdog mode 1
Watchdog run WDR = 0 the watchdog counter is inactive and reset WDR = 1 the watchdog counter is active and able to generate a reset when Timer 1 is running
This three bits select the time interval for a Timer 1 interrupt.
Timer 1 control bit 0
Timer 1 control bit 1
Timer 1 control bit 2
Timer 1 reset Write (T1R = 1) resets the interval timer
T1C1 0 0 1 1 0 0 1 1
WDR
Bit 3
Bit 3
T1R
T1C2
---
T1C0 0 1 0 1 0 1 0 1
2
2
WDM1
T1C1
1
1
Divider 32 64 256 1024 4096 16384 65536 262144
WDM0
T1C0
prescaler control register T1C. The interrupt mask IMT1 is placed in the interrupt mask register IMR2. The watchdog timer is controlled by the watchdog control register WDC and port CWD. A write access to CWD resets the watchdog counter.
0
0
Address: `C'h Subaddress 0
Address: `C'h Subaddress 4
Reset value: 0x00b
Reset value: 0000b
Time Interval 0.9765625 ms 1.953125 ms 7.8125 ms 31.25 ms 125 ms 500 ms 2s 8s
Rev. A2, 01-Oct-98
M44C260/M48C260
AAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A
2.3 Timer 2
TA/TB pin is used as counter output. The duty cycle can be programmed with the pulse and space reload register. Timer 2 consists of the two timer/counter blocks Timer A and Timer B. Each block has one 8-bit downcounter and a programmable prescaler. The clock inputs can be programmed to count the system clocks, Timer A clocks or external clocks. The maximum clock rate for external clocks is the half system clock frequency (SYSCL/2). Each counter has a reload register for the pulse time and a reload register for the space time. Every counter underflow toggles the output and reloads the downcounter alternately from the pulse reload register or from the space reload register. This allows the generation of any duty cycles. In addition, both counters have a capture mode. In this mode an external signal or the Counter B output causes the current counter value to be captured into the corresponding capture register. The timer has two I/O pins, TA for Timer A and TB for Timer B. Used as output, the pins have a high level during the pulse time and a low level during the space time of the timer. As input, the pins are used for the external counter clock or the capture signal. The inputs have a programmable edge detection to select the active edge of an external clock or capture signal. Interrupts can be generated when a counter underflow or a capture event occurs. The interrupt function for Timer 2 can be programmed with the interrupt control register. Both counter blocks share one interrupt vector (INT5).
WDM 1 0 0 1 1
WDM 0 0 1 0 1
Divider 2048 8192 32768 524288
Delay Time to Reset (s) 0.5 2 8 16
D Capture mode
Counter A/B is supplied by the system clock. The TA/TB pin is used as input. An external signal at the input causes the current counter value to be captured into the capture register.
D Event counter
Counter A/B counts external clocks at the TA/TB pin. The capture register contains the current counter value and can be read.
Combined Timer Modes
D 16-bit timer
Counter A is supplied with the system clock and its output is coupled with the input of Counter B. In this mode the counter is used to generate timer interrupts.
D 16 bit capture mode
Counter A is supplied with the system clock and Counter B with the output of Counter A. An external signal at the TA pin causes the current counter value will be captured into the capture registers.
D 16-bit event counter
The output of Counter A is coupled with the input of Counter B to count external clocks at TA. The capture register of both counters contain the current counter values.
Timer 2 Modes There are various timer/counter modes for both blocks of Timer 2. They can be used separately or combined. The timer modes can be programmed with the timer control and mode registers. Single Timer Modes
D Burst generator
Counter A is supplied with the system clock and its output is coupled with the input of Counter B. The output of Counter B controls the output signal of Counter A at the TA pin. The TA output is enabled during the pulse and disabled during the space of Counter B.
D 8-bit timer
Counter A/B is supplied by the system clock and is used to generate timer interrupts.
D Event counter with time gate
Counter A counts the clocks at the TA pin and Counter B is supplied with the system clock. Each underflow of Counter B causes the counter value of Counter A to be captured into its capture register.
D Pulse width modulation
Counter A/B is supplied by the system clock. The
Rev. A2, 01-Oct-98
19 (51)
M44C260/M48C260
Timer 2 Register All timer register are I/O mapped. The access to the Timer 2 status control register (T2SC) can be done with a direct I/O operation to T2SC. The status is read with an IN operation and a command to control the timer is written with an OUT operation. The remaining registers of Timer 2 are subport registers of port T2SUB. The access to those registers needs an extended I/O operation. The timer function can be configured with the mode registers TAM1, TAM2, TBM1, TBM2 and the interrupt control register T2IC. The timing depends on the contents of the prescaler control register T2PC and the reload registers. The capture registers are used to read the counter value.
SYSCL
TAM1
Counter A
TARCH[r] ACS
TAM1
+
TAM1
AOE AGB
TAM2
TA
ACE
TAM2
ACB
AE1AE0
TBM1
INTERRUPT
INT5
BCS1 BCS0 SYSCL
T2IC T2SC [READ]
Counter B
BCE
TBM2 BCA
TBM2 BE1 BE0
TB
BOE TBM1
94 8987
TBRCH[r]
Note: all control bit switches are shown at value "0"
Figure 17. Timer 2
Reload register
PULSE
TxRH[w] TxRL[w]
SPACE
TxRCH[w]TxRCL[w]
T2PC
Input Counter A/B
Prescaler
Output Counter A/B
DOWN COUNTER A/B
A/B
Toggle
T2SC[w] x = A for Counter A, B for Counter B r = READ w = WRITE
Capture register
TxRCH[r] TxRCL[r]
Capture Input A/B
Figure 18. Counter A/B
94 8986
20 (51)
Rev. A2, 01-Oct-98
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA A A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AAAAAAAAAAAAA A A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAA
TBM, TBR: Timer B control bits to start or stop Timer B. TAM, TAR: Timer A control bits to start or stop Timer A. *) TAPC: TASU: TBPC: TBSU: Read (T2SC) TBM 1 0 0 0 0 0 0 1 1 ACE and BCE are the capture enable control bits in the timer mode registers TAM2 and TBM2. Timer A end of pulse/capture status bit. When ACE = 0 this bit will be set at the end of pulse time of Counter A. When ACE = 1 this bit will be set when a capture event for Counter A occurs. Timer A end of space/underflow status bit. When ACE* = 0 this bit will be set at the end of space time of Counter A. When ACE = 1 this bit will be set with each Counter A underflow. Timer B end of pulse/capture status bit. When BCE = 0 this bit will be set at the end of pulse time of Counter B. When BCE = 1 this bit will be set when a capture event for Counter B occurs. Timer B end of space/underflow status bit. When BCE* = 0 this bit will be set at the end of space time of Counter B. When BCE = 1 this bit will be set with every Counter B underflow. TAM 1 0 0 0 0 1 1 0 0 TBR x 1 0 1 0 1 0 x x TAR x 0 1 1 0 x x 1 0 TBSU NOP STOP_A-RUN_B RUN_A-STOP_B RUN_AB STOP_AB RUN_B STOP_B RUN_A STOP_A Timer 2 Commands TBPC TASU pulse reload register. taking the value from the counter with the next clock A RUN command starts the the prescaler and counter. A STOP command resets TAPC Reset value: 0000b
AAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAA AA
2.3.1
Status register Control register Write (T2SC)
Rev. A2, 01-Oct-98 The status bits TASU, TAPC, TBSU, TBPC will be reset after a READ access to T2SC!
Timer 2 Status/Control Register (T2SC)
TBM
Bit 3
TAM
2
TBR
M44C260/M48C260
1
TAR
0
Reset value: 0000b
Address: 8
21 (51)
M44C260/M48C260
2.3.2 Timer 2 Subport (T2SUB)
Address: 9
Table 7. Timer 2 subports
AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAA
Low-nibble High-nibble Low-nibble High-nibble Low-nibble --- ACB --- BCA IMBS BPC1 --- --- High-nibble Low-nibble AGB ACS ACE AE1 BCS1 BCS0 BCE BE1 IMBP IMAS BPC0 APC1 --- --- --- --- AOE AE0 BOE BE0 IMAP APC0 --- --- * [w] write only, [r] read only
Subaddr. Name 0 TARCH [w]* TARCH [r]* 1 TARCL [w]* TARCL [r]* 2 TARH 3 TARL 4 TBRCH [w]* TBRCH [r]* 5 TBRCL [w]* TBRCL [r]* 6 TBRH 7 TBRL 8 TAM1 9 TAM2 A TBM1 B TBM2 C T2IC D T2PC E --- F ---
Meaning Timer A reload high Timer A capture high Timer A reload low Timer A capture low Timer A reload high Timer A reload low Timer B reload high Timer B capture high Timer B reload low Timer B capture low Timer B reload high Timer B reload low Timer A mode register 1 Timer A mode register 2 Timer B mode register 1 Timer B mode register 2 Timer 2 interrupt control Timer 2 prescaler control
Bit 3
Bit 2 Bit 1 High-nibble
Bit 0
2.3.3
Timer 2 Reload Register
register or the value (n) from the pulse reload register and toggles the counter output. The pulse and space width can be calculated as following: Pulse time: Pulse = (n+1) x prescaler clocks Spacetime: Space = (m+1) x prescaler clocks 0
The 8-bit wide reload registers of Timer A and B are used to program the pulse and space width of the counter output signal. The first clock after a start command loads the downcounter with the value (n) from the pulse reload register and sets the counter output to 1. The downcounter decrements with each following clock and each underflow reloads alternately the value (m) from the space reload
v m, n v 255
Prescaler out Counter out
n n-1 n-2 n+1 1 0 m m-1 m-2 m+1 1 0 n
PULSE
SPACE
22 (51)
Rev. A2, 01-Oct-98
M44C260/M48C260
Timer 2 Space Reload Register The space reload register of Timer 2 is programmed by two write accesses to the subport addresses TARCH and TARCL or TBRCH and TBRCL of the Timer 2 subport T2SUB. The value (m) in the space reload register determines the space width. At the end of the pulse, the downcounter reloads the 8-bit value from the space reload register with the next clock of the prescaler output. Space width: Space = (m+1) prescaler clocks 0 m 255 Timer 2 Pulse Reload Register The pulse reload register of Timer 2 is programmed by two write accesses to the subport addresses TERH and TARL or TBRH and TBRL of the Timer 2 subport T2SUB. The value (n) in the pulse reload register determines the space width. At the end of space the downcounter reloads the 8-bit value from the pulse reload register with the next clock of the prescaler output. Pulse width: Pulse = (n+1) prescaler clocks 0 n 255
2.3.4
Timer 2 Capture Register
The capture register is used to capture the current downcounter value when a capture event occurs. The value is kept in the capture register until the next capture event and can be read independent of the state of the downcounter. The capture events are programmable with the timer mode registers TAM2 and TBM2. The capture registers are also used to read the counter value when the external capture mode is disabled. In this case the 8-bit counter value is transferred into the capture register by reading the high nibble TARCH or TBRCH. If the 16-bit event counter mode is enabled the complete 16-bit value is captured by reading first the high nibble TARCH of Timer A. This mechanism ensures the coherence of the counter high and low nibble during the read access.
2.3.5
Timer A Mode Register 1 (TAM1)
Address: 9 - Subaddress: 8
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAA
Bit 3 --- 2 1 0 TAM1 AGB ACS AOE Reset value: 0000b AGB Counter A output gated by Counter B output AGB = 1 enables the burst generation mode. The output of Timer A is enabled during the pulse time of the Counter B and disabled (TA= 0) during the space time of the Counter B. Counter A clock select This bit selects the source of the Counter A clock. When ACS = 0 the timer is supplied with internal SYSCL. When ACS = 1 the timer is supplied with an external clock on TA pin. Timer A output enable AOE = 0 disables the counter output TA. AOE = 1 enables the counter output TA. ACS AOE Rev. A2, 01-Oct-98 23 (51)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAA A A AAAAAAAAAAAAAAAA AAAAAAAAAAA A AA AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAA
2.3.7
BOE BCS0 BCS1 BCS1 0 1 x TBM1 BCS0 0 0 1
AAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAA A A AA A
2.3.6
M44C260/M48C260
24 (51) AE0 AE1 ACE ACB AE1 0 0 1 1
TAM2
Timer B Mode Register 1 (TBM1)
Timer A Mode Register 2 (TAM2)
AE0 0 1 0 1
Timer A edge select bit 0 With these bits the active edge for the counter clocks and capture signal is selected.
Timer A edge select bit 1
Timer A capture enable ACE = 1 enables the capture mode for Counter A. The occurrence of a capture event causes that the current downcounter value is loaded into the capture register.
Timer A captured by Timer B Selects the capture source for Timer A. When ACB = 0 the signal at the TA pin is used to generate a capture event. When ACB = 1 each transition at the Counter B output is used to generate a capture event for Timer A.
Timer B output enable BOE = 0 disables the counter output TB. BOE = 1 enables the counter output TB.
These bits select the source of Counter B clock.
Timer B clock select bit 0
Timer B clock select bit 1
Counter B Input Signal System clock (SYSCL) Output signal of Counter A External input signal at TB
Active Edge for Counter Clock/Capture Events positive edge at TA pin negative edge at TA pin first positive edge after timer start and then each transition at TA pin first negative edge after timer start and then each transition at TA pin
ACB
Bit 3
Bit 3
---
ACEAAAA AE1
BCS1
2
2
BCS0
1
1
AE0
0
BOE
0
Address: 9 - Subaddress: Ah
Address: 9 - Subaddress: 9
Reset Value: 0000b
Reset value: 0000b
Rev. A2, 01-Oct-98
AAAAA A A AAAAAAAAAAAAAAA A A AAAAA A A AAAAAAAAAAAAAAA AAAAAAAAAAA A AAAAAAAAAA AAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAA AAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A
2.3.9
APC0 APC1 BPC0 BPC1 BPC1/APC1 0 0 1 1 T2PC
AAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A AA A
2.3.8
BE0 BE1 BCE BCA BE1 0 0 1 1 TBM2
Rev. A2, 01-Oct-98
Timer 2 Prescaler Control Register (T2PC)
Timer B Mode Register 2 (TBM2)
BE0 0 1 0 1
Timer A prescaler control bit 0 These bits determine the divider for the prescaler of Timer A.
Timer A prescaler control bit 1
Timer B prescaler control bit 0 These bits determine the divider for the prescaler of Timer B.
Timer B prescaler control bit 1
Timer B edge select bit 0 With these bits the active edge for the counter clocks and capture signal is selected.
Timer B edge select bit 1
Timer B capture enable BCE = 1 enables the capture mode for Counter B. A capture event loads the current downcounter value into the capture register.
Timer B is captured with Timer A capture signal. With BCA = 1 the external capture signal for Timer A is used to capture Timer B simultaneously with Timer A.
Active Edge for Clock/Capture Events positive edge on TB pin negative edge on TB pin first positive edge after start timer and then each transition on TB pin first negative edge after start timer and then each transition on TB pin
BPC0/APC0 0 1 0 1
BPC1
BCA
Bit 3
Bit 3
BCE
BPC0
2
2
Divider 1 4 16 64
BE1
APC1
1
1
BE0
APC0
0
0
M44C260/M48C260
Address: 9 - Subaddress: Dh
Address: 9 - Subaddress: Bh
Reset value: 0000b
Reset Value: 0000b
25 (51)
M44C260/M48C260
2.3.10 Timer 2 Interrupt Control Register (T2IC)
Address: 9 - Subaddress: Ch Bit 3 T2IC IMBS 2 IMBP 1 IMAS 0 IMAP Reset value: 0000b
AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAA
IMBS Interrupt mask Timer B end of space/underflow IMBS = 1 enables an INT5 interrupt, if BCE* = 0 at the end of space of Counter B, or if BCE = 1 at each Counter B underflow. Interrupt mask Timer B end of pulse/capture IMBP = 1 enables an INT5 interrupt, if BCE = 0 at the end of pulse of Counter B, or if BCE = 1 with a capture event for Counter B. IMBP IMAS Interrupt mask Timer A end of space/underflow IMAS = 1 enables an INT5 interrupt, if ACE* = 0 at the end of space of Counter A, or if ACE = 1 at each Counter A underflow. Interrupt mask Timer A end of pulse/capture IMAP = 1 enables an INT5 interrupt, if ACE = 0 at the end of pulse of Counter A, or if ACE = 1 with a capture event for Counter A. IMAP Each interrupt source can be enabled or disabled individually by setting the corresponding maskbit. *) ACE and BCE are the capture enable control bits in the timer mode registers TAM2 and TBM2.
T2SC[r] : TBSU TBPC TASU TAPC
Timer A end of pulse / capture Timer A end of space / underflow Timer B end of pulse / capture Timer B end of space / underflow INT5
T2IC :
IMBS
IMBP
IMAS
IMAP
[r] = READ
94 8988
Figure 19. Timer 2 interrupt mask register
26 (51)
Rev. A2, 01-Oct-98
M44C260/M48C260
2.3.11 Timer I/O (TA/TB)
input mode, when AOE/BOE = 1 the pin is switched to output mode. The pins also can be read with an INinstruction via Port 4 (TA with IP41 and TB with IP42). The timer I/O pins TA and TB are used as input for the external clock or capture signal and as output for the counter. The mode is controlled with AOE and BOE control bit. When AOE/BOE = 0 the pin is switched to
I/O bus (IP41/IP42) Port4_IN Counter input (edge sense) Counter output
V DD
V DD
*
TA/TB
AOE/AOB-controlbit *) optional pull-up / pull-down resistor
*
94 8989
Figure 20. Timer I/O (TA/TB)
Rev. A2, 01-Oct-98
27 (51)
M44C260/M48C260
2.4 EEPROM
The EEPROM of the M44C260/M48C260 is 128 bit wide and organized as an array of 16*8-bit. The EEPROM rows are I/O mapped and are subports of port ESUB. The access to any 8-bit row of the EEPROM is done by an extended 8-bit I/O operation or by special postincrement access. The EEPROM rows 12 to 15 can be write protected by hardware and software.
Row 15
12
High nibble Low nibble
Write protectable
Memory
0
NWP
Control logic
INT 1
EMS
ESUB
94 8990
Figure 21. EEPROM
2.4.1
EEPROM SubPort (ESUB) Address: Bh - Subaddress: 0-Fh
Read operation A read operation needs an OUT- and two IN-instructions to port ESUB. First the OUT operation writes the row adqFORTH example: Row address ESUB OUT ESUB IN ESUB IN ( (
dress. The following two IN-instructions read the high nibble and then the low nibble of the addressed row.
--) --Data_High) -- Data_High Data_Low)
(Data_High
Write operation A write operation needs three OUT-instructions to port ESUB. The first operation writes the row address. The following two OUT-instructions write the low nibble and
then the high nibble to the addressed row. After reset, rows 12 to 15 are write protected. To enable write operations to these rows the write enable bit (EWE) must be set. In all cases write accesses to these rows are disabled when pin NWP is low.
28 (51)
Rev. A2, 01-Oct-98
M44C260/M48C260
qFORTH example: Row address ESUB OUT ESUB OUT ESUB OUT (Data_High Data_Low (Data_High Data_Low (Data_High -- Data_High Data_Low) --Data_High) --)
The internal EEPROM write cycle needs about 16 ms (with connected quartz crystal and running crystal oscillator). During this cycle the EEPROM ready bit is reset (EPR = 0). After the data high nibble is written to the port ESUB, the internal write cycle is started. During the internal write cycle (while EPR = 0), only read and write accesses to the EMS register are possible. All other EEPROM accesses have no effect. Postincrement operations The postincrement mode supports a fast access to consecutive EEPROM rows. A postincrement access is started by setting the EPI bit in the EEPROM mode register (EMS) followed by writing the row start address to port ESUB. After that, the read or write operations to the consecutive EEPROM area, beginning at the start ad-
dress, need only two IN- or OUT-instructions to read or write the data. The row address is incremented automatically after each complete row access (2 nibbles). A write access to the EEPROM mode register (EMS) terminates the postincrement mode. Note: In the postincrement mode, it is not possible to change from read to write operations or vice versa before the current postincrement operation is finished.
Write ready interrupt (INT1) At the end of the internal write cycle an interrupt is generated when the interrupt mask bit IMEP in the EEPROM mode register EMS is set. With this interrupt, successive write operations can be executed interrupt controlled within the INT1 interrupt service routine.
2.4.2
EEPROM Mode/Status Register (EMS)
Address: Ah
AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAA AA
--- --- EWE --- EPI --- IMEP EPR Reset value: 0000b Reset value: xxx1b Status register Read (EMS) EWE EEPROM write enable bit EWE = 0 disables write accesses to rows 12-15 EWE = 1 enables write accesses to rows 12-15 when the NWP pin is high EPI EEPROM postincrement mode enable EPI = 1 activates a postincrement access after the next row address is written to port ESUB Interrupt mask for EEPROM write ready interrupt When IMEP is set an INT1 is generated with the end of the internal EEPROM write cycle EEPROM ready status flag EPR = 0 indicates that the EEPROM is not ready for read or write operations (an internal write cycle is executed) EPR = 1 indicates that the EEPROM is ready for read and write operations IMEP EPR After a write access to the EMS-Register, postincrement operations are terminated and any incomplete EEPROM read and write sequence must be started again! Rev. A2, 01-Oct-98 29 (51)
Mode register Write (EMS)
Bit 3
2
1
0
M44C260/M48C260
3
3.1
Appendix
Emulation
single byte instructions. These operations are performed and no source or destination address information . Only BRANCH, CALL and RAM access instructions need address information and a length of two bytes for long address operations. In total, there are five types of instruction formats with a length of one and two bytes. Zero address operations such as arithmetical, logical, shift and rotate operations are performed with data placed on the top of the expression stack (TOS and TOS-1). Also I/O- and stack operations are single byte zero address operations and are performed with the top expression stack location. A literal is a 4-bit constant value which is placed on the data stack. In the MARC4 native code they are represented as LIT_, where is the hexadecimal representation from 0 to 15 (0...F). This range is a result of the MARC4's 4-bit data width. The 6-bit short address and the 12-bit long address formats are both used to address the byte-wide ROM via CALL and conditional branch instructions. This results in a ROM address space of up to 4K 8-bit words. The MARC4 instruction includes both short and long call instructions as well as conditional branch instructions. On execution the address part of the instruction's word is directly loaded into the program counter. Long call and branch instructions can jump anywhere within the program memory area. The lower six bits from the short call (SCALL) and short branch (SBRA) instruction are handled in a different way. The six bit SCALL address is multiplied by three and then loaded into the PC. This allows calls within the zero page (000 to 1FFh). The six bit SBRA address is loaded immediately into the lower six bits of the PC. This allows jumps within the 64 byte segment addressed by the upper six bits of the PC. The CALL and SCALL instructions write the incremented program counter contents to the return stack. This address is loaded back to the PC when the associated EXIT or RTI instruction is encountered. The long RAM address format is used by the four 8-bit RAM address registers which can be pre-increment, post-decrement or loaded directly from the MARC4's internal bus. This results in a direct accessible RAM address space of up to 256 4-bit.
For emulation all MARC4 controllers have a special emulation mode. It is activated by setting the TE pin to logic HIGH level during reset. In this mode the internal CPU core is inactive and the I/O buses are available via Port 0 and Port 1 to allow the emulator the access to the on-chip peripherals. The emulator contains a special emulation CPU with a MARC4 core and additional breakpoint logic and takes over the core function. The basic function of the emulator is to evaluate the customer's program and hardware in real time. Thus, the analysation of any timing, hardware or software problems the simulation of the application is possible. For more information about emulation see "Emulator Manual".
3.2
Programming the EEPROM Program Memory
Programming the 4K 8-bit EEPROM program memory is done using a special PC-controlled programming device. Details on how to use this device and the corresponding software are given in the Programming Device User Manual. To start programming the data memory, the microcontroller is switched to a special I/O mode, where the core and all peripherals are set inactive and the two I/O buses are available via Port 0 (data) and Port 1 (control). Then the customer application data is transfered to the controller via Port 0 in blocks of 64 nibble size. Programming is started automatically after each block. The programming high voltage is generated on chip. After programming the memory, a verify run is started where the just written data is read out and compared bit by bit to the original source file. This ensures that the content of the ROM is error free.
3.3
MARC4 Instruction Set
The MARC4 instruction set is optimized for the high level programming language qFORTH. A lot of MARC4 instructions are qFORTH words. This enables the compiler to generate a fast and compact program code. The MARC4 is a zero address machine with a compact and efficient instruction code. Most of the instructions are
30 (51)
Rev. A2, 01-Oct-98
M44C260/M48C260
1) Zero address operation (ADD,SUB, INC, OR,...) 2) Immediate data operation Literal (LIT_0, LIT_1, ...) 3) Short ROM address operation (SCALL, SBRA) 4) Long ROM address operation (CALL, BRA) 5) RAM address operation (>SP, >X,...) Opcode 76543210 Opcode 7654 Opcode 76 Opcode 7654 Opcode 76543210 Figure 22. MARC4 opcode formats 4 bit data 3210
94 8708
6 bit address 543210 11 3210 12 bit address 0
76543210 8 bit address 76543210
3.3.1
MARC4 Instruction Set Overview
Description Arithmetic operations: Add Add with carry Subtract Subtract with borrow Decimal adjust Increment TOS Decrement TOS Decrement. 4-bit index on return stack Compare operations: Compare equal Compare not equal Compare less than Compare less equal Compare greater than Compare greater equal Logical operations: Exclusive OR AND OR 1's complement Shift left into carry Shift right into carry Rotate left through carry Rotate right through carry Cycles/ Bytes 1/1 1/1 1/1 1/1 1/1 1/1 1/1 2/1
Mnemonic
Description Flag operations: Toggle branch flag Set branch flag Disable all interrupts Store TOS into CCR Fetch CCR onto TOS Program branching: Conditional long branch Long call (current page) Conditional short branch Short call (zero page) Return from subroutine Return from interrupt Software interrupt Activate sleep mode No operation Register operations: Fetch the current SP Fetch the current RP Fetch the contents of X Fetch the contents of Y Move the top 2 into SP Move the top 2 into RP Move the top 2 into X Move the top 2 into Y Store direct address to SP Store direct address to RP Store direct address into X Store direct address into Y
Mnemonic
Cycles/ Bytes 1/1 1/1 1/1 1/1 1/1 2/2 3/2 2/1 2/1 2/1 2/1 1/1 1/1 1/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/2 2/2 2/2 2/2
ADD ADDC SUB SUBB DAA INC DEC DECR
CMP_EQ CMP_NE CMP_LT CMP_LE CMP_GT CMP_GE XOR AND OR NOT SHL SHR ROL ROR
1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1
Rev. A2, 01-Oct-98
AAA A A AAAAAAAAAAAAAAA A A AAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAA AAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAA A A AAAAAAAAAAAAAAA A A AAA AAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA AAAAAAAAAAAAA A
TOG_BF SET_BFC DI CCR! CCR@ BRA $xxx CALL $xxx SBRA $xxx SCALL$xxx EXIT RTI SWI SLEEP NOP SP@ RP@ X@ Y@ SP! RP! X! Y! >SP $xx >RP $xx >X $xx >Y $xx
AAA A A AAAAAAAAAAAAAAA A A AAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAA AAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAA A A AAA AAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A AAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A A AAA A A AAAAAAAAAAAAAAA A AAA AAA A A A A AAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA AAAAAAAAAAAAA A
31 (51)
M44C260/M48C260
Mnemonic Description Stack operations: Exchange the top 2 nibble Copy TOS-1 to the top Duplicate the top nibble Move TOS-2 to the top Remove the top nibble Move the top nibble onto the return stack Move the top 2 nibble onto the return stack Move the top 3 nibble onto the return stack Copy 1 nibble from the return stack Copy 2 nibbles from the return stack Copy 3 nibbles from the return stack Remove the top of return stack (12-Bit) Push immediate value Cycles/ Bytes 1/1 1/1 1/1 3/1 1/1 1/1 3/1 4/1 1/1 2/1 4/1 1/1 1/1 Mnemonic Description Memory operations: Fetch 1 nibble from RAM indirect addressed by Xor Y-register Fetch 1 nibble from RAM indirect addr. by pre-increm. X- or Y-register Fetch 1 nibble from RAM indirect addr. by post-dejcrem. X- or Y-register Fetch 1 nibble from RAM direct addressed by X- or Y-register Store 1 nibble into RAM indirect addressed by [X] Store 1 nibble into RAM indirect addressed by preincremented [X] Store 1 nibble into RAM indirect addr. by post-decrem. X- or Y-register Store 1 nibble into RAM direct addressed by X- or Y-register I/O operations: Read I/O-Port onto TOS Write TOS to I/O port Cycles/ Bytes 1/1 SWAP OVER DUP ROT DROP >R 2>R 3>R R@
2R@ 3R@
DROPR LIT_n
TABLE
(1 nibble) onto TOS ROM data operations: Fetch 8-bit constant from ROM
3
3.3.2
qFORTH Language Overview
MARC4 controllers are programmed in the high level language qFORTH which is based on the FORTH-83 language standard. The qFORTH compiler generates a native code for a 4-bit FORTH-architecture single chip microcomputer, the TEMIC MARC4.MARC4 applications are all programmed in qFORTH which is designed specifically for efficient real time control. Since the qFORTH compiler generates highly optimized codes, there is no advantage or point in programming the MARC4 in assembly code. The high level of code efficiency generated by the qFORTH compiler is achieved by the use of modern optimization techniques such as branch-instruction size minimization, fast procedure calls, pointer tracking and many peephole optimizations.
32 (51)
AA A AAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAA A A AA A AAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAA A AAAA A A A A AAAAAAAAAAAAAA AAAAAAAAAAAA AA AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A AA AAAAAAAAAAA A A A A AAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAA A AAAA A A AA A AAAAAAAAAAAAAA AAAAAAAAAAAA AA AAAAAAAAAAAAAAA A AAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAA AA A A AAAAAAAAAAA A A A A A AAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAAAAA
[X]@ [Y]@ [+X]@ [+Y]@ [X-]@ [Y-]@ 1/1 1/1 [>X]@ $xx [>Y]@ $xx [X]! 2/2 1/1 1/1 [Y]! [+X]! [+Y]! [X-]! [Y-]! 1/1 [>X]! $xx [>Y]! $xx IN OUT 2/2 1/1 1/1
AAAAAAAAAAA A A AAAAA AA A A AAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAA A A A AAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAA AAAAAAAAAA A A A A AAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAA A A AAA A A AA A AAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAA A A AAA AAAAAAAAAAAAAAA AAAAAAAAAAAA A AAA A A A A AAAAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAA AAAAAAAAAA A A A A AAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAA A A AAA A A AAAAAAAAAAAAAAA A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A AAAAAAAAAAAAA A A AAAAAAAAAAAAAAA
Language features:
Expandability Many of the fundamental qFORTH operations are directly implemented in the MARC4 instruction set. Stack oriented All operations communicate with one another via the data stack and use the reverse polish form of notation (RPN) Structured programming qFORTH supports structured programming Reentrant Different tasks can share the same code. Recursive qFORTH routines can call themselves. Native code inclusion In qFORTH there is no separation of high level constructs from the native code mnemonics.
Rev. A2, 01-Oct-98
M44C260/M48C260
3.4
3.4.1
The qFORTH Language - Quick Reference Guide
Arithmetic/Logical
EXP ( n1 n2 -- n1-n2 ) EXP ( n1 n2 -- n1+n2 ) EXP ( n1 n2 -- n1+/n+/C ) EXP ( n1 n2 -- n1+n2+C ) EXP ( n -- n+1 ) EXP ( n -- n-1 ) EXP ( n -- n*2 ) EXP ( n -- n DIV 2 ) EXP ( d1 d2 -- d1+d2 ) EXP ( d1 d2 -- d1-d2 ) EXP ( d -- d/2 ) EXP ( d -- d*2 ) EXP ( d1 n -- d2 ) EXP ( d1 n -- d2 ) EXP ( n1 n2 -- n1^n2 ) EXP ( n1 n2 -- n1 v n2 ) EXP ( -- ) EXP ( -- ) EXP ( n -- n*2 ) EXP ( n -- n/2 ) EXP ( n -- -n ) EXP ( d -- -d ) EXP ( n -- /n ) EXP ( n1 n2 -- n3 ) Subtract the top two nibbles Add up the two top 4-bit values 1's compl. subtract with borrow Add with carry top two values Increment the top value by 1 Decrement the top value by 1 Multiply the top value by 2 Divide the 4-bit top value by 2 Add the top two 8-bit values Subtract the top two 8-bit values Divide the top 8-bit value by 2 Multiply the top 8-bit value by 2 Add a 4-bit to an 8-bit value Subtract 4-bit from an 8-bit value Bitwise AND of top two values Bitwise OR the top two values Rotate TOS left through carry Rotate TOS right through carry Shift TOS value left into carry Shift TOS value right into carry 2's complement the TOS value 2's complement top 8-bit value 1's complement of the top value Bitwise Ex-OR the top 2 values
+ -C +C 1+ 12* 2/ D+ DD2/ D2* M+ MAND OR ROL ROR SHL SHR NEGATE DNEGATE NOT XOR
3.4.2
> < >= <= <> = 0<> 0= D> D< D>= D<= D= D<> D0<> D0= DMAX DMIN MAX MIN
Comparisons
EXP ( n1 n2 -- ) EXP ( n1 n2 -- ) EXP ( n1 n2 -- ) EXP ( n1 n2 -- ) EXP ( n1 n2 -- ) EXP ( n1 n2 -- ) EXP ( n -- ) EXP ( n -- ) EXP ( d1 d2 -- ) EXP ( d1 d2 -- ) EXP ( d1 d2 -- ) EXP ( d1 d2 -- ) EXP ( d1 d2 -- ) EXP ( d1 d2 -- ) EXP ( d -- ) EXP ( d -- ) EXP ( d1 d2 -- dMax ) EXP ( d1 d2 -- dMin ) EXP ( n1 n2 -- nMax ) EXP ( n1 n2 -- nMin ) If n1>n2, then branch flag set If n1=n2, then branch flag set If n1<=n2, then branch flag set If n1<>n2, then branch flag set If n1=n2, then branch flag set If n <>0, then branch flag set If n = 0, then branch flag set If d1>d2, then branch flag set If d1=d2, then branch flag set If d1<=d2, then branch flag set If d1=d2, then branch flag set If d1<>d2, then branch flag set If d <>0, then branch flag set If d =0, then branch flag set 8-bit maximum value of d1, d2 8-bit minimum value of d1, d2 4-bit maximum value of n1, n2 4-bit minimum value of n1, n2
Rev. A2, 01-Oct-98
33 (51)
M44C260/M48C260
3.4.3
AGAIN BEGIN CASE DO ELSE ENDCASE ENDOF EXECUTE EXIT IF LOOP OF REPEAT THEN UNTIL WHILE +LOOP #DO #LOOP ?DO ?LEAVE -?LEAVE
Control Structures
EXP ( -- ) EXP ( -- ) EXP ( n -- n ) EXP ( limit start -- ) RET ( -- u|limit|start ) EXP ( -- ) EXP ( n -- ) EXP ( n -- n ) EXP ( ROMAddr -- ) RET ( ROMAddr -- ) EXP ( -- ) EXP ( -- ) EXP ( c n -- ) EXP ( -- ) EXP ( -- ) EXP ( -- ) EXP ( -- ) EXP ( n -- ) RET ( u|limit|I -- u|limit|I+n ) EXP ( n -- ) RET ( -- u|u|n ) EXP ( -- ) RET ( u|u|I--u|u|I-1 ) EXP ( Limit Start -- ) EXP ( -- ) EXP ( -- ) Ends an infinite loop BEGIN .. AGAIN BEGIN of most control structures Begin of CASE .. ENDCASE block Initializes an iterative DO..LOOP Executed when IF condition is false End of CASE..ENDCASE block End of OF .. ENDOF block Execute word located at ROMAddr Unstructured EXIT from `:'-definition Conditional IF .. ELSE .. THEN block Repeat LOOP, if index+13.4.4
0 .. Fh, 0 .. 15 ' R ?DUP DEPTH DROP DUP I J
Stack Operations
EXP ( -- n ) EXP ( -- n ) EXP ( -- ROMAddr ) EXP ( n1 n2 n -- n n1 n2) EXP ( n -- ) RET ( -- u|u|n ) EXP ( n -- n n ) EXP ( -- n ) EXP ( n -- ) EXP ( n -- n n ) EXP ( -- I ) RET ( u|u|I -- u|u|I ) EXP ( -- J ) RET ( u|u|J u|u|I -- u|u|J u|u|I ) EXP ( n1 n2 -- n2 ) EXP ( n1 n2 -- n1 n2 n1 ) EXP ( x -- n[x] ) EXP ( -- n ) EXP ( -- n ) RET ( u|u|n -- ) EXP ( -- n ) RET ( u|u|n -- u|u|n ) EXP ( n -- ) Push 4-bit literal on EXP stack Places ROM address of colon-definition on EXP stack Move top value to 3rd stack pos. Move top value onto the return stack Duplicate top value, if n <>0 Get current expression stack depth Remove the top 4-bit value Duplicate the top 4-bit value Copy loop index I from return to expression stack Fetch index value of outer loop [2nd return stack level entry] Drop second to top 4-bit value Copy 2nd over top 4-bit value Copy the x-th value from the expression stack onto TOS Get # of unused RET stack entries Move top 4-bits from return to expression stack Copy top 4-bits from return to expression stack Move n-th value within stack to top
NIP OVER PICK RFREE R> R@ ROLL
34 (51)
Rev. A2, 01-Oct-98
M44C260/M48C260
ROT SWAP TUCK 2>R EXP ( n1 n2 n -- n2 n n1) EXP ( n1 n2 -- n2 n1 ) EXP ( n1 n2 -- n2 n1 n2 ) EXP ( n1 n2 -- ) RET ( -- u|n2|n1 ) EXP ( n1 n2 -- ) EXP ( d -- d d ) EXP ( d1 d2 -- d2 ) EXP ( d1 d2 -- d1 d2 d1 ) EXP ( d1 d2 d -- d d1 d2) EXP ( -- n1 n2 ) RET ( u|n2|n1 -- ) EXP ( -- n1 n2 ) RET ( u|n2|n1 -- u|n2|n1) EXP ( d1 d2 d -- d2 d d1) EXP ( d1 d2 -- d2 d1 ) EXP ( d1 d2 -- d2 d1 d2 ) EXP ( n1 n2 n3 -- ) RET ( -- n3|n2|n1 ) EXP ( n1 n2 n3 -- ) EXP ( t -- t t ) EXP ( -- n1 n2 n3 ) RET ( n3|n2|n1 -- ) EXP ( -- n1 n2 n3 ) RET ( n3|n2|n1 -- n3|n2|n1 ) Move 3rd stack value to top pos. Exchange top two values on stack Duplicate top value, move under second item Move top two values from expression to return stack Drop top 2 values from the stack Duplicate top 8-bit value Drop 2nd 8-bit value from stack Copy 2nd 8-bit value over top value Move top 8-bit value to 3rd pos'n Move top 8-bits from return to expression stack Copy top 8-bits from return to expression stack Move 3rd 8-bit value to top value Exchange top two 8-bit values Tuck top 8-bits under 2nd byte Move top 3 nibbles from the expression onto the return stack Remove top 3 nibbles from stack Duplicate top 12-bit value Move top 3 nibbles from return to the expression stack Copy 3 nibbles (1 entry) from the return to the expression stack
2DROP 2DUP 2NIP 2OVER 2 2R@ 2ROT 2SWAP 2TUCK 3>R 3DROP 3DUP 3R>
3R@
3.4.5
Memory Operations
EXP ( n addr -- ) EXP ( addr -- n ) EXP ( n addr -- ) EXP ( addr -- ) EXP ( addr -- ) EXP ( d addr -- ) EXP ( addr -- d ) EXP ( d addr -- ) EXP ( d addr -- ) EXP ( ROMAddr n -- d ) EXP ( d addr -- ) EXP ( addr n -- ) EXP ( addr n n1 -- ) EXP ( n from to -- ) EXP ( ROMAddr -- d ) EXP ( n addr -- ) EXP ( nh nm nl addr -- ) EXP ( addr -- nh nm nl ) EXP ( nh nm nl addr -- ) EXP ( nh nm nl addr -- ) EXP ( d addr -- ) EXP ( d addr -- ) Store a 4-bit value in RAM Fetch a 4-bit value from RAM Add 4-bit value to RAM contents Increment a 4-bit value in RAM Decrement a 4-bit value in RAM Store an 8-bit value in RAM Fetch an 8-bit value from RAM Add 8-bit value to byte in RAM Subtract 8-bit value from a byte in RAM Indexed fetch of a ROM constant Exclusive-OR 8-bit value with byte in RAM Sets n memory cells to 0 Fill n memory cells with n1 Move a n-digit array in memory Fetch an 8-bit ROM constant Ex-OR value at address with n Store 12-bit value into a RAM array Fetch 12-bit value from RAM Add 12-bits to 3 RAM cells Subtract 12-bits from 3 nibble RAM array Add byte to a 3 nibble RAM array Subtract byte from 3 nibble array
! @ +! 1+! 1-! 2! 2@ D+! D-! DTABLE@ DTOGGLE ERASE FILL MOVE ROMByte@ TOGGLE 3! 3@ T+! T-! TD+! TD-!
Rev. A2, 01-Oct-98
35 (51)
M44C260/M48C260
3.4.6 Predefined Structures
In-line comment definition Comment until end of the line Begin of a colon definition Exit; ends any colon definition Index (=0) for first array element Index for last array element Begins an in-line macro definition Ends an In-line macro definition Allocates space for a 4-bit array Allocates space for an 8-bit array Defines a 4-bit constant Defines an 8-bit constant Allocates space for a long 4-bit array with up to 255 elements Allocates space for a long byte array Run-time array access using a variable array index Define ROM look-up table with 8-bit values Allocates memory for 4-bit value Creates an 8-bit variable Allocate space for nibbles of un-initialized RAM Fixed

placement Interrupt service routine entry Entry point address on return stack underflow Entry point on power-on reset ( ccccccc) \ ccccccc : ; [FIRST] [LAST] CODE END-CODE ARRAY 2ARRAY CONSTANT 2CONSTANT LARRAY 2LARRAY Index ROMCONST VARIABLE 2VARIABLE ALLOT AT

: INTx : $AutoSleep : $RESET
RET ( -- ) RET ( ROMAddr -- ) EXP ( -- 0 ) EXP ( -- n|d ) EXP ( -- ) EXP ( -- ) EXP ( n -- ) EXP ( n -- ) EXP ( n -- ) EXP ( d -- ) EXP ( d -- ) EXP ( d -- ) EXP (n|d addr--addr') EXP ( -- ) EXP ( -- ) EXP ( -- )
RET ( -- ROMAddr ) EXP ( -- )
3.4.7
Assembler Mnemonics
EXP ( n1 n2 -- n1+n2 ) EXP ( n1 n2 -- n1+n2+C ) EXP ( n -- ) EXP ( -- n ) EXP ( n1 n2 -- n1 ) EXP ( n1 n2 -- n1 ) EXP ( n1 n2 -- n1 ) EXP ( n1 n2 -- n1 ) EXP ( n1 n2 -- n1 ) EXP ( n1 n2 -- n1 ) EXP ( -- ) EXP ( -- ) EXP ( -- ) EXP ( n>9 or C set -- n+6) EXP ( n -- 10+/n+C ) EXP ( n -- n-1 ) RET ( u|u|I -- u|u|I-1 ) EXP ( -- ) RET ( u|u|u -- ) RET ( ROMAddr -- ) EXP ( -- ) EXP ( port -- data ) EXP ( n -- n+1 ) EXP ( -- ) EXP ( n -- /n ) Add the top two 4-bit values Add with carry top two values Write top value into the CCR Fetch the CCR onto top of stack If n1=n2, then branch flag set If n1>=n2, then branch flag set If n1>n2, then branch flag set If n1<=n2, then branch flag set If n1n2, then branch flag set Clear branch and carry flag Set branch and carry flag Toggle the branch flag BCD arithmetic adjust [addition] 9's complement for BCD subtract Decrement top value by 1 Decrement value on the return stack Disable interrupts Drop element from return stack Exit from current `:'-definition Enable interrupts Read data from an I/O port Increment the top value by 1 No operation 1's complement of the top value Rev. A2, 01-Oct-98
ADD ADDC CCR! CCR@ CMP_EQ CMP_GE CMP_GT CMP_LE CMP_LT CMP_NE CLR_BCF SET_BCF TOG_BF DAA DAS DEC DECR DI DROPR EXIT EI IN INC NOP NOT 36 (51)
M44C260/M48C260
RP! RP@ RTI SLEEP SWI0 SWI7 SP! SP@ SUB SUBB TABLE OUT X@ [X]@ [+X]@ [X-]@ [>X]@ $xx X! [X]! [+X]! [X-]! [>X]! $xx Y@ [Y]@ [+Y]@ [Y-]@ [>Y]@ $xx Y! [Y]! [+Y]! [Y-]! [>Y]! $xx >RP $xx >SP $xx >X $xx >Y $xx EXP ( d -- ) EXP ( -- d ) RET ( RETAddr -- ) EXP ( -- ) EXP ( -- ) EXP ( d -- ) EXP ( -- d ) EXP ( n1 n2 -- n1-n2 ) EXP ( n1 n2 -- n1+/n2+C ) EXP ( -- d ) RET ( RetAddr RomAddr --) EXP ( data port -- ) EXP ( -- d ) EXP ( -- n ) EXP ( -- n ) EXP ( -- n ) EXP ( -- n ) EXP ( d -- ) EXP ( n -- ) EXP ( n -- ) EXP ( n -- ) EXP ( n -- ) EXP ( -- d ) EXP ( -- n ) EXP ( -- n ) EXP ( -- n ) EXP ( -- n ) EXP ( d -- ) EXP ( n -- ) EXP ( n -- ) EXP ( n -- ) EXP ( n -- ) EXP ( -- ) EXP ( -- ) EXP ( -- ) EXP ( -- ) Store as return stack pointer Fetch current RET stack pointer Return from interrupt routine Enter 'sleep-mode', enable all interrupts Software triggered interrupt Store as stack pointer Fetch current stack pointer 2's complement subtraction 1's compl. subtract with borrow Fetches an 8-bit constant from an address in ROM Write data to I/O port Fetch current x register contents Indirect x fetch of RAM contents Pre-incr. x indirect RAM fetch Postdecr. x indirect RAM fetch Direct RAM fetch, x addressed Move 8-bit address to x register Indirect x store of RAM contents Pre-incr. x indirect RAM store Postdecr. x indirect RAM store Direct RAM store, x addressed Fetch current Y register contents Indirect Y fetch of RAM contents Pre-incr. Y indirect RAM fetch Postdecr. Y indirect RAM fetch Direct RAM fetch, Y addressed Move address to Y register Indirect Y store of RAM contents Pre-incr. Y indirect RAM store Postdecr. Y indirect RAM store Direct RAM store, Y addressed Set return stack pointer Set expression stack pointer Set x register immediate Set Y register immediate
Notes: RET (-) EXP (-) True condition False condition n d addr ROMaddr Return address stack effects Expression (or data) stack effects Means branch flag set in CCR Means branch flag reset in CCR 4-bit data value 8-bit data value 8-bit RAM address 12-bit ROM address
Rev. A2, 01-Oct-98
37 (51)
M44C260/M48C260
4
4.1
Electrical Characteristics
Absolute Maximum Ratings
Symbol VDD VIN tshort Tamb Tstg RthJA Tsld Value - 0.3 to + 7.0 VSS -0.3 VIN VDD +0.3 indefinite -40 to +85 -40 to +130 110 260 Unit V V sec C C K/W C
Voltages are given relative to VSS.
AAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A A AAAAAAAA AA AAAA A A A A AA AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AA AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any condition above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating condition for an extended period may affect device reliability. All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize build-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., VDD).
Parameters Supply voltage Input voltage (on any pin) Output short circuit duration Operating temperature range Storage temperature range Thermal resistance (PLCC) Soldering temperature (t 10 s)
4.2
DC Operating Characteristics
Test Conditions / Pins Symbol IDD Min. Typ. Max. ( ) values for M48C260 0.9 (1.3) 1.6 (2.1) 1.3 (1.8) 2.1 (2.9) 2.1 (2.7) 3.1 (4.0) 3.6 (4.4) 5.2 (6.4) 0.3 (0.9) 0.5 (1.6) 0.4 (1.0) 0.8 (1.7) 0.6 (1.3) 1.0 (2.0) 0.8 (1.9) 1.3 (2.3) 0.4 (0.4) 1.0 (1.0) 0.5 (0.5) 1.0 (1.0) 0.8 (0.8) 0.8 (0.8) Unit mA mA mA mA mA mA mA mA A A A A
Supply voltage VDD = 2.4 to 6.2 V, VSS = 0 V, Tamb = -40 to +85C, unless otherwise specified. Parameters Power supply Active current (CPU active)
VDD = 2.4 V fSYSCL=1MHz
fSYSCL=2MHz VDD = 6.2 V fSYSCL=1MHz fSYSCL=2MHz VDD = 2.4 V fSYSCL=1MHz fSYSCL=2MHz VDD = 6.2 V fSYSCL=1MHz fSYSCL=2MHz
Power down current (CPU sleep, RC oscillator active) Sleep current (CPU sleep, RC oscillator inactive) Sleep current (CPU sleep, RC oscillator inactive)
IPD
VDD = 2.4 V VDD = 6.2 V VDD = 2.4 V VDD = 6.2 V Tamb = 25C
ISleep
ISleep
38 (51)
Rev. A2, 01-Oct-98
AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Rev. A2, 01-Oct-98 Supply voltage VDD = 2.4 to 6.2 V, VSS = 0 V, Tamb = 25C, unless otherwise specified
AAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A A AAAAAAAA AA AAAA A A A A AAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AAA AA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AAA AAAAAAAA AAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA AAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAA AA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Supply voltage VDD = 2.4 to 6.2 V, VSS = 0 V, Tamb = 25C, unless otherwise specified Parameters Test Conditions / Pins Symbol Min. Typ. Brown-out voltage: VDD VBO 1.75 Schmitt-trigger input voltage: Pin INT6, TA, TB, Port 40 and Port 3 Negative-going threshold VDD = 2.4 to 6.2 V VT- VSS voltage Positive-going threshold VDD = 2.4 to 6.2 V VT+ 0.7*VDD voltage Hysteresis (VT VT-) VDD = 2.4 to 6.2 V VH 0.1*VDD Input voltage: Pin NRST, TE, NWP, TCL, and Port 0, 1, 2, Port 43: Input voltage LOW VDD = 2.4 to 6.2 V VIL VSS Input voltage HIGH VDD = 2.4 to 6.2 V VIH 0.8*VDD Input current: Bidirectional Ports 0, 1, 2, 3, input Port 4 with pull-up resistor Pin NRST, TCL, INT6 Input LOW current VDD= 2.4 V VIL= VSS IIL -2.7 -6.7 VDD= 6.2 V -28 -60 Input current: Bidirectional Ports 0, 1, 2, 3, input Port 4 with pull-down resistor Pin TE, NWP, TA, TB Input HIGH current VDD = 2.4 V, VIH = VDD IIH 2.7 6.3 VDD = 6.2 V 30 60 Output current: Bidirectional Ports 0, 1, 2, 3 and TA, TB Output LOW current VDD = 2.4 V IOL 0.8 1.6 ,VOL = 0.2*VDD 6 11 VDD = 6.2 V Output HIGH current VDD = 2.4 V IOH -0.6 -1.3 VOH = 0.8*VDD -4 -7.5 VDD = 6.2 V Output current: Pin TCL Output LOW current VDD = 2.4 V IOL 1.6 3.2 VOL = 0.2*VDD 12 22 VDD = 6.2 V Output HIGH current VDD = 2.4 V IOH -1.2 -2.6 VOH = 0.8*VDD -8 -15 VDD = 6.2 V
4.3
Parameters Test Conditions / Pins Timer 2A and 2B input timing Timer input clock Timer input LOW time Rise/fall time < 10 ns Timer input HIFG time Rise/fall time < 10 ns Interrupt request input timing Int. request LOW time Rise/fall time < 10 ns Int. request HIGH time Rise/fall time < 10 ns
AC Characteristics
Symbol
tIRL tIRH
fTI tTIL tTIH
M44C260/M48C260
Min.
50 50
50 50
Typ.
0.2*VDD VDD
0.3*VDD
SYSCL
Max.
Max.
-13 -103
VDD
34 -4.4
17 -2.2
2.25
-24
-12
12 100
5.6
2.8
39 (51) Unit Unit mA mA mA mA mA mA mA mA A A A A ns ns - ns ns V V V V V
AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AA AAA AA AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AA AAA A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAA AAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AA AAA AA AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA A A A AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AA A A A A A AA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AAAA A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAA AAAAAAAAAAAAAAAAAAAAAA AA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Note 1: With connected crystal (pin 5, 6) and after start up time of crystal oscillator.
Note 3: This parameter is tested initially and after a design or process change that effects the parameter.
Note 2: Dependent on the connected quartz crystal.
M44C260/M48C260
40 (51) External 32 kHz crystal parameters Crystal frequency Series resistance Static capacitance Dynamic capacitance TCL fall time Reset timing Power-on reset time NRES input LOW time Data EEPROM EEPROM write time Note 1 EEPROM write cycles Note 1, 3 EEPROM data retention Note 1, 3 Program EEPROM (M48C260 only) EEPROM write cycles Note 3 Operation cycle time System clock cycle CCS = 1 Note 1 CCS = 0 RC oscillator Frequency Note 1 Stability Note 1 Stabilization time Note 1 32 kHz oscillator Frequency Start up time Stability Note 2 Integrated input/output capacitances Parameters TCL clock TCL input clock TCL input LOW time TCL input HIGH time TCL rise time Test Conditions / Pins Symbol tSYSCL fTCL tTCLL tTCLH tTCLR COUT tTCLF TPOR TPOR tEEW nW TDR fRC1 f/f tS fX tSQ f/f CIN nW fX RS C0 C1 4*SYSCL 5*105 Min. -10 100 10 32.768 30 1.5 3 32.768 1000 2000 1000 1000 500 1000 Typ. 100 16 106 10
2 0.250AAAAA 0.250AAAAA 10
Max.
Rev. A2, 01-Oct-98 500 50 1 10 10 ms - years MHz s s kHz s ppm kHz ppm s Unit kHz k pF fF pF s s ns ns ns -
M44C260/M48C260
Crystal Brown-out voltage
2.6 2.4 OSCIN OSCOUT VBO ( V ) 2.2 2.0 1.8 1.6 1.4 1.2 1 -40 C0
94 8991
VBOmax
Equivalentcircuit:
C1 L RS
VBOmin
-20
0
20
40
60
80
100
Tamb ( C )
Figure 23. Equivalent crystal circuit
12 10 8 6 4 2 0 2
94 8998
Figure 24. Brown-out voltage vs. ambient temperature
0
VOL = 0.2@VDD Tamb = 25C IOH ( mA )
-1 -2
VOH = 0.8@VDD Tamb = 25C
IOL ( mA )
-3 -4 -5 -6 -7 -8
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VDD ( V )
94 8999
2
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VDD ( V )
Figure 25. Output LOW current vs. supply voltage
150 140 130 I OL /I OL25 ( % ) 120 110 100 90 80 70 60 -40 -20
94 9000
Figure 27. Output HIGH current vs. supply voltage
140 130 120 IOH /I OH25 ( % ) 110 100 90 80 70 60 -40 -20
94 9001
0
20
40
60
80 100 120
0
20
40
60
80 100 120
Tamb ( C )
Tamb ( C )
Figure 26. Output LOW current standardized to 25C vs. temp.
Figure 28. Output HIGH current standardized to 25C vs temp.
Rev. A2, 01-Oct-98
41 (51)
M44C260/M48C260
0 -1 IOH ( mA ) -2 -3 -4 -5 0
94 8992
6 max. min. 5 4 3 2 min. max. VDD = 2.4 V Tamb = 25C 0.5 1.0 1.5 2.0 2.5
94 8995
typ.
IOL ( mA )
typ.
1 0 0 0.5 1.0 1.5
VDD = 2.4 V Tamb = 25C 2.0 2.5
VOH ( V )
VOL ( V )
Figure 29. Output HIGH current vs. output HIGH voltage
0 -2 -4 -6 -8 -10 -12 0
94 8993
Figure 32. Output LOW current vs. output LOW voltage
14 max. 12
min. 10 IOL ( mA ) typ. 8 6 4 max. VDD = 3.6 V Tamb = 25C 1 2 VOH ( V ) 3 4
94 8996
IOH ( mA )
typ.
min.
2 0 0 1 2 VOL ( V )
VDD = 3.6 V Tamb = 25C 3 4
Figure 30. Output HIGH current vs. output HIGH voltage
0 -5 min. IOH ( mA ) -10 -15 -20 -25 max. -30 0
94 8994
Figure 33. Output LOW current vs. output LOW voltage
35 30 25 IOL ( mA ) typ. 20 15 min. 10 VDD = 6.2 V Tamb = 25C 0
94 8997
max.
typ.
VDD = 6.2 V Tamb = 25C 1 2 3 4 5 6
5 0 1 2 3
4
5
6
VOH ( V )
VOL ( V )
Figure 31. Output HIGH current vs. output HIGH voltage
Figure 34. Output LOW current vs. output LOW voltage
42 (51)
Rev. A2, 01-Oct-98
M44C260/M48C260
0 -2 -4 IIL (m A ) -6 -8 -10 -12 max. -14 0
94 9002
14 12 min. IIH (m A ) 10 8 typ. 6 4 VDD = 2.4 V Tamb = 25C 0.5 1.0 1.5 2.0 2.5
94 9005
VDD = 2.4 V Tamb = 25C
max.
typ.
min.
2 0 0 0.5 1.0 1.5 2.0 2.5
VIL ( V )
VIH ( V )
Figure 35. Input LOW current vs. input LOW voltage
0 -5 -10 min.
Figure 38. Input HIGH current vs. input HIGH voltage
35 30 25 VDD = 3.6 V Tamb = 25C max.
IIL (m A )
IIH (m A )
-15 -20 -25 -30 -35 -40 0
typ.
20 15 10 typ.
max.
VDD = 3.6 V Tamb = 25C 1.0 1.5 2.0 2.5 3.0 3.5 4.0
94 9006
5 0 0 0.5 1.0 1.5 2.0 2.5
min.
0.5
3.0
3.5
4.0
94 9003
VIL ( V )
VIH ( V )
Figure 36. Input LOW current vs. input LOW voltage
Figure 39. Input HIGH current vs. input HIGH voltage
120
0 -20 -40 IIL (m A ) typ. -60 -80 -100 -120 0
94 9004
min.
100 80 IIH (m A ) 60
VDD = 6.2 V Tamb = 25C
max.
typ. 40
max.
VDD = 6.2 V Tamb = 25C 1 2 3 4 5 6
94 9007
20 0 0 1 2 3 4 5
min.
6
VIL ( V )
VIH ( V )
Figure 37. Input LOW current vs. input LOW voltage
Figure 40. Input HIGH current vs. input HIGH voltage
Rev. A2, 01-Oct-98
43 (51)
M44C260/M48C260
0 -10 -20 IIL (m A ) -30 -40 -50 -60 -70 2
94 9008
70 VIL = VSS Tamb = 25C IIH (m A ) 60 50 40 30 20 10 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VDD ( V )
94 9009
VIH = VDD Tamb = 25C
2
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VDD ( V )
Figure 41. Input LOW current vs. supply voltage
140 130 120 IIL /I IL25 ( % ) IIH /I IH25 ( % ) 0 20 40 60 80 100 120 110 100 90 80 70 60 -40 -20
94 9010
Figure 43. Input HIGH current vs. supply voltage
150 140 130 120 110 100 90 80 70 60 -40 -20
94 9011
0
20
40
60
80 100 120
Tamb ( C )
Tamb ( C )
Figure 42. Input LOW current standardized to 25C vs. temperature
Figure 44. Input HIGH current standardized to 25C vs. temperature
44 (51)
Rev. A2, 01-Oct-98
M44C260/M48C260
4.4
Note:
Schmitt-Trigger Inputs
The values for switch levels are standardized to supply voltage.
The following figures show the Schmitt-trigger input specs used at timer inputs TA, TB and interrupt inputs.
VT+ = (VIn /VDD ) x 100 ( % )
70 60 50 40 30 20 10 0 2
max. typ. min.
V H= ((V T+ - VT -)/V ) x 100 ( % ) DD
80
30 25 20 15 10 Tamb = 25 C 5 0
Tamb = 25 C
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VDD ( V )
94 9014
2
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Tamb ( C )
94 9013
Figure 45. Schmitt-trigger positive going threshold voltage
80
Figure 47. Schmitt-trigger hysteresis vs. supply voltage
140 VThres = (V /V ) x 100 ( % ) T T25 130 120 110 100 90 80 70 60 -40 -20
94 9015
VT - = (VIn /V ) x 100 ( % ) DD
70 60 50 40 30 min. 20 10 0 2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VDD ( V ) max. typ.
Tamb = 25 C
0
20
40
60
80 100 120
94 9012
Tamb ( C )
Figure 46. Schmitt-trigger negative going threshold voltage
Figure 48. Threshold temperature drift
Note:
For a pulse to be recognizable, it must be a minimum of 50 ns long with a rise time 10 ns.
Rev. A2, 01-Oct-98
45 (51)
AAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAA AAAAA A A A AA A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A
Table 8. Pad coordinates
The M44C260 is also available in the form for COB mounting. Therefore the substrate, i.e., the backside of the die, sould be connected to VSS.
5
Pad size:
Die size:
Thickness:
M44C260/M48C260
46 (51) Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Pad Layout
90 m * 90 m
3.46 mm x 4.19 mm
380 + 25 m
Name BP22 BP23 BP10 BP11 BP12 BP13 IP43 IP42 IP41 IP40 TCL VSS dig. VSS ana. BP30 BP31
VDD ana.
VDD dig.
XTALO
XTALI
NRST
BP20
X Point 0.0 404.5 809.0 1398.5 1811.0 2223.5 2686.5 3056.0 3056.0 3056.0 3056.0 3056.0 3056.0 3056.0 3056.0
BP21
TE
BP22
0,0
NWP
BP23
BP03
BP10
Y Point 0.0 0.0 0.0 0.0 0.0 0.0 0.0 509.0 965.0 1363.0 1792.0 2247.5 2457.5 2720.5 3301.0
M44C260
Figure 49. Pad layout
BP02
BP11
BP12
BP01 BP00 BP33
Number 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
BP13
IP43
Name BP32 BP33 BP00 BP01 BP02 BP03 NWP TE XTALI XTALO VDD dig. VDD ana. NRST BP20 BP21
VSS ana. VSS dig.
TCL
BP30
BP32
IP41
IP40
BP31
IP42
95 10245
X Point 3056.0 2651.5 2247.0 1830.5 1136.5 720.0 303.5 0.0 0.0 0.0 0.0 24.0 0.0 0.0 0.0
Rev. A2, 01-Oct-98 Y Point 3741.5 3741.5 3741.5 3741.5 3741.5 3741.5 3741.5 3660.0 3103.0 2625.0 2315.0 2044.0 1707.0 1164.5 424.5
AAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A
Table 9. Pad coordinates
Rev. A2, 01-Oct-98 Pad size: Die size: Thickness: Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 90 m * 90 m 4.00 mm x 8.55 mm 380 + 25 m Name BP22 BP23 BP10 BP11 BP12 BP13 IP43 IP42 IP41 IP40 TCL VSS dig. VSS ana. BP30 BP31
VDD dig. VDD ana. XTALO XTALI
The M48C260 is also available in the form for COB mounting. Therefore the substrate, i.e., the backside of the die, sould be connected to VSS.
X Point 0.0 0.0 0.0 0.0 3577.5 3577.5 3577.5 3577.5 3577.5 3577.5 3577.5 3577.5 3577.5 3577.5 3577.5
NRST
BP20
BP21
NWP
BP03
BP11
BP10
BP23
BP22
TE
0,0
BP02
Y Point 1668.0 1060.0 456.0 0.0 -3.5 452.5 978.5 1667.5 2463.5 3261.5 4063.5 4757.0 4990.0 5667.0 6462.5
Figure 50. Pad layout
M48C260
Number 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
M44C260/M48C260
BP01
Name BP32 BP33 BP00 BP01 BP02 BP03 NWP TE XTALI XTALO VDD dig. VDD ana. NRST BP20 BP21
BP00
BP13
IP43
TCL
BP33
VSS ana. VSS dig.
BP12
IP42
BP30
BP31
BP32
IP41
IP40
95 1xxxx
X Point 3577.5 3577.5 3577.5 3109.0 476.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 34.0 0.0 0.0 0.0
Y Point 7265.0 7768.0 8080.0 8080.0 8080.0 8080.0 7770.0 7264.5 6465.5 5662.5 4990.0 4725.0 4063.0 3263.0 2462.0
47 (51)
M44C260/M48C260
6 Package Information
12.9 12.7 9.25 8.75 7.5 7.3
Package SSO28
Dimensions in mm
2.35 0.30
0.80
0.25 0.25 0.10 10.4 10.50 10.20
12
technical drawings according to DIN specifications
95 11494
Package SSO20
Dimensions in mm
7.33 7.07
6.39 6.00 5.38 5.20
1.78 1.68 0.38 0.25 0.21 0.05 5.85
0.20 0.09 7.90 7.65
0.65
technical drawings according to DIN specifications
95 11495
48 (51)
Rev. A2, 01-Oct-98
M44C260/M48C260
7 Standard Design of M48C260
The mC above is a standard design, as given below (J is realised). In case the customer wants another configuration, please consult TEMIC. BP00
BP01
BP02
BP03
BP10
BP11
BP12
BP13
BP20
BP21
BP22
J J J J J J J J J J J J J J J J J J J J J J -
CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Open drain [N] Open drain [P] Pull-up Pull-down CMOS Open drain [N] Open drain [P] Pull-up Pull-down CMOS Open drain [N] Open drain [P] Pull-up Pull-down
BP23
BP30
BP31
BP32
BP33
IP40-INT6 IP41-TA
IP42-TB
IP43 TE
J J J J J J J J J J J J J J J J J
CMOS Open drain [N] Open drain [P] Pull-up Pull-down CMOS Open drain [N] Open drain [P] Pull-up Pull-down CMOS Open drain [N] Open drain [P] Pull-up Pull-down CMOS Open drain [N] Open drain [P] Pull-up Pull-down CMOS Open drain [N] Open drain [P] Pull-up Pull-down Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down Pull-up Pull-down Pull-up Pull-down
Rev. A2, 01-Oct-98
49 (51)
M44C260/M48C260
8
BP00
Ordering Information for M44C260
Please insert ROM CRC and select the option setting from the list below.
BP01
BP02
BP03
BP10
BP11
BP12
BP13
BP20
BP21
BP22
J J J J J J J J -
CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Open drain [N] Open drain [P] Pull-up Pull-down CMOS Open drain [N] Open drain [P] Pull-up Pull-down CMOS Open drain [N] Open drain [P] Pull-up Pull-down _________.HEX
BP23
BP30
BP31
BP32
BP33
IP40-INT6 IP41-TA
IP42-TB
IP43 NWP TE
J J -
CMOS Open drain [N] Open drain [P] Pull-up Pull-down CMOS Open drain [N] Open drain [P] Pull-up Pull-down CMOS Open drain [N] Open drain [P] Pull-up Pull-down CMOS Open drain [N] Open drain [P] Pull-up Pull-down CMOS Open drain [N] Open drain [P] Pull-up Pull-down Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down Pull-up Pull-down Pull-up Pull-down Pull-up Pull-down
File
-
CRC: _________h Type: Normal / Short Size: _________ KByte
Approval
Date: ___.___.___
Signature: _______________
50 (51)
Rev. A2, 01-Oct-98
M44C260/M48C260
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2594, Fax number: 49 ( 0 ) 7131 67 2423
Rev. A2, 01-Oct-98
51 (51)

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