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HV430 High Voltage Ring Generator
Ordering Information
Operating Voltage VPP1-VNN1 325V Package Options SOW-20 HV430WG
Features
105Vrms ring signal Output over current protection 5.0V CMOS logic control Logic enable/disable to save power Adjustable deadband in single-control mode Power-on reset Fault output for problem detection
General Description
The Supertex HV430 is a high voltage PWM ring generator integrated circuit. The high voltage outputs, VPGATE and VNGATE, are used to drive the gates of external high voltage P-channel and N-channel MOSFETs in a push-pull configuration. Over current protection is implemented for both the P-channel and Nchannel MOSFETs. External sense resistors set the over-current trip point. The RESET input functions as a power-on reset when connected to an external capacitor. The FAULT output indicates an over-current condition and is cleared after 4 consecutive cycles with no overcurrent condition. A logic low on RESET or ENABLE clears the FAULT output. It is active-low and open-drain to allow wire OR'ing of multiple drivers. Pgate and Ngate are controlled independently by logic inputs PIN and NIN when the MODE pin is at logic high. A logic high on PIN will turn on the external P-channel MOSFET. Similarly, a logic high on NIN will turn on the external N-channel MOSFET. Lockout circuitry prevents the N and P switches from turning on simultaneously. A pulse width limiter restricts pulse widths to no less than 100200ns. +340V +220V +220V -220V -220V +7.5V -65C to +150C 600mW For applications where a single control input is desired, the MODE pin should be connected to SGND. The PWM control signal is then input to the NIN pin. A user-adjustable deadband in the control logic ensures break-before-make on the outputs, thus avoiding cross conduction on the high voltage output during switching. A logic high on NIN will turn the external P-Channel MOSFET on and the N-Channel off, and vice versa. The IC can be powered down by applying a logic low on the ENABLE pin, placing both external MOSFETs in the off state.
Applications
Line access cards Set-top/Street box
Absolute Maximum Ratings
VPP1 - VNN1, power supply voltage VPP1, positive high voltage supply VPP2, positive gate voltage supply VNN1, negative high voltage supply VNN2, negative gate voltage supply VDD, logic supply Storage temperature Power dissipation
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1
HV430
Electrical Characteristics
(Over operating supply voltage unless otherwise specified, TA = -40C to +85C.)
External Supplies
Symbol VPP1 IPP1Q IPP1 VNN1 INN1Q INN1 VDD IDDQ IDD Parameter High voltage positive supply VPP quiescent current VPP operating current High voltage negative supply VNN1 quiescent current VNN1 operating current Logic supply voltage VDD quiescent current VDD operating current 4.50 300 VPP1-325 250 Min 50 250 Typ Max 200 500 2.0 -50 500 1.0 5.50 400 1.0 Unit V A mA V A mA V A mA PIN=NIN=0V, RDB =18k PIN=NIN=100kHz, RDB =18k PIN=NIN=0V, RDB =18k No load VOUTP and VOUTN switching at 100kHz PIN=NIN=0V No load VOUTP and VOUTN switching at 100kHz Conditions
Internal Supplies
Symbol VPP2 VNN2 Parameter Positive linear regulator output voltage Negative linear regulator output voltage Min VPP1-16 VNN1+10 Typ Max VPP1-10 VNN1+14 Unit V V Conditions
Positive High Voltage Output
Symbol VPgate RsourceP RsinkP triseP tfallP tpwp(min) tdelayP VPsen tshortP Parameter Output voltage swing VPgate source resistance VPgate sink resistance VPgate rise time VPgate fall time VPgate minimum pulse width (internally limited) PIN to Pgate delay time VPgate current sense voltage VPgate current sense off time VPP1-0.85 VPP1-1.0 100 150 Min VPP2 Typ Max VPP1 12.5 12.5 50 50 200 300 VPP1-1.15 150 Unit V ns ns ns ns V ns mode=1 Conditions No load on VPgate IOUT=80mA IOUT=-80mA Cload=1.4nF Cload=1.4nF
2
HV430
Negative High Voltage Output
Symbol VNgate RsourceN RsinkN triseN tfallN tpwn(min) tdelayN VNsen tshortN Parameter Output voltage swing VNgate source resistance VNgate sink resistance VNgate rise time VNgate fall time VNgate minimum pulse width (internally limited) NIN to VNgate delay time VNgate current sense voltage VNgate current sense OFF time VNN1+0.85 VNN1+1.0 100 150 Min VNN2 Typ Max VNN1 15.0 15.0 50 50 200 300 VNN1+1.15 150 Unit V ns ns ns ns V ns mode=1 Conditions No load on VNgate IOUT=80mA IOUT=-80mA Cload=1.0nF Cload=1.0nF
Control Circuitry
Symbol VIL VIH IINdn Rup VOL VOH VRST(OFF) VRST(ON) VRST(HYS) Ireset tRST(ON) tRST(OFF) tEN(ON) tEN(OFF) tFLT(HOLD) tDB Parameter Logic input low voltage Logic input high voltage Input pull-down current Input pull-up resistance Logic output low voltage Logic output high voltage Reset voltage, device off Reset voltage, device on Reset hysteresis voltage Reset pull-up current RESET on delay RESET off delay ENABLE on delay ENABLE off delay FAULT hold time Deadband time 35 105 tdelay(N-P) tdelay(P-N) tdelay(N-P) tdelay(P-N) N-off to P-on transistion delay P-off to N-on transistion delay Delay difference tdelayN(off) - tdelayP(on) Delay difference tdelayP(off) - tdelayN(on) -80 -80 0 0 4 50 140 70 175 300 300 80 80 50 100 4.50 3.2 3.7 0.3 7 10 13 1.0 1.0 150 1.0 3.5 4.0 Min 0 2.7 0.5 100 1 200 Typ Max 0.60 5.0 5 300 0.50 Unit V V A k V V V V V A s s s s NIN/PIN cycles ns ns ns ns ns ns ENABLE=1 Mode=0, Rdb=5.6k Mode=0, Rdb=18k Mode=0, Rdb<27k Mode=0, Rdb<27k Mode=1 Mode=1 VDD=5.0V VDD=5.0V PIN, NIN, ENABLE MODE VDD=5.0V, IOUT=-0.5mA VDD=5.0V, IOUT=0.5mA VDD=5.0V VDD=5.0V VDD=5.0V VRESET=0-4.5V Conditions
3
HV430
Truth Table
Logic Inputs* NIN L L H H H L X X PIN L H L H X X X X mode H H H H L L X X EN H H H H H H L X RESET > Vreset(on) > Vreset(on) > Vreset(on) > Vreset(on) > Vreset(on) > Vreset(on) X < Vreset(off) Output External N-Channel MOSFET OFF OFF ON OFF OFF ON OFF OFF External P-Channel MOSFET OFF ON OFF OFF ON OFF OFF OFF
* Unused logic inputs should be connected to VDD or GND.
Block Diagram and Application Circuit
VPP1 VDD +5V VPP2
FAULT De-glitcher clk reset
VDD
VPP2 Regulator
VPP1
Down Translator
Current Trip
VPSEN
Rsense
PIN
Up Translator
P Driver
VPGATE
MODE DEADBAND Control Logic NC
Ringer Output
NC Up Translator N Driver VNGATE
NIN
ENABLE VDD
Down Translator
Current Trip
VNSEN
10A
RESET
SIG GND
PWR GND
VNN2 Regulator VNN2
VNN1
Rsense
VNN1
Note: P IN, NIN, and ENABLE are internally pulled low. MODE is internally pulled high. A Reset capacitor in the range of 1-10F will yield a couple-second turn-on delay. Tantalum is recommended.
4
HV430
Single-Control Mode Timing
1 VDD
N IN
0
tN-Pdelay tP-Ndelay
GND
ON
VPP2
P OUT
OFF
tPrise tPfall tP-Ndeadband
VPP1
tN-Pdeadband
ON
VNN2
N OUT
OFF
tNfall tNrise
VNN1
Dual-Control Mode Timing
1 VDD
P IN
0
tPdelay(on) tPpulse(min) tPdelay(off)
GND
ON
VPP2
P OUT
OFF
tPrise tPfall
VPP1
1
VDD
N IN
0
tNdelay(on) tNpulse(min) tNdelay(off)
GND
ON
VNN2
N OUT
OFF
tNrise tNfall
VNN1
5
HV430
ENABLE Timing
1 VDD
ENABLE
0 GND
1
VDD Switching
N IN /P IN
0
tEN(ON)
GND
tEN(OFF)
ON
VPP2 Off Switching Off VPP1
P OUT
OFF
ON
VNN2 Off Switching Off VNN1
N OUT
OFF
RESET Timing
VRESET(ON)
RESET
VRESET(OFF) GND
1
VDD Switching
N IN /P IN
0
tRST(ON)
GND
t RST(OFF)
ON
VPP2 Off Switching Off VPP1
P OUT
OFF
ON
VNN2 Off Switching Off VNN1
N OUT
OFF
6
HV430
FAULT Timing
ENABLE or RESET
1 VDD
0
GND
1
VDD
N IN
0 GND
ON
VPP2
P OUT
OFF VPP1
ON
VNN2
N OUT
OFF VNN1
Over
N SENSE
OK
tFAULT(HOLD)
ENABLE or RESET clears FAULT immediately
VDD
FAULT
w/ext pull-up GND
Note: Nsense overcurrent shown. Psense operates identically.
7
HV430
Pin Description
VPP1 VPP2 VNN1 VNN2 VDD SGnd PGnd PIN NIN ENABLE MODE Positive high voltage supply. Positive gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should be connected between VPP2 and VPP1. Negative high voltage supply. Negative gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should be connected between VNN2 and VNN1. Logic supply voltage. Low voltage logic ground. High voltage power ground. Logic control input. When mode is high, logic input high turns ON the external high voltage P-channel MOSFET. Internally pulled low. Logic control input. When mode is high, logic input high turns ON the external high voltage N-channel MOSFET. Internally pulled low. Logic enable input. Logic high enables IC. Internally pulled low. Logic mode input. 0=single-control; 1=dual-control. When MODE is high, NIN and PIN independently control NOUT and POUT, respectively. When MODE is low, NIN controls both outputs in a complementary manner. (See Truth Table) Logic output. Fault is at logic low when either current limit sense pin, VPsen or VNsen, is activated. Remains active until overcurrent condition clears or ENABLE=0 or RESET=0. Power-on reset. A capacitor connected between this pin and ground determines the delay time between application of VDD and when the device outputs are enabled. Low leakage tantalum recommended. A resistor between this pin and ground sets the `break-before-make' time between output transitions. Applicable only in single-control mode. For minimum deadtime, a 5.6k resistor to ground should be used. For dual-input mode, tie to Vdd. Gate drive for external P-channel MOSFET. Gate drive for external N-channel MOSFET. Pulse by pulse over current sensing for P-Channel MOSFET. Pulse by pulse over current sensing for N-Channel MOSFET.
FAULT RESET DEADBAND
VPgate VNgate VPsen VNsen
Pin Configuration
VDD Fault Mode PIN NIN Enable Reset Deadband SGND PGND
1
2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VPP2 VPP1 VPSEN VPGATE N/C N/C VNGATE VNSEN VNN1 VNN2
top view SOW 20
12/13/010
(c)2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
8
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 * FAX: (408) 222-4895 www.supertex.com

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