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SH66P20A
OTP 4-bit Microcontroller
Features
SH6610C-based single-chip 4-bit microcontroller ROM: 1K X 16 bits RAM: 64 X 4 bits (Data memory) Operation voltage: 2.4V - 6.0V (Typical 3.0V or 5.0V) 12 CMOS bi-directional I/O pins 4-level subroutine nesting (including interrupts) One 8-bit auto re-load timer/counter Warm-up timer for power on reset Powerful interrupt sources: - Internal interrupt (Timer0) - External interrupts: PortB & PortC (Falling edge) Oscillator (user option) - Xtal oscillator: 32.768KHz ~ 4MHz - Ceramic resonator: 400K ~ 4MHz - RC oscillator: 400K ~ 4MHz - External clock:30K ~ 4MHz Instruction cycle time: - 4/32.768KHz ( 122us) for 32.768KHz OSC clock - 4/4MHz (= 1us) for 4MHz OSC clock Two low power operation modes: HALT and STOP OTP type Code protection Built-in watchdog timer
General Description
SH66P20A is a 4-bit microcontroller. This chip integrates the SH6610C 4-bit CPU core with SRAM, 1K program ROM, Timer and I/O Port.
Pin Configuration
PORTA.2 PORTA.3 T0
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
PORTA.1 PORTA.0 OSCI OSCO VDD PORTC.3 PORTC.2 PORTC.1 PORTC.0
SH66P20A
RESET
GND PORTB.0 PORTB.1 PORTB.2 PORTB.3
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1
V2.3
SH66P20A
Block Diagram
OSCI XTAL/RC OTP OPTION OSC OSCO
CPU
OTP PROTECT
RC
WATCHDOG TIMER
PRESCALER
PORTA (4 BITS) PORTA [3:0] PORTB (4 BITS) PORTB [3:0] PORTC (4 BITS) PORTC [3:0]
8-BIT TIMER WDT TIME OUT TIMER INTERRUPT
REG.
OTP 1024 X 16BIT
DATA RAM 64 X 4BIT
GND
VDD
T0
Pin Description
Pin No. 1-2 3 4 5 6-9 10 - 13 14 15 16 17 - 18 Note: Designation PORTA2, 3 T0 RESET GND PORTB0 - 3 PORTC0 - 3 VDD OSCO OSCI PORTA0, 1 I/O I/O I I P I/O I/O P O I I/O Bit programmable I/O Timer Clock/Counter (Schmitt Trigger input) Reset input (Active Low) Ground pin Bit programmable I/O, Vector Interrupt (Active falling edge) Bit programmable I/O, Vector Interrupt (Active falling edge) Power supply pin OSC output pin. There is a signal with a frequency of Fosc/4 for RC mode OSC input pin can be connected to crystalceramic or external resistor Bit programmable I/O Description
The all pins excluding pin15 are shared with OTP programming.
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SH66P20A
Function Description
1. CPU The CPU contains the following function blocks: Program Counter, Arithmetic Logic Unit (ALU), Carry Flag, Accumulator, Table Branch Register, Data Pointer (INX, DPH, DPM, and DPL), and Stack. 1.1. PC (Program Counter) The Program Counter is used to address the 1K program ROM. It consists of 12-bits: Page Register (PC11), and Ripple Carry Counter (PC10, PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0). The program counter normally increases by one (+1) with every execution of an instruction except in the following cases: (1) When executing a jump instruction (such as JMP, BA0, BNC), (2) When executing a subroutine call instruction (CALL), (3) When an interrupt occurs, (4) When the chip is at the INITIAL RESET mode. The program counter is loaded with data corresponding to each instruction. 1.2. ALU and CY The ALU performs arithmetic and logic operations. It provides the following functions: Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI) Decimal adjust for addition/subtraction (DAA, DAS) Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM) 2. ROM The SH66P20A can address up to 1024 X 16 bit of program area from $000 to $3FF. Service routine such as starting vector address. Vector Address Area ($000 to $004) The program is sequentially executed. There is an area address $000 through $004 that is reserved for a special interrupt service routine such as starting vector address. Address $000H $001H $002H $003H $004H Instruction JMP instruction NOP JMP instruction NOP JMP instruction Function Jump to RESET service routine Reserved Jump to TIMER0 service routine Reserved Jump to PBC service routine Decision (BA0, BA1, BA2, BA3, BAZ, BNC) Logic Shift (SHR) The Carry Flag (CY) holds the ALU overflow which the arithmetic operation generates. During an interrupt servicing or call instruction, the carry flag is pushed into the stack and restored back from the stack by the RTNI instruction. It is unaffected by the RTNW instruction. 1.3. Accumulator The Accumulator is a 4-bit register holding the results of the arithmetic logic unit. In conjunction with the ALU, data transfer between the accumulator and system register, or data memory can be performed. 1.4. Stack This group of registers is used to save the contents of CY & PC (11 - 0) sequentially with each subroutine call or interrupt. It is organized to 13 bits X 4 levels. The MSB is saved for CY. Four levels are the maximum allowed total for subroutine calls and interrupts. The contents of Stack are returned sequentially to the PC with the return instructions (RTNI/RTNW). Stack is operated on a first-in, last-out basis. This 4-level nesting includes both subroutine call and interrupt requests. Note that program execution may enter an abnormal state if the number of calls and interrupt requests exceed 4, where then the bottom of stack will be shifted out.
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SH66P20A
3. RAM Built-in RAM consists of general-purpose data memory and system register. Direct addressing in one instruction can accessed data memory and system register. The following is the memory allocation map: $000 - $01F: System register and I/O. $020 - $05F: Data memory (64 X 4 bits). The Configuration of System Register Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B - $0D $0E $0F $10 $11 $12 $13 - $15 $16 $17 $18 $19 - $1B $1C $1D $1E $1F Bit3 T0L.3 T0H.3 LPD3 PA.3 PB.3 PC.3 TBR.3 INX.3 DPL.3 PA3OUT PB3OUT PC3OUT WDT Bit2 IET0 IRQT0 TM0.2 T0L.2 T0H.2 LPD2 PA.2 PB.2 PC.2 TBR.2 INX.2 DPL.2 DPM.0 PA2OUT PB2OUT PC2OUT Bit1 TM0.1 T0L.1 T0H.1 LPD1 PA.1 PB.1 PC.1 TBR.1 INX.1 DPL.1 DPM.1 PA1OUT PB1OUT PC1OUT T0S Bit0 IEP IRQP TM0.0 T0L.0 T0H.0 LPD0 PA.0 PB.0 PC.0 TBR.0 INX.0 DPL.0 DPM.0 PA0OUT PB0OUT PC0OUT T0E R/W R/W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W W W W W W Remarks Interrupt enable flags Interrupt request flags Timer0 Mode register (Prescaler) Reserved Timer0 load/counter register low digit Timer0 load/counter register high digit Reserved LPD Control (0AH: Enable, 05H: Disable) PORTA PORTB PORTC Reserved Table Branch Register Pseudo index register Data pointer for INX low nibble Data pointer for INX middle nibble Reserved Reserved Set PORTA to be output port Set PORTB to be output port Set PORTC to be output port Reserved. Bit0: T0 signal edge, Bit1: T0 signal source Reserved Bit3: WDT time-out bit (write one only) Reserved
* System Register $00 - $12 (Please refer to "SH6610C User's manual").
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SH66P20A
4. Low Power Detection (LPD) The LPD function is to monitor the supply voltage and applies an internal reset in the microcontroller at the time of battery replacement. If the applied circuit satisfies the following conditions, the LPD can be incorporated by software control. - High reliability is not required - Power supply voltage VDD = 2.4V to 6.0 V - Operating ambient temperature TA = -20 to + 70 4.1. Functions of LPD Circuit The LPD circuit has the following functions: - Generates an internal reset signal when VDD VLPD - Cancels the internal reset signal when VDD > VLPD Here, VDD: power supply voltage, VLPD: LPD detect voltage, it is about 1.9 0.3V 4.2. LPD Control Register The LPD circuit is controlled by software enable flag Address $07 Bit3 LPD3 Bit2 LPD2 Bit1 LPD1 Bit0 LPD0 R/W W Remark LPD Enable Control (LPD3 ~ 0): 1010: LPD Enable (Default); 0101: LPD Disable
LPD3 1 0
LPD2 0 1
LPD1 1 0
LPD0 0 1
LPD Enable/Disable flag. Enable LPD circuit (Power-on initial). Disable LPD circuit.
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SH66P20A
5. I/O Ports The SH66P20A provides 12 I/O pins. When every I/O is used as an input port, the port control register controls ON/OFF of the output buffer. Sections below show the circuit configuration of I/O ports. Each of these ports contains 4 bits I/O pins. ON/OFF of the output buffer for port can be controlled by the port control register. Port I/O mapping address is shown as follows: Address $08 $09 $0A Bit3 PORT A.3 PORT B.3 PORT C.3 Bit2 PORT A.2 PORT B.2 PORT C.2 Bit1 PORT A.1 PORT B.1 PORT C.1 Bit0 PORT A.0 PORT B.0 PORT C.0 R/W R/W R/W R/W
Equivalent circuit for a single I/O pin
VDD
DATA
D DATA
Q
AND
WRITE RESET DATA IN
CK
SET
QB
I/O PIN
READ CONTROL D PXXOUT WRITE RESET CK RESET QB OR GND Q
System Register $16 - $18 Address $16 $17 $18 Bit3 PA3OUT PB3OUT PC3OUT Bit2 PA2OUT PB2OUT PC2OUT Bit1 PA1OUT PB1OUT PC1OUT Bit0 PA0OUT PB0OUT PC0OUT R/W W W W Description Set PORTA to be output port Set PORTB to be output port Set PORTC to be output port
I/O control register: PAXOUT, PBXOUT, PCXOUT (X = 0, 1, 2, 3) 1: Set I/O as an output buffer 0: Set I/O as an input buffer (initial power-on)
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SH66P20A
PORTB & PORTC interrupt The PORTB and PORTC are used as port interrupt sources. Since PORT I/O is bit programmable I/O, so only the input port can generate an external interrupt. Any one of the PORTB and PORTC input pin transitions from VDD to GND will generate an interrupt request. And further falling edge transition would not be able to make interrupt request until all of the pins return to VDD. Following is the port interrupt function block-diagram.
PORTC.3 PC3OUT PORTC.2 PC2OUT PORTC.1 PC1OUT PORTC.0 PC0OUT PORTB.3 PB3OUT PORTB.2 PB2OUT PORTB.1 PB1OUT PORTB.0 PB0OUT
FALLING EDGE DETECTION
PORT INTERRUPT
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SH66P20A
6. T0 & WDT System Register $1C Address $1C BIT3 BIT2 BIT1 T0S BIT0 T0E R/W W Remark Bit0: T0 signal edge Bit1: T0 signal source
T0E: T0 signal edge. 0: Increment on low-to-high transition T0 pin (initial power-on). 1: Increment on high-to-low transition T0 pin. T0S: T0 signal source. 0: OSC 1/4 (initial power-on). 1: Transition on T0 pin. T0, OSC1/4 & WDT
OSC/4 0 M U X TIMER0 (8bits)
T0
EOR
1
T0E
T0S
3
Built-in RC Oscillator
TM0 [2:0]
WDT & Warm-up Counter
3
WDT Timeout
System Register $1E Address $1E Bit3 WDT Bit2 Bit1 Bit0 R/W W Remark Bit3: WDT time-out bit (write one only)
The input clock of watchdog timer is generated by a built-in RC oscillator,so that the WDT will always run even in the STOP mode. SH66P20A generates a RESET condition when watchdog times-out. Watchdog can be enabled or disabled permanently by user option. To prevent it from timing out and generating a device RESET condition, one can write this bit as "1" before timing-out. The WDT has a time-out period of more than 7ms (VDD = 5V). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:2048 can be assigned to the WDT under software controlled by writing to the TM0 register.
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SH66P20A
Pre-scaler divide ratio (valid for VDD = 5V): TM0.2 1 1 1 1 0 0 0 0 TM0.1 1 1 0 0 1 1 0 0 TM0.0 1 0 1 0 1 0 1 0 Prescaler divide ratio 1:1 1:2 1:4 1:8 1:32 1:128 1:512 1:2048 (Power on initial) Timer-out period 7ms 14ms 28ms 56ms 224ms 896ms 3,584ms 14,336ms
0.875ms RC OSC
Internal SCALER_1 /8
WDT Time out Period 7ms
WDT PRESCALER TM0
/1
/2
/4 /8
/32 /128 /512 /2048
Final WDT Time OUT period
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SH66P20A
7. Timer0 SH66P20A has one 8-bit timer. The time/counter has the following features: . 8-bit timer/counter . Readable and writable . Automatic reloadable counter . 8-prescaller scale is available . Internal and external clock select . Interrupt on overflow from $FF to $00 . Edge select for external event Following is a simplified timer block diagram:
Fosc/4 T0C T0 System clock PRE-SCALER 8-BIT COUNTER
T0M T0E
T0S
7.1. Configuration and Operation Timer-0 consists of an 8-bit write-only timer load register (TL0L, TL0H), and an 8-bit read-only timer counter (TC0L, TC0H). The counter and load register both have low order digits and high order digits. The timer counter can be initialized by writing data into the timer load register (TL0L, TL0H). Load register programming: write the low-order digit first and then the high-order digit. The timer counter is loaded with the content of load register automatically when the high order digit is written or counter counts overflow from $FF to $00. Timer Load Register: Since the register H would control the physical READ and WRITE operation. Please follow these rules: Write Operation: Low nibble first; High nibble to update the counter. Read Operation: High nibble first; Low nibble followed.
Load Reg. L
Load Reg. H
8-bit timer counter Latch Reg. L
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SH66P20A
7.2. Timer0 Interrupt The timer overflow will generate an internal interrupt request, when the counter counts overflow from $FF to $00. If the interrupt enable flag is enabled, then a timer interrupt service routine will proceed. This can also be used to wake CPU from HALT mode. 7.3. Timer0 mode register The timer can be programmed in several different prescaler ratio by setting Timer Mode register (TM0). The 8-bit counter counts prescaler overflow output pulses. The timer mode registers (TM0) are 3-bit registers used for timer control as shown in table1. These mode registers select the input pulse sources into the timer. Timer 0 Mode Register ($02) TM0.2 0 0 0 0 1 1 1 1 TM0.1 0 0 1 1 0 0 1 1 TM0.0 0 1 0 1 0 1 0 1 Prescaler Divide Ratio /2
11 9 7 5 3 2 1 0
Ratio N 2048 (initial) 512 128 32 8 4 2 1
/2 /2 /2 /2 /2 /2 /2
7.4. External Clock/Event T0 as TMR0 Source When external clock/event input is used for TM0, it is synchronized with CPU system clock. Therefore the external source must follow certain constrains. The output from T0M multiplex is T0C. It is sampled by system clock in instruction frame cycle. Therefore it is necessary for T0C to be high at least 2 tOSC and low at least 2 tOSC. When prescaler ratio selects /20, T0C is the same as the system clock input. Therefore the requirement is as follows: T0H = T0CH = T0 high time 2 tosc + T T0L = T0CL = T0 low time 2 tosc + T When other prescaler ratio is selected, the TM0 is scaled by the asynchronous ripple counter and so the prescaler output is symmetrical. Then: T0C high time = T0C low time = Where T0 = Timer0 input period N = prescaler value The requirement is, therefore:
N * T0 4 * t OSC + 2 T 2 tosc + T , or T0 2 N N * T0 2
The limitation is applied for T0 period time only. The pulse width is not limited by this equation. It is summarized as follows: T0 = Timer0 period
4 * t OSC + 2 T N
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SH66P20A
8. Interrupt Two interrupt sources are available on for: - Timer0 overflow interrupt - Port's falling edge detection interrupt ( PBC ) Interrupt Control Bits and Interrupt Service The interrupt control flags are mapped on $00 through $01 of the system register. They can be accessed or tested by program. Those flags are cleared to 0 at initialization by chip reset. Address $00 $01 Bit3 Bit2 IET0 IRQT0 Bit1 Bit0 IEP IRQP Remarks Interrupt enable flags Interrupt request flags
When IEx is set to 1 and the interrupt request is generated (IRQx is 1), the interrupt will be activated and vector address will be generated from the priority PLA corresponding to the interrupt sources. When an interrupt occurs, the PC and CY flag will be saved into stack memory and jump to interrupt service vector address. After the interrupt occurs, all interrupt enable flags (IEx) are reset to 0 automatically, so when IRQx is 1 and IEx is set to 1 again, the interrupt will be activated and vector address will be generated from the priority PLA corresponding to the interrupt sources. Interrupt Servicing Sequence Diagram:
Inst. cycle 1 2 3 4 5
Instruction Execution N
Instruction Execution I1
Instruction Execution I2 Vector Generated Stacking Fetch Vector address Reset IE.X
Interrupt Generated
Interrupt Accepted
Start at vector address
Interrupt Nesting: During the SH6610C CPU interrupt service, the user can enable any interrupt enable flag before returning from the interrupt. The servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the interrupt request is ready and the instruction of execution N is IE enable, then the interrupt will start immediately after the next two instruction executions. However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then the interrupt service will be terminated.
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SH66P20A
System Clock and Oscillator System clock generator produces the basic clock pulses that provide the system clock with CPU and peripherals. Instruction cycle time (1) 4/32.768KHz ( 122us) for 32.768KHz system clock. (2) 4/4MHz (= 1us) for 4MHz system clock. Oscillator (1) Crystal oscillator: 32.768KHz - 4MHz.
C1 C1, C2 Setting : Crystal 32.768K ~ 4MHz
Crystal 32.768KHz : C1, C2 < 56p (VDD = 5V); C1, C2 < 56p (VDD = 3V). Crystal 4MHz : C1, C2 < 33p (VDD = 5V); C1, C2 < 10p (VDD = 3V).
C2
(2) Ceramic resonator: 400KHz - 4MHz.
C1 C1, C2 Setting : Ceramic 400K ~ 4MHz
Ceramic 400KHz : 20p < C1, C2 < 470p (VDD = 5V); 20p < C1, C2 < 150p (VDD = 3V). Ceramic 4MHz : 20p < C1, C2 < 100p (VDD = 5V); C1, C2 < 10p (VDD = 3V).
C2
(3) RC oscillator: 400KHz - 4MHz.
VDD R OSCI OSCO Fosc/4
(4) External input clock: 30KHz - 4MHz.
OSCI
External clock source
OSCO
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SH66P20A
Initial State
Hardware Program counter CY Data memory System register AC Timer counter Timer load register WDT counter WDT prescaler I/O Ports T0S T0E WDT LPD After power on reset $000 Undefined Undefined Undefined Undefined 0 0 0 0 Input 00 0 1010
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SH66P20A
Instruction Set
All instructions are one cycle and one word instructions. The characteristics is memory-oriented operation. Arithmetic and Logical Instruction Accumulator Type Mnemonic ADC ADCM ADD ADDM SBC SBCM SUB SUBM EOR EORM OR ORM AND ANDM SHR Immediate Type Mnemonic ADI ADIM SBI SBIM EORIM ORIM ANDIM X, I X, I X, I X, I X, I X, I X, I Instruction Code 01000 iiii xxx xxxx 01001 iiii xxx xxxx 01010 iiii xxx xxxx 01011 iiii xxx xxxx 01100 iiii xxx xxxx 01101 iiii xxx xxxx 01110 iiii xxx xxxx AC AC Function Mx + I Mx + -I + 1 AC, Mx Mx + I AC, Mx Mx + -I + 1 AC, Mx Mx I AC, Mx Mx | I AC, Mx Mx & I Flag Change CY CY CY CY X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) X (, B) Instruction Code 00000 0bbb xxx xxxx 00000 1bbb xxx xxxx 00001 0bbb xxx xxxx 00001 1bbb xxx xxxx 00010 0bbb xxx xxxx 00010 1bbb xxx xxxx 00011 0bbb xxx xxxx 00011 1bbb xxx xxxx 00100 0bbb xxx xxxx 00100 1bbb xxx xxxx 00101 0bbb xxx xxxx 00101 1bbb xxx xxxx 00110 0bbb xxx xxxx 00110 1bbb xxx xxxx 11110 0000 000 0000 AC AC, Mx AC AC, Mx AC AC, Mx AC AC, Mx AC AC, Mx AC AC, Mx AC AC, Mx Function Mx + AC + CY Mx + AC + CY Mx + AC Mx + AC Mx + -AC + CY Mx + -AC + CY Mx + -AC + 1 Mx + -AC + 1 Mx AC Mx AC Mx | AC Mx | AC Mx & AC Mx & AC CY Flag Change CY CY CY CY CY CY CY CY
0 AC [3]; AC [0] CY; AC shift right one bit
* In the assembler ASM66 V1.0, EORIM mnemonic is EORI. However, EORI has the same operation identical with EORIM. Same for the ORIM with respect to ORI, and ANDIM with respect to ANDI. Decimal Adjustment Mnemonic DAA X DAS X Instruction Code 11001 0110 xxx xxxx 11001 1010 xxx xxxx Function AC; Mx Decimal adjustment for add. AC; Mx Decimal adjustment for sub. Flag Change CY CY
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SH66P20A
Transfer Instruction Mnemonic LDA STA LDI X (, B) X (, B) X, I Instruction Code 00111 0bbb xxx xxxx 00111 1bbb xxx xxxx 01111 iiii xxx xxxx AC Mx Mx AC Function Flag Change
AC, Mx I
Control Instruction Mnemonic BAZ X BNZ X BC X BNC X BA0 X BA1 X BA2 X BA3 X CALL X Instruction Code 10010 xxxx xxx xxxx 10000 xxxx xxx xxxx 10011 xxxx xxx xxxx 10001 xxxx xxx xxxx 10100 xxxx xxx xxxx 10101 xxxx xxx xxxx 10110 xxxx xxx xxxx 10111 xxxx xxx xxxx 11000 xxxx xxx xxxx PC PC PC PC PC PC PC PC ST PC PC RTNW H; L RTNI HALT STOP JMP X TJMP NOP Where, PC AC -AC CY Mx p ST Program counter Accumulator Complement of accumulator Carry flag Data memory ROM page = 0 Stack TBR Table Branch Register I | & bbb Immediate data Logical exclusive OR Logical OR Logical AND RAM bank = 000 11010 000h hhh llll 11010 1000 000 0000 11011 0000 000 0000 11011 1000 000 0000 1110p xxxx xxx xxxx 11110 1111 111 1111 11111 1111 111 1111 PC PC X (Include p) (PC11-PC8) (TBR) (AC) AC Function X if AC = 0 X if AC 0 X if CY = 1 X if CY 1 X if AC (0) = 1 X if AC (1) = 1 X if AC (2) = 1 X if AC (3) = 1 CY; PC + 1 X (Not including p) ST; TBR hhhh; llll CY Flag Change
CY; PC ST
No Operation
OTP Options
- Oscillator: Crystal Osc, Ceramic resonator or RC oscillator. - WDT: Enable or Disable.
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SH66P20A
Absolute Maximum Rating*
DC Supply Voltage . . . . . . . . . . . . . . . . . . -0.3V to + 7.0V Input/Output Voltage . . . . . . . . .GND -0.2V to VDD + 0.2V Operating Ambient Temperature . . . . . . . -10 to + 60 Storage Temperature . . . . . . . . . . . . . . . -55 to + 125
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics (VDD = 5.0V GND = 0V, TA = 25, FOSC = 4MHz [external clock], unless otherwise specified.) Parameter Operating Voltage Operating Current Stand by Current (HALT) Stand by Current (HALT) OSC = 32768Hz Crystal Stand by Current (STOP) Input Low Voltage Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Input High Voltage Input Leakage Current Input Leakage Current Input Leakage Current Input Leakage Current Input Leakage Current Output High Voltage Output Low Voltage Symbol VDD IOP ISB1 ISB32k ISB2 VIL1 VIL2 VIL3 VIH1 VIH2 VIH3 IIL1 IIL2 IIL3 IIL4 IIL5 VOH VOL -3 -3 VDD - 0.7 GND + 0.6 GND GND GND 0.8 X VDD 0.85 X VDD 0.85 X VDD -1 -5 1 1 1 5 3 3 Min. 4.5 Typ 5 1.3 Max. 6 1.5 300 10 1 0.2 X VDD 0.15 X VDD 0.15 X VDD VDD VDD VDD 1 Unit V mA A A A V V V V V V A A A A A V V All output pins unloaded (Execute NOP instruction) All output pins unload, WDT off LPD off (If WDT on, ISB1 = ISB1 + 20A) All output pins unload, WDT off LPD off (If WDT on, ISB32k = I SB1 + 20A) All output pins unloaded, LPD off, WDT off (If WDT on, I SB2 = I SB2 + 20A) I/O Ports, pins tri-state RESET , T0 OSCI (Driven by external clock) I/O Ports, pins tri-state RESET , T0 OSCI (Driven by external Clock) I/O Ports, GND < VI/O < VDD V RESET = GND + 0.25V V RESET = VDD T0, GND < VT0 < VDD For OSCI I/O Ports, IOH = -10mA OSCO, IOH = -0.7mA I/O Ports, IOL = 20mA OSCO, IOL = 1.6mA Condition
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SH66P20A
AC Electrical Characteristics (VDD = 5.0V GND = 0V, TA = 25, FOSC = 4MHz [external clock], unless otherwise specified.) Parameter Oscillator Start Time Oscillator Start Time Oscillator Start Time Oscillator Start Time WDT Period Frequency Stability (crystal) Frequency Variation (crystal) Frequency Stability (ceramic) Frequency Variation (RC) Temperature Stability (RC) Notes: Negative current is defined as the flowing out of the pin. Max. current into VDD = 50mA. Max. current out of VSS = 150mA. Max. output current sunk by any I/O pin = 25mA. Max. output current sourced by any I/O pin = 20mA. Max. output current sunk by any I/O port = 50mA. Max. output current sourced by any I/O port = 40mA. Symbol TOSC1 TOSC2 TOSC3 TST TWDT F/F F/F F/F F/F F/F 7 12 1 10 0.1 20 7.5 Min. Typ. Max. 2 20 2 5 Unit s ms ms ms ms PPM PPM % % % Crystal oscillator: [F(5.0) - F(4.5)]/F(5.0) Crystal oscillator: C1 = C2 = 5 - 30P Ceramic resonator Oscillator: [F(5.0) - F(4.5)]/F(5.0) Include supply voltage and chip to chip variation RC oscillator: [F(-10C) - F(60C)]/F(-10C) Condition X'tal osc = 32.768KHz Ceramic Osc = 400KHz RC Osc = 400KHz WDT RC oscillator = 1/18ms Hz
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SH66P20A
DC Electrical Characteristics (VDD = 3.0V, GND = 0V, TA = 25, FOSC = 4MHz [external clock], unless otherwise specified) Parameter Operating Voltage Operating Current Symbol VDD IOP Min. 2.4 Typ 3 0.8 Max. 4.5 1.0 Unit V mA A All output pins unloaded (Execute NOP instruction) All output pins unload, WDT off LPD off (If WDT on, ISB1 = ISB1 + 8A) All output pins unload, WDT off LPD off (If WDT on, ISBX = ISB1 + 8A) Condition
Stand by Current (HALT)
ISB1
140
Stand by Current (HALT) OSC = 32768 Crystal Stand by Current (STOP) Input Low Voltage Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Input High Voltage Input Leakage Current Input Leakage Current Input Leakage Current Input Leakage Current Input Leakage Current Output High Voltage Output Low Voltage
ISB32k
5
A
ISB2 VIL1 VIL2 VIL3 VIH1 VIH2 VIH3 IIL1 IIL2 IIL3 IIL4 IIL5 VOH VOL -2.3 -2.3 VDD - 0.7 GND GND GND 0.8 X VDD 0.85 X VDD 0.85 X VDD -1 -3.8 1 1 1
1 0.2 X VDD 0.15 X VDD 0.15 X VDD VDD VDD VDD 1 3.8 2.3 2.3
A V V V V V V A A A A A V
All output pins unloaded,
LPD off WDT off (If WDT on, ISB2X = ISB2 + 8A) I/O Ports, pins tri-state RESET , T0 OSCI (Driven by external clock) I/O, Ports, pins tri-state RESET , T0 OSCI (Driven by external Clock) I/O Ports, GND < VI/O < VDD V RESET = GND + 0.25V V RESET = VDD T0, GND < VT0 < VDD For OSCI I/O Ports, IOH = -7mA OSCO, IOH = -0.7mA I/O Ports, IOL = 8mA OSCO, IOL = 1.0mA
GND + 0.4
V
AC Electrical Characteristics (VDD = 3.0V, GND = 0V, TA = 25, FOSC = 4MHz [external clock], unless otherwise specified) Parameter Oscillator Start Time Oscillator Start Time Oscillator Start Time Oscillator Start Time WDT Period Frequency Stability (crystal) Frequency Variation (crystal) Frequency Stability (ceramic) Frequency Variation (RC) Temperature Stability (RC) Symbol TOSC1 TOSC2 TOSC3 TST TWDT F/F F/F F/F F/F F/F 7 12 1 10 0.1 20 7.5 Min. Typ Max. 3.5 35 5 8.5 Unit s ms ms ms ms PPM Crystal oscillator: [F(3.0)-F(2.7)]/F(3.0) PPM Crystal oscillator: C1 = C2 = 5 - 30P % % % Ceramic resonator Oscillator: [F(3.0) - F(2.7)]/F(3.0) Include supply voltage and chip to chip variation RC oscillator:[F(-10C) - F(60C)]/F(-10C) Condition Crystal Osc = 32.768KHz Ceramic Osc = 400KHz RC Osc = 400KHz WDT RC oscillator = 1/18ms Hz
19
SH66P20A
AC Characteristics Symbol TCY TIW TIWH TIWL Parameter Instruction cycle time T0 input width High pulse width LOW pulse width Min. 1 (TCY + 40)/N 1/2 tIW 1/2 tIW Typ. Max. 122 Unit s ns ns ns N = Prescaler divide ratio Condition
Timing Waveform
T0 Input Waveform
TiwH TiwL
T0 Tiw
RC OSCO Timing Waveform
RC - OSC PORT OSCO - RC
T1 T2 T3 T4 T5 T6 T7 T8 T1 T2 T3 T4 T5 T6
Built-in RC Oscillator
RESET
OSC
WDT Built-in RC Tosc1 (Tosc2, Tosc3) Twdt
20
SH66P20A
Typical RC oscillator Resistor vs. Frequency: (VDD = 3V, for reference only)
F (KHz)
10000
100
0 200 400 600 800 1000 1200 1400 1600 1800
R (K)
Typical RC oscillator Resistor vs. Frequency: (VDD = 5V, for reference only)
F (KHz)
10000
100
0 200 400 600 800 1000 1200 1400 1600 1800
R (K)
21
SH66P20A
Application Circuits (for reference only)
AP1: a. Operating voltage: 3.0V. b. Oscillator: Crystal 32.768KHz. c. PORTA - C: I/O.
33K
PA.0 PA.1 PA.2 PA.3
PB.0 PB.1 PB.2 PB.3 T0 VDD GND
PC.0 PC.1 PC.2 PC.3
I/O
SH66P20A
47K RESET OSCI OSCO 20p 20p
AP2: a. Operating voltage: 5.0V. b. Oscillator: Crystal 4MHz. c. PORTA - C: I/O.
47K
I/O
PA.0 PA.1 PA.2 PA.3 PC.0 PC.1 PC.2 PC.3 I/O
SH66P20A
PB.0 PB.1 PB.2 PB.3 T0 VDD GND
47K RESET OSCI OSCO 20p
20p
22
SH66P20A
AP3: a. Operating voltage: 5.0V. b. Oscillator: Ceramic 400KHz. c. PORTA - C: I/O.
33K PA.0 PA.1 PA.2 PA.3
PB.0 PB.1 PB.2 22K PB.3 T0 VDD GND
PC.0 PC.1 PC.2 PC.3
I/O
SH66P20A
47K
RESET
OSCI OSCO 100p 100p
0.1
AP4: a. Operating voltage: 5.0V. b. Oscillator: RC 400KHz. c. PORTA - C: I/O. d. Timer0 input: T0.
I/O 47K
PA.0 PA.1 PA.2 PA.3 PC.0 PC.1 PC.2 PC.3 I/O
SH66P20A
PB.0 PB.1 PB.2 PB.3 T0 VDD GND
47K RESET OSCI OSCO 470K
1000p
23
SH66P20A
AP5: Reset Protection Circuit 1
VDD
SH66P20A
33K 10K RESET 40K
RESET will be pulled to GND when VDD goes lower than Zener voltage + 0.7V.
AP6: Reset Protection Circuit 2
VDD R1
SH66P20A
10K RESET R2 40K
RESET will be pulled to GND when (VDD X R1/(R1 + R2)) is lower than 0.7V
24
SH66P20A
Bonding Diagram
P O R T A . 3 P O R T A . 2 P O R T A . 1 P O R T A . 0
G N D
G N D
O S C I
3 T0
RESET
2
1
21
20
19
18
4 Y 5 6 7 8 9 10 11 P O R T B . 3
GND GND PORTB.0 PORTB.1 PORTB.2
SH66P20A
(0,0) X
17 16 15
OSCO VDD PORTC.3 1520m
14 13 12 P O R T C . 0
PORTC.2 PORTC.1
1480m
unit : m Pad No. 1 2 3 4 5 6 7 8 9 10 11 Designation PORTA.2 PORTA.3 GND T0 RESET GND GND PORTB.0 PORTB.1 PORTB.2 PORTB.3 X -229.80 -480.30 -640.10 -659.55 -659.55 -657.35 -657.35 -659.55 -659.55 -659.55 -592.90 Y 677.60 677.60 691.20 558.75 415.75 283.30 161.40 26.40 -224.10 -397.70 -675.65 Pad No. 12 13 14 15 16 17 18 19 20 21 Designation PORTC.0 PORTC.1 PORTC.2 PORTC.3 VDD OSCO OSCI GND PORTA.0 PORTA.1 X 577.95 664.60 664.60 664.60 627.30 625.40 422.45 290 155 -95.50 Y -675.65 -397.70 -224.10 26.40 195.40 325.40 645.65 641.55 677.60 677.60
note: The all GND pins must be connected together outside the chip and the substrate must be connected with GND.
25
SH66P20A
Ordering Information
Part No. SH66P20A-yyxxx/018DU SH66P20AM-yyxxx/018MU Package 18L DIP 18L SOP Packing Tube Tube
Note: (1) "-yyxxx": "yy" means 2 bits option and "xxx" means 3 bits code seriary number. If the product is OTP type and in blank order, those bits should be none. (2) The data after mark "/" in Part No. block is the package and packing information for ordering. (3) The size of those package types are showed in "Package Information" (Page27 - Page28). (4) Any other package or packing request, please refer to following table. Package D F H J K L M N Q S T V W X DIP QFP CHIP CER-DIP SKINNY PLCC SOP OTHER GOOD DIE ON WAFER SOJ TO92 VSOP/TSOP WAFER TSSOP R U A D L B T S N Packing Normal package size and in tray packing Normal package size and in tube packing Normal package size and in tape & reel packing Larger package size and in tray packing Larger package size and in tube packing Larger package size and in tape & reel packing Smaller package size and in tray packing Smaller package size and in tube packing Smaller package size and in tape & reel packing
26
SH66P20A
Package Information
DIP 18L Outline Dimensions
D 18 10
unit: inches/mm
E1
1 S
9 E C
A2
A
A1
Base Plane Seating Plane B B1 e1 eA
L
Symbol A A1 A2 B B1 C D E E1 e1 L eA S
Dimensions in inches 0.175 Max. 0.010 Min. 0.130 0.010 0.018 +0.004 -0.002 0.060 +0.004 -0.002 0.010 +0.004 -0.002 0.900 Typ. (0.920 Max.) 0.300 0.010 0.250 Typ. (0.262 Max.) 0.100 0.010 0.130 0.010 0 ~ 15 0.345 0.035 0.055 Max.
Dimension in mm 4.45 Max. 0.25 Min. 3.30 0.25 0.46 +0.10 -0.05 1.52 +0.10 -0.05 0.25 +0.10 -0.05 22.86 Typ. (23.37 Max.) 7.62 0.25 6.35 Typ. (6.65 Max.) 2.54 0.25 3.30 0.25 0 ~ 15 8.76 0.89 1.40 Max.
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension S includes end flash.
27
SH66P20A
SOP 18L Outline Dimensions unit: inches/mm
18
9 e1 ~ ~
HE
E
L 1 b 9
Detail F
D e1 c A2 Seating Plane y A1 S
e
D
A
LE See Detail F
Symbol A A1 A2 b C D E e e1 HE L LE S y
Dimensions in inches 0.110 Max. 0.004 Min. 0.092 0.005 0.016 +0.004 -0.002 0.010 +0.004 -0.002 0.455 0.015 0.295 0.010 0.050 0.006 0.376 NOM. 0.406 0.012 0.030 0.008 0.055 0.008 0.037 Max. 0.004 Max. 0 ~ 10
Dimensions in mm 2.79 Max. 0.10 Min. 2.33 0.13 0.41 +0.10 -0.05 0.25 +0.10 -0.05 11.56 0.38 7.49 0.25 1.27 0.15 9.50 NOM. 10.31 0.31 0.76 0.20 1.40 0.20 0.94 Max. 0.10 Max. 0 ~ 10
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.
28
SH66P20A
Data Sheet Revision History
Version 2.3 2.2 2.1 1.0 Content Add package and packing information in ordering information Change RC Frequency Variation to 20% Add Reset Protection Circuit (AP5 and AP6) Original Date Jul. 2004 Apr. 2002 Feb. 2002 Jun. 2000
29

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