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LSIs for MPEG
MN673794
1. Overview
This IC is used to process a variety of items including the following ones: NTSC/PAL signal (Y/C and composite video) I/O, 3D Y/C separation, TBC, DD conversion, frame sync, sync/clock generation, Rec 656 I/O, and DV input. Features Analog input block Composite video/Component Y input (10 bits at 27.0 MHz) Component C input (10 bits at 27.0 MHz) Analog control block AGC (Auto Gain Control) control, clamp control, ACC (Auto Color Control) control Digital I/O block Digital video I/O (ITU-R Rec 656: Y/Cr/Cb multiple, 8 bits at 27 MHz) Signal processing block 3D Y/C separation (image movement adaptive processing: NTSC), 2D Y/C separation (PAL) TBC (Time Base Corrector) processing (velocity error correction/jitter correction) Frame sync processing (See Note.) NR processing (Y/C recursive NR) Y/C separation is performed only in two dimensions (due to memory sharing) when the NR function is in use. Copyright VBLK detection Macrovision (AGC pulse and color stripe) detection VBID detection Closed caption detection WSS detection Note: This IC uses a 27-MHz fixed clock. Therefore, input signals into the IC are not synchronized with output signals from the IC. Therefore, a frame-skip or frame-hold occurs to standard and nonstandard signals, the frequency of occurrence of which varies with the difference in frame frequency between input signals and the 27-MHz fixed clock. If the user does not want the occurrence of any frame-skip or frame-hold to standard signals, externally generate 27-MHz clock pulses synchronized with the frames of the input signals, and input the clock pulses into the IC. A frame-skip refers to loss of the image in a single frame. A frame-hold refers to the duplicated output of the image in the previous frame.
Publication date: June 2002
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MN673794 2. Specifications
2.1 Electrical Characteristics * Maximum operating frequency 27.0 MHz
* Operating supply voltage 3.0 V to 3.6 V (Analog power supply) 3.0 V to 3.6 V (Digital I/O power supply 1) 2.0 V to 2.4 V (Digital I/O power supply 2: DV interface only) 3.0 V to 3.6 V when DV interface is not in use. 1.65 V to 1.95 V (Internal digital power supply) 2.3 V to 2.7 V (Internal DRAM power supply) * Package 208-pin QFP with 28-mm square (0.5-mm pitch) (Package code No. LQFP208-P-2828)
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2.2 Pin Descriptions Table 2.2 shows the explanation of the pins of the IC. Table 2.2 Pin Descriptions (1/4)
Pin No. 1 2 3 4 5 6 7 Pin name CLK18O2 VDD3 CLK45I VSS VDDI DSF7 DSF6 I/O O Power supply I GND Power supply I/O I/O GND I/O I/O Power supply I/O I/O GND I/O I/O Power supply O O GND O O Power supply O GND GND I/O Power supply GND I I I O Power supply GND I I I O Power supply GND I I I O Power supply O GND O I Power supply O Voltage Type Drive 4 mA 4 mA 4 mA Function 18-MHz clock output 2 Digital I/O (3.3 V) use 4.5-MHz clock input (VSS when not used) Digital use Internal digital use Shuffling data I/O (MSB) (open or VSS when not used) Shuffling data I/O (open or VSS when not used) Clock 18 MHz 4.5 MHz 18 MHz 18 MHz 18 MHz 18 MHz 18 MHz 18 MHz 18 MHz 18 MHz 18 MHz 18 MHz 18 MHz 27 MHz 27 MHz 1 MHz 1 MHz 1 MHz BST YES YES YES YES YES YES YES YES YES YES -
3.3 V CMOS 3.3 V Crystal interface 1.8 V 2.2 V CMOS-100 k PD 2.2 V CMOS-100 k PD 2.2 V CMOS-100 k PD 2.2 V CMOS-100 k PD 2.2 V 2.2 V CMOS-100 k PD 2.2 V CMOS-100 k PD 2.2 V CMOS-100 k PD 2.2 V CMOS-100 k PD 2.2 V 2.2 V 2.2 V 2.2 V 2.2 V 2.2 V 2.2 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V CMOS CMOS CMOS CMOS CMOS Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog -
8 VSS 9 DSF5 10 DSF4 11 VDD2 12 DSF3 13 DSF2 14 VSS 15 DSF1 16 DSF0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 VDD2 CASHD CASVD VSS CLK188 CLK450 VDD2 CLK18O1 VSS AVSS1 TPLL AVDD1 AVSS2 VREFCK IREFCK COMPCK CK45O AVDD2 AVSS3 VREFC IREFC COMPC OUTC AVDD3 AVSS4 VREFY IREFY COMPY OUTY AVDD4 AGCO AVSS5 CLPOS
Digital use 4 mA Shuffling data I/O (open or VSS when not used) 4 mA Shuffling data I/O (open or VSS when not used) Digital I/O (2.2 V) use 4 mA Shuffling data I/O (open or VSS when not used) 4 mA Shuffling data I/O (open or VSS when not used) Digital use 4 mA Shuffling data I/O (open or VSS when not used) 4 mA Shuffling data I/O (LSB) (open or VSS when not used) Digital I/O (2.2 V) use 2 mA CAS HD output 2 mA CAS VD output Digital use 2 mA Clock 2 mA Clock Digital I/O (2.2 V) use 4 mA 18-MHz clock output 1 Digital use PLL (18 MHz) use PLL (18 MHz) test use PLL (18 MHz) use D/A (CLK) use D/A (CLK) reference voltage input D/A (CLK) bias current setting D/A (CLK) stabilization 4.5-MHz clock output D/A (CLK) use D/A (COUT) use D/A (COUT) reference voltage input D/A (COUT) bias current setting D/A (COUT) stabilization C output (analog) D/A (COUT) use D/A (YOUT) use D/A (YOUT) reference voltage input D/A (YOUT) bias current setting D/A (YOUT) stabilization Y output (analog) D/A (YOUT) use AGC control output Voltage dividing resistor DAC (ACC, CLAMP, and AGC) use Clamp control output (for sync tip clamp use) Reference voltage input for voltage dividing resistor DAC use (Capacitance coupling to AVSS) Voltage dividing resistor DAC (ACC, CLAMP, and AGC) use ACC control output
50 VREFMA 51 AVDD5 52 ACCO
3.3 V Analog
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Table 2.2 Pin Descriptions (2/4)
Pin No. 53 54 55 56 Pin name AVDD6 CIN AVSS6 VREFLC I/O Type Voltage Power supply 3.3 V Analog I Analog GND I Analog I I I I GND Power supply Power supply I GND I I I I I GND Power supply GND O Power supply O I/O I/O GND I/O I/O Power supply I/O I/O GND Power supply GND I/O I/O Power supply I/O I/O GND I O Power supply I I I GND I I I I 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 1.8 V 3.3 V 3.3 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 1.8 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Drive 2 mA 2 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 2 mA Function A/D (C) use C input (analog) A/D (C) use A/D (C) reference voltage low-level input A/D (C) intermediate reference potential input (AVSS capacitance connection) A/D (C) intermediate reference potential input (AVSS capacitance connection) A/D (C) intermediate reference potential input (AVSS capacitance connection) A/D (C) reference voltage high-level input A/D (C) use A/D (C) use A/D (Y and composite) use Composite video input (analog) A/D (Y and composite) use A/D (Y and composite) reference voltage low-level input A/D (Y and composite) intermediate reference potential input (AVSS capacitance connection) A/D (Y and composite) intermediate reference potential input (AVSS capacitance connection) A/D (Y and composite) intermediate reference potential input (AVSS capacitance connection) A/D (Y and composite) reference voltage high-level input A/D (Y and composite) use A/D (Y and composite) use Digital use 6.75-MHz output Digital I/O (3.3 V) use Clamp pulse (sync chip) output Test I/O (MSB) (open or VSS) Test I/O (open or VSS) Digital use Test I/O (open or VSS) Test I/O (open or VSS) Internal digital use Test I/O (open or VSS) Test I/O (open or VSS) Digital use DRAM (5 Mbits) use Digital use Test I/O (open or VSS) Test I/O (open or VSS) Digital I/O (3.3 V) use Test I/O (open or VSS) Test I/O (LSB) (open or VSS) Digital use Boundary scan clock input Boundary scan data output Internal digital use Boundary scan data input Boundary scan reset input (VSS or RST when not used Boundary scan mode input Digital use Test mode (MSB) (open or VSS) Test mode (open or VSS) Test mode (open or VSS) Test mode (open or VSS) Clock 27 MHz 27 MHz 27 MHz BST -
57 VREFMLC 58 VREFMC 59 VREFHMC 60 61 62 63 64 65 66 VREFHC AVSS7 AVDD7 AVDD8 VIDEO AVSS8 VREFLY
67 VREFMLY 68 VREFMY 69 VREFHMY 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 VREFHY AVSS9 AVDD9 VSS ANACLK VDD3 GCP TESTIO9 TESTIO8 VSS TESTIO7 TESTIO6 VDDI TESTIO5 TESTIO4 VSS VDDDRAM0 VSSDRAM0 TESTIO3 TESTIO2 VDD3 TESTIO1 TESTIO0 VSS TCK TDO VDDI TDI TRST TMS VSS TEST5 TEST4 TEST3 TEST2
CMOS
CMOS CMOS-100 k PD CMOS-100 k PD CMOS-100 k PD CMOS-100 k PD CMOS-100 k PD CMOS-100 k PD CMOS-100 k PD CMOS-100 k PD CMOS-100 k PD CMOS-100 k PD CMOS-100 k PD 3-state CMOS CMOS-100 k PU CMOS-100 k PU CMOS-100 k PU CMOS-100 k PD CMOS-100 k PD CMOS-100 k PD CMOS-100 k PD
When the boundary scan function is not used, set the TRST pin (pin 98) to reset input or VSS.
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Table 2.2 Pin Descriptions (3/4)
Pin No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Pin name TEST1 TEST0 VDDI VSS MINTC1 MINTIN1 MINTEST VDD3 PDRAM0 PDRAM1 VSSDRAM1 VDDDRAM1 NTDRAM VSS VDDI CLK27I VSS R656IN7 R656IN6 VDD3 R656IN5 R656IN4 VSS VDDDRAM2 VSSDRAM2 R656IN3 R656IN2 VDD3 R656IN1 R656IN0 VSS CLK27O VDDI R656OUT7 R656OUT6 VSS R656OUT5 R656OUT4 VDD3 R656OUT3 R656OUT2 VSS R656OUT1 R656OUT0 VDDI VSS HD VD VDD3 APCE VSS CSYNCO I/O Type Voltage I 3.3 V CMOS-100 k PD I 3.3 V CMOS-100 k PD Power supply 1.8 V GND I 3.3 V CMOS I 3.3 V CMOS I 3.3 V CMOS-30 k PD Power supply 3.3 V I 3.3 V CMOS-100 k PD I 3.3 V CMOS-100 k PD GND Power supply 2.5 V I 3.3 V CMOS-100 k PD GND Power supply 1.8 V I 3.3 V CMOS GND I 3.3 V CMOS-100 k PD I 3.3 V CMOS-100 k PD Power supply 3.3 V I 3.3 V CMOS-100 k PD I 3.3 V CMOS-100 k PD GND Power supply 2.5 V GND I 3.3 V CMOS-100 k PD I 3.3 V CMOS-100 k PD Power supply 3.3 V I 3.3 V CMOS-100 k PD I GND O Power supply O O GND O O Power supply O O GND O O Power supply GND I/O I/O Power supply O GND O 3.3 V 3.3 V 1.8 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 1.8 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V CMOS-100 k PD CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS-100 k PU CMOS-100 k PU 3-state CMOS CMOS Drive 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 2 mA 2 mA Function Test mode (open or VSS) Test mode (LSB) (open or VSS) Internal digital use Digital use Test input VSS) Test input VSS) Test input open or VSS) Digital I/O (3.3 V) use DRAM test input (open or VSS) DRAM test input (open or VSS) Digital use DRAM (5 Mbits) use DRAM test input (open or VSS) Digital use Internal digital use 27-MHz clock for Rec 656 input (VSS when not used) Digital use Digital video (Rec 656) input (MSB) (open or VSS when not used) Digital video (Rec 656) input (open or VSS when not used) Digital I/O (3.3 V) use Digital video (Rec 656) input (open or VSS when not used) Digital video (Rec 656) input (open or VSS when not used) Digital use DRAM (7 Mbits) use Digital use Digital video (Rec 656) input (open or VSS when not used) Digital video (Rec 656) input (open or VSS when not used) Digital I/O (3.3 V) use Digital video (Rec 656) input (open or VSS when not used) Digital video (Rec 656) input (LSB) (open or VSS when not used) Digital use 27-MHz clock output Internal digital use Digital video (Rec 656) output (MSB) Digital video (Rec 656) output Digital use Digital video (Rec 656) output Digital video (Rec 656) output Digital I/O (3.3 V) use Digital video (Rec 656) output Digital video (Rec 656) output Digital use Digital video (Rec 656) output Digital video (Rec 656) output (LSB) Internal digital use Digital use Test I/O (open or VDD3) Test I/O (open or VDD3) Digital I/O (3.3 V) use Phase error output Digital use Composite sync detection output Clock 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz BST YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES
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Table 2.2 Pin Descriptions (4/4)
Pin No. 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Pin name MICONRWW VDD3 MICONRWR VSSDRAM3 VDDDRAM3 RST VSS CLK27XI CLK27XO VDDI VSS MAD6 MAD5 MAD4 VDD3 MAD3 MAD2 MAD1 MAD0 VSS MDA15 MDA14 VDDI MDA13 MDA12 VSS MDA11 MDA10 VDD3 MDA9 MDA8 VSS MDA7 MDA6 VDDI MDA5 MDA4 VSS MDA3 MDA2 VDD3 MDA1 MDA0 VSS MCSALE MNRE MNWENBW MICOMSEL NC3 VDDI INF FRP I/O Type Voltage O 3.3 V CMOS Power supply 3.3 V O 3.3 V CMOS GND Power supply 2.5 V I 3.3 V CMOS-100 k PU GND I Crystal interface O Crystal interface Power supply 1.8 V GND I/O 3.3 V Schmitt CMOS I/O 3.3 V Schmitt CMOS I/O 3.3 V Schmitt CMOS Power supply 3.3 V I/O 3.3 V Schmitt CMOS I/O 3.3 V Schmitt CMOS I/O 3.3 V Schmitt CMOS I/O 3.3 V Schmitt CMOS GND I/O 3.3 V CMOS I/O 3.3 V CMOS Power supply 1.8 V I/O 3.3 V CMOS I/O 3.3 V CMOS GND I/O 3.3 V CMOS I/O 3.3 V CMOS Power supply 3.3 V I/O 3.3 V CMOS I/O 3.3 V CMOS GND I/O 3.3 V CMOS I/O 3.3 V CMOS Power supply 1.8 V I/O 3.3 V CMOS I/O 3.3 V CMOS GND I/O 3.3 V CMOS I/O 3.3 V CMOS Power supply 3.3 V I/O 3.3 V CMOS I/O 3.3 V CMOS GND I/O 3.3 V Schmitt CMOS I/O 3.3 V Schmitt CMOS I/O 3.3 V Schmitt CMOS 3.3 V Schmitt CMOS I/O I/O 3.3 V Schmitt CMOS Power supply 1.8 V I 3.3 V CMOS-100 k PD O 3.3 V CMOS Drive 2 mA 2 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 4 mA Function Microcontroller interrupt write sync signal output Digital I/O (3.3 V) use Microcontroller interrupt read) sync signal output Digital use DRAM (7 Mbits) use Reset input Digital use 27-MHz clock (crystal) input 27-MHz clock (crystal) output Internal digital use Digital use Microcontroller interface data/address input MSB Microcontroller interface data/address input Microcontroller interface data/address input Digital I/O (3.3 V) use Microcontroller interface data/address input Microcontroller interface data/address input Microcontroller interface data/address input Microcontroller interface data/address input LSB Digital use Microcontroller interface data/address I/O MSB Microcontroller interface data/address I/O Internal digital use Microcontroller interface data/address I/O Microcontroller interface data/address I/O Digital use Microcontroller interface data/address I/O Microcontroller interface data/address I/O Digital I/O (3.3 V) use Microcontroller interface data/address I/O Microcontroller interface data/address I/O Digital use Microcontroller interface data/address I/O Microcontroller interface data/address I/O Internal digital use Microcontroller interface data/address I/O Microcontroller interface data/address I/O Digital use Microcontroller interface data/address I/O Microcontroller interface data/address I/O Digital I/O (3.3 V) use Microcontroller interface data/address I/O Microcontroller interface data/address I/O (LSB) Digital use Microcontroller interface chip select input Microcontroller interface read input Microcontroller interface write input Microcontroller interface selection input Microcontroller interface mode selection input (Normal mode: VSS) Internal digital use DV interface frame signal input (open or VSS when not used) FRP output Clock 27 MHz 27 MHz 27 MHz 27 MHz 24 MHz 18 MHz BST YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES
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2.3 Pin Assignment Figure 2.3 shows the pin assignment of the IC.
M IM CN M OW C M V MM ME S F I DN N N V DD A S R N DC B R S A A L E PF I 3 WE S 01 E L MM CC VV I I LL DSC C M M M M MM KK DSO O V MM MM V M M M M V D D D D V D D M M M M V M M M V 2 2 D D NVN V D D D D D V D D D A A V A A D A A V A A A A D A A AV D 7 7 V R D DD R R R DR D A A S A A D A A S A A D 1 1 S 1 1 D 1 1 S D D D D D D D DS D X X S S A A D W W 3 2 3 S 4 5 I 6 7 S 8 9 3 0 1 S 2 3 I 4 5 S 0 1 2 3 3 4 5 6S I O I S T M M 3 W R
CLK18O2 VDD3 CLK45I VSS VDDI DSF7 DSF6 VSS DSF5 DSF4 VDD2 DSF3 DSF2 VSS DSF1 DSF0 VDD2 CASHD CASVD VSS CLK188 CLK450 VDD2 CLK18O1 VSS AVSS1 TPLL AVDD1 AVSS1 VREFCK IREFCK COMPCK CK45O AVDD1 AVSS1 VREFC IREFC COMPC OUTC AVDD1 AVSS1 VREFY IREFY COMPY OUTY AVDD1 AGCO AVSS1 CLPOS VREFMA AVDD1 ACCO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
MN673794
CSYNCO VSS APCE VDD3 VD HD VSS VDDI R656OUT0 R656OUT1 VSS R656OUT2 R656OUT3 VDD3 R656OUT4 R656OUT5 VSS R656OUT6 R656OUT7 VDDI CLK27O VSS R656IN0 R656IN1 VDD3 R656IN2 R656IN3 VSSDRAM VDDDRAM VSS R656IN4 R656IN5 VDD3 R656IN6 R656IN7 VSS CLK27I VDDI VSS NTDRAM VDDDRAM VSSDRAM PDRAM1 PDRAM0 VDD3 MINTEST MINTIN1 MINTC1 VSS VDDI TEST0 TEST1
54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103
AC AVV VVV V I VRR RRR DN S E E E E E D SFF FFF 1 1 L M MH H C L C MC CC
AA A VA VV V I V S D D DS S D D ES 1 1 1 O1
V V V V V A A V A V G T T V T T V T T V V V T T V T T V T T V T T TV T T T T R R R R R V V S N D C E E S E E D E E S D S E E D E E SC D D D R MS E E E E E E E E E S D S A D P S S S S S D S S S D S S S D S S SK OD I S S S S S S S F F F F F S D C 3 T T T T I T T DD T T 3 T T IT TT TT L MM H H 1 1 L I I I I RR I I I I II 54 32 K Y L Y MY OO O O O O A A O O OO YY 9 8 7 6 5 4 MM 3 2 1 0
Figure 2.3 Pin Assignment
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RST
CLK27XI CLK27XO
DRAM (5Mbit)
Clock Generation ANACLK CLK27O
R656IN 70
input processing
8
CLK27I S Frame E sync L S E reducL tion Rec.656 S output E L processing
Noise
R656OUT 70
2.4 Block Diagram Figure 2.4 shows the block diagram of the IC.
Analog input processing
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2D/3D YC
separation
DRAM (7Mbit)
Digital clamp
VIDEO
A/D
Line TBC/ DD
Conversion
LPF
DD
10bit
6 MHz
27 MHz
Conversion
Sync
Copyright detection
Microcontroller
APCE CSYNCO GCP
separation
CLPOS
D/A MDA150 Microcontroller interface DD
S E
decode Chroma
AGCO
D/A
ACCO
D/A
Analog control
CIN
conversion
L
A/D
ACC APC
LPF
10bit
6 MHz
MAD60 MNWENBW MNRE MCSALE
27 MHz
MICONRWW MICONRWR
NC3 MICOMSEL
8
MN673794 3. Microcontroller Interface
(1) Overview Data is written to and read from the internal registers of the IC through microcontroller interfaces. A microcontroller to be connected to the IC has two types of interfaces in consideration of two cases, where the address, data, and control line are synchronous with the system clock of the IC and where they are not synchronous with the system clock. The two types of interfaces are available in both cases. One of them is an address/data multiple bus interface, which enables the data bus to be overlapped with addresses, and the other is an interface for address/data bus separation. These cases and types are selectable with the external pins of the IC as shown in table 3.1. Table 3.1 Pin setting (Pin number)
No. 205 (NC3) 0 1 0 1 0 0 1 1
No. 204 (MICOMSEL)
Protocol Settings for Microcontroller Interface Protocol Sync/Async with Separation/Multiple system clock address data bus Async Separation Sync Separation Async Multiple Sync Multiple
(2) Microcontroller Interface Signals Table 3.2 shows the respective microcontroller interface signals and corresponding pins that appear in the microcontroller timing chart. Table 3.2 Interface Signals and Corresponding Pins Interface Interface (separation/multiple) (separation/multiple) Signal signals not synchronous signals synchronous with with system clock system clock
MAD MDA MCSALE MNWENBW MNRE Adress Data CS WE RE
Address Data CS (chip select) WE (write enable) RE (read enable)
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(3) Timing [a] System Clock Async/Separation Bus Interface Figure 3.3 (a) is the timing chart of the interface.
READ cycle (trdc) WRITE cycle (twrc)
tawrs
MAD[6:0] Valid Valid
tawrh tdwrh twrw_cs
tdwrs
MDA[15:0] Read Data Write Data
trdout
MCSALE
twrcs_w
trdw
MNRE MNWENBW
twrw
Timing
[ns] Min 148 148 74 74 10 10 Max 30
trdc trdout twrc trdw twrw twrcs_w twrw_cs tdwrs tdwrh tawrs tawrh
Read cycle Read data valid Write cycle Read pulse (MNRE) width Write pulse (MNWENBW) width CS enable after WE active WE negate after CS disable Write data setup Write data hold Write address setup Write address hold
twrw
0
twrw
10
Figure 3.3 (a) Microcontroller Interface Timing 1
* Note) * When the signal timing changes to the read cycle from the write cycle, data reading must start at least 50 ns after the write cycle completes. *
In the case of continuous data writing, a minimum of 148 ns is required between the falling edge of the present write enable (MNWENBW) and that of the next write enable.
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[b] System Clock Async/Multiple Bus Interface Figure 3.3 (b) is the timing chart of the interface.
READ cycle (trdc) MAD[6:0] WRITE cycle (twrc)
trdout
MDA[15:0] Address Read Data Valid Address
twrs
twrh
Write Data
MCSALE MNRE MNWENBW
trdw twrw
Timing
trdc trdout twrc trdw twrw twrs twrh
Read cycle Read data valid Write cycle Read pulse (MNRE) width Write pulse (MNWENBW) width Write data setup Write data hold
twrw
10
Min 148 148 74 74
[ns]
Figure 3-3 (b) Microcontroller Interface Timing 2
Max 30
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[c] System Clock Sync /Separation Bus Interface Figure 3.3 (c) is the timing chart of the interface.
CLK (I)
t cyc
Address (I) CS (I) Write timing WE (I)
Address Valid
Data (I)
Data Valid
t WDS t WDH
Read timing RE (I) Data (O)
t RREDT
Data Valid
t RCSDT
Parameter 27-MHz clock cycle Write data setup based on rising edge of write enable WE Write data hold (based on rising edge of write enable WE) Read data delay (based on falling edge of read enable RE) Read data hold (based on rising edge of chip select CS)
Figure 3.3 (c)
Symbol tCYC tWDS tWDH tRREDT tRCSDT
Min tCYC tCYC 0 0
Typ 37
Max
Unit ns ns ns
tCYC
ns ns
Microcontroller Interface Timing 3
* *
Address, Data, CS, WE, and RE input signals are input not synchronous with the CLK clock signal. The CS must be disabled (i.e., set high) whenever data is read from or written to any address.
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[d] System Clock Async/Multiple Bus Interface Figure 3.4 (d) is the timing chart of the interface.
CLK (I) CS (I) Write timing WE (I) Address (I) /Data (I) Read timing RE (I) Address (I) /Data (O) Address Valid t RAS tRAH t RRED
T
t cyc
Address Valid t WAS tWAH
Data Valid t WDS t WDH
Data Valid t RCSD
T
Parameter Symbol Min Typ 27-MHz clock cycle tCYC 37 Write address setup tWAS tCYC based on falling edge of address latch enable ALE Write address hold tCYC tWAH based on falling edge of address latch enable ALE Read address setup tCYC tRAS based on falling edge of address latch enable ALE Read address hold tCYC tRAH based on falling edge of address latch enable ALE Write data setup tWDS tCYC based on rising edge of write enable WE Write data hold tWDH tCYC (based on rising edge of write enable WE) Read data delay tRREDT 0 (based on falling edge of read enable RE) Read data hold tRCSDT 0 (based on rising edge of chip select CS) Figure 3.3 (d) Microcontroller Interface Timing 4
Max
Unit ns ns ns ns ns ns ns
tCYC
ns ns
* Address, Data, CS, WE, and RE input signals are input not synchronous with the CLK clock signal.
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(4) Microcontroller Registers [a] Read/Write Addresses 0040h to 0046h, 0048h, and 004Ah are read-only registers. Data can be written to and read from addresses with register marks if they are not read-only registers. Although data can be written to addresses with no register marks, the accuracy of data read from such addresses is not guaranteed. [b] Special Registers Addresses 0043h and 0044h are registers the functions of which vary with the signal mode settings for the registers. NTSC mode: Register for VBID detection PAL mode: Register for WSS detection (The register table in WSS mode is different.) [c] Video Signal Mode Settings A video signal mode is set with three bits. These bits have the following meanings. Bit Meaning 0 1 [2] Line 525-line mode 625-line mode [1] Processing frequency (4fsc) 14 MHz line 17 MHz line [0] Phase Alt No Yes Make the following settings for respective signal modes. [2:0] 000 001 010 011 100 101 110 111 System NTSC PAL-M NTSC443 (PAL-60) PAL-N PAL
Make sigmod 0000h [2:0] settings for the signal modes of the analog input processing block, frame sync processing block, Rec 656 input processing block, and Rec 656 output processing block. Make sigmodpb 0000h [6:4] settings for the signal modes of the analog output processing block.
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MN673794
RST
CLK27XI
CLK27XO
DRAM (5Mbit)
Clock Generation ANACLK CLK27O
[d] Write Registers
R656IN 70 Rec.656
input processing
8
CLK27I S Frame E sync L S E reducL tion Rec.656 S output E L processing
Noise
R656OUT 70
Analog input processing
Figure 3.4 shows the block diagram for the write registers.
SDF00032AEM
2D/3D YC
separation
DRAM (7Mbit)
Digital clamp
VIDEO
A/D
Line TBC/ DD
Conversion
LPF
DD
10bit
6 MHz
27 MHz
Conversion
Sync
Copyright detection
Microcontroller
APCE CSYNCO GCP
separation
CLPOS
D/A
AGCO
D/A
ACCO
S E
decode Chroma
D/A
Analog control
Microcontroller interface ACC APC
CIN
L
A/D
LPF
DD
10bit
6 MHz
conversion
MDA150 MAD60 MNWENBW MNRE MCSALE
27 MHz
MICONRWW MICONRWR
NC3 MICOMSEL Explanations of registers
15
MN673794
1. Control system
cpsh
Register name
Address 0000h[15]
Description Used to select the mode of the analog input processing block. 0: Component input, 1: Composite input
Default
1
fsinsel r656outsel sigmod
0000h[13:12] Used to select the input of the frame sync block. 00: Analog input, 01: Rec 656 input, 10: Test use, 11: Not used 0000h[11] 0000h[2:0] Used to select the input of the Rec 656 output processing block. 0: Noise reduction output, 1: Rec 656 input Used to set the signal modes of the analog input processing block, frame sync processing block, Rec 656 input processing block, and Rec 656 output processing block. 000: NTSC, 001: PAL-M 010: NTSC443, 011: PAL-60 100: 101: PAL-N 110: 111: PAL Description The detected movement area is displayed dark (for evaluation). 0: Normal, 1: Movement detection display A threshold value to determine movement with two-frame differential movement detected. (Compared with the 9-bit absolute value converted from the 10-bit difference between the 9-bit input signal and 2-frame, 9bit delay signal.) 000: 3D fixed, 001: 4 or more, 010: 8 or more, 011: 12 or more 100: 16 or more, 101: 20 or more, 110: 24 or more, 111: 28 or more (To fix the setting to 3D, set the F3DSEL register to 000 and the F2DSEL register to 000. To fix the setting to 2D, set the F3DSEL to any value other than 000 and set the F2DSEL to 000.)
00 0 00
2. Y/C separation
HYOZI
Register name
Address 0008h[6]
Default
0
F3DSEL
0008h[5:3]
100
F2DSEL
0008h[2:0]
A threshold value to determine movement with one-frame differential movement detected. (Compared with the 9-bit absolute value converted from the 10-bit difference between the 9-bit input signal and 1-frame, 9bit delay signal.) 000: 2D fixed, 001: 4 or more, 010: 8 or more, 011: 12 or more 100: 16 or more, 101: 20 or more, 110: 24 or more, 111: 28 or more (To fix the setting to 3D, set the F3DSEL register to 000 and the F2DSEL register to 000. To fix the setting to 2D, set the F3DSEL to any value other than 000 and set the F2DSEL to 000.)
100
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MN673794
3. Y/C delay adjustment Register name Address cdly2 0009h[7:6]
Description Used to adjust the delay of the component C signal (in 4fsc increments). (DD conversion output of C signal of analog input processing block) 00: No delay, 01: +1 clock 10: -2 clock, 11: -1 clock Used to adjust the delay of the component C signal (in 27 MHz increments). (LPF output of C signal of analog input processing block) 0: No delay, 1: +1 clock Used to adjust the delay of the CbCr multiple signal (in 4fsc increments). (Before TBC input into the analog input processing block) 00: No delay, 01: +1 clock 10: -2 clock, 11: -1 clock Used to reverse the polarity of the CbCr separation flag for the CbCr multiple signal. If the tint is reversed with tbccdly delay adjustments, invert this flag. (Before TBC input into the analog input processing block) 0: No reversion, 1: Reversion
Default 00
cdly1
0009h[5]
0
tbccdly
0009h[9:8]
00
cflgdly
0029h[0]
0
4. Rec 656 output Register name Address VideoOutsel 002Eh[1:0]
Description Used to switch over the valid pixels of the Rec 656 output signal to blue or black background. 0X: Normal, 10: Black background, 11: Blue background
Default 00
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MN673794
5. Noise reduction (NR) Register name Address Setnrin 003Ch[15] SetTof
Description Used to switch over the input into the noise reduction block. 0: Frame sync output, 1: Rec 656 input
Default
0
003Ch[14:13] Used to make through/NR settings in the noise reduction block. 0X: NR block through 10: NR OFF, 11: NR ON 003Ch[12] 003Ch[9:5] Used to set the circulation-type 3D control. 0: Frame circulation NR, 1: Field circulation NR Used to set the threshold value that enables the C in the Y frame/field differential signal to bypass the NR. Threshold value=SetMdet[6:2]*2 (Example: If the SetMdet value is 01000, a threshold of 16 will be set.) 003Ch[4:3] Used to set the width (range) that enables the C in the Y frame/field differential signal to bypass the NR. 00: +1, 01: 1, 10: 2, 11: 3
00
Set3dnr SetMdet
0 01000
01
SetMvVi ydnslp yupslp
003Ch[2]
The detected movement area is displayed dark (for evaluation). 0: Normal, 1: Movement detection display
0 010 1000
003Dh[12:10] Used to set the negative slope of the maximum Y frame/field differential value. (See below for the characteristics.) 003Dh[9:6] Used to set the positive slope of the minimum Y frame/field differential value. Gain=yupslp[3:0]/16 (See below for the characteristics.) Used to set the change point between the above ydnslp (negative slope) and yupslp (positive slope). (See below for the characteristics.)
yudchg cdnslp cupslp
003Dh[5:0]
010000 010 1000
003Eh[12:10] Used to set the negative slope of the maximum C frame/field differential value. (Same as Y in characteristics.) 003Eh[9:6] Used to set the positive slope of the minimum C frame/field differential value. Gain=cupslp[3:0]/16 (Same as Y in characteristics.) Used to set the change point between the above cdnslp (negative slope) and cupslp (positive slope). (Same as Y in characteristics.)
cudchg
003Eh[5:0]
010000
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MN673794
ROM output yupslp cupslp ydnslp cdnslp
yudchg cudchg
Frame/field differential value
NR-ROM Characteristics
Input
-
ROM
-
Output
Frame/Field Memory
NR Block Diagram
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MN673794
6. Frame sync Register name
wr_offset
Address 0017h[4:0]
Description Frame sync, write line start position offset (23 lines + offset value)
Default 00000
7. Analog power down (Possible to reduce the power consumption of the corresponding functions when the functions are not in use.) Register name Address Description Default yadpdwn 0039h[8] 0 Used to power down the component Y/composite Y (analog output) ADC. 0: Normal, 1: Power down cadpdwn ydapdwn cdapdwn clkdapdwn agcdapdwn accdapdwn clpdapdwn pllpdwn 0039h[7] 0039h[6] 0039h[5] 0039h[4] 0039h[3] 0039h[2] 0039h[1] 0039h[1] Used to power down the component C (analog output) ADC. 0: Normal, 1: Power down Used to power down the component Y (analog output) DAC. 0: Normal, 1: Power down Used to power down the component C (analog output) DAC. 0: Normal, 1: Power down Used to power down the DAC for DV 18-MHz clock generation. 0: Normal, 1: Power down Used to power down the AGC control DAC. 0: Normal, 1: Power down Used to power down the ACC control DAC. 0: Normal, 1: Power down Used to power down the clamp control DAC. 0: Normal, 1: Power down Used to power down the 4x PLL for DV 18-MHz clock generation. 0: Normal, 1: Power down 0 0 0 0 0 0 0 0
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MN673794
[e] Read Registers 1. Macrovision immvh 0041h[15] spiso spgcnt sppos spcnt
Result of AGC pulse detection 0: No, 1: Yes 0041h[14:13] Result of color stripe phase detection 00: 0 , 01: 90 , 10: 180 , 11: 270 0041h[12:8] Result of detection of the number of color stripe groups per field 0041h[7:6] 0041h[5:0] Result of detection of the color stripe split position 00: No, 01: Latter half, 10: First half, 11: Indefinite Result of detection of the number of color stripe lines per field (Implement the spcnt/spgcnt based on the result of spcnt and spgcnt detection. Then determine if the 4- or 2-line mode is set.) Result of detection of sync reduction 00: V=H, 01: H>V, 11: V>H Detection data First data = 0043h[0] Number of data items the intermediate values of which are detected (from the 600 kHz LPF signal) (Number of bits out of the 14 data bits) Number of data items the intermediate values of which are detected (from the 6 MHz LPF signal) (Number of bits out of the 14 data bits) The number of line where the data is detected 00: Not detected, 01: 19(282)H, 10: 20(283)H, 11: 21(284)H Result of reference pulse detection 0: Not detected, 1: Detected Reliability of the detection result 0: Not good 1: OK (The imvwdet bit is set to 1 and all data fixed with CRC added.)
agcflg
0042h[9:8]
2. VBID imdatavw immidvw1
0043h[13:0] 0044h[13:9]
immidvw2
0044h[8:4]
imvwlno imvwdet imvwok
0044h[3:2] 0044h[0] 0044h[1]
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3. WSS imdatavw immidvw1 immidvw2 imvwlno imvwdet imvwok
0043h[13:0] 0044h[13:9] 0044h[8:4] 0044h[3:2] 0044h[0] 0044h[1]
Detection data First data = 0043h[0] Number of data items the intermediate values of which are detected (from the 1 MHz LPF signal) Number of data items the intermediate values of which are detected (from the 6 MHz LPF signal) The number of line where the data is detected 00: Not detected, 01: 19(282)H, 10: 20(283)H, 11: 21(284)H Result of Clock Run-In detection 0: Not detected, 1: Detected Reliability of the detection result 0: Not good 1: OK (The imvwdet bit is set to 1 and start code and bi-phase acceptable) Detection data First data = 0045h[0] Number of data items the intermediate values of which are detected (from the 600 kHz LPF signal) Number of data items the intermediate values of which are detected (from the 6 MHz LPF signal) The number of line where the data is detected 00: Not detected, 01: 20(283)H, 10: 21(284)H, 11: 22(285)H Result of Clock Run-In detection 0: Not detected, 1: Detected Reliability of the detection result 0: Not good 1: OK (The imccdet bit is set to 0 and all data fixed)
4. Closed caption imdatacc 0045h[15:0]
immidcc1 immidcc2 imcclno imccdet imccok
0046h[12:9] 0046h[7:4] 0046h[3:2] 0046h[0] 0046h[1]
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MN673794
5. Others
Register name
bg32cnt ckreg imjack NSTD
Address 0040h[7:4] 0040h[3:0] 0042h[7:0] 0046h[15]
odev ghsfew lownoise
0048h[5] 0048h[4] 0048h[3:0]
Description Color killer use 1/4 of the number of lines with no burst gate generated during a period of 128H. Color killer use The total number (absolute value) of APC errors resulted during a period of 128H. Result of detection of weak electromagnetic field sync noise (The number of pulses in the sliced and binary-coded Csync in a single field) Standard signal discrimination (Discriminated as a standard signal if the number of clocks per 1H period is within a range of 9107.) 0: Standard 1: Nonstandard Field discrimination 0: Second field (even), 1: First field (odd) Signal detection result 0: Detected, 1: Not detected Result of weak electromagnetic field detection The integrated noise value (0 to 15) in a period of 6H V-blanking. Discrimination of frame skipping in the frame sync block 0: No skip, 1: Skipped Discrimination of frame hold in the frame sync block 0: No hold, 1: Hold
Default
frmchg_skip 004Ah[1] frmchg_hold 004Ah[0]
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MN673794
f Register map Tables 3.4-1 and 3.4-2 show the register maps.
Table 3.4-1 Write Register Map 0008h 0009h 0017h 0029h 002Eh 0039h 003Ch 003Dh 003Eh D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default 8000 sigmod [2:0] cpsh fsinsel [1:0] r656 outsel F2D SEL [2:0] 8124 tbccdly [1:0] Setnrin SetTof [1:0] Set3dnr ydnslp cdnslp [2:0] [2:0] -
cdly2 HYOZI [1:0] F3D SEL [2:0] cdly1 0000
wr_ offset [4:0]
yad pdwn yupslp cupslp [3:0] [3:0] cad pdwn Set yda Mdet pdwn [6:0] cda pdwn clkda pdwn agcda pdwn yudchg cudchg accda SetMvVi [5:0] [5:0] pdwn clpda Video pdwn OutSel pll cflgdly [1:0] pdwn 0000 0000 0000 0108 0A10 0BA0
0000
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MN673794
Table 3.4-2 Read Register Map 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0048h 004Ah D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default
-
immvh spiso [1:0]
-
-
-
NSTD -
-
-
spgcnt [4:0]
agcflg [1:0]
immid vw1 [4:0]
immid cc1 [3:0]
-
bg32 cnt [4:0]
sppos [1:0]
imdata immid vw [13:0] vw2 [4:0] imjack [7:0]
imdata cc [15:0]
-
-
immid cc2 [3:0]
odev ghsfew
ckreg [3:0]
spcnt [5:0]
imvw lno [1:0] imvwok
imvwdet
low noise frmchg imccok [3:0] _skip frmchg imccdet _hold

imcc lno [1:0]
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MN673794 Product standards
A. Absolute Maximum Ratings
(VSS= 0 V) Parameter A1 A2 A3 A4 A5 A6 A7 A8 A9 External supply voltage Internal supply voltage Input pin voltage Output pin voltage
Output current (TYPE-HL2) Output current (TYPE-HL4) Output current (TYPE-HL8)
Symbol VDD VDDI VI VO IO IO IO PD TOPR TSTG
Rating -0.3 to 4.6 -0.3 to 3.6
Unit
V -0.3 to VDD+0.3 (Upper limit: 4.6) -0.3 to VDD+0.3 (Upper limit: 4.6) 6 12 24 1920 -20 to +80 -40 to 125 mW mA
Power dissipation
Operating ambient temperature
A10 Storage temperature
TYPE-HL2 pins CASHD, CASVD, CLK188, CLK450, ANACLK, GCP, CSYNCO, MICONRWW, MICONRWR, APCE, TDO TYPE-HL4 pins CLK27O, CLK18O2, CLK18O1, R656OUT7 to R656OUT0, FRP, HD, VD, TESTIO9 to TESTIO0,DSF7 to DSF0, MAD6 to MAD0, MCSALE, MNR, MNWENBW, MICOMSEL, NC3 TYPE-HL8 pins MDA15 to MDA0 Note) (1) The external supply pins are VDD3, VDD2, and AVDD pins and the internal supply pins are VDDI and VDDDRAM pins. (2) The absolute maximum ratings are the limit values beyond which the IC may be broken. They do not assure operations. (3) Connect all VDD pins externally and directly to the power supply. Connect all VSS pins externally and directly to ground. (4) Connect one or more bypass capacitors of 0.1 F or larger between the power supply pin and ground. (5) Connect MINTEST pin to VSS pin.
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B. Recommended Operating Conditions
(VSS= 0 V) Limits Parameter Symbol Conditions Min B1 B2 B3 B4 B5 B6 B7 B8 B9
Supply voltage (External 1) Supply voltage (External 2) Supply voltage (Internal) Supply voltage (Internal DRAM) Supply voltage (Analog)
Unit Typ 3.3 2.2 1.8 2.5 3.3 Max 3.6 2.4 1.95 2.7 3.6 80 27 27 4.5 V V V V V MHz MHz MHz
VDD VDD2 VDDI VDDDRAM AVDD Ta fOSC fIN1 fIN2 CLK27XI pin CLK27I CLK45I
3.0 2.0 1.65 2.3 3.0 -20
Ambient temperature Oscillator frequency Clock 1 input frequency Clock 2 input frequency
C. Pin Capacitance
C1 C2 C3
Input pin Output pin I/O pin
CIN COUT CIO
VDD=VI=0 V fin=1 MHz Ta=25
7 7 7
8 8 8
pF pF pF
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D. Electrical Characteristics
(1) DC Characteristics VSS=AVSS=VSSDRAM=0 V, Ta=-20 to 80 Limits Parameter Symbol Conditions Min D1 Operating supply current IDDI
VDD3=AVDD=3.6 V VDD2=2.4 V VDDI=1.95 V VDDDRAM=2.7 V VI=VDD or VSS fIN1=27 MHz fIN2=4.5 MHz fOSC1=27 MHz Output: Open
Unit Typ Max
300
mA
D2
Operating supply current
IDDDRAM
VDD3=AVDD=3.6 V VDD2=2.4 V VDDI=1.95 V VDDDRAM=2.7 V VI=VDD or VSS fIN1=27 MHz fIN2=4.5 MHz fOSC1=27 MHz Output: Open
80
mA
D3
Operating supply current
IDDANA
VDD3=AVDD=3.6 V VDD2=2.4 V VDDI=1.95 V VDDDRAM=2.7 V VI=VDD or VSS fIN1=27 MHz fIN2=4.5 MHz fOSC1=27 MHz Output: Open
302
mA
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MN673794
Limits Parameter Symbol Conditions Min Typ Max Unit
D4 D5 D6 High-level input voltage Low-level input voltage Input leakage current
CLK27I VIH3 VIL3 ILIPD3 VI=VDD3 or VSS
VDD3 x0.7
VDD3
VDD3 x0.3
V V A
0
5
D7 D8 D9 High-level input voltage Low-level input voltage Input leakage current VIH4 VIL4 ILIPD4 RPU4 VI=VDD3 VDD3=0.0 V
RST, TDI, TRST, TMS
VDD3 x0.7
VDD3
VDD3 x0.3
V V A k
0
10 33 100 300
D10 Pull-up resistor
TCK, TEST5 to TEST0, PDRAM1, PDRAM0, NTDRAM, R656IN7 to R656IN0, INF D11 High-level input voltage D12 Low-level input voltage D13 Input leakage current D14 Pull-up resistor VIH5 VIL5 ILIPD5 RPD5 VI=VSS VDD3=3.3 V 33 100
VDD3 x0.7
VDD3
VDD3 x0.3
V V A k
0
10 300
D15 High-level input voltage D16 Low-level input voltage D17 Input leakage current D18 Pull-up resistor VIH6 VIL6 ILIPD6 RPD6 VI=VSS VDD3=3.3 V
MINTEST
VDD3 x0.7
VDD3
VDD3 x0.3
V V A k
0
10 10 30 90
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Limits Parameter Symbol Conditions Min Typ Max Unit
D19 High-level input voltage D20 Low-level input voltage D21 Input leakage current
MINTC1, MINTIN1 VIH7 VIL7 ILIPD7 VI=VDD3 or VSS
VDD3 x0.7
VDD3
VDD3 x0.3
V V A
0
5
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MN673794
Limits Parameter Symbol Conditions Min Typ Max Unit
ANACLK, GCP, CSYNCO, MICONRWW, MICONRWR D22 High-level output voltage D23 Low-level output voltage VOH9 VOL9
IOH=-2 mA,VI=VDD3 or VSS
VDD3 -0.6
V 0.4 V
IOL=2 mA,VI=VDD3 or VSS
D24 High-level output voltage D25 Low-level output voltage
CLK27O, CLK18O2, R656OUT7 to R656OUT0, FRP VOH10 VOL10
IOH=-4 mA,VI=VDD3 or VSS
VDD3 -0.6
V 0.4 V
IOL=4 mA,VI=VDD3 or VSS
D26 High-level output voltage D27 Low-level output voltage D28 Output leakage current
APCE, TDO VOH11 VOL11 IOZ11
IOH=-2 mA,VI=VDD3 or VSS
VDD3 -0.6
V 0.4 5 V A
IOL=2 mA,VI=VDD3 or VSS
VO=Hi-z state VI=VDD3 or VSS VO=VDD3 or VSS
CASHD, CASVD, CLK188, CLK450 D29 High-level output voltage D30 Low-level output voltage VOH12 VOL12
IOH=-0.5 mA,VI=VDD2 or VSS
VDD2 -0.4
V 0.4 V
IOL=0.5 mA,VI=VDD2 or VSS
D31 High-level output voltage D32 Low-level output voltage
CLK18O1 VOH13 VOL13
IOH=-1.0 mA,VI=VDD2 or VSS
VDD2 -0.4
V 0.4 V
IOL=1.0 mA,VI=VDD2 or VSS
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Limits Parameter Symbol Conditions Min Typ Max Unit
D33 High-level input voltage D34 Low-level input voltage D35 High-level output voltage D36 Low-level output voltage D37 Output leakage current VIH14 VIL14 VOH14 VOL14 IOZ14
IOH=-8 mA,VI=VDD3 or VSS
MDA15 to MDA0
VDD3 x0.7
VDD3
VDD3 x0.3
V V V
0
VDD3 -0.6
IOL=8 mA,VI=VDD3 or VSS
0.4 5
V
VO=Hi-z state VI=VDD3 or VSS VO=VDD3 or VSS
D38 High-level input voltage D39 Low-level input voltage D40 Input pull-up resistor D41 High-level output voltage D42 Low-level output voltage D43 Output leakage current VIH15 VIL115 RPU15 VOH15 VOL15 IOZ15 VI=0.0 V
IOH=-4 mA,VI=VDD3 or VSS
HD, VD
VDD3 x0.7
VDD3
VDD3 x0.3
V V k V
0 33
VDD3 -0.6
100
300
IOL=4 mA,VI=VDD3 or VSS
0.4 10
V A
VO=pull-up state VI=VDD3 or VSS VO=VDD3
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Limits Parameter Symbol Conditions Min Typ Max Unit
TESTIO9 to TESTIO0 D44 High-level input voltage D45 Low-level input voltage D46 Input pull-down resistor D47 High-level output voltage D48 Low-level output voltage D49 Output leakage current VIH16 VIL116 RPD16 VOH16 VOL16 IOZ16 VI=VDD3
IOH=-4 mA,VI=VDD3 or VSS
VDD3 x0.7
VDD3
VDD3 x0.3
V V k V
0 33
VDD3 -0.6
100
300
IOL=4 mA,VI=VDD3 or VSS
0.4 10
V A
VO=pull-down state VI=VDD3 or VSS VO=VSS
MAD6 to MAD0, MCSALE, MNRE, MNWENBW, MICOMSEL, NC3 D50 High-level output voltage D51 Low-level output voltage D52 Output leakage current VOH17 VOL17 IOZ17
IOH=-4 mA,VI=VDD3 or VSS
VDD3 -0.6
V 0.4 5 V A
IOL=4 mA,VI=VDD3 or VSS
VO=Hi-z state VI=VDD3 or VSS VO=VDD3 or VSS
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MN673794
Limits Parameter Symbol Conditions Min Typ Max Unit
DSF7 to DSF0 D53 High-level input voltage D54 Low-level input voltage D55 Input pull-down resistor D56 High-level output voltage D57 Low-level output voltage D58 Output leakage current VIH18 VIL118 RPD18 VOH18 VOL18 IOZ18 VI=VDD3
IOH=-1.0 mA,VI=VDD2 or VSS
VDD2
x0.7
VDD2 VDD2
x0.3
V V k V
0 33 VDD2
-0.4
100
300
IOL=1.0 mA,VI=VDD2 or VSS
0.4 10
V A
VO=pull-down state VI=VDD3 or VSS VO=VDD3
CLK27XO D59 Internal feedback resistor Rf7 VI=VDD3 or VSS VDD3=3.3 V 0.33 1.00 3.00 M
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(2) AC Characteristics (Under the recommended operating conditions) Limits Parameter Symbol Conditions Min Typ Max Unit
D60 Input setup time D61 Input hold time
R656IN7 to R656IN0
tS1
Fig. 3-1
10.0 5.0
ns ns
tH1
D62 Output delay time
R656OUT to R656OUT0
tD2
Fig. 3-1
5.0
27.0
ns
D63 Input setup time D64 Input hold time
DSF7 to DSF0
tS3
Fig. 3-2
10.0 5.0
ns ns
tH3
D65 Output delay time
CASHD, CASVD
tD4
Fig. 3-2
5.0
45.0
ns
D66 Output delay time
FRP
tD5
Fig. 3-2
5.0
45.0
ns
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E. Analog Characteristics
(AVDD = 3.3 V, AVSS = 0 V, Ta = 25) Limits Parameter <10-bit A/D converter> E1 E2 E3
Low-level reference voltage High-level reference voltage
Symbol VIDEO, CIN VREFL1 VREFH1 NLE1
Conditions Min Typ Max
Unit
AVSS
0.5 2.5 AVDD 8.0
V V LSB
Integral nonlinearity
fADCK1=27.0 MHz VREFH=2.5 V VREFL=0.5 V
6.0
E4
Differential nonlinearity
DNLE1
fADCK1=27.0 MHz VREFH=2.5 V VREFL=0.5 V
2.0
4.0
LSB
E5
Clock frequency
fADCK1
27
MHz
<10-bit high-speed D/A converter> E6
Zero-scale output voltage
VZS2
VREF=1.235 V
0
V[p-p]
D9 to D0ALL "L" E7
Full-scale output voltage
VFS2
VREF=1.235 V
1.0
V[p-p]
D9 to D0ALL "H" E8 Integral nonlinearity NLE2 fADCK2=27 MHz VREF=1.235 V 1.5 3.0 LSB
E9
Differential nonlinearity
DNLE2
fADCK2=27 MHz VREF=1.235 V
1.0
3.0
LSB
E10
Clock frequency
fADCK2
27
MHz
SDF00032AEM
36
MN673794
(AVDD = 3.3 V, AVSS = 0 V, Ta = 25) Limits Parameter Symbol Conditions Min <10-bit voltage dividing type D/A converter> E11
Zero-scale output voltage
Unit Typ Max
VZS3
D9 to D0ALL "L"
-0.1
0
0.1
V
E12
Full-scale output voltage
VFS3
D9 to D0ALL "H"
3.1
3.2
3.3
V
E13
Integral nonlinearity
NLE3
fADCK3=1 MHz
1.0
3.0
LSB
E14
Differential nonlinearity
DNLE3
fADCK3=1 MHz
1.0
2.0
LSB
E15
Clock frequency
fADCK3
1
MHz
SDF00032AEM
37
MN673794
CLK27I
R656IN7 to R656IN0 tH1 tS1
CLK27O
R656OUT7 to R656OUT0 tD2
Fig. 3-1
I/O signal timing
SDF00032AEM
38
MN673794
CLK18O1
DSF7 to DSF0 (Input) tH3 tS3
CASHD, CASVD tD4
CLK18O2
FRP
tD5
Fig. 3-2
I/O signal timing
SDF00032AEM
39
MN673794
Package Dimensions (Unit: mm) LQFP208-P-2828 (Lead-free package)
30.000.20 28.000.10 156 157 105
104
(1.25) 53 1 52 1.70 max. 0.08 M 1.400.10 0.50 0.200.05 (1.00)
0.150.05
208
(1.25)
28.000.10
30.000.20
Seating plane
0.10
SDF00032AEM
0.100.10
0 to 8 0.500.20
40
Request for your special attention and precautions in using the technical information and semiconductors described in this book
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this book is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license. (3) We are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this book. (4) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (5) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd.
2002 MAY

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