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Features
* Up to 128-voice Top-quality Wavetable Synthesis Chip
- Two 64-voice RISC DSP Cores - Two High-speed CISC Control Processor - Versatile Programmable Digital Audio Routing Between the Two DSPs Voices Can Be Allocated for Synthesis and/or Effects and/or Audio Processing Maximum Single-shot PCM Wavesize of 4M Samples (93 Seconds @ 44.1 kHz) Samples Can Be Stored in 16-bit Floating Point Format (20-bit Dynamic), 16-bit Linear, 8-bit Linear Standard Audio Processing Firmware Includes Equalizer, Surround, MPEG Audio Decoder (Level 2) Sophisticated Built-in Cache Memories - Allows Use of Standard 100 ns 16-bit ROMs/RAMs - Guarantees Crisp Response Even Under Heavy Traffic Conditions GS(R) Sound Set(1) under License from Roland(R) Corporation, Other Sound Sets Available 16-channel Audio-in, 16-channel Audio-out @ 22 Bits Audio/Channel 28-bit Internal Audio Path Two Serial MIDI-In, Two Serial MIDI-Out Firmware/Wavetable Data Can Reside in ROM, DRAM, SDRAM Up to 256M Bytes of External Memory with Support of SIMM (DRAM) and DIMM (SDRAM) High-speed 16-bit Burst Transfer for Firmware Download or Streaming Audio Compatible with SAM9707, Uses Proven Design and Development Tools - Sound Editor, Sound Bank Editor - Algorithm Compiler, Assembler, Source Debugger - Direct Development from PC Environment, No Special Emulator Required Top Technology - Single Low-frequency Crystal and Built-in PLL - 3.3V Supply, 5V-tolerant I/Os - Space-saving 144-lead TQFP Package - Power-down Mode Typical Applications: Karaokes, High-range Multimedia, Classical Organs, Digital Pianos, Professional Keyboards, Musical Samplers 1. The GS Sound Set is subject to special licensing conditions. Not to be used for musical instruments.
* * * * * * * * * * * * *
128-voice Integrated Sound Synthesizer SAM9708
*
*
Note:
Description
The SAM9708 is a 128-voice integrated synthesizer, integrating two PDSP blocks and a memory management unit (MMU). One PDSP block is a combination of a specialized 64-slot RISC-based digital signal processor (DSP), a general-purpose 16-bit CISC-based control processor (P16), a cache memory and an "intelligent" peripheral I/O interface. Both PDSPs are fully independent and share the same external memory through the MMU.
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Block Diagrams
Figure 1. SAM9708 Block Diagram
16-bit Bus
PDSP 1
MIDI and Audio
MMU
Memory
PDSP 2
Figure 2. PDSP Block Diagram
I/O Functions 16-bit Bus MIDI
Control/Status MIDI UART Timers Host I/F
P16 Processor
16-bit CISC Processor Core Includes 256 x 16 Data RAM 256 x 16 Boot ROM
MMU
Synthesis/DSP
RISC DSP Core Includes 512 x 38 Alg RAM 128 x 28 MA1 RAM 256 x 32 MA2 RAM 256 x 32 MB RAM 128 x 16 MX RAM 256 x 16 MY RAM 64 x 13 ML RAM
Audio
Cache Memory 128 x 16
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Pin Description by Function
Table 1. Power Group
Name GND VC3 VCC1 VCC2 Pin Count 19 8 5 5 Type PWR PWR PWR PWR Function Power Ground. All GND pins should be returned to digital ground. Core Power, +3.3V nominal (3V to 4.5V). All VC3 pins should be returned to +3.3V. Pad (except Memory Pad) Power, +3.0V to +5.5V. All VCC pins should be returned to +5V (or 3.3V in case of single 3.3V supply). Memory Pad Power, +3.0V to +5.5V. All VCC pins should be returned to +5V (for RAM or DRAM) or 3.3V (for SDRAM or 3.3V ROM).
Table 2. ISA Bus Group(1)
Name PC_D[15:0](2, 3) Pin Count 16 Type I/O Function 16-bit data bus to host processor. Information on these pins is: - 2 x parallel MIDI (MPU-401 type applications) - 2 x high-speed burst data transfers to/from external memory Selects one of 8 internal registers: 0, 1: MPU-401 register processor #1 2, 3: Burst data (16-bit) processor #1 4 - 5: MPU-401 register processor #2 6 - 7: Burst data (16-bit) processor #2 Chip select from host, active low. Write from host, active low. Read from host, active low. Open drain output buffer. Driven low during 16-bit burst mode transfers to synchronize host to the SAM9708 memory. Open drain output buffer; driven low during 16-bit burst mode transfers. Indicates to host that a 16-bit I/O is in progress. Tri-state output pin, active high. Can be connected directly to host IRQ line.
PC_A[2:0]
3
IN
PC_CS PC_WR PC_RD PC_READY PC_IO16 PC_IRQ Notes:
1 1 1 1 1 1
IN IN IN TSout TSout TSout
1. ISA bus group pins are powered by VCC1 power rail. 2. PC_D pads have 4 mA drive capabilities; other output pads have 16 mA drive capabilities. 3. To interface with PC ISA bus, VCC1 should be connected to 5V power and PC_D bus should be buffered. Direction is given by PC_RD signal.
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Table 3. MIDI and Audio Group(1)
Name MIDI1_IN MIDI2_IN MIDI1_OUT MIDI2_OUT OVCK_OUT BCK_OUT WS_OUT SD_OUT[7:0] SD_IN[7:0] Pin Count 1 1 1 1 1 1 1 8 8 Type IN I/O OUT OUT OUT OUT OUT OUT I/O Function Main MIDI input. Routed to PDSP#1, can also be routed to PDSP#2. Auxiliary MIDI input. Routed to PDSP#2(2) Main MIDI output. Outputs from PDSP#1. Auxiliary MIDI output. Outputs from PDSP#2(2) Buffered X2 output. Typically used to drive external sigma/delta DAC/ADC at fS x 256. Audio data bit clock. Provides timing to SD_OUT. Audio data word select. WS_OUT timing can be selected to be I2S- or Japanese-compatible. 8 stereo serial audio data output (16 audio channels). Each output holds 64 bits (2 x 32) of serial data per frame. Audio data has 22-bit precision(2). 8 stereo serial audio data input (16 audio channels). Each input holds 64 bits (2 x 32) of serial data per frame. Audio data in is received with 20-bit precision(2).
Notes:
1. MIDI and Audio group pins are powered by VCC1 power rail. 2. These pins have alternate functions as GPIO pins (general-purpose input/output pins). See "General-purpose Input/Output Routing" on page 23 for more details.
Table 4. Memory Group(1)
Name CK_OUT WA[26:0] Pin Count 1 27 Type OUT OUT Function Master clock for SDRAM operation. Frequency is 4 times the X1 frequency (typ 45.1584 MHz). External memory address (ROM/SRAM/DRAM/SDRAM), up to 128M words (256M bytes). DRAM/SDRAM addresses are time-multiplexed on these pins as follows: WA0 - WA8: DRA0 - DRA8 WA18: DRA9 WA20: DRA10 WA22: DRA11 SRAM byte select. Should be connected to the lower RAM address when 8-bit wide SRAM is used. The type of RAM (16-bit/8-bit) can be selected by program. PCM ROM/SRAM/DRAM/SDRAM data PCM ROM chip select, active low SRAM chip select, active low SRAM/DRAM/SDRAM write enable, active low. Timing compatible with SIMM DRAM early write feature. PCM ROM/SRAM output enable, active low
RBS
1
OUT
WD[15:0] WCS0 WCS1 WWE WOE
16 1 1 1 1
I/O OUT OUT OUT OUT
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Table 4. Memory Group(1) (Continued)
Name RAS Pin Count 1 Type I/O Function DRAM/SDRAM row address strobe. At the end of reset RAS is tested to determine memory type configuration (pulled high to select SDRAM type). RAS should be pulled to VCC or GND through an external 10K resistor. DRAM/SDRAM column address strobe. At the end of reset CAS is tested to determine memory type configuration (pulled high to select DRAM type). CAS should be pulled to VCC or GND through an external 10K resistor. Indicates that a DRAM/SDRAM memory refresh cycle is in progress. To be used with multiple SIMM/DIMM modules to force refresh simultaneously on all modules. At the end of reset REFRESH is tested to select bootstrap state (pulled high to start built-in CPU bootstrap in case of ROMless applications).
CAS
1
I/O
REFRESH
1
I/O
Note:
1. Memory group pins are powered by VCC2 power rail.
Table 5. Miscellaneous Group
Name LFT TEST LDTEST PDWN RESET X1, X2 Pin Count 1 1 1 1 1 2 Type ANA IN IN IN IN - Function PLL low pass filter. Should be connected to an external RC network. Test pin. Should be returned to GND. Test pin. Should be returned to GND. Power down, active low Master reset input, active low. Schmidt trigger input. Crystal connection. Crystal frequency should be fS x 256 (typ 11.2896 MHz). Crystal frequency is internally multiplied by 4 to provide the IC master clock. X1 can also be used as external clock input (3.3V input). X2 CANNOT BE USED TO DRIVE EXTERNAL CIRCUITRY
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Pinout by Pin Number
Table 6. Pinout by Pin Number
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name PC_D[10] PC_D[9] PC_D[8] PC_IO16 VCC1 GND PC_READY VC3 GND PC_RD PC_WR PC_A[0] PC_A[1] PC_IRQ PC_A[2] PC_CS VC3 GND PC_D[0] VCC1 GND PC_D[1] PC_D[2] PC_D[3] PC_D[4] PC_D[5] PC_D[6] PC_D[7] MIDI1_IN MIDI2_IN MIDI1_OUT MIDI2_OUT SD_IN[0] SD_IN[1] VCC1 GND Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Name SD_IN[2] SD_IN[3] SD_OUT[0] SD_OUT[1] VC3 GND SD_OUT[2] SD_OUT[3] WS_OUT BCK_OUT OVCK_OUT SD_IN[4] SD_IN[5] SD_IN[6] GND VCC1 SD_IN[7] SD_OUT[4] SD_OUT[5] SD_OUT[6] SD_OUT[7] VC3 GND LFT X1 X2 VC3 GND WD[15] WD[14] WD[13] WD[12] VCC2 GND WD[11] WD[10] Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Name WD[9] WD[8] WD[7] WD[6] WD[5] WD[4] WD[3] VC3 VCC2 GND GND WD[2] WD[1] WD[0] WWE WOE WCS0 WCS1 CK_OUT RBS WA[0] WA[1] WA[2] WA[3] VCC2 GND VC3 GND WA[4] WA[5] RAS CAS REFRESH WA[6] WA[7] WA[8] Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name VCC2 GND WA[9] VC3 GND WA[10] WA[11] WA[12] WA[13] WA[14] WA[15] WA[16] WA[17] WA[18] WA[19] VCC2 GND WA[20] WA[21] WA[22] WA[23] WA[24] WA[25] WA[26] GND RESET TEST LDTEST PDWN PC_D[15] PC_D[14] PC_D[13] PC_D[12] VCC1 GND PC_D[11]
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Absolute Maximum Ratings
Table 7. Absolute Maximum Ratings (All voltages with respect to 0V, GND = 0V)
Symbol Parameter Ambient temperature (Power applied) Storage temperature Voltage on any pin (except X1) Voltage on X1 pin VCC VC3 Supply voltage Supply voltage Maximum IOL per I/O pin (except IRQ, I/O ready) Maximum IOL, IRQ, I/O ready Min -40 -65 -0.5 -0.5 -0.5 -0.5 Typ Max +85 +150 VCC + 0.5 VC3 + 0.5 6.5 4.5 4.4 16.16 Unit C C V V V V mA mA
Recommended Operating Conditions
Table 8. Recommended Operating Conditions
Symbol VCC VC3 tA Note: Parameter Supply voltage(1) Supply voltage Operating ambient temperature Min 3 3 0 Typ 3.3/5.0 3.3 Max 5.5 4.5 70 Unit V V C
1. When using 3.3V supply, care must be taken that voltage applied on pin does not exceed VCC + 0.5V.
DC Characteristics
Table 9. DC Characteristics (tA = 25C, VC3 = 3.3V 10%)
Symbol VIL VIH VOL Parameter Low-level input voltage High-level input voltage Low-level output voltage D[15:0], IRQ, I/O ready: IOL = -24 mA Others except LFT: IOL = -3.2 mA High-level output voltage D[15:0], IRQ, I/O ready: IOH = 10 mA Others except LFT: IOH = 0.8 mA Power supply current (crystal frequency = 12 MHz) Power down supply current VCC 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Min -0.5 -0.5 2.3 3.3 0 3 Typ Max 1.0 1.7 3.8 5.5 0.45 0.45 Unit V V V
VOL
2.8 4.5 100 25 TBD 140 35 TBD
V
ICC
mA A
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DSP RISC Signal Processor
Each of the two DSP engines operates on a frame-timing basis with the frame subdivided into 64 process slots. Each process is itself divided into 16 micro-instructions known as "algorithms". Up to 32 different DSP algorithms can be stored on-chip in each DSP private Alg RAM memory, allowing the device to be programmed for a number of audio signal generation/processing applications. Each DSP engine is capable of generating 64 simultaneous voices using algorithms such as wavetable synthesis with interpolation, alternate loop and 24 dB resonant filtering for each voice, for a total polyphony of 128 voices. Slots may be linked together (ML RAM) to allow implementation of more complex synthesis algorithms. Each DSP also includes a 20 x 16 pipelined two's complement multiplier, a 28-bit pipelined adder and eight 24-bit final accumulators. A typical application uses around 75% of the capacity of the DSP engines for synthesis, thus providing a minimum of 96-voice wavetable polyphony. The remaining processing power is used for typical function like reverberation, chorus, direct sound, surround effect, equalizer, etc. Frequently-accessed DSP parameter data are stored in 5 banks of on-chip RAM memory for each DSP. Sample data or delay lines, which are accessed relatively infrequently, are stored in external ROM, SRAM, DRAM or SDRAM memory. The combination of localized micro-program memory and localized parameter data allows micro-instructions to execute in 20 ns (50 MIPS) on each DSP. Separate buses from each of the on-chip parameter RAM memory banks allow highly parallel data movement to increase the effectiveness of each micro-instruction. With this architecture, a single micro-instruction can accomplish up to 6 simultaneous operations (add, multiply, load, store, etc.), providing a total potential throughput of 600 million operations per second (MOPS).
P16 Control Processor and I/O Functions
Each of the two P16 control processors is a general-purpose 16-bit CISC processor core, that runs from external memory. A boot/macro ROM is included on-chip to accelerate commonly executed routines and to allow the use of RAM only devices for the external memory. Each P16 also includes 256 words of local RAM data memory. Each P16 control processor writes to the parameter RAM blocks within its associated DSP in order to control the synthesis process. In a typical application, the P16 control processor parses and interprets incoming commands from the MIDI UART or from the parallel 16-bit interface and then controls the DSP by writing into the parameter RAM banks of its associated DSP core. Slowly-changing synthesis functions, such as LFOs, are implemented in the P16 control processor by periodically updating the DSP parameter RAM variables. Each P16 control processor interfaces with other private peripheral devices, such as the system control and status registers, the on-chip MIDI UART, the on-chip timers and the ISA PC 16-bit interface through specialized "intelligent" peripheral I/O logic. This I/O logic automates many of the system I/O transfers to minimize the amount of overhead processing required from the P16. The parallel interface is implemented using three address lines (A2, A1, A0), a chip select signal, read and write strobes from the host and a 16-bit data bus (PC_D0 - PC_D15). This data bus cannot drive the PC bus directly. External buffers and an external decoder (PAL) or plug and play IC are required to map the 16-bit I/O addresses and AEN from the PC into the three address lines and chip select from the SAM9708. The PDSP#1 responds on addresses 0 to 3 (A2A1A0 = 0XX), while PDSP#2 responds on addresses 4 to 7 (A2A1A0 = 1XX). Each PDSP parallel interface supports a byte-wide I/O interface and a 16-bit port dedicated to burst transfers.
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The byte-wide I/O interface is normally used to implement a MPU-401 UART-mode compatible interface. It is specified by address A1A0 = 0X, address 00 being the data register, address 01 being the status/control registers. Besides the standard two status bits of the MPU-401, two additional bits are provided to expand the MPU-401 protocol. Address A1A0 = 010 specifies a 16-bit I/O port. It is mainly used for burst audio transfers to/from the PC using very efficient PC instructions like REP OUTSW or REP INSW which operate at maximum ISA bus bandwidth. This port may also be used for fast program or sound bank uploads.
DSP Cache RAM
The memory management unit (MMU) allows external ROM and/or RAM memory resources to be shared between the two DSPs and the two P16 control processors. This allows a single device (i.e., DRAM) to serve as sample memory storage/delay lines for the DSPs and as program storage/data memory for the P16 control processors. The DSP cache RAM allows a dramatic reduction in the traffic with the external ROM/RAM, allowing use of standard 120 ns ROM parts with sampling frequencies up to 48 kHz. Average access request rate to external memory is only one for every two frames for each slot, which gives 64 accesses per synthesis frame. The MMU can provide up to 169 memory accesses per frame, which leaves over 100 accesses free per frame to be used by the P16 processors. This means that under full 128-voice polyphony traffic conditions, each P16 instruction average execution time is around 400 ns at 48 kHz sampling frequency. 128-voice polyphony can be assured only when all samples are played at nominal frequency or down-transposed. Simultaneously playing a large number of up-transposed samples can adversely affect polyphony. For more details of possible polyphony for a given application, please refer to the application note "SAM9708 Memory Management Unit".
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Timing Diagrams
All timing conditions: VCC = 5V, VC3 = 3.3V, tA = 25C; signals I/O READY, I/O CS16, D0 - D15 with 220 ohms pull-up, 30 pF capacitance; signal IRQ with 470 ohms pull-down, 30 pF capacitance; all other outputs except X2 and LFT load capacitance = 30 pF. All timings refer to tCK, which is the internal master clock period. The internal master clock frequency is 4 times the frequency at pin X1. Therefore tCK = tXTAL/4. The sampling rate is given by 1/(tCK * 1024). The maximum crystal frequency/clock frequency at X1 is 12.288 MHz (48 kHz sampling rate). Figure 3. Host Interface Read Cycle
A0 - A2
tAVCS
PC Host Interface
CS
tCSLRDL tPRD tRDHCSB
RD
tRDLIORL tPIOR
I/O READY
tCSLIOCS tCSHIOCS tIORHDV tRDLDV tRDH
I/O CS16
D0 - D15
Note:
D8 - 15 valid only if A2A1 = 10 and SBHE = 0.
Figure 4. Host Interface Write Cycle
A0 - A2
tAVCS
CS
tCSLWRL tPWR tWRHCSB
WR
tWRLIORL tPIOR
I/O READY
tCSLIOCS tIORHWRH tCSHIOCS
I/O CS16
tDWS
tDWB
D0 - D15
Note:
D8 - 15 valid only if A2A1 = 10
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. Table 10. PC Host Interface Timing Parameters
Symbol tAVCS tCSLDRL tRDHCSH tPRD tRDLDV tDRH tRDLIORL tPIRO tIORHDV tCSLIOCS tCSHIOCS tCSLRWRL tWRHCSH tPWR tWRLIORL tIORHWRH tDWS tDWH Notes: Parameter Address valid to chip select low Chip select low to RD low RD high to CS high RD pulse width Data out valid from RD (1) Data out hold from RD I/O ready low from RD I/O ready pulse width
(2)
Min 0 5 5 50
Typ
Max
Unit ns ns ns ns
20 5 0 10 10 128
(2)
ns ns ns tck ns ns ns ns ns ns
(2)
I/O ready rising to data out valid I/O CS16 low from CS low (3) I/O CS16 high from CS high Chip select low to WR low WR high to CS high WR pulse width I/O ready low from WR low I/O ready high to WR high Write data setup time Write data hold time
(2) (3)
0 0 0 5 5 50 128 5 10 0 20 20
tck ns ns ns
(2)
1. When data is already loaded into internal SAM9708 output register. In this case I/O READY says high during the read cycle. 2. I/O READY goes into low only if the data is not ready to be loaded into/read from internal SAM9708 register. 128 tck corresponds to a single worst-case situation. At fCK = 12.288 MHz, I/O READY is likely to never go low when using standard ISA bus timing. 3. I/O CS16 is asserted low by SAM9708 if A2A1 = 10 to indicate fast 16-bit ISA bus transfer to the PC.
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External Memory Timing
External Memory Overview
The following memories can be connected to the SAM9708: * * * * ROM or Flash memories, 16 bits wide Static RAMs, 8 bits or 16 bits wide DRAMs, 16 bits wide SDRAMs, 16 bits wide
DRAMs and SDRAMs cannot be connected at the same time. The type of dynamic RAM connection is determined at power-up by sensing the level of pins RAS and CAS (see Table 4 on page 4 and "Memory Type Configuration and Boot Configuration" on page 25). Eight-bit wide static RAM can be connected using the additional Ram Byte Select (RBS) address signal. RBS allows access to two bytes of SRAM within one regular memory cycle, thereby providing 16 bits of data. Eight-bit wide SRAM can be connected only under control of WCS1. The selection 8 bits/16 bits is done by firmware. ROM and static RAMs use linear addressing (address lines WA0 to WA26). DRAM and SDRAMs use time-multiplexed addressing with a ROW/COL scheme (address lines DRA0 to DRA11). Additionally, SDRAMs use the DRA0/DRA11 lines for configuration and the DRA10 line for auto precharge. ROM/SRAMs and DRAM/SDRAM address line share the same pins of the SAM9708. The timing is determined by the input signal DRAM. If DRAM is high at the beginning of a memory cycle, this indicates DRAM/SDRAM access. If only one type of memory is connected (i.e., SDRAM), then the DRAM signal can be hardwired. Otherwise, it should be derived from an external decoding of high-order address lines.
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External Memory Timing Overview
One memory cycle consists of six internal master clock cycles (6 x tCK). The internal master clock period is one-fourth of the clock period at X1. The internal master clock is provided at pin CK_OUT when external SDRAM is connected (RAS sensed high during RESET). Basic notes on SDRAM timing: * * * * * RESET should be held low at least 100 s (SDRAM timing requirement on idle cycles) SDRAM mode is fixed to sequential, burst length = 1, CAS latency 2, standard operation, programmed write burst length. SDRAM cycles for read: NOP - ACTIVE - NOP - READ AUTO PRECHARGE - NOP - NOP. SDRAM cycles for write: NOP - ACTIVE - NOP - WRITE AUTO PRECHARGE - NOP NOP SDRAM cycles for refresh: NOP - AUTO REFRESH - NOP - NOP - NOP - NOP
Figure 5. ROM and SRAM Basic Timing, DRAM = Low
0 CLK 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1
WAxx
WOE WWE
RBS
WDxx
ROM/SRAM16 READ
SRAM16 WRITE
SRAM8 WRITE
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Figure 6. DRAM Basic Timing, DRAM = High
0 CLK 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1
DRAxx
RAS CAS
WWE
REFRESH
WDxx
DRAM READ
DRAM WRITE
DRAM REFRESH
Figure 7. SDRAM Basic Timing, DRAM = High
0 DRCLK 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1
DRAxx
row
col
RAS CAS
WWE
REFRESH
WDxx
SDRAM READ
SDRAM WRITE
SDRAM AUTO REFRESH
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Figure 8. SDRAM Init Sequence, DRAM = High
0 DRCLK 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1
DRAxx
row
col
RAS CAS
WWE
REFRESH
PRECHARGE A10 = 1
AUTO REFRESH (TWO CYCLES)
LOAD MODE REG DRA = 020H
Table 11. RAS/CAS Correspondence to Physical Address(1)
Signal WA0/DRA0 WA1/DRA1 WA2/DRA2 WA3/DRA3 WA4/DRA4 WA5/DRA5 WA6/DRA6 WA7/DRA7 WA8/DRA8 WA18/DRA9 WA20/DRA10 WA22/DRA11 Note: Valid for DRAM and SDRAM unless otherwise stated. Value at RAS Time WA0 WA1 WA2 WA3 WA4 WA5 WA6 WA7 WA8 WA18 WA20 WA22 Value at CAS Time WA9 WA10 WA11 WA12 WA13 WA14 WA15 WA16 WA17 WA19 (DRAM) Don't care (SDRAM) WA21 (DRAM) High (SDRAM) WA23 (DRAM) Don't care (SDRAM)
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Detailed External DRAM Timing
Figure 9. Read Cycle
tRC tRAS RAS tRCD CAS tASR DRA0 - DRA11 tRAH tASC tCAH tCAS tCRP tRP
WOE tCAC tRAC WD0 - WD15 tOFF
Figure 10. Write Cycle (Early Write)
tRC tRAS RAS tRCD CAS tASR DRA0 - DRA11 tWCS tWCH tRAH tASC tCAH tCAS tCRP tRP
WWE
tDS WD0 - WD15
tDH
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Figure 11. Refresh Cycle (RAS Only)
tRC tRAS RAS tASR DRA0 - DRA11
counter
tRP
tRAH
Table 12. External DRAM Timing Parameters
Symbol tRC tRAC tCAC tOFF tRP tRAS tCAS tRCD tCRP tASR tRAH tASC tCAH tWCS tWCH tDS tDH Parameter Read/Write/Refresh cycle Access time from RAS/ Access time from CAS/ CAS high to output Hi-Z RAS precharge time RAS pulse width CAS pulse width RAS to CAS delay time CAS to RAS precharge time Row address setup time Row address hold time Column address setup time Column address hold time Write command set-up time Write command hold time Write data set-up time Write data hold time Refresh counter average period (12-bit counter) 2 * tck - 5 tck - 5 tck - 5 tck - 5 3 * tck - 5 2 * tck 3 * tck 2 * tck 3 * tck 512 * tck 2 * tck 4 * tck - 5 3 * tck - 5 2 * tck Min Typ 6 * tck 5 * tck - 5 3 * tck - 5 2 * tck - 5 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
The following points should be noted: * The multiplexed CAS, RAS addressing can support memory DRAM chips up to 16 Mbits x N as long as the number of row address lines and column address lines are identical. For example, device type 416C1200 is supported because it is a 1M x 16 organization with 10-bit row and 10-bit column. Device type 416C1000 is not supported because it is a 1M x 16 organization with 12-bit row and 8-bit column. The signal WOE is normally not used for DRAM connection. It is represented only for reference purposes. As RAS only counter refresh method is employed, several banks of DRAMs can be connected using simple external CAS decoding. Linear address lines (WAx) can be used to select between DRAM banks. For example, a 1M x 32 SIMM module may be connected as two 1M x 16 banks, with CAS0 and CAS1 selections issued from CAS and WA20. During a whole DRAM cycle (from RAS low to CAS rising), WCS0 is asserted low.
* *
*
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*
The equivalence between multiplexed DRAM address lines (DRA0 to DRA11) and the corresponding linear addressing (WA0 to WA23) is as follows:
DRA11 RAS time CAS time WA22 WA23 DRA10 WA20 WA21 DRA9 WA18 WA19 DRA8 WA8 WA17 DRA7 WA7 WA16 DRA6 WA6 WA15 DRA5 WA5 WA14 DRA4 WA4 WA13 DRA3 WA3 WA12 DRA2 WA2 WA11 DRA1 WA1 WA10 DRA0 WA0 WA9
*
To save DRAM power consumption, CAS and RAS are cycled only when necessary. Therefore, depending on firmware loaded, total board power consumption may increase with synthesis processing traffic.
Detailed External ROM Timing
Figure 12. ROM Read Cycle
tRC WCS0 tSOE WA0 - WA26 tPOE WOE tOE tACE WD0 - WD15 tDF
Table 13. External ROM Timing Parameters
Symbol tRC tCSOE tPOE tACE tOE tDF Parameter Read cycle time Chip select low/address valid to WOE low Output enable pulse width Chip select/address access time Output enable access time Chip select or WOE high to input data High Z 6 * tck - 5 5 * tck - 5 0 tck - 5 2 * tck - 5 5 * tck Min Typ 6 * tck 2 * tck + 5 Max Unit ns ns ns ns ns ns
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External RAM Timing
Figure 13. 16-bit SRAM Read Cycle
tRC WCS1 tCSOE WA0 - WA26 tPOE WOE
WWE tACE WD0 - WD15
tOE
tDF
Figure 14. 16-bit SRAM Write Cycle
tWC WCS1 tCSWE WA0 - WA26
WOE tWP WWE tDW WD0 - WD15 tDH
Table 14. External 16-bit SRAM Timing Parameters
Symbol tRC tCSOE tPOE tACE tOE tDF tWC Parameter Read cycle time Chip select low/address valid to WOE low Output enable pulse width Chip select/address access time Output enable access time Chip select or WOE high to input data Hi-Z Write cycle time 6 * tck - 5 5 * tck - 5 0 6 * tck 2 * tck - 5 2 * tck - 5 5 * tck Min Typ 6 * tck 2 * tck + 5 Max Unit ns ns ns ns ns ns ns
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Table 14. External 16-bit SRAM Timing Parameters (Continued)
Symbol tCSWE tWP tDW tDH Parameter Write enable low from CS or Address or WOE Write pulse-width Data out setup time Data out hold time 5 * tck - 10 10 Min tck - 10 5 * tck Typ Max Unit ns ns ns ns
Figure 15. 8-bit SRAM Read Cycle
tRC WCS1 tCSOE WA0 - WA26 tPOE WOE
WWE tACE RBS
tORB
tOE WD0 - WD7
tACH
LOW
tDF
HIGH
Figure 16. 8-bit SRAM Write Cycle
tWC WCS1 tCSWE WA0 - WA26
WOE tWP WWE tAS RBS tDW1 tDH1 WD0 - WD7
LOW
tWP
tDW2
HIGH
tDH2
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Table 15. External 8-bit SRAM Timing Parameters
Symbol tRC tCSOE tPOE tACE tOE tORB tACH tDF tWC tCSWE tWP tDW1 tDH1 tAS tDW2 tDH2 Parameter Word (2 x bytes) read cycle time Chip select low/address valid to WOE low Output enable pulse width Chip select/address low byte access time Output enable low byte access time Output enable low to byte select high Byte select high byte access time Chip select or WOE high to input data High Z Word (2 x bytes) write cycle time 1st WWE low from CS or Address or WOE Write (low and high byte) pulse width Data out low byte setup time Data out low byte hold time RBS high to second write pulse Data out high byte setup time Data out high byte hold time tck - 10 2 * tck - 5 2 * tck - 10 10 tck - 5 2 * tck - 10 10 2 * tck - 5 0 6 * tck 2 * tck - 5 3 * tck - 5 2 * tck - 5 2 * tck 2 * tck - 5 5 * tck Min Typ 6 * tck 2 * tck + 5 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Digital Audio Timing
Figure 17. Digital Audio Timing Diagram
tCW WSBD tCW tCLBD
CLBD tSOD DABD0 - 7 DAAD0 - 7 tSOD
Table 16. Digital Audio Timing Parameters
Symbol tCW tSOD tCLBD Parameter CLBD rising to WSBD change DABDx/DAADx valid prior/after CLBD rising CLBD cycle time Min 8 * tck - 10 8 * tck - 10 16 * tck Typ Max Unit ns ns ns
Figure 18. Digital Audio Frame Format
WSBD (I2S) CLBD
DABD0-7 DAAD0-7 MSB LSB (16 bits) LSB (18 bits)
Note: DAAD is always 20 bits.
LSB (20 bits)
MSB
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Audio Routing
Each PDSP can process eight digital audio inputs and generate eight digital audio outputs for a total of 16 digital audio-in and 16 digital audio-out. The eight outputs from DSP#2 can be individually routed on DSP#1 inputs.
Figure 19. Audio Routing
SD_IN[7:4] PDSP#1 SD_OUT[3:0]
SD_IN[3:0]
PDSP#2
SD_OUT[7:4]
MIDI Routing
Th e de fa ult co nfigu ration assign s MIDI_IN 1/MID I_ OU T1 to PD SP#1 an d MIDI_IN2/MIDI_OUT2 to PDSP#2. Alternatively, MIDI_IN1 can be routed as the same MIDI input to both PDSPs. In this case, the MIDI_IN2 is available as a general-purpose input. Also, if the MIDI_OUT2 is not necessary, it can be defined as a general-purpose output.
Generalpurpose Input/Output Routing
MIDI_IN2, MIDI_OUT2, AUDIO_IN[7, 6, 5, 3, 2, 1, 0] and AUDIO_OUT[7:1] pins can be individually routed as general-purpose inputs or outputs as identified in Table 17.
Table 17. General-purpose Input/Output Routing
GPIO GPIO_OUT[0] DSP#1 GPIO_OUT[1] DSP#1 GPIO_OUT[2] DSP#1 GPIO_OUT[3] DSP#1 GPIO_OUT[4] DSP#1 GPIO_OUT[5] DSP#1 GPIO_OUT[6] DSP#1 GPIO_OUT[7] DSP#1 GPIO_OUT[0] DSP#2 GPIO_OUT[1] DSP#2 GPIO_OUT[2] DSP#2 GPIO_OUT[3] DSP#2 GPIO_OUT[4] DSP#2 GPIO_OUT[5] DSP#2 GPIO_OUT[6] DSP#2 GPIO_OUT[7] DSP#2 Pin MIDI2_OUT SD_OUT[1] SD_OUT[2] SD_OUT[3] SD_IN[0] SD_IN[1] SD_IN[2] SD_IN[3] SD_OUT[4] SD_OUT[5] SD_OUT[6] SD_OUT[7] MIDI2_IN SD_IN[5] SD_IN[6] SD_IN[7]
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Table 17. General-purpose Input/Output Routing (Continued)
GPIO GPIO_IN[0] DSP#1 GPIO_IN[1] DSP#1 GPIO_IN[2] DSP#1 GPIO_IN[3] DSP#1 GPIO_IN[0] DSP#2 GPIO_IN[1] DSP#2 GPIO_IN[2] DSP#2 GPIO_IN[3] DSP#2 Pin SD_IN[0] SD_IN[1] SD_IN[2] SD_IN[3] MIDI2_IN SD_IN[5] SD_IN[6] SD_IN[7]
Bi-processor Operation
Each PDSP has access to the same memory space. Sample data, buffers and programs can therefore be shared between the two PDSPs, thus minimizing memory requirements. Each P16 has the possibility to test a read-only bit that identifies the PDSP number it belongs to (PDSPID). This allows the firmware to make decisions according to the processor currently executing the code. As an example, consider implementation of a 128-voice synthesizer. An easy way to share traffic between the two PDSPs would be to have PDSP#1 process even MIDI-numbered notes, while the PDSP#2 would process odd MIDI-numbered notes. In this case, there would only be a single firmware processed by both P16s, with some coding as follows:
If (PDSPID == 0 && noteeven) then ProcessNote(); If (PDSPID == 1 && noteodd) then ProcessNote();
The two PDSPs may also execute completely different firmware. In this case, as both types of firmware start from address 100H, a test on PDSPID should be done at the beginning of the program to jump to the correct firmware.
Reset and Power-down
During power-up, the RESET input should be held low until the crystal oscillator and PLL are stabilized. This may take about 20 ms. The RESET signal is normally derived from the PC master reset. However, a typical RC/diode power-up network can also be used for some applications. After the low-to-high transition of RESET, the following occurs: * If REFRESH is sampled high at the low to high transition of RESET then the external SDRAM init cycles are executed (see "Memory Type Configuration and Boot Configuration" on page 25). * * * Both Synthesis/DSP enter an idle state. If REFRESH is low, then both P16 program execution starts from address 0100H in ROM space (WCS0 low). If REFRESH is high, then both P16 program execution starts from address 0000H in internal bootstrap ROM space. Each internal bootstrap expects to receive 256 words from its respective 16-bit burst transfer port, which will be stored from 0100H to 01FFH into the external DRAM space. The bootstrap then resumes control at address 0100H. If PDWN is asserted low, then all I/Os and outputs will be floated and the crystal oscillator and PLL will be stopped. The chip enters a deep power-down sleep mode. To exit power down, PDWN has to be asserted high, then RESET applied.
*
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Memory Type Configuration and Boot Configuration
At the end of power-up, when RESET input goes from low to high, RAS, CAS and REFRESH pins are sampled by the SAM9708 to determine memory type configuration and boot type. RAS, CAS and REFRESH must be pulled to VCC or GND through an external 10K resistor to select these different power-up configurations. One memory type can be used for low pages (addresses [0-8000000h[, AD[27]=0) and a different type for high pages (addresses [8000000h-10000000h[). Memory types allowed are Flash/ROM, SRAM, DRAM or SDRAM. When using RAM (SRAM, DRAM or SDRAM) in low page, P16 must start in bootstrap state. When in bootstrap state, P16 program execution starts at address 0. If not in bootstrap, program execution starts at address 100h. Bootstrap is selected via the REFRESH pin.
Table 18. Memory Type and Boot Configuration
Pin Level Detected at Reset REFRESH RAS Stand-alone Mode Low Low Low Low Low Low High High Bootstrap Mode High High High Note: Low Low High Low High X SRAM DRAM SDRAM WCS0 RAS, CAS RAS, CAS Flash/ROM Flash/ROM Flash/ROM WCS1 WCS1 WCS1 Low High Low High CAS Memory Type Flash/ROM Flash/ROM Flash/ROM Flash/ROM Selected by WCS0 WCS0 WCS0 WCS0 Memory Type SRAM DRAM SDRAM Selected by WCS1 RAS, CAS RAS, CAS Low Page High Page
Selected by firmware
1. When accessing DRAM or SDRAM, DRAM/SDRAM is selected by signals RAS and CAS (WCS0 and WCS1 are inactive) and addresses are time-multiplexed on WA[..] pins as follows: * WA0 - WA8: DRA0 - DRA8 * WA18: DRA9 * WA20: DRA10 * WA22: DRA11 When accessing SRAM, Flash or ROM, SRAM/Flash/ROM are selected by signals WCS0, WCS1 (RAS and CAS are inactive) and WA[26..0] address pins: * if low pages: WCS0 = 0, WCS1 = 1 * if high pages: WCS0 = 1, WCS1 = 0
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Recommended Board Layout
GND, VCC, VC3 Distribution, Decouplings
Like all HCMOS high-integration ICs, some rules of board layout should be followed for reliable device operation: All GND, VCC, VC3 pins should be connected. GND and VCC planes are strongly recommended below the SAM9708. The board GND and VCC distribution should be in grid form. If 3.3V is not available, then VC3 can be connected to VCC by two 1N4148 diodes in series. Recommended decoupling is 0.1 F at each corner of the IC with an additional 10 F decoupling close to the crystal. VC3 requires a single 0.1F decoupling close to the IC.
Crystal, LFT
The paths between the crystal, the crystal compensation capacitors, the LFT filter R-C-R and the SAM9708 should be short and shielded. The ground return from the compensation capacitors and LFT filter should be the GND plane from SAM9708. Parallel layout from D0 - D15 and DRA0 - DRA11/WD0 - WD15 should be avoided. The D0 D15 bus is an asynchronous high-transient current-type bus. Even on short distances, it can induce pulses on DRA0 - DRA11/WD0 - WD15 which can corrupt address and/or data on these buses. A ground plane should be implemented below the D0 - D15 bus, which connects both to the PC-ISA connector and to the SAM9708 GND. A ground plane should be implemented below the DRA0 - DRA11/WD0 - WD15 bus, which connects both to the DRAM SIMM grounds and to the SAM9708.
Buses
Analog Section
A specific AGND ground plane should be provided, which connects to the GND ground by a single trace. No digital signals should cross the AGND plane. Refer to the Codec vendor recommended layout for correct implementation of the analog section.
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Recommended Crystal Compensation and LFT Filter
Figure 20. Recommended Crystal Compensation and LFT Filter
134 61 X1 62 60
C4 22 pF C1 22 pF C2 2.2 nF C3 10 nF R1 100
RESET X1 X2 LFT PDWN
137
GND
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Mechanical Dimensions
Figure 21. 144-lead TQFP Package Drawing
Table 19. 144-lead TQFP Package Dimensions (in millimeters)
Min A A1 A2 D D1 E E1 L P B 0.17 1.40 0.05 1.35 21.90 19.90 21.90 19.90 0.45 Nom 1.50 0.10 1.40 22.00 20.00 22.00 20.00 0.60 0.50 0.22 0.27 Max 1.60 0.15 1.45 22.10 20.10 22.10 20.10 0.75
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical Atmel(R) is the registered trademark of Atmel Corporation. Roland(R) , GS(R) Sound Set and the GS logo are registered trademarks of Roland Corporation. General MIDI logo is under licence of Midi Manufacturers Association. Other terms and product names may be the trademarks of others. Printed on recycled paper.
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